Low-power-consumption voltage stabilizer circuit based on low-voltage CMOS process device

Abstract

The invention relates to a low-power-consumption voltage stabilizer circuit based on a low-voltage CMOS (complementary metal oxide semiconductor) process device. The band-gap reference circuit comprises a band-gap reference used for generating reference voltage and loading the generated reference voltage to a voltage stabilizer; the voltage stabilizer receives the reference voltage and converts the received reference voltage into target output voltage, the voltage value of the target output voltage is larger than that of the reference voltage, and the target output voltage is matched with the highest voltage supported by the low-voltage CMOS technology; and the load isolation circuit is connected with the voltage stabilizer, loads the target output voltage to the connected load through the load isolation circuit, and isolates the connected load from the voltage stabilizer. Under the condition of being compatible with an advanced CMOS logic process, the requirements of 5V and other high-voltage working scenes can be met, and the voltage endurance capability and the level conversion function are achieved with extremely low power consumption.

Description

Technical Field

[0001] The present invention relates to a voltage regulator circuit, and in particular to a low-power voltage regulator circuit based on low-voltage CMOS process devices. Background Art

[0002] With the continuous upgrading of the process, under the current CMOS logic and radio frequency (RF) processes, 5V devices are gradually regarded as high-voltage devices, and foundries generally no longer provide corresponding 5V devices. For example, in CMOS RF processes below 55nm, the highest supported device is 3.3V. If 5V devices are required, the BCD (Bipolar-CMOS-DMOS) process needs to be used. However, RF circuits require accurate device models. Therefore, the BCD process is not suitable for the research and development of RF chips.

[0003] In addition, in practical applications, it is generally required that the chip can work normally in a wide power supply voltage range. Therefore, in addition to the overall functional circuit, an LDO (Low Dropout) voltage regulator needs to be additionally integrated inside the chip to convert the high voltage of the external power supply into the low voltage required by other circuits. For low-voltage chips, since the working voltage of the LDO voltage regulator is relatively high, it is difficult for the LDO voltage regulator to be controlled by other digital circuits inside the chip. Therefore, after the chip is powered on, the LDO voltage regulator needs to work all the time, which will greatly increase the power consumption of the chip. In this case, when it is necessary to reduce the power consumption of the chip, it is necessary to reduce the power consumption of the LDO voltage regulator.

[0004] For a working environment with a relatively high working voltage, in the design, a common solution is to use high-voltage devices, such as LDMOS devices. When high-voltage devices are used, there are generally the following problems: in the CMOS process, when manufacturing high-voltage-resistant devices, multiple additional mask plates are required, which will greatly increase the area of the chip and result in relatively high power consumption of the chip.

[0005] Taking all factors into consideration, in the actual application process, the existing CMOS RF process conditions still need to be compatible with the working scenarios of 5V specific environments. Therefore, how to meet the requirements in high-voltage working scenarios such as 5V and effectively reduce power consumption at the same time is a technical problem that urgently needs to be solved at present. Summary of the Invention

[0006] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a low-power voltage regulator circuit based on low-voltage CMOS process devices, which can meet the requirements of high-voltage working scenarios such as 5V while being compatible with the continuously improving CMOS RF process, achieving both high-voltage operation and low power consumption.

[0007] According to the technical solution provided by the present invention, a low-power voltage regulator circuit based on low-voltage CMOS process devices, the low-power voltage regulator circuit is prepared based on a low-voltage CMOS logic process, and the low-power voltage regulator circuit can operate under a high-voltage power supply voltage. Among them, the low-power voltage regulator circuit includes: A bandgap reference for generating a reference voltage and loading the generated reference voltage to the voltage regulator; A voltage regulator that receives the reference voltage and converts the received reference voltage into a target output voltage, where the voltage value of the target output voltage is greater than the voltage value of the reference voltage, and the target output voltage is adapted to the highest voltage supported by the low-voltage CMOS process; A load isolation circuit connected to the voltage regulator, and the target output voltage is loaded to the connected load through the load isolation circuit, and the connected load is isolated from the voltage regulator.

[0008] The high-voltage power supply voltage is higher than the highest voltage supported by the low-voltage CMOS logic process, and the voltage value of the high-voltage power supply voltage is greater than the voltage value of the target output voltage; There are no resistor devices in the low-power voltage regulator circuit, and the bias current during the operation of the low-power voltage regulator circuit is in the nA level.

[0009] The bandgap reference includes a micro current source, a linear negative temperature drift voltage generation circuit, and a temperature drift compensation circuit connected in sequence. Among them, The micro current source generates a low-temperature drift reference current under the high-voltage power supply voltage and loads the low-temperature drift reference current to the linear negative temperature drift voltage generation circuit; The linear negative temperature drift voltage generation circuit generates a reference voltage that linearly decreases with temperature based on the low-temperature drift reference current and loads the reference voltage to the temperature drift compensation circuit; The temperature drift compensation circuit is used to compensate the temperature drift coefficient of the reference voltage to generate a low-temperature drift reference voltage after compensating the temperature drift coefficient.

[0010] The micro current source includes a current source matrix and a detection feedback control circuit adaptively connected to the current source matrix. Among them, The current source matrix generates a basic current under the high-voltage power supply voltage, The detection feedback control circuit detects the basic current and performs feedback control on the current source matrix based on the detected basic current, so that the basic current generated by the current source matrix is kept stable through feedback control, and a low-temperature drift reference current is formed based on the stable basic current.

[0011] The current source matrix includes a PMOS transistor M11 operating in the linear region and a basic current generation circuit adaptively connected to the PMOS transistor M11. Among them, The source terminal of PMOS transistor M11 is connected to the high-voltage power supply voltage. The drain terminal of PMOS transistor M11 is connected to the basic current generation circuit. The gate terminal of PMOS transistor M11 is connected to the output terminal of the detection feedback control circuit. The detection feedback control circuit is also adaptively connected to the basic current generation circuit to obtain the basic current generated by the basic current generation circuit, detect the obtained basic current, and generate a feedback control voltage. The detection feedback control circuit loads the feedback control voltage onto the gate terminal of PMOS transistor M11 to adjust the operating state of PMOS transistor M11 through the feedback control voltage, and keep the basic current generated by the basic current generation circuit stable based on the operating state of PMOS transistor M11.

[0012] The detection feedback control circuit includes a feedback control main circuit and a voltage conversion branch. Among them, The basic current generated by the basic current generation circuit is obtained through the feedback control main circuit, and the feedback control reference voltage corresponding to the basic current is generated through conversion by the voltage conversion branch. The feedback control main circuit generates a feedback control voltage based on the feedback control reference voltage. The feedback control main circuit includes PMOS transistor M12. The source terminal of PMOS transistor M12 is connected to the high-voltage power supply voltage. The gate terminal of PMOS transistor M12 is adaptively connected to the basic current generation circuit. The drain terminal of PMOS transistor M12 is connected to the source terminal of PMOS transistor M13 and the source terminal of PMOS transistor M14. The gate terminal of PMOS transistor M14 is connected to the voltage conversion branch. The drain terminal of PMOS transistor M14 is connected to the drain terminal of NMOS transistor M16, the gate terminal of NMOS transistor M16, the gate terminal of NMOS transistor M15, the drain terminal of NMOS transistor M15, the drain terminal of PMOS transistor M13, and the gate terminal of PMOS transistor M13 to form a feedback control output terminal connected to the gate terminal of PMOS transistor M11, and is connected to the gate terminal of PMOS transistor M11 through the feedback control output terminal. The source terminal of NMOS transistor M15 is connected to the drain terminal of NMOS transistor M17. The gate terminal of NMOS transistor M17 is connected to the gate terminal of NMOS transistor M18, the drain terminal of NMOS transistor M18, and the source terminal of NMOS transistor M16. The source terminal of NMOS transistor M17 is connected to the drain terminal of NMOS transistor M19. The gate terminal of NMOS transistor M19 is connected to the gate terminal of NMOS transistor M20, the drain terminal of NMOS transistor M20, and the source terminal of NMOS transistor M18. Both the source terminals of NMOS transistor M19 and NMOS transistor M20 are grounded.

[0013] The temperature drift compensation circuit includes a number of cascaded temperature drift compensation units. Among them, Each stage of the temperature drift compensation unit can generate a voltage difference with the same temperature coefficient, so as to effectively compensate the temperature drift coefficient of the reference voltage through multiple cascaded temperature drift compensation units. The temperature drift compensation unit at least includes a temperature drift compensation PMOS current mirror unit and a temperature drift compensation NMOS differential pair transistor unit. Among them, The temperature drift compensation PMOS current mirror unit is connected to the high-voltage power supply voltage and is adaptively connected to the temperature drift compensation NMOS differential pair transistor unit; The temperature drift compensation NMOS differential pair transistor unit at least includes a temperature drift compensation NMOS differential input transistor, a temperature drift compensation NMOS differential output transistor, and a temperature drift compensation NMOS control transistor; The drain terminals of the temperature drift compensation NMOS differential input transistor, the temperature drift compensation NMOS differential output transistor, and the gate terminal of the temperature drift compensation NMOS differential output terminal are adaptively connected to the temperature drift compensation PMOS current mirror unit. The source terminals of the temperature drift compensation NMOS differential input transistor and the temperature drift compensation NMOS differential output transistor are both connected to the drain terminal of the temperature drift compensation NMOS control transistor. The source terminal of the temperature drift compensation NMOS control transistor is grounded, and the gate terminal of the temperature drift compensation NMOS control transistor is connected to the bias voltage VBN1; When the temperature drift compensation units are cascaded, the gate terminal of the temperature drift compensation NMOS differential input transistor is connected to the gate terminal of the temperature drift compensation NMOS differential output transistor in the previous stage of the temperature drift compensation unit; The gate terminal of the temperature drift compensation NMOS differential output terminal is connected to the temperature drift compensation NMOS differential input transistor in the next stage of the temperature drift compensation unit, and a reference voltage with zero temperature drift is output through the gate terminal of the temperature drift compensation NMOS differential output transistor in the last stage of the temperature drift compensation unit.

[0014] The voltage regulator includes an operational amplifier circuit, a voltage regulation bias current circuit, a voltage regulation current mirror circuit, and a voltage regulation conversion feedback circuit. Among them, The first input terminal of the operational amplifier circuit receives the reference voltage. The second input terminal of the operational amplifier circuit is adaptively connected to the voltage regulation conversion feedback circuit, and the voltage regulation bias current circuit provides the operational amplifier bias current required for the operation of the operational amplifier circuit; The output terminal of the operational amplifier circuit is connected to the voltage regulation conversion feedback circuit through the voltage regulation current mirror circuit, so as to load a voltage conversion reference current to the voltage regulation conversion feedback circuit through the voltage regulation current mirror circuit; Based on the voltage conversion reference current, the voltage regulation conversion feedback circuit generates a target output voltage and loads a conversion sampling voltage to the second input terminal of the operational amplifier circuit, so that the operational amplifier circuit loads a stable voltage conversion reference current to the voltage regulation conversion feedback circuit through the voltage regulation current mirror circuit, and the target output voltage generated by the voltage regulation conversion feedback circuit is kept stable.

[0015] The operational amplifier circuit includes a PMOS transistor M56, wherein, The gate terminal and source terminal of the PMOS transistor M56 are adaptively connected to the regulated bias current circuit, and the drain terminal of the PMOS transistor M56 is connected to the source terminal of the PMOS transistor M57 and the source terminal of the PMOS transistor M58. The gate terminal of the PMOS transistor M57 forms the first input terminal of the operational amplifier circuit, and the gate terminal of the PMOS transistor M58 serves as the second input terminal of the operational amplifier circuit; The drain terminal of the PMOS transistor M57 is connected to the drain terminal, gate terminal of the NMOS transistor M59, and gate terminal of the NMOS transistor M60. The drain terminal of the NMOS transistor M60 is connected to the drain terminal of the PMOS transistor M58, and the drain terminal of the NMOS transistor M60 and the drain terminal of the PMOS transistor M58 are connected to each other to form the output terminal of the operational amplifier circuit; The source terminals of the NMOS transistor M59 and the NMOS transistor M60 are both grounded.

[0016] The regulated voltage conversion feedback circuit includes a plurality of MOS impedance units connected in series in sequence, wherein, Among the series-connected MOS units, at least one MOS impedance unit formed by an NMOS transistor group and at least one MOS impedance unit formed by a PMOS transistor group are included; The regulated current mirror circuit is adaptively connected to a MOS impedance unit formed by an NMOS transistor group, and outputs a target output voltage through the MOS impedance unit; The regulated voltage conversion feedback circuit is connected to the second input terminal of the operational amplifier circuit through a MOS impedance unit formed by a PMOS transistor group; When forming a MOS impedance unit by an NMOS transistor group, the NMOS transistors in the NMOS transistor group are all configured in a diode-connected state to form an NMOS-diode unit, and the NMOS-diode units are connected in series in sequence; When forming a MOS impedance unit by a PMOS transistor group, the PMOS transistors in the PMOS transistor group are all configured in a diode-connected state to form a PMOS-diode unit, and the PMOS-diode units are connected in series in sequence; The NMOS transistors in the NMOS transistor group and the PMOS transistors in the PMOS transistor group all adopt inverse ratio transistors, and both the NMOS transistors and the PMOS transistors adopt MOS transistors with longer conductive channels.

[0017] Advantages of the present invention: The bandgap reference, voltage regulator, and load isolation circuit are prepared by using a low-voltage CMOS process, and no resistor devices are used in the bandgap reference, voltage regulator, and load isolation circuit. Thus, it can be compatible with the existing CMOS RF process, and can reduce the chip area and power consumption; A reference voltage is provided by a bandgap reference. The voltage regulator generates a target power supply based on the reference voltage. Isolation between the voltage regulator and the load can be achieved through a load isolation circuit. During operation, the bandgap reference, the voltage regulator, and the load isolation circuit can all operate under a high-voltage power supply voltage, and the target output voltage is adapted to the highest voltage supported by the low-voltage CMOS process, thereby meeting high-voltage operating scenarios such as 5V. Without using resistor devices, through the circuit design of the bandgap reference, the voltage regulator, and the load isolation circuit, the bias current during operation can be in the nA range, effectively reducing the power consumption of the voltage regulator circuit. Description of the Drawings

[0018] Figure 1 It is a circuit block diagram of an embodiment of the low-power voltage regulator circuit of the present invention.

[0019] Figure 2 It is a circuit schematic diagram of an embodiment of the bandgap reference of the present invention.

[0020] Figure 3 It is a circuit schematic diagram of an embodiment of the voltage regulator of the present invention. Detailed Embodiments

[0021] The present invention will be further described below with reference to specific drawings and embodiments.

[0022] Under the condition of being compatible with existing CMOS logic and radio frequency processes, in order to meet the requirements of high-voltage operating scenarios such as 5V and effectively reduce power consumption, the present invention provides a low-power voltage regulator circuit based on low-voltage CMOS process devices. Specifically, the low-power voltage regulator circuit is prepared based on a low-voltage CMOS logic process, and the low-power voltage regulator circuit can operate under a high-voltage power supply voltage. Among them, the low-power voltage regulator circuit includes: A bandgap reference for generating a reference voltage and loading the generated reference voltage to the voltage regulator; A voltage regulator that receives the reference voltage and converts the received reference voltage into a target output voltage, where the voltage value of the target output voltage is greater than the voltage value of the reference voltage, and the target output voltage is adapted to the highest voltage supported by the low-voltage CMOS process; A load isolation circuit connected to the voltage regulator, through which the target output voltage is loaded to the connected load, and the connected load is isolated from the voltage regulator.

[0023] It should be noted that the low-power voltage regulator circuit of the present invention can be prepared by using the existing CMOS logic process, that is, the low-power voltage regulator circuit of the present invention can be compatible with the existing CMOS RF process (CMOS logic and radio frequency process) during preparation. Specifically, under the condition of being compatible with the existing CMOS RF process, the method of preparing the low-power voltage regulator circuit can be consistent with the prior art. As can be seen from the description of the background technology, the CMOS RF process is a low-voltage logic development process. With the continuous upgrading of the current process, the highest voltage supported by the CMOS RF process generally does not exceed 3.3V. Therefore, the low-power voltage regulator circuit of the present invention can work under a high-voltage power supply voltage, specifically referring to that the voltage value of the high-voltage power supply voltage is higher than the highest voltage supported by the low-voltage CMOS process. For example, the voltage value of the high-voltage power supply voltage can be 5V as mentioned above. Figure 1 、 Figure 2 and Figure 3 among them, V DD is the high-voltage power supply voltage, that is, Figures 1 - 3 the voltage in V DD can all be 5V. Specifically, when the low-power voltage regulator circuit can work under a high-voltage power supply voltage, that is, the low-power voltage regulator circuit of the present invention can meet the requirements of a 5V high-voltage working scenario.

[0024] Figure 1 An embodiment of the low-power voltage regulator circuit of the present invention is shown in

[0025] Figure 1 . As can be seen from the figure, the low-power voltage regulator circuit of the present invention can at least include a bandgap reference, a voltage regulator, and a load isolation circuit. It should be understood that the bandgap reference, the voltage regulator, and the load isolation circuit should all be prepared by using the low-voltage CMOS RF process. Specifically, when working under a high-voltage power supply voltage, the bandgap reference can generate a reference voltage, and the voltage regulator can convert the reference voltage into a target output voltage. Generally, the voltage value of the reference voltage is lower than the voltage value of the target output voltage, and the target output voltage should be adapted to the highest voltage supported by the low-voltage CMOS process. Among them, the target output voltage being adapted to the highest voltage supported by the low-voltage CMOS process specifically means that the target output voltage does not exceed the highest voltage supported by the low-voltage CMOS RF process. As can be seen from the above description, when the highest voltage supported by the low-voltage CMOS process can be 3.3V, at this time, the target output voltage should not exceed 3.3V.

[0026] As can be seen from the above description, when a resistive device is used, it will increase the area of the chip / circuit and the power consumption. Therefore, in order to achieve the purpose of low power consumption, in an embodiment of the present invention, there is no resistive device in the low-power voltage regulator circuit, and the bias current during the operation of the low-power voltage regulator circuit is in the nA level.

[0027] It can be understood that there is no resistive device in the low-power voltage regulator circuit of the present invention, that is, a resistive device is not used to design the low-power voltage regulator circuit. At this time, there are no resistive devices in the bandgap reference, voltage regulator, and load isolation circuit.

[0028] In addition, in order to further reduce the power consumption, the bias current during the operation of the low-power voltage regulator circuit can be in the nA level. Since the operating circuit of the low-power voltage regulator circuit is small, the voltage regulator responds slowly to load changes. Therefore, in order to prevent the influence of load changes on the voltage regulator, the present invention can load the target output voltage to the load connected to the load isolation circuit through the load isolation circuit, and the load isolation circuit can isolate the voltage regulator from the load.

[0029] Figure 1 An embodiment of the load isolation circuit of the present invention is shown. In the figure, the load isolation circuit includes an NMOS transistor MN1. At this time, the gate terminal of the NMOS transistor MN1 is connected to the output terminal of the voltage regulator, and the drain terminal of the NMOS transistor MN1 is connected to the voltage V DD connection, and the source terminal of the NMOS transistor MN1 is connected to the load. Figure 1 In the figure, the low-voltage output voltage output from the source terminal of the NMOS transistor MN1 is the above-mentioned target output voltage. It can be understood that the load isolation circuit can also adopt other forms, specifically based on being able to meet the working current in the nA level and avoiding the influence of load transformation on the voltage regulator. No further examples will be given here.

[0030] In an embodiment of the present invention, the bandgap reference includes a micro-current source, a linear negative temperature drift voltage generation circuit, and a temperature drift compensation circuit connected in sequence. Among them, The micro-current source generates a low-temperature drift reference current under the high-voltage power supply voltage and loads the low-temperature drift reference current to the linear negative temperature drift voltage generation circuit; The linear negative temperature drift voltage generation circuit generates a reference voltage that linearly decreases with temperature based on the low-temperature drift reference current and loads the reference voltage to the temperature drift compensation circuit; The temperature drift compensation circuit is used to compensate the temperature drift coefficient of the reference voltage to generate a low-temperature drift reference voltage after the temperature drift coefficient compensation.

[0031] In order to generate a reference voltage under a high-voltage power supply voltage, in an embodiment of the present invention, the bandgap reference may include a micro current source, a linear negative temperature drift voltage generation circuit, and a temperature drift compensation circuit connected in sequence. Among them, a low-temperature drift reference current can be generated through the micro current source. The generated low-temperature drift reference current specifically refers to that the current is less affected by the external high-voltage power supply voltage and temperature changes; through the linear negative temperature drift voltage generation circuit, the low-temperature drift reference current can be converted into a reference voltage that linearly decreases with temperature. The reference voltage linearly decreases with temperature, specifically referring to that when the temperature increases, the reference voltage linearly decreases.

[0032] Since the reference voltage has a negative temperature characteristic, in order to obtain a reference voltage with low temperature drift, the present invention can use a temperature compensation circuit to compensate the temperature coefficient of the reference voltage, so as to generate a reference voltage with low temperature drift after temperature coefficient compensation. Among them, generating a reference voltage with low temperature drift specifically means that the reference voltage is less affected by the external high-voltage power supply voltage and temperature, so as to provide a stable reference voltage for the voltage regulator.

[0033] In an embodiment of the present invention, the micro current source includes a current source matrix and a detection feedback control circuit adaptively connected to the current source matrix. Among them, The current source matrix generates a basic current under the high-voltage power supply voltage, The detection feedback control circuit detects the basic current and performs feedback control on the current source matrix based on the detected basic current, so that the basic current generated by the current source matrix is kept stable through feedback control, and a low-temperature drift reference current is formed based on the stable basic current.

[0034] In order to generate a low-temperature drift reference current, the micro current source may include a current source matrix and a detection feedback control circuit. Among them, the current source matrix can be used to generate a basic current, and the detection feedback control circuit can perform feedback control on the basic current generated by the current source matrix, so that the basic current generated by the current source matrix is kept stable after feedback control, and then a low-temperature drift reference current can be formed based on the stable basic current. From the above description, it can be seen that the basic current being kept stable specifically means that the basic current is less affected by the external high-voltage power supply voltage and temperature.

[0035] In an embodiment of the present invention, the current source matrix includes a PMOS transistor M11 operating in the linear region and a basic current generation circuit adaptively connected to the PMOS transistor M11. Among them, The source terminal of the PMOS transistor M11 is connected to the high-voltage power supply voltage, the drain terminal of the PMOS transistor M11 is connected to the basic current generation circuit, and the gate terminal of the PMOS transistor M11 is connected to the output terminal of the detection feedback control circuit; The detection feedback control circuit is also adaptively connected to the basic current generation circuit to obtain the basic current generated by the basic current generation circuit, detect the obtained basic current, and generate a feedback control voltage; The detection feedback control circuit loads the feedback control voltage to the gate terminal of PMOS transistor M11 to adjust the operating state of PMOS transistor M11 through the feedback control voltage, and makes the basic current generated by the basic current generation circuit stable based on the operating state of PMOS transistor M11.

[0036] Figure 2 An embodiment of the bandgap reference of the present invention is shown in Figure 2 As can be seen from the embodiment shown in, the current source matrix should at least include PMOS transistor M11 and the basic current generation circuit. Among them, in order to satisfy the low-temperature drift reference current generated by the above micro current source, PMOS transistor M11 should work in the linear region, that is, PMOS transistor M11 can be used as a linear resistor. The method of configuring PMOS transistor M11 to work in the linear region can be consistent with the prior art and will not be elaborated here. The basic current can be generated by the basic current generation circuit. During feedback control, the detection feedback control circuit should obtain the basic current, generate a feedback control voltage according to the basic current, adjust the operating state of PMOS transistor M11 through the feedback control voltage, and then make the basic current generated by the basic current generation circuit stable.

[0037] Figure 2 An embodiment of the basic current generation circuit is shown in. As can be seen from the figure, the basic current generation circuit includes NMOS transistors M1, M2, M3, M4, PMOS transistors M5, M6, M7, M8, M9, and M10, where The source terminal of PMOS transistor M9 is connected to the voltage V DD , the gate electrodes of PMOS transistor M9 and the gate terminal of PMOS transistor M10 are both connected to the detection feedback control circuit, the source terminal of PMOS transistor M10 is connected to the drain terminal of PMOS transistor M11. In addition, the gate terminal of PMOS transistor M9 and the gate terminal of PMOS transistor M10 are also connected to the drain terminal of PMOS transistor M9 and the source terminal of PMOS transistor M7, and the drain terminal of PMOS transistor M10 is connected to the source terminal of PMOS transistor M8; The gate terminal of PMOS transistor M7 is connected to the gate terminal of PMOS transistor M8, the drain terminal of PMOS transistor M7, and the source terminal of PMOS transistor M5. The gate terminal of PMOS transistor M5 is connected to the drain terminal of PMOS transistor M5 and the drain terminal of NMOS transistor M3. The drain terminal of PMOS transistor M8 is connected to the source terminal of PMOS transistor M6. The gate terminal of PMOS transistor M6 is connected to the drain terminal of PMOS transistor M6, the gate terminal of NMOS transistor M3, the gate terminal of NMOS transistor M4, and the drain terminal of NMOS transistor M4. The source terminal of NMOS transistor M4 is connected to the gate terminal of NMOS transistor M1, the drain terminal of NMOS transistor M2, and the gate terminal of NMOS transistor M2. The source terminals of NMOS transistor M1 and NMOS transistor M2 are both grounded. The gate terminals of NMOS transistor M1 and NMOS transistor M2 both receive the bias voltage VBN1. The gate terminals of NMOS transistor M3 and NMOS transistor M4 both receive the bias voltage VBN2.

[0038] It should be noted that the bias voltage VBN1 and the bias voltage VBN2 can be generated by an existing bias circuit. NMOS transistor M1 and NMOS transistor M2 form a current mirror. NMOS transistor M3 and NMOS transistor M4 form a current mirror. PMOS transistor M5 and PMOS transistor M6 are connected in a diode form. PMOS transistor M7 and PMOS transistor M8 form a current mirror. PMOS transistor M9 and PMOS transistor M10 also form a current mirror. Specifically, during operation, NMOS transistors M2 to M4 and PMOS transistors M5 to M8 can all generate voltage drops, that is, they can all achieve voltage division, thereby preventing overvoltage from breaking down the MOS transistors used in the low-power voltage stabilization circuit of the present invention. In addition, the current source matrix can also adopt other forms, specifically based on the ability to generate the above-mentioned basic current and stabilize the basic current through feedback control, and no further examples will be given here.

[0039] In an embodiment of the present invention, the detection feedback control circuit includes a feedback control main circuit and a voltage conversion branch, where The basic current generated by the basic current generation circuit is obtained through the feedback control main circuit, and the feedback control reference voltage corresponding to the basic current is generated through conversion by the voltage conversion branch. The feedback control main circuit generates a feedback control voltage based on the feedback control reference voltage; The feedback control main circuit includes PMOS transistor M12. The source terminal of PMOS transistor M12 is connected to the high-voltage power supply voltage. The gate terminal of PMOS transistor M12 is adaptively connected to the basic current generation circuit. The drain terminal of PMOS transistor M12 is connected to the source terminal of PMOS transistor M13 and the source terminal of PMOS transistor M14; The gate terminal of PMOS transistor M14 is connected to the voltage conversion branch. The drain terminal of PMOS transistor M14 is connected to the drain terminal of NMOS transistor M16, the gate terminal of NMOS transistor M16, the gate terminal of NMOS transistor M15, the drain terminal of NMOS transistor M15, the drain terminal of PMOS transistor M13, and the gate terminal of PMOS transistor M13 to form a feedback control output terminal connected to the gate terminal of PMOS transistor M11, and is connected to the gate terminal of PMOS transistor M11 through the feedback control output terminal; The source terminal of NMOS transistor M15 is connected to the drain terminal of NMOS transistor M17, and the gate terminal of NMOS transistor M17 is connected to the gate terminal of NMOS transistor M18, the drain terminal of NMOS transistor M18, and the source terminal of NMOS transistor M16; The source terminal of NMOS transistor M17 is connected to the drain terminal of NMOS transistor M19, and the gate terminal of NMOS transistor M19 is connected to the gate terminal of NMOS transistor M20, the drain terminal of NMOS transistor M20, and the source terminal of NMOS transistor M18; Both the source terminal of NMOS transistor M19 and the source terminal of NMOS transistor M20 are grounded.

[0040] Figure 2 An embodiment of the detection feedback control circuit is shown, and from Figure 2 it can be seen that when the gate terminal of PMOS transistor M12 is adaptively connected to the basic current generation circuit, it specifically means that at least the gate terminal of PMOS transistor M12 is connected to the gate terminal of PMOS transistor M9 and the gate terminal of PMOS transistor M10.

[0041] Figure 2 An embodiment of the voltage conversion branch is also shown, and from the figure it can be seen that the voltage conversion branch may include PMOS transistor M23, NMOS transistor M21, and NMOS transistor M21. Among them, the source terminal of PMOS transistor M23 is connected to the voltage V DD , the gate terminal of PMOS transistor M23, the drain terminal of PMOS transistor M23, and the drain terminal of NMOS transistor M22 are all connected to the gate terminal of PMOS transistor M14, the source terminal of NMOS transistor M22 is connected to the drain terminal of NMOS transistor M21, the source terminal of NMOS transistor M21 is grounded, the gate terminal of NMOS transistor M22 is connected to the bias voltage VBN2, and the gate terminal of NMOS transistor M21 is connected to the bias voltage VBN1. Specifically, when NMOS transistor M21 is turned on under the bias voltage VBN1 and NMOS transistor M22 is turned on under the bias voltage VBN2, a feedback control reference voltage corresponding to the basic current can be generated through the conversion of PMOS transistor M23 In specific implementation, NMOS transistor M19 and NMOS transistor M20 form a current mirror, and NMOS transistors M17 and M18 also form a current mirror. In addition, PMOS transistors M13 and M14 form a differential pair. Generally, PMOS transistors M13 and M14 should be PMOS transistors of different sizes, that is, an asymmetric differential pair can be formed based on PMOS transistors M13 and M14. After the feedback control is connected to the gate terminal of the main circuit and PMOS transistor M11, a negative feedback connection form can be formed. Among them, based on the asymmetric differential pair, a feedback control voltage can be generated based on the feedback control reference voltage. In addition, during operation, voltage drops can occur on PMOS transistors M15, M16, NMOS transistors M17, and NMOS transistors M18, so as to achieve voltage division and withstand voltage protection.

[0042] Furthermore, Figure 2 An embodiment of the linear negative temperature drift voltage generation circuit is also shown in [the figure]. As can be seen from the figure, the linear negative temperature drift voltage generation circuit may include PMOS transistor M24, PMOS transistor M25, PMOS transistor M26, PMOS transistor M27, and PNP transistor Q1, where The source terminal of PMOS transistor M24 is connected to voltage V DD , the gate terminal of PMOS transistor M24 should be connected to at least the gate terminals of PMOS transistor M9 and PMOS transistor M10. The drain terminal of PMOS transistor M24 is connected to the source terminal of PMOS transistor M25. The gate terminal and drain terminal of PMOS transistor M25 are connected to the source terminal of PMOS transistor M26. The gate terminal and drain terminal of PMOS transistor M26 are connected to the source terminal of PMOS transistor M27; The gate terminal and drain terminal of PMOS transistor M27 are connected to the emitter terminal of PNP transistor Q1, and a linear negative temperature drift voltage output terminal is formed. The base terminal and collector terminal of PNP transistor Q1 are both grounded.

[0043] Specifically, the reference voltage can be loaded onto the temperature drift compensation circuit through the linear negative temperature drift voltage output terminal. For the above linear negative temperature drift voltage generation circuit, PMOS transistor M24 can form a current mirror with PMOS transistor M9 and PMOS transistor M10 to mirror the generated low temperature drift reference circuit to the linear negative temperature drift voltage generation circuit. PMOS transistors M25, M26, and M27 are all in diode connection mode. A large voltage drop can be generated through PMOS transistors M25 to M27 to prevent overvoltage from breaking down the MOS transistors in the low-power voltage regulator of the present invention. In addition, through the voltage drop of PMOS transistors M25 to M27, a reference voltage that linearly decreases with temperature can be generated at the emitter terminal of PNP transistor Q1.

[0044] In an embodiment of the present invention, the temperature drift compensation circuit includes several cascaded temperature drift compensation units, where Each stage of the temperature drift compensation unit can generate a voltage difference with the same temperature coefficient to effectively compensate the temperature drift coefficient of the reference voltage through multiple cascaded temperature drift compensation units. The temperature drift compensation unit at least includes a temperature drift compensation PMOS current mirror unit and a temperature drift compensation NMOS differential pair transistor unit, where The temperature drift compensation PMOS current mirror unit is connected to the high-voltage power supply voltage and is adaptively connected to the temperature drift compensation NMOS differential pair transistor unit; The temperature drift compensation NMOS differential pair transistor unit at least includes a temperature drift compensation NMOS differential input transistor, a temperature drift compensation NMOS differential output transistor, and a temperature drift compensation NMOS control transistor; The drain terminals of the temperature drift compensation NMOS differential input transistor, the temperature drift compensation NMOS differential output transistor, and the gate terminal of the temperature drift compensation NMOS differential output terminal are adaptively connected to the temperature drift compensation PMOS current mirror unit. The source terminals of the temperature drift compensation NMOS differential input transistor and the temperature drift compensation NMOS differential output transistor are both connected to the drain terminal of the temperature drift compensation NMOS control transistor. The source terminal of the temperature drift compensation NMOS control transistor is grounded, and the gate terminal of the temperature drift compensation NMOS control transistor is connected to the bias voltage VBN1. When the temperature drift compensation units are cascaded, the gate terminal of the temperature drift compensation NMOS differential input transistor is connected to the gate terminal of the temperature drift compensation NMOS differential output transistor in the previous stage of the temperature drift compensation unit; The gate terminal of the temperature drift compensation NMOS differential output terminal is connected to the temperature drift compensation NMOS differential input transistor in the next stage of the temperature drift compensation unit, and a zero-temperature-drift reference voltage is output through the gate terminal of the temperature drift compensation NMOS differential output transistor in the last stage of the temperature drift compensation unit.

[0045] In order to compensate for the temperature drift coefficient of the reference voltage, the temperature drift compensation circuit may include multiple temperature drift compensation units, and the multiple temperature drift compensation units are connected in a cascaded manner. Among them, each stage of the temperature compensation unit can generate a voltage difference with the same temperature coefficient, and the temperature coefficient of the generated voltage difference is opposite to that of the reference voltage, and the difference in the voltage differences generated by each stage of the temperature compensation unit is equal. Therefore, in specific implementation, the number of temperature drift compensation units in the cascaded state in the temperature drift compensation circuit can be determined according to the temperature coefficient of the reference voltage. That is, the number of temperature drift compensation units in the cascaded state should be based on the effective compensation of the temperature drift coefficient of the reference voltage. Among them, the effective compensation of the temperature drift coefficient of the reference voltage specifically means that a reference voltage with low temperature drift can be generated. For example, the reference voltage with low temperature drift can be a reference voltage with zero temperature drift.

[0046] In specific implementation, when the temperature drift compensation units are connected in cascade, the temperature drift compensation units in the temperature drift compensation circuit are preferably of the same circuit form. Specifically, for the temperature drift compensation unit, it may include a temperature drift compensation PMOS current mirror unit and a temperature drift compensation NMOS differential pair tube unit. Among them, the temperature drift compensation PMOS current mirror unit is connected to the high-voltage power supply voltage and is adaptively connected to the temperature drift compensation NMOS differential pair tube unit.

[0047] It can be understood that after multiple temperature drift compensation units are cascaded, there is a first-stage temperature drift compensation unit and a last-stage temperature drift compensation unit. Among them, the first-stage temperature drift compensation unit is the temperature drift compensation unit connected to the linear negative temperature drift voltage generation circuit, and the last-stage temperature drift compensation unit is the temperature drift compensation unit that outputs the reference voltage. The other-stage temperature drift compensation units are cascaded with the previous-stage temperature drift compensation unit and the next-stage temperature drift compensation unit correspondingly.

[0048] Figure 2 An embodiment of the temperature drift compensation circuit is shown in []. It can be seen from the figure that Figure 2 the temperature drift compensation circuit in [] includes at least a first-stage temperature drift compensation unit, a second-stage temperature drift compensation unit, and a last-stage temperature drift compensation unit. The following combines Figure 2 to specifically illustrate the situation of the temperature drift compensation unit. Specifically, For the first-stage temperature drift compensation unit, the temperature drift compensation PMOS current mirror unit includes at least PMOS transistor M31, PMOS transistor M32, PMOS transistor M33, and PMOS transistor M34. NMOS transistor M29 forms a temperature drift compensation NMOS differential input transistor, NMOS transistor M30 forms a temperature drift compensation NMOS differential output transistor, and NMOS transistor M28 forms a temperature drift compensation NMOS control transistor. Among them, the source terminals of PMOS transistor M33 and PMOS transistor M34 are both connected to the voltage V DD, the gate terminal of PMOS transistor M33 is connected to the gate terminal of PMOS transistor M34, the drain terminal of PMOS transistor M33, and the source terminal of PMOS transistor M31. The drain terminal of PMOS transistor M34 is connected to the source terminal of PMOS transistor M32. The gate terminal of PMOS transistor M31 is connected to the drain terminal of PMOS transistor M31 and the drain terminal of NMOS transistor M29. The gate terminal of NMOS transistor M29 is connected to the linear negative temperature drift voltage output terminal. The source terminal of NMOS transistor M29 is connected to the drain terminal of NMOS transistor M28; The gate terminal of PMOS transistor M32 is connected to the drain terminal of PMOS transistor M32, the drain terminal of NMOS transistor M30, and the gate terminal of NMOS transistor M30. The source terminal of NMOS transistor M30 is connected to the drain terminal of NMOS transistor M28. The gate terminal of NMOS transistor M30 is also connected to the gate terminal of NMOS transistor M37 in the second-stage temperature drift compensation unit. The source terminal of NMOS transistor M28 is grounded.

[0049] For the second-stage temperature drift compensation unit, the temperature drift compensation PMOS current mirror unit at least includes PMOS transistors M38, M39, M40, and M41. NMOS transistor M37 forms a temperature drift compensation NMOS differential input transistor. NMOS transistor M36 forms a temperature drift compensation NMOS differential output transistor. NMOS transistor M35 forms a temperature drift compensation NMOS control transistor. Among them, The source terminals of PMOS transistor M40 and PMOS transistor M41 are both connected to voltage V DD , the gate terminal of PMOS transistor M40 is connected to the gate terminal of PMOS transistor M41, the drain terminal of PMOS transistor M40, and the source terminal of PMOS transistor M39. The drain terminal of PMOS transistor M41 is connected to the source terminal of PMOS transistor M38. The gate terminal of PMOS transistor M39 is connected to the drain terminal of PMOS transistor M39 and the drain terminal of NMOS transistor M37. The gate terminal of NMOS transistor M37 is at least connected to the gate terminal of NMOS transistor M30. The source terminal of NMOS transistor M37 is connected to the drain terminal of NMOS transistor M35; The gate terminal of PMOS transistor M38 is connected to the drain terminal of PMOS transistor M38, the drain terminal of NMOS transistor M36, and the gate terminal of NMOS transistor M36. The source terminal of NMOS transistor M36 is connected to the drain terminal of NMOS transistor M35. The gate terminal of NMOS transistor M36 is also connected to the gate terminal of the temperature drift compensation NMOS differential input transistor in the third-stage temperature drift compensation unit. The source terminal of NMOS transistor M35 is grounded.

[0050] For the last-stage temperature drift compensation unit, the temperature drift compensation PMOS current mirror unit includes at least PMOS transistor M45, PMOS transistor M46, PMOS transistor M47, and PMOS transistor M48. NMOS transistor M44 forms a temperature drift compensation NMOS differential input transistor, NMOS transistor M43 forms a temperature drift compensation NMOS differential output transistor, and NMOS transistor M42 forms a temperature drift compensation NMOS control transistor. Among them, The source terminals of PMOS transistor M47 and PMOS transistor M48 are both connected to the voltage V DD , the gate terminal of PMOS transistor M47 is connected to the gate terminal of PMOS transistor M48, the drain terminal of PMOS transistor M47, and the source terminal of PMOS transistor M46. The drain terminal of PMOS transistor M48 is connected to the source terminal of PMOS transistor M45. The gate terminal of PMOS transistor M46 is connected to the drain terminal of PMOS transistor M46 and the drain terminal of NMOS transistor M44. The gate terminal of NMOS transistor M44 is connected to the gate terminal of the temperature drift compensation NMOS differential output transistor in the previous-stage temperature drift compensation unit. The source terminal of NMOS transistor M44 is connected to the drain terminal of NMOS transistor M42; The gate terminal of PMOS transistor M45 is connected to the drain terminal of PMOS transistor M45, the drain terminal of NMOS transistor M43, and the gate terminal of NMOS transistor M43. The source terminal of NMOS transistor M43 is connected to the drain terminal of NMOS transistor M42; The source terminal of NMOS transistor M42 is grounded. The gate terminal of NMOS transistor M43 also serves as the output terminal of the entire temperature drift compensation circuit. That is, a reference voltage with zero temperature drift can be output through the gate terminal of NMOS transistor M43, Figure 2 and VOUT1 in

[0051] is the reference voltage with zero temperature drift.

[0052] In an embodiment of the present invention, the voltage regulator includes an operational amplifier circuit, a voltage regulation bias current circuit, a voltage regulation current mirror circuit, and a voltage regulation conversion feedback circuit. Among them, The first input terminal of the operational amplifier circuit receives the reference voltage. The second input terminal of the operational amplifier circuit is adaptively connected to the voltage regulation conversion feedback circuit, and the voltage regulation bias current circuit provides the operational amplifier bias current required for the operation of the operational amplifier circuit; The output terminal of the operational amplifier circuit is connected to the voltage regulation conversion feedback circuit through the voltage regulation current mirror circuit to load a voltage conversion reference current to the voltage regulation conversion feedback circuit through the voltage regulation current mirror circuit; Based on the voltage conversion reference current, the voltage stabilization conversion feedback circuit generates a target output voltage and loads a conversion sampling voltage to the second input terminal of the operational amplifier circuit, so that the operational amplifier circuit loads a stable voltage conversion reference current to the voltage stabilization conversion feedback circuit through the voltage stabilization current mirror circuit, and enables the target output voltage generated by the voltage stabilization conversion feedback circuit to be stable.

[0053] In order to generate a target output voltage based on a reference voltage, the voltage regulator of the present invention may include an operational amplifier circuit, a voltage stabilization bias current circuit, a voltage stabilization current mirror circuit, and a voltage stabilization conversion feedback circuit. Among them, the voltage stabilization bias current circuit can provide the operational amplifier bias circuit required for the operation of the operational amplifier circuit. Through the operational amplifier circuit, the reference voltage and the conversion sampling voltage loaded by the voltage stabilization conversion feedback circuit can be received. Based on the reference voltage and the conversion sampling voltage, the operational amplifier circuit can generate an error amplification voltage. The error amplification voltage can be the difference between the reference voltage and the conversion sampling voltage, that is, the operational amplifier circuit is operating in the state of a comparator at this time.

[0054] The error amplification circuit output by the operational amplifier circuit can generate a voltage conversion reference current through the voltage stabilization current mirror circuit, and load the generated voltage conversion reference current into the voltage stabilization conversion feedback circuit, so that the voltage stabilization conversion feedback circuit outputs a target output voltage. Of course, the conversion sampling voltage can be obtained by the voltage stabilization conversion feedback circuit at the same time. It can be understood that the conversion sampling voltage is the sampled value after sampling the target output voltage, and the conversion sampling voltage is in a proportional relationship with the target output voltage, that is, the state of the target output voltage can be characterized by the conversion sampling voltage.

[0055] In an embodiment of the present invention, the operational amplifier circuit includes a PMOS transistor M56, where The gate terminal and source terminal of the PMOS transistor M56 are adaptively connected to the voltage stabilization bias current circuit. The drain terminal of the PMOS transistor M56 is connected to the source terminal of the PMOS transistor M57 and the source terminal of the PMOS transistor M58. The gate terminal of the PMOS transistor M57 forms the first input terminal of the operational amplifier circuit, and the gate terminal of the PMOS transistor M58 serves as the second input terminal of the operational amplifier circuit; The drain terminal of the PMOS transistor M57 is connected to the drain terminal, gate terminal of the NMOS transistor M59, and gate terminal of the NMOS transistor M60. The drain terminal of the NMOS transistor M60 is connected to the drain terminal of the PMOS transistor M58, and the drain terminal of the NMOS transistor M60 and the drain terminal of the PMOS transistor M58 are connected to each other to form the output terminal of the operational amplifier circuit; The source terminals of the NMOS transistor M59 and the NMOS transistor M60 are both grounded.

[0056] Figure 3An embodiment of an operational amplifier circuit is shown. As can be seen from the figure, the operational amplifier circuit may include PMOS transistor M56, PMOS transistor M57, PMOS transistor M58, NMOS transistor M59, and NMOS transistor M60. From the above description, the reference voltage is applied to the gate terminal of PMOS transistor M57, and the conversion sampling voltage is applied to the gate terminal of PMOS transistor M58. Thereafter, the reference voltage and the conversion sampling voltage can be compared, and an error amplified voltage is output from the output terminal of the operational amplifier circuit.

[0057] Figure 3 An embodiment of a voltage stabilizing bias current circuit is also shown. In the figure, the voltage stabilizing bias current circuit includes NMOS transistor M49, NMOS transistor M50, PMOS transistor M51, PMOS transistor M52, PMOS transistor M53, PMOS transistor M54, and PMOS transistor M55, where The drain terminal of NMOS transistor M49 is connected to the gate terminal of NMOS transistor M49 and the gate terminal of NMOS transistor M50, and the bias reference current is also received through the drain terminal of NMOS transistor M49. The source terminals of NMOS transistor M49 and NMOS transistor M50 are both grounded; The drain terminal of NMOS transistor M50 is connected to the drain terminal of PMOS transistor M51 and the gate terminal of PMOS transistor M51. The source terminal of PMOS transistor M51 is connected to the drain terminal of PMOS transistor M52 and the gate terminal of PMOS transistor M52. The source terminal of PMOS transistor M52 is connected to the drain terminal of PMOS transistor M53, the gate terminal of PMOS transistor M53, and the gate terminal of PMOS transistor M56; The source terminals of PMOS transistor M53 and PMOS transistor M56 are both connected to the drain terminal of PMOS transistor M55 and the gate terminal of PMOS transistor M55. The source terminal of PMOS transistor M55 is connected to the drain terminal of PMOS transistor M54 and the gate terminal of PMOS transistor M54. The source terminal of PMOS transistor M54 is connected to the voltage V DD 。

[0058] Figure 3 In this case, Current Bias is the bias reference current applied to the drain terminal of NMOS transistor M49. NMOS transistor M49 and NMOS transistor M50 form a current mirror. PMOS transistor M51, PMOS transistor M52, PMOS transistor M54, and PMOS transistor M54 are all in diode-connected states. PMOS transistor M53 and PMOS transistor M56 form a current mirror. Thus, an operational amplifier bias current can be provided for the operational amplifier circuit. Among them, the situation of the operational amplifier bias current can be generated by the voltage stabilizing bias current circuit processing the bias reference current, that is, the situation of the operational amplifier bias current can be determined by the working parameters of the voltage stabilizing bias current circuit, specifically to meet the working requirements of the operational amplifier circuit.

[0059] Figure 3 An embodiment of the voltage-stabilized current mirror circuit is also shown. As can be seen from the figure, the voltage-stabilized current mirror circuit includes NMOS transistor M61, PMOS transistors M62, M63, M64, and M65. Among them, The gate terminal of NMOS transistor M61 is connected to the drain terminal of NMOS transistor M60 and the drain terminal of PMOS transistor M58. The source terminal of NMOS transistor M61 is grounded. The drain terminal of NMOS transistor M61 is connected to the drain terminal and the gate terminal of PMOS transistor M62. The source terminal of PMOS transistor M62 is connected to the drain terminal and the gate terminal of PMOS transistor M63; The source terminal of PMOS transistor M63 is connected to the drain terminal, the gate terminal of PMOS transistor M64, and the gate terminal of PMOS transistor M65. The source terminals of PMOS transistor M64 and PMOS transistor M65 are both connected to the voltage V DD .

[0060] As can be seen from the shown voltage-stabilized current mirror circuit, secondary amplification can be achieved through NMOS transistor M61. PMOS transistors M62 and M63 are in diode connection states to provide impedance. PMOS transistors M64 and M65 are connected to form a current mirror, so that a voltage conversion reference current can be loaded to the voltage-stabilized conversion feedback circuit. That is, the voltage-stabilized conversion feedback circuit serves as the active load of the voltage-stabilized current mirror circuit.

[0061] In an embodiment of the present invention, the voltage-stabilized conversion feedback circuit includes a plurality of MOS impedance units connected in series in sequence. Among them, In the series-connected MOS units, at least one MOS impedance unit formed by an NMOS transistor group and at least one MOS impedance unit formed by a PMOS transistor group are included; The voltage-stabilized current mirror circuit is adaptively connected to a MOS impedance unit formed by an NMOS transistor group and outputs a target output voltage through the MOS impedance unit; The voltage-stabilized conversion feedback circuit is connected to the second input terminal of the operational amplifier circuit through a MOS impedance unit formed by a PMOS transistor group; When forming a MOS impedance unit by an NMOS transistor group, the NMOS transistors in the NMOS transistor group are all configured to be in diode connection states to form an NMOS-diode unit, and the NMOS-diode units are connected in series in sequence; When forming a MOS impedance unit by a PMOS transistor group, the PMOS transistors in the PMOS transistor group are all configured to be in diode connection states to form a PMOS-diode unit, and the PMOS-diode units are connected in series in sequence; The NMOS transistors in the NMOS transistor group and the PMOS transistors in the PMOS transistor group both use inverse ratio transistors, and both the NMOS transistors and the PMOS transistors use MOS transistors with longer conductive channels.

[0062] In the case of not using resistor devices, in order to achieve the above voltage conversion and voltage feedback, the voltage stabilizing conversion feedback circuit of the present invention can adopt a plurality of cascaded MOS impedance units, where the MOS impedance unit is an impedance formed by using MOS transistors. Specifically, in the voltage stabilizing conversion feedback circuit, there can be at least one MOS impedance unit formed by an NMOS transistor group and at least one MOS impedance unit formed by a PMOS transistor group. Among them, the NMOS transistor group includes at least two NMOS transistors, and the PMOS transistor group includes at least two PMOS transistors. The number of NMOS transistors in the NMOS transistor group and the number of PMOS transistors in the PMOS transistor group can be specifically selected according to needs to form the required MOS impedance.

[0063] When forming a MOS impedance unit by an NMOS transistor group, the NMOS transistors in the NMOS transistor group are all configured in a diode-connected state. Therefore, each NMOS transistor in the NMOS transistor group can form an NMOS-diode unit. When there are two or more NMOS transistors in the NMOS transistor group, the formed NMOS-diode units are cascaded in sequence to form a MOS impedance unit in sequence. Similarly, when forming a MOS impedance unit by a PMOS transistor group, the PMOS transistors in the PMOS transistor group are all configured in a diode-connected state. Therefore, each PMOS transistor in the PMOS transistor group can form a PMOS-diode unit. When there are two or more PMOS transistors in the PMOS transistor group, the formed PMOS-diode units are cascaded in sequence to form a MOS impedance unit in sequence. It should be noted that when configuring a MOS transistor in a diode-connected state, the gate terminal of the current MOS transistor can be connected to the drain terminal of the current MOS transistor, and the specific way of configuring in a diode-connected state can be selected according to needs.

[0064] In the case of not using a resistor, in order to provide the required impedance and make the bias current of the low-power consumption voltage stabilizing circuit of the present invention be in the nA level, in an embodiment of the present invention, the NMOS transistors in the NMOS transistor group and the PMOS transistors in the PMOS transistor group both use inverse ratio transistors, and both the NMOS transistors and the PMOS transistors use MOS transistors with longer conductive channels, that is, the NMOS transistors and the PMOS transistors use inverse ratio transistors, and NMOS transistors and PMOS transistors with longer conductive channels are selected, which should be able to provide a sufficiently large impedance capacity, so as to reduce the bias current during operation.

[0065] Figure 3In the illustrated embodiment of the voltage regulator, the voltage regulation conversion feedback circuit includes a MOS impedance unit formed by a group of NMOS transistors and two MOS impedance units formed by PMOS transistor groups. Among them, the three MOS impedance units are connected in series in sequence. The MOS impedance unit formed by the group of NMOS transistors is connected to the voltage regulation current mirror circuit, and the target output voltage can be output through the MOS impedance unit formed by the group of NMOS transistors. The first MOS impedance unit formed by the PMOS transistor group is connected to the operational amplifier circuit to load the conversion sampling voltage to the operational amplifier circuit.

[0066] Figure 3 In the MOS impedance unit composed of NMOS transistors, it includes NMOS transistor M66 and NMOS transistor M67. Among them, the drain terminal of NMOS transistor M66 is connected to the drain terminal of PMOS transistor M65 and the gate terminal of NMOS transistor M66, and the regulated output terminal of the voltage regulator is formed. The above-mentioned target output voltage can be output through the regulated output terminal. The source terminal of NMOS transistor M66 is connected to the drain terminal of NMOS transistor M67 and the gate terminal of NMOS transistor M67.

[0067] Figure 3 In it, PMOS transistor M68 and PMOS transistor M69 form a PMOS transistor group, and PMOS transistor M70 and PMOS transistor M71 form a PMOS transistor group. Specifically, the source terminal of PMOS transistor M68 is connected to the source terminal of NMOS transistor M67. The gate terminal of PMOS transistor M68 is connected to the drain terminal of PMOS transistor M68 and the source terminal of PMOS transistor M69. The gate terminal of PMOS transistor M69 is connected to the drain terminal of PMOS transistor M69, the source terminal of PMOS transistor M70, and a feedback sampling node is formed after the connection. The feedback sampling node is connected to the gate terminal of PMOS transistor M58; The gate terminal of PMOS transistor M70 is connected to the drain terminal of PMOS transistor M70 and the source terminal of PMOS transistor M71. Both the gate terminal and the drain terminal of PMOS transistor M71 are grounded.

[0068] During specific implementation, the voltage regulation conversion feedback circuit can also adopt other forms, specifically based on being able to meet voltage conversion and provide the required impedance to meet the bias current of nA level when the low-power voltage regulation circuit works.

Claims

1. A low power consumption voltage regulator circuit based on a low voltage CMOS process device, characterized in that: The low power consumption voltage regulator circuit is prepared based on a low voltage CMOS logic process, and the low power consumption voltage regulator circuit can operate under a high voltage power supply voltage, wherein the low power consumption voltage regulator circuit comprises: A bandgap reference, used for generating a reference voltage and loading the generated reference voltage to a voltage regulator; A voltage regulator receives a reference voltage and converts the received reference voltage into a target output voltage, wherein a voltage value of the target output voltage is greater than a voltage value of the reference voltage, and the target output voltage is adapted to a maximum voltage supported by a low voltage CMOS process; A load isolation circuit is connected to the voltage regulator, and applies the target output voltage to the connected load via the load isolation circuit, and isolates the connected load from the voltage regulator; The high voltage power supply voltage is higher than the highest voltage supported by the low voltage CMOS logic process, and the voltage value of the high voltage power supply voltage is greater than the voltage value of the target output voltage; The low power consumption voltage regulator circuit has no resistance device, and the bias current of the low power consumption voltage regulator circuit when working is at nA level; The bandgap reference includes a micro-current source, a linear negative temperature drift voltage generation circuit and a temperature drift compensation circuit connected in sequence, wherein: The micro-current source generates a low-temperature drift reference current under a high-voltage power supply voltage, and loads the low-temperature drift reference current to a linear negative temperature drift voltage generating circuit; The linear negative temperature drift voltage generating circuit generates a reference voltage that decreases linearly with temperature based on a low temperature drift reference current, and loads the reference voltage to the temperature drift compensation circuit; The temperature drift compensation circuit is used to compensate the temperature drift coefficient of the reference voltage to generate a reference voltage with low temperature drift after the temperature drift coefficient is compensated.

2. The low-power voltage regulator circuit based on a low-voltage CMOS process device according to claim 1, characterized in that: The micro-current source comprises a current source matrix and a detection feedback control circuit adapted to be connected to the current source matrix, wherein: The current source base generates a basic current at a high voltage supply voltage, The detection feedback control circuit detects the basic current and performs feedback control on the current source matrix based on the detected basic current, so that the basic current generated by the current source matrix remains stable through feedback control, and a low-temperature drift reference current is formed based on the stable basic current.

3. The low power consumption voltage regulator circuit based on low voltage CMOS process device according to claim 2 is characterized in that: The current source substrate includes a PMOS tube M11 operating in a linear region and a basic current generating circuit adapted to be connected to the PMOS tube M11, wherein: The source terminal of the PMOS tube M11 is connected to the high voltage power supply voltage, the drain terminal of the PMOS tube M11 is connected to the basic current generating circuit, and the gate terminal of the PMOS tube M11 is connected to the output terminal of the detection feedback control circuit; The detection feedback control circuit is also adaptively connected to the basic current generating circuit to obtain the basic current generated by the basic current generating circuit, and detects the obtained basic current and generates a feedback control voltage; The detection feedback control circuit loads the feedback control voltage to the gate terminal of the PMOS tube M11 to adjust the working state of the PMOS tube M11 through the feedback control voltage, and based on the working state of the PMOS tube M11, the basic current generated by the basic current generating circuit remains stable.

4. The low power consumption voltage regulator circuit based on low voltage CMOS process device according to claim 3 is characterized in that: The detection feedback control circuit includes a feedback control main circuit and a voltage conversion branch, wherein: The basic current generated by the basic current generating circuit is obtained through the feedback control main circuit, and the feedback control reference voltage corresponding to the basic current is generated through the voltage conversion branch. The feedback control main circuit generates a feedback control voltage based on a feedback control reference voltage; The feedback control main circuit includes a PMOS tube M12, the source terminal of the PMOS tube M12 is connected to the high voltage power supply voltage, the gate terminal of the PMOS tube M12 is adaptively connected to the basic current generation circuit, and the drain terminal of the PMOS tube M12 is connected to the source terminal of the PMOS tube M13 and the source terminal of the PMOS tube M14; The gate terminal of the PMOS tube M14 is connected to the voltage conversion branch. The drain terminal of the PMOS tube M14 is connected to the drain terminal of the NMOS tube M16, the gate terminal of the NMOS tube M16, the gate terminal of the NMOS tube M15, the drain terminal of the NMOS tube M15, the drain terminal of the PMOS tube M13, and the gate terminal of the PMOS tube M13 to form a feedback control output terminal connected to the gate terminal of the PMOS tube M11, and is connected to the gate terminal of the PMOS tube M11 through the feedback control output terminal; The source terminal of the NMOS tube M15 is connected to the drain terminal of the NMOS tube M17, and the gate terminal of the NMOS tube M17 is connected to the gate terminal of the NMOS tube M18, the drain terminal of the NMOS tube M18, and the source terminal of the NMOS tube M16; The source terminal of the NMOS tube M17 is connected to the drain terminal of the NMOS tube M19, and the gate terminal of the NMOS tube M19 is connected to the gate terminal of the NMOS tube M20, the drain terminal of the NMOS tube M20, and the source terminal of the NMOS tube M18; The source terminal of the NMOS tube M19 and the source terminal of the NMOS tube M20 are both grounded.

5. The low power consumption voltage regulator circuit based on low voltage CMOS process device according to claim 1 is characterized in that: The temperature drift compensation circuit comprises a plurality of temperature drift compensation units connected in cascade, wherein: Each level of temperature drift compensation unit can generate a voltage difference with the same temperature coefficient, so that the temperature drift coefficient of the reference voltage can be effectively compensated through multiple cascaded temperature drift compensation units. The temperature drift compensation unit at least includes a temperature drift compensation PMOS current mirror unit and a temperature drift compensation NMOS differential pair tube unit, wherein: The temperature drift compensation PMOS current mirror unit is connected to the high voltage power supply voltage and is adaptively connected to the temperature drift compensation NMOS differential pair tube unit; The temperature drift compensation NMOS differential pair tube unit at least includes a temperature drift compensation NMOS differential input tube, a temperature drift compensation NMOS differential output tube and a temperature drift compensation NMOS control tube; The drain terminals of the temperature drift compensation NMOS differential input tube and the temperature drift compensation NMOS differential output tube and the gate terminal of the temperature drift compensation NMOS differential output terminal are adaptively connected to the temperature drift compensation PMOS current mirror unit, The source terminal of the temperature drift compensation NMOS differential input tube and the source terminal of the temperature drift compensation NMOS differential output tube are both connected to the drain terminal of the temperature drift compensation NMOS control tube, the source terminal of the temperature drift compensation NMOS control tube is grounded, and the gate terminal of the temperature drift compensation NMOS control tube is connected to the bias voltage VBN1; When the temperature drift compensation units are cascaded, the gate end of the temperature drift compensation NMOS differential input tube is connected to the gate end of the temperature drift compensation NMOS differential output tube in the previous stage temperature drift compensation unit; The gate end of the temperature drift compensation NMOS differential output end is connected to the temperature drift compensation NMOS differential input tube in the next stage temperature drift compensation unit, and outputs a zero temperature drift reference voltage through the gate end of the temperature drift compensation NMOS differential output tube in the last stage temperature drift compensation unit.

6. The low power consumption voltage regulator circuit based on low voltage CMOS process device according to any one of claims 1 to 5, characterized in that: The voltage stabilizer includes an operational amplifier circuit, a voltage-stabilized bias current circuit, a voltage-stabilized current mirror circuit, and a voltage-stabilized conversion feedback circuit, wherein: The first input terminal of the operational amplifier circuit receives the reference voltage, the second input terminal of the operational amplifier circuit is adaptively connected to the voltage stabilization conversion feedback circuit, and the voltage stabilization bias current circuit provides the operational amplifier bias current required for the operation of the operational amplifier circuit; The output end of the operational amplifier circuit is connected to the voltage-stabilizing conversion feedback circuit through the voltage-stabilizing current mirror circuit, so as to load a voltage conversion reference current to the voltage-stabilizing conversion feedback circuit through the voltage-stabilizing current mirror circuit; Based on the voltage conversion reference current, the voltage stabilizing conversion feedback circuit generates a target output voltage, and loads a conversion sampling voltage to the second input terminal of the operational amplifier circuit, so that the operational amplifier circuit loads a stable voltage conversion reference current to the voltage stabilizing conversion feedback circuit via the voltage stabilizing current mirror circuit, and the target output voltage generated by the voltage stabilizing conversion feedback circuit remains stable.

7. The low power consumption voltage regulator circuit based on low voltage CMOS process device according to claim 6 is characterized in that: The operational amplifier circuit includes a PMOS tube M56, wherein: The gate terminal and the source terminal of the PMOS tube M56 are adaptively connected to the voltage-stabilizing bias current circuit, the drain terminal of the PMOS tube M56 is connected to the source terminal of the PMOS tube M57 and the source terminal of the PMOS tube M58, the gate terminal of the PMOS tube M57 forms the first input terminal of the operational amplifier circuit, and the gate terminal of the PMOS tube M58 serves as the second input terminal of the operational amplifier circuit; The drain terminal of the PMOS tube M57 is connected to the drain terminal of the NMOS tube M59, the gate terminal of the NMOS tube M59, and the gate terminal of the NMOS tube M60. The drain terminal of the NMOS tube M60 is connected to the drain terminal of the PMOS tube M58. The drain terminal of the NMOS tube M60 and the drain terminal of the PMOS tube M58 are connected to each other to form the output terminal of the operational amplifier circuit. The source terminal of the NMOS tube M59 and the source terminal of the NMOS tube M60 are both grounded.

8. The low power consumption voltage regulator circuit based on low voltage CMOS process device according to claim 6 is characterized in that: The voltage stabilization conversion feedback circuit comprises a plurality of MOS impedance units connected in series, wherein: The serially connected MOS units include at least one MOS impedance unit formed by an NMOS tube group and at least one MOS impedance unit formed by a PMOS tube group; The voltage-stabilizing current mirror circuit is adaptively connected to a MOS impedance unit formed by an NMOS tube group, and outputs a target output voltage through the MOS impedance unit; The voltage stabilizing conversion feedback circuit is connected to the second input terminal of the operational amplifier circuit through a MOS impedance unit formed by a PMOS tube group; When the MOS impedance unit is formed by the NMOS tube group, the NMOS tubes in the NMOS tube group are all configured in a diode connection state to form an NMOS-diode unit, and the NMOS-diode units are connected in series in sequence; When the MOS impedance unit is formed by the PMOS tube group, the PMOS tubes in the PMOS tube group are all configured in a diode connection state to form a PMOS-diode unit, and the PMOS-diode units are connected in series in sequence; The NMOS tubes in the NMOS tube group and the PMOS tubes in the PMOS tube group are both inverse ratio tubes, and both the NMOS tubes and the PMOS tubes are MOS tubes with longer conductive channels.

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