Chip, task processing management method, and computer system
By setting up a power consumption management unit in the chip to receive and latch the core information of the functional unit, the problem of increasing chip power consumption is solved, and the effect of reducing chip power consumption without affecting the normal operation of the functional unit is achieved.
Patent Information
- Application Number
- CN202411140429.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2025-06-20
AI Technical Summary
With the increase in chip integration and the increase in computing power demand, the power consumption of chips is also increasing, resulting in the limitation of chip applications by power supply and heat dissipation capabilities.
A power consumption management unit is set up in the chip to receive core information when the functional unit is in the working state, and latch these information when the functional unit is in the low power state, and transmit the latched information back to the functional unit when the functional unit exits the low power state to configure the core composition structure.
Through this technical solution, the power consumption of the chip can be reduced and static power consumption can be reduced without affecting the normal operation of the functional unit, thereby improving the application capability of the chip.
Smart Images
Figure CN120179052A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present application relate to the field of computer technologies, and particularly to a chip, a task processing management method, and a computer system. Background Art
[0002] With the improvement of chip integration and the continuous increase in computing power requirements, the power consumption of chips is also rising continuously. Due to the limitations of chip power supply capacity and heat dissipation capacity, the power consumption of chips has imposed significant limitations on the applications of chips.
[0003] Therefore, in this context, how to provide technical solutions to reduce the power consumption of chips has become a technical problem that those skilled in the art urgently need to solve. Summary of the Invention
[0004] In view of this, embodiments of the present invention provide a chip, a task processing management method, and a computer system to reduce the power consumption of the chip.
[0005] To achieve the above object, embodiments of the present invention provide the following technical solutions.
[0006] In a first aspect, embodiments of the present invention provide a chip, including:
[0007] A functional unit, including a core component structure, where the core component structure is a structure for enabling the functional unit to work properly;
[0008] A power consumption management unit, configured to at least receive core information transmitted by the functional unit when the functional unit is in a working state, where the core information is information for controlling the functional unit to work properly by the core component structure of the functional unit in the working state;
[0009] The power consumption management unit is further configured to latch the received core information for a first functional unit in a low power consumption state; and to send the latched core information to the first functional unit for configuring the core component structure when the first functional unit exits the low power consumption state.
[0010] In a second aspect, embodiments of the present invention provide a task processing management method, applied to the chip in the first aspect, including:
[0011] When the functional unit of the chip is in a working state, at least receive core information transmitted by the functional unit, where the core information is information for controlling the functional unit to work properly by the core component structure of the functional unit in the working state;
[0012] And, for the first functional unit in the low-power state, latch the received core information; when the first functional unit exits the low-power state, send the latched core information to the first functional unit for configuring the core composition structure.
[0013] In a third aspect, an embodiment of the present invention provides a computer system, including the chip as described in the first aspect.
[0014] A chip provided by an embodiment of the present invention includes: a functional unit including a core composition structure, where the core composition structure is a structure for enabling the functional unit to work properly; a power consumption management unit configured to, when the functional unit is in the working state, at least receive the core information transmitted by the functional unit, where the core information is information for controlling the functional unit to work properly by the core composition structure in the working state; the power consumption management unit is further configured to latch the received core information for the first functional unit in the low-power state; and to send the latched core information to the first functional unit for configuring the core composition structure when the first functional unit exits the low-power state.
[0015] It can be seen that in the technical solution provided by the embodiment of the present invention, a power consumption management unit is provided in the chip to at least receive the core information transmitted by the functional unit when the functional unit is in the working state; and for the first functional unit in the low-power state, latch the core information it receives, and when the first functional unit exits the low-power state, the latched core information can be transmitted to the first functional unit again. Since the core information is information for controlling the functional unit to work properly by the core composition structure in the working state. Therefore, when the first functional unit exits the low-power state, the power consumption management unit transmits the core information to the first functional unit again, so as not to affect the normal operation of the first functional unit. Since in the idle working state of the functional unit, even if there is no task to be processed at this time, the overall power consumption of the chip will increase due to the leakage current of each functional unit. The leakage current of the functional unit is related to the power supply situation of the functional unit. Therefore, in the embodiment of the present invention, latching the core information of the first functional unit in the low-power state using the power consumption management unit can reduce the power consumption of the first functional unit, reduce the power consumption of the chip, and at the same time, does not affect the normal operation of the first functional unit when it exits the low-power state. Description of the Drawings
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.
[0017] Figure 1 is a schematic structural diagram of a chip provided by an embodiment of the present invention;
[0018] Figure 2 is a schematic structural diagram of a SOC chip provided by an embodiment of the present invention;
[0019] Figure 3 is another schematic structural diagram of a chip provided by an embodiment of the present invention;
[0020] Figure 4 is another schematic structural diagram of a chip provided by an embodiment of the present invention;
[0021] Figure 5 is still another schematic structural diagram of a chip provided by an embodiment of the present invention;
[0022] Figure 6 is a schematic structural diagram of cross - power - domain processing provided by an embodiment of the present invention;
[0023] Figure 7 is a schematic design structure diagram of cross - power - domain processing provided by an embodiment of the present invention;
[0024] Figure 8 is a schematic flowchart of a task processing management method of a chip provided by an embodiment of the present invention;
[0025] Figure 9 is another schematic flowchart of a task processing management method provided by an embodiment of the present invention;
[0026] Figure 10 is a schematic structural diagram of a computer system provided by an embodiment of the present invention. Detailed implementation manners
[0027] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0028] The power consumption of a chip includes dynamic power consumption and static power consumption. With the evolution of chip technology, the proportion of static power consumption in the chip power consumption is getting larger and larger. Therefore, it is very necessary to effectively reduce the static power consumption of the chip to reduce the power consumption of the chip.
[0029] Based on this, an embodiment of the present invention provides a chip for reducing the static power consumption of the chip to reduce the power consumption of the chip.
[0030] Please refer toFigure 1 , Figure 1 is a schematic structural diagram of a chip provided by an embodiment of the present invention.
[0031] As Figure 1 described above, the chip 1 provided by the embodiment of the present invention may include:
[0032] A functional unit 11, including a core component structure 111, and the core component structure 111 is a structure for enabling the functional unit 11 to work properly;
[0033] A power consumption management unit 12, configured to at least receive core information transmitted by the functional unit 11 when the functional unit 11 is in a working state, and the core information is information for controlling the functional unit 11 to work properly by the core component structure 111 in the working state;
[0034] The power consumption management unit 12 is further configured to latch the received core information for a first functional unit in a low power consumption state; and is configured to send the latched core information to the first functional unit for configuring the core component structure 111 when the first functional unit exits the low power consumption state.
[0035] The first functional unit in the low power consumption state refers to a functional unit that has completed task processing and is in an idle working state.
[0036] Being in the low power consumption state indicates that the power consumption of the first functional unit is reduced. For example, power supply to the first functional unit can be stopped to make the first functional unit in the low power consumption state.
[0037] The core information is information for controlling the functional unit 11 to work properly by the core component structure 111 in the working state, so as to ensure the correct logic function of the first functional unit, so that when the first functional unit exits the low power consumption state, task processing can be performed accurately without error.
[0038] The functional unit 11 can be designed according to the design requirements of the chip 1, that is, the corresponding logic circuit can be divided and designed according to the logic function that the chip 1 needs to implement in the design requirements, so as to obtain at least one functional unit.
[0039] To facilitate understanding of the layout of the functional units in the chip 1, a SOC (System on Chip) chip is taken as an example for illustration.
[0040] Please refer to Figure 2 , Figure 2 is a schematic structural diagram of a SOC chip provided by an embodiment of the present invention.
[0041] As Figure 2As shown, the SOC chip contains a CPU 15 (Central Processing Unit) and three functional units: functional unit 111, functional unit 112, and functional unit 113. Each functional unit is designed according to the design requirements of the chip. The logic circuits of the functional units can be the same or different. The CPU 15 and all functional units are connected to the bus 16. The CPU 15 manages and configures each functional unit through the bus 16, and each functional unit also performs data reception and transmission through the bus 16 to complete the specified task processing (realization of logical functions).
[0042] In one embodiment, in order to improve the performance of chip 1, some designs further divide the bus 16 into a management bus and a data bus to separately process configuration management information and functional service data information.
[0043] Since the functional unit 11 transmits at least core information to the power management unit 12 when in the working state, when the first functional unit is in the low-power state, the power management unit 12 can timely record the core information transmitted by the first functional unit, so that when the first functional unit exits the low-power state and processes tasks again, the latched core information can be transmitted to the first functional unit, so that the first functional unit can continue to process tasks normally.
[0044] It can be seen that the technical solution provided by the embodiment of the present invention sets a power management unit 12 in chip 1 to at least receive the core information transmitted by the functional unit 11 when the functional unit 11 is in the working state; and for the first functional unit in the low-power state, latch the core information received by it, and when the first functional unit exits the low-power state, the latched core information can be transmitted to the first functional unit again. Since the core information is the information for controlling the normal operation of the functional unit 11 by the core component structure 111 in the working state. Therefore, when the first functional unit exits the low-power state, the power management unit 12 transmits the core information to the first functional unit again, so that the normal operation of the first functional unit can be not affected. It can be seen that in the embodiment of the present invention, since the core information of the first functional unit in the low-power state is latched by the power management unit, the power consumption of the first functional unit (the first functional unit in the low-power state) can be reduced, and the power consumption of the chip can be reduced while not affecting the normal operation of the first functional unit when it exits the low-power state.
[0045] During the design process of Chip 1, at least one functional unit can be designed according to the design requirements to implement the logical functions included in the design requirements. To facilitate accurately latching the core information of the first functional unit in the low-power state, the status of each functional unit can be distinguished. Therefore, in one embodiment, the functional unit 11 may include: a first functional unit in the low-power state and a second functional unit not in the low-power state; the first functional unit, the second functional unit, and the power management unit 12 are located in different power domains.
[0046] Setting the power domains where the first functional unit, the second functional unit, and the power management unit 12 are located as different regions can facilitate independent power control of the first functional unit, the second functional unit, and the power management unit 12, and there will be no mutual influence.
[0047] Please continue to refer to Figure 1 , in one embodiment, the first functional unit is located in the first power domain 13, the power management unit 12 is located in the second power domain 14, and the second functional unit is located in the third power domain 19;
[0048] When the first functional unit is in the low-power state, the first power domain 13 is powered off, and the second power domain 14 and the third power domain 19 remain powered on;
[0049] When the first functional unit exits the low-power state, the first power domain 13 is powered on, and the second power domain 14 and the third power domain 19 remain powered on.
[0050] The first power domain 13 refers to the power domain where the first functional unit in the low-power state is located. The third power domain 19 refers to the power domain where the second functional unit not in the low-power state is located.
[0051] That is to say, the first functional unit is a general term for the functional units in the low-power state, and correspondingly, the first power domain can be a general term for the power domains where the functional units in the low-power state are located.
[0052] The second functional unit is a general term for the functional units not in the low-power state, and correspondingly, the third power domain can be a general term for the power domains where the functional units not in the low-power state are located.
[0053] If the first functional unit is in the low-power state, it indicates that the power consumption of the first functional unit is decreasing at this time, and the change in the power consumption of the functional unit is positively correlated with the power supply situation. Therefore, the first power domain 13 where the first functional unit in the low-power state is located is powered off; correspondingly, when the first functional unit exits the low-power state, the first power domain 13 where it is located is powered on.
[0054] In an embodiment of the present invention, a functional unit that is not in a low-power state is defined as a second functional unit. Therefore, the power domain where the second functional unit is located always remains powered on.
[0055] The power consumption management unit 12 needs to receive at least the core information transmitted by the functional unit in real time, and latch and return the received core information. Therefore, the power consumption management unit 12 is always in a working state, and the second power domain 14 where it is located always remains powered on, that is, the second power domain 14 is a normally-on power domain.
[0056] It should be noted that each functional unit 11 corresponds to a power domain to independently supply power to each functional unit 11 without affecting the respective operations of the functional units 11.
[0057] The power consumption management unit 12 receives at least the core information of the functional unit in real time, and latches and returns the core information it receives. Therefore, when the chip includes at least one functional unit 11, the number of power consumption management units 12 is also multiple, so that each functional unit has a power consumption management unit 12 that can receive the core information transmitted by it.
[0058] In one embodiment, the power consumption management unit 12 can correspond to the functional unit 11 one by one. At this time, the number of power consumption management units 12 is equal to the number of functional units 11, so that when the functional unit is the first functional unit in a low-power state, the power consumption management unit 12 can quickly and accurately latch the core information of the first functional unit, and quickly return the latched core information subsequently.
[0059] It should be noted that during the normal operation of the chip 1, each functional unit 11 transmits at least core information to the corresponding connected power consumption management unit 12 in real time; when the functional unit is the first functional unit in a low-power state at this time, the core information of the first functional unit is latched, which is convenient for returning to the first functional unit when the first functional unit exits the low-power state subsequently, so as to ensure the continuous normal operation of the first functional unit.
[0060] The connection method in which the power consumption management unit 12 corresponds to the functional unit 11 one by one can refer to Figure 3 . Figure 3 It is another structural schematic diagram of the chip provided by the embodiment of the present invention.
[0061] Figure 3 In the shown chip 1, there are 3 functional units: functional unit 111, functional unit 112, functional unit 113, and 3 power consumption management units corresponding to each functional unit: power consumption management unit 121, power consumption management unit 122, power consumption management unit 123; CPU 15, bus 16; among them, each functional unit has a power domain that supplies power to it.
[0062] Taking the functional unit 111 as an example of the first functional unit in the low-power state, the power domain where the functional unit 111 is located is the first power domain 13. After the power consumption management unit 121 latches the core information of the first functional unit (functional unit 111), the first power domain 13 is powered down. At this time, it should be noted that the power domains where the other second functional units that are not in the low-power state are located (all belonging to the aforementioned third power domain) remain powered on. Figure 3 The second functional units in [reference] are: functional unit 112 and functional unit 113. The third power domain includes the power domain where the functional unit 112 is located and the power domain where the functional unit 113 is located.
[0063] Figure 3 As shown, each functional unit has an independent power domain, and the power control switch of each power domain is independent, that is, each power domain has a corresponding power supply. In other embodiments, multiple independent power domains can also be powered by the same power supply. When powered by the same power supply, each power domain is respectively added with a corresponding power gating to achieve independent power-on and power-off for each independent power domain. For example, since the functional unit 111 is in the low-power state and thus can be temporarily not used, the first power domain 13 can be powered down, which can save the static power consumption of the functional unit 111.
[0064] That is to say, the power-on and power-off of the power domain of each functional unit 11 are independent. Thus, when powering down the power domain of one of the functional units 11, it will not affect the power supply of the power domains of other functional units 11.
[0065] Of course, a power consumption management unit 12 can also be connected to multiple functional units 11 at the same time. At this time, the number of power consumption management units 12 is less than the number of functional units 11. For example, a power consumption management unit 12 is connected to 2 functional units at the same time, so as to reduce the number of power consumption management units 12 arranged and save the usage area of the chip 1.
[0066] The structure of a power consumption management unit 12 connected to multiple functional units 11 can refer to Figure 4 , Figure 4 which is another schematic structural diagram of the chip provided by the embodiment of the present invention.
[0067] Figure 4 In the shown chip 1, there are 2 power consumption management units: power consumption management unit 121 and power consumption management unit 122. Taking the power consumption management unit 121 connected to 2 functional units: functional unit 111 and functional unit 112, and the power consumption management unit 122 connected to one functional unit: functional unit 113 as an example, and continuing to take the functional unit 111 as the first functional unit and the power domain where the functional unit 111 is located as the first power domain 13 for display.
[0068] As shown Figure 4 in FIG. 1, the power consumption management unit 121 may include a logic circuit jointly used by the functional unit 111 and the functional unit 112. Therefore, in some embodiments, a single power consumption management unit may be connected to multiple functional units.
[0069] To facilitate the management of power-on and power-off of the first power supply domain 13 where the first functional unit is located, in one implementation, the power consumption management unit 12 is further configured to generate a first power-off signal when it detects that the functional unit is the first functional unit in a low power consumption state, so that the power supply domain where the first functional unit is located is powered off based on the first power-off signal;
[0070] The chip 1 may further include:
[0071] A first power-on signal sending module, configured to determine whether the first functional unit is included among the functional units used when the chip 1 processes tasks. If so, a first power-on signal is sent to the power consumption management unit 12 connected to the first functional unit, so that the power supply domain where the first functional unit is located is powered on based on the first power-on signal.
[0072] Since the chip 1 processes different tasks, different tasks use different functional units. Therefore, the first power-on signal sending module can determine whether the first functional unit is used among the various functional units used by the chip 1 when processing tasks, so as to clarify whether the first functional unit needs to exit the low power consumption state to process tasks again.
[0073] If it is determined that the first functional unit is included among the used functional units, it means that the first functional unit needs to exit the low power consumption state to process tasks again. Then, the power supply domain (the first power supply domain) where the first functional unit is located is powered on based on the first power-on signal to supply power to the first functional unit; ensuring that the first functional unit can receive core information and process tasks again.
[0074] Since the functional unit 11 can transmit at least core information to the corresponding connected power consumption management unit 12 in real time, the power consumption management unit 12 can determine whether the functional unit 11 has completed task processing and is in a low power consumption state based on the core information received in real time.
[0075] To enhance the flexibility of power-on and power-off management of the first power supply domain 13 of the first functional unit, in one implementation, in addition to the method of combining the chip 1 by the power consumption management unit 12 to control the power-on and power-off of the power supply domain where the first functional unit is located, the power-on and power-off of the power supply domain where the first functional unit is located can also be implemented only by the chip 1 itself. At this time, the chip 1 may further include:
[0076] The first power domain control module is configured to determine whether the first functional unit is included in the functional units used when the chip processes tasks. If so, it sends a second power-on signal to the power consumption management unit connected to the first functional unit, so that the power domain where the first functional unit is located is powered on based on the second power-on signal. Or, when it is determined that the first functional unit has completed task processing, it generates a second power-off signal, so that the power domain where the first functional unit is located is powered off based on the second power-off signal.
[0077] Designing the functional module that controls the power-on and power-off of the power domain where the first functional unit is located independently of the power consumption management unit 12 can simplify the design of the power consumption management unit 12 and ensure the stability of the operation of the power consumption management unit 12.
[0078] Please refer to Figure 5 , Figure 5 which is another schematic structural diagram of the chip provided by the embodiment of the present invention.
[0079] As Figure 5 described, in order to facilitate the first functional unit to exit the low power consumption state and quickly complete task processing when performing tasks again, in one embodiment, the functional unit 11 may further include a non-core component structure 112; the power consumption management unit 12 is configured to at least receive core information transmitted by the functional unit 11 when the functional unit 11 is in the working state, including:
[0080] Receiving core information and non-core information transmitted by the functional unit, where the non-core information is information generated during the normal operation of the functional unit during the working state by the non-core component structure.
[0081] Since the functional unit 11 is designed based on the design requirements of the chip 1, each functional unit 11 has a corresponding logical function that can be realized. When the chip 1 processes different tasks, due to the differences in tasks, the combination of logical functions used to complete the tasks is also different, and thus the functional units 11 used are also different. Therefore, in order to ensure that the basic logical function of the first functional unit remains unchanged when performing tasks again, the core information can be latched. The non-core information can be information of intermediate variables (intermediate information) generated by the functional unit during the execution of tasks (during normal operation).
[0082] For example, if the basic logic function of a functional unit is a logic circuit that executes x*y+z=m, then the functional unit may include an input component structure A that receives the input (x*y+z) and a final output component structure B(m) that stores the final output result. The core information may be the information of the input component structure A and the final output component structure B. The input hardware structure A and the final output component structure B are the core component structures 111 described above.
[0083] A component structure for storing intermediate variables, such as an intermediate component structure C that stores the result of x*y. The intermediate component structure C is a non-core component structure 112. The information of the non-core component structure is non-core information, that is, whether or not this non-core information is transmitted will not affect the normal use of the functional unit.
[0084] Of course, the above is only an example to explain the component structures corresponding to the core information and the non-core information. In actual use, the core component structure and the non-core component structure can be determined according to the specific logic function of the functional unit.
[0085] The transmission of non-core information can cause a first functional unit in a low-power state to exit the low-power state so as to speed up the execution of the tasks of the first functional unit when performing tasks again.
[0086] In one embodiment, the power management unit 12 may include a management register, and the management register is used to latch the received core information and non-core information for a first functional unit in a low-power state.
[0087] A management register (Management Register) may refer to a register used to store management information in a computer system or network device. These registers can be accessed by system software or management tools for monitoring, configuring, or controlling the behavior of hardware devices.
[0088] During the chip design process, in order to ensure the stability and security of the chip and at the same time provide a clear and consistent interface for software engineers to develop application programs, hardware designers can design the component structures in the functional unit 11 as: component structures recognizable by software and component structures unrecognizable by software.
[0089] Therefore, please continue to refer to Figure 5 In one embodiment, the core component structure 111 includes a recognizable core component structure 111a and an unrecognizable core component structure 111b, and the non-core component structure 112 includes a recognizable non-core component structure 112a and an unrecognizable non-core component structure 112b;
[0090] The core information includes: the recognizable core information that controls the normal operation of the functional unit 11 when the recognizable core component structure 111a is in the working state, and the unrecognizable core information that controls the normal operation of the functional unit when the unrecognizable core component structure 111b is in the working state;
[0091] The non-core information includes: the recognizable non-core information generated during the normal operation of the functional unit 11 when the recognizable non-core component structure 112a is in the working state, and the unrecognizable non-core information generated during the normal operation of the functional unit 11 when the unrecognizable non-core component structure 112b is in the working state.
[0092] Both the recognizable non-core information and the unrecognizable non-core information are intermediate information generated during the normal operation of the functional unit.
[0093] In order to enable the power consumption management unit 12 to easily receive and latch information of different component structures, in one embodiment, the management register may include: a first management register, a second management register, a third management register, and a fourth management register;
[0094] The first management register is used to latch the recognizable core information of the recognizable core component structure received for the first functional unit in the low power consumption state;
[0095] The second management register is used to latch the recognizable non-core information of the recognizable non-core component structure received for the first functional unit in the low power consumption state;
[0096] The third management register is used to latch the unrecognizable core information of the unrecognizable core component structure received for the first functional unit in the low power consumption state;
[0097] The fourth management register is used to latch the unrecognizable non-core information of the unrecognizable non-core component structure received for the first functional unit in the low power consumption state.
[0098] When the power consumption management unit 12 includes a management register, the number of management registers can be set according to the division of the component structure in the functional unit 11, so as to accurately receive and latch the information of each type of component structure.
[0099] In one embodiment, the recognizable core component structure 111a is a core configuration register, and the unrecognizable core component structure 111b is a core state machine; the recognizable core information is core configuration information, and the unrecognizable core information is core state information;
[0100] The power consumption management unit 12 is further configured to latch the received core information for the first functional unit in the low power state, including:
[0101] For the first functional unit in the low power state, latch the core configuration information of the core configuration register and the core state information of the core state machine received.
[0102] When the recognizable core component structure 111a is a core configuration register, the recognizable core information of the core configuration register can be expressed as: the current working state of the functional unit and the current key parameter configuration of the core configuration register. To ensure the normal operation of the functional unit, it is necessary to ensure that the configuration of the core configuration register remains unchanged.
[0103] Correspondingly, the state information that does not affect the normal operation of the functional unit 11 is recognizable non-core information, and the corresponding hardware structure is the recognizable non-core component structure 112a, such as input / output devices.
[0104] For example, when the first functional unit in the low power state is a PCIe controller at this time, the core configuration register can be a protocol configuration space register, and the recognizable core information transmitted can be the parameters in the protocol configuration space register (including the current working state and protocol configuration information, etc.) and the key parameter configuration.
[0105] The unrecognizable core component structure 111b can be, for example, a core state machine included inside the functional unit, and the unrecognizable core information can be: the core state information (state identifier) of the core state machine.
[0106] In the embodiments of the present invention, when the functional unit is in the low power state (i.e., the first functional unit), the state identifier that has the possibility of not being able to restore the reset initial value and affects the functional correctness of the functional unit is defined as core information, and the remaining state identifiers are defined as non-core information.
[0107] Among the components that cannot be recognized by software, the state identifier that does not affect the normal operation of the functional unit is unrecognizable non-core information, and the corresponding component structure is the unrecognizable non-core component structure 112b, such as some internal flip-flops or combinational logic of the functional unit.
[0108] Non-core information of the non-core component structure: the unrecognizable non-core information of the unrecognizable non-core component structure 112b and the recognizable non-core information of the recognizable non-core component structure 112a, the loss or restoration of the reset initial value of which does not affect the normal operation of the functional unit.
[0109] Please continue to refer to Figure 5, to meet the overall working requirements of the chip 1, in one implementation, the chip 1 may further include: a processor 15; the power consumption management unit 12 may also be used to, when determining that the chip 1 is powered on and starts up, based on the access address allocated to the chip 1, allocate the initial value of the recognizable core information to the recognizable core component structure 111a of the connected functional unit 11, and allocate the initial value of the recognizable non-core information to the recognizable non-core component structure 112a of the connected functional unit 11;
[0110] and, when determining that the chip 1 is powered on and starts up, allocate the initial value of the predefined unrecognizable core information to the unrecognizable core component structure 111b of the connected functional unit 11, and allocate the initial value of the predefined unrecognizable non-core information to the unrecognizable non-core component structure 112b of the connected functional unit 11;
[0111] wherein, the power domain where the processor 15 is located is the same as the power domain where the power consumption management unit 12 is located.
[0112] As Figure 5 shown, the processor 15 and the power consumption management unit 12 are in the same second power domain 14, and the second power domain 14 is a normally-on power domain, that is, during the entire working process of the chip 1, it always remains powered on.
[0113] The power consumption management unit 12 is in a working state when the chip 1 completes power-on startup and starts to process tasks, and real-time receives the core information and non-core information transmitted by at least one connected functional unit 11. When one of the functional units 11 is in a low-power state, that is, the first functional unit, the core information and non-core information transmitted by the first functional unit are synchronously latched. When the first functional unit exits the low-power state and resumes task processing, the latched core information and non-core information are transmitted to the first functional unit.
[0114] The component structure of the functional unit 11 includes a recognizable core component structure 111a and a recognizable non-core component structure 112a. Therefore, the recognizable initial values (the initial value of the recognizable core information and the initial value of the recognizable non-core information) can be transmitted to the functional unit 11 by using the access address allocated to the power consumption management unit 12 in the chip 1 to complete the initialization of the recognizable core component structure 111a and the recognizable non-core component structure 112a.
[0115] The unrecognizable core component structure 111b and the unrecognizable non-core component structure 112b in the functional unit 11 cannot be accessed and configured by the chip 1. Therefore, no access address needs to be allocated in the power management unit 12. At this time, based on the predefined unrecognizable initial values: the initial value of the unrecognizable core information and the initial value of the unrecognizable non-core information, the power management unit 12 can directly perform the transmission.
[0116] When designing the chip 1, the chip 1 can be divided into multiple power domains according to the design requirements of the chip 1 (as Figure 1 shown), and each power domain can be independently powered. The CPU 15, the bus 16, and the power management unit 12 are in the same always-on power domain: the second power domain 14. Therefore, when information is transmitted between the functional unit 11 and the power management unit 12, it is a cross-power-domain transmission between different power domains, and cross-power-domain processing needs to be performed at this time.
[0117] For the convenience of understanding the implementation of cross-power-domain processing under multiple power domains, Figure 6 is a schematic structural diagram of cross-power-domain processing provided by an embodiment of the present invention.
[0118] For example Figure 6 shown, the SOC chip is divided into 4 power domains. Among them, the CPU 15 and the bus 16 use the second power domain 14 (the second power domain 14 is an always-on power domain), and the functional units 111, 112, and 113 all use independent power domains. When signal transmission is performed, the interconnection signals between each functional unit and the bus 16 all need to perform cross-power-domain processing. When the functional unit is not in use, the corresponding power domain can be powered down to reduce power consumption. For example, when the functional unit 111 is not in use temporarily (at this time, it is the first functional unit in the low-power state), the power domain corresponding to the functional unit 111 (the first power domain) can be powered down, which can save the static power consumption of the functional unit 111.
[0119] Therefore, in the embodiment of the present invention, in order to reduce the static power consumption of the functional unit, a design of cross-power-domain processing is carried out in the chip design.
[0120] Please refer to Figure 7 , Figure 7 is a schematic design structure diagram of cross-power-domain processing provided by an embodiment of the present invention.
[0121] As Figure 7 shown, the chip 1 may further include: at least one set of sideband signal groups 17 for connecting the power management unit 12 and the functional unit 11; a cross-power-domain processing module 18 for performing cross-power-domain processing when information is transmitted between the functional unit 11 and the power management unit 12;
[0122] The cross - power - domain processing module 18 includes: at least one level - conversion unit 181 and at least one isolation unit 182;
[0123] When the information transmission direction of the side - band signal group 17 is from the power - consumption management unit 12 to the functional unit 11, if the voltage of the power domain where the power - consumption management unit 12 is located is different from the voltage of the power domain where the functional unit 11 is located, the level - conversion unit 181 performs cross - power - domain processing on the voltage of the power domain where the functional unit 11 is located; otherwise, no cross - power - domain processing is performed.
[0124] When the information transmission direction of the side - band signal group 17 is from the functional unit 11 to the power - consumption management unit 12, if the voltage of the power domain where the power - consumption management unit 12 is located is different from the voltage of the power domain where the functional unit 11 is located, the isolation unit 182 and the level - conversion unit 181 perform cross - power - domain processing on the voltage of the power domain where the functional unit 11 is located; otherwise, the isolation unit 182 performs cross - power - domain processing on the voltage of the power domain where the functional unit 11 is located.
[0125] Figure 7 The shown side - band signal group 17 may refer to a group of lines for transmitting information (core information, non - core information) between the functional unit 11 and the power - consumption management unit 12.
[0126] Such as Figure 7 As shown, the second power domain 14 where the power - consumption management unit 12 is located belongs to a normally - on power domain, and the power domain where the functional unit 11 is located can be adjusted in real time according to the working state of the functional unit 11. Figure 7 Taking the power - consumption management unit 12 including a management register as an example for display.
[0127] When the information is transmitted from the power - consumption management unit 12 to the functional unit 11, that is, in the side - band signal group 17, on one side - band signal sent from the second power domain 14 to the power domain where the functional unit 11 is located, if the voltages of the two power domains are different, the level - conversion unit 181 (levelshift unit) is used for cross - power - domain processing. If the voltages of the two power domains are the same, no processing is required.
[0128] When the information is transmitted from the functional unit 11 to the power - consumption management unit 12, that is, in the side - band signal group 17, on one side - band signal sent from the power domain where the functional unit 11 is located to the second power domain 14, if the voltages of the two power domains are different, the isolation unit 182 (isolation unit) and the levelshift unit are used for cross - power - domain processing. If the voltages of the two power domains are the same, only the isolation unit is used for cross - power - domain processing.
[0129] In one embodiment, the chip 1 may further include:
[0130] A chip power control module;
[0131] The chip power control module is configured to send a chip power-on signal when it is determined that the chip 1 is performing task processing, so that the power consumption management unit 12 is initialized based on the chip power-on signal, or send a chip power-off signal when it is determined that the chip 1 has completed task processing, so that the chip 1 is powered off.
[0132] The chip power control module can control the power-on and power-off of the chip according to the usage of the chip.
[0133] To fully illustrate that the chip provided by the embodiments of the present invention can reduce the static power consumption of functional units to reduce the power consumption of the chip, continue to use the Figure 3 shown structure as an example to demonstrate the use of the chip.
[0134] As Figure 3 shown, the chip 1 includes: a CPU 15, functional units 111, 112, 113, power consumption management units 121, 122, 123 respectively connected to each functional unit, a bus 16, and a cross-power domain processing module 18. The functional units 111, 112, 113 all have independent power domains, and other designs are all in the second power domain 14.
[0135] Among them, when it is determined that a certain functional unit is the first functional unit in the low power consumption state, the corresponding power consumption management unit 12 is used to latch the core information and non-core information transmitted by it. At this time, the power domain where the first functional unit is located is the first power domain 13.
[0136] The CPU 15, each power consumption management unit 12, and each functional unit 11 are all interconnected with the bus 16. Each functional unit 11 corresponds to a power consumption management unit 12.
[0137] Each pair of the functional unit 11 and the power consumption management unit 12 is connected by a group of sideband signal groups 17. Each group of sideband signal groups 17 includes:
[0138] A sideband signal with the power consumption management unit 12 as the source end and the functional unit 11 as the destination end, transmitting the initialization configuration sent by the power consumption management unit 12 to the functional unit 11: the initial value of the recognizable core information and the initial value of the recognizable non-core information, and the predefined status information: the initial value of the unrecognizable core information and the initial value of the unrecognizable non-core information.
[0139] A sideband signal with the functional unit 11 as the source end and the power consumption management unit 12 as the destination end transmits the current configuration sent by the functional unit 11 to the power consumption management unit 12: recognizable core information and recognizable non-core information, and the current status information: unrecognizable core information and unrecognizable non-core information, for the power consumption management unit 12 to latch when the functional unit 11 is the first functional unit in the low power state.
[0140] It should be noted that only when the chip 1 completes power-on startup and each functional unit 11 is in a normal working state, the power consumption management unit 12 will determine the task processing situation of the functional unit 11 in real time to latch the current configuration and current status information.
[0141] Of course, the bus signals interconnected between each functional unit 11 and the bus 16 and the sideband signals interconnected with the corresponding power consumption management unit 12 are also designed across power domains. For example, it is set that the core composition structure of the functional unit 111 includes: 40 8-bit core configuration registers (recognizable core composition structure) and 8 8-bit core state machines (unrecognizable core composition structure).
[0142] Here, the case where the functional unit 111 only transmits core information is taken as an example for illustration.
[0143] To store the core information, the power consumption management unit 121 is designed with a total of 48 8-bit management registers, which correspond one-to-one with the aforementioned core configuration registers and core state machines, and the first 40 management registers are assigned unique access addresses. The functional unit 112 has 20 8-bit core configuration registers, and the functional unit 113 has 10 8-bit core state machines. The corresponding power consumption management unit design is similar and will not be elaborated here.
[0144] Here, taking the functional unit 111 corresponding to the power consumption management unit 121 as the first functional unit in the low power state as an example, the chip power-on and power-off processes and the processes of the functional unit 111 entering and exiting the low power state (the power-on and power-off processes of the functional unit 111) are described.
[0145] The chip power-on process includes:
[0146] 1. The second power domain is powered on;
[0147] 2. Chip reset release: The CPU 15 and the power consumption management unit 121 are reset and released, and the functional unit 111 is in the reset state;
[0148] 3. The CPU 15 configures the first 40 management registers of the power consumption management unit 121 (the other 8 management registers use the predefined initial state identifier as the reset value);
[0149] 4. The power domain of the functional unit 111 is powered on;
[0150] 5. The function unit 111 is reset and released. The 40 core configuration registers and 8 core state machines use the signal output by the power management unit 121 as the initial value, and other non-core configuration registers and non-core state machines use the reset value when the chip 1 is powered on and started.
[0151] 6. The function unit 111 enters the normal working state.
[0152] The chip power-down process includes:
[0153] 1. The function unit 111 and the chip 1 finish processing tasks and enter the idle state.
[0154] 2. Reset the function unit 111.
[0155] 3. Power down the power domain where the function unit 111 is located.
[0156] 4. Reset the chip.
[0157] 5. Power down the second power domain 14.
[0158] The process for the function unit 111 to be in the low-power state includes:
[0159] 1. The function unit 111 finishes processing tasks and enters the idle state. At this time, it is the first function unit.
[0160] 2. The power management unit 121 latches the core information transmitted by the first function unit.
[0161] 3. Reset the function unit 111.
[0162] 4. Power down the power domain where the function unit 111 is located (which is called the first power domain 13 at this time).
[0163] The process for the function unit 111 to exit the low-power state includes:
[0164] 1. Power on the first power domain 13.
[0165] 2. Release the reset of the function unit 111. The 40 core configuration registers and 8 core state machines use the signal (core information) latched and sent by the power management unit 121 as the initial value for working again, and other non-core configuration registers and non-core state machines use the reset value transmitted by the chip received when the function unit 111 is powered on again.
[0166] 3. The function unit 111 restores the core information before entering the low-power state and can work normally.
[0167] The embodiment of the present invention also provides a task processing management method for a chip, which is used to be implemented on the chip described in any one of the foregoing embodiments to reduce the power consumption of the chip.
[0168] Please refer to Figure 8 , Figure 8 which is a schematic flowchart of a task processing management method for a chip provided by an embodiment of the present invention.
[0169] As Figure 8 shown, the process may include the following steps:
[0170] Step S100, when the functional unit of the chip is in a working state, at least receive core information transmitted by the functional unit.
[0171] The core information is information that controls the normal operation of the functional unit in the working state of the core composition structure of the functional unit.
[0172] Latch at least the core information so that when the first functional unit exits the low-power state and processes tasks again, task processing can continue based on the reacquired latched core information.
[0173] Step S101, latch the received core information for the first functional unit in the low-power state; when the first functional unit exits the low-power state, send the latched core information to the first functional unit for configuring the core composition structure.
[0174] It can be seen that in the technical solution provided by the embodiment of the present invention, a power consumption management unit is provided in the chip to at least receive core information transmitted by the functional unit when the functional unit is in a working state; and for the first functional unit in the low-power state, latch the received core information, and when the first functional unit exits the low-power state, the latched core information can be transmitted to the first functional unit again. Since the core information is information that controls the normal operation of the functional unit in the working state of the core composition structure. Therefore, when the first functional unit exits the low-power state, the power consumption management unit transmits the core information to the first functional unit again, so that the normal operation of the first functional unit can be not affected. It can be seen that in the embodiment of the present invention, since the core information of the first functional unit in the low-power state is latched by using the power consumption management unit, the power consumption of the first functional unit (the first functional unit in the low-power state) can be reduced while reducing the power consumption of the chip, and the normal operation of the first functional unit when it exits the low-power state is not affected.
[0175] Please refer to Figure 9 , Figure 9 which is another schematic flowchart of the task processing management method provided by the embodiment of the present invention.
[0176] As Figure 9 shown, the task processing management method may include:
[0177] Step S201: Receive the core information and non-core information transmitted by the functional unit.
[0178] The non-core information is the information generated during the normal operation of the functional unit in the working state of the non-core component structure.
[0179] The non-core information is the intermediate information formed based on the logic of the corresponding task being processed during the normal operation of the functional unit, and the non-core information in different task processing procedures is different.
[0180] In one implementation, the core component structure includes an identifiable core component structure and an unidentifiable core component structure, and the non-core component structure includes an identifiable non-core component structure and an unidentifiable non-core component structure;
[0181] The core information includes: the identifiable core information that controls the normal operation of the functional unit in the working state of the identifiable core component structure, and the unidentifiable core information that controls the normal operation of the functional unit in the working state of the unidentifiable core component structure;
[0182] The non-core information includes: the identifiable non-core information generated during the normal operation of the functional unit in the working state of the identifiable non-core component structure, and the unidentifiable non-core information generated during the normal operation of the functional unit in the working state of the unidentifiable non-core component structure.
[0183] Please continue to refer to Figure 9 , the method further includes:
[0184] Step S2001: When it is determined that the chip is powered on and started, based on the access address allocated by the chip, allocate the initial value of the identifiable core information to the identifiable core component structure of the connected functional unit, and allocate the initial value of the identifiable non-core information to the identifiable non-core component structure of the connected functional unit.
[0185] Step S2002: When it is determined that the chip is powered on and started, allocate the initial value of the predefined unidentifiable core information to the unidentifiable core component structure of the connected functional unit, and allocate the initial value of the predefined unidentifiable non-core information to the unidentifiable non-core component structure of the connected functional unit;
[0186] Wherein, the power domain where the processor is located is the same as the power domain where the power consumption management unit is located.
[0187] Step S202: Latch the core information and non-core information transmitted by the first functional unit in the low-power state, and power down the first power domain.
[0188] Step S203: When the first functional unit exits the low-power state, the first power domain is powered on so that the first functional unit receives the core information and non-core information.
[0189] Step S204: When it is determined that the first functional unit exits the low-power state, the latched core information and non-core information are transmitted to the first functional unit.
[0190] An embodiment of the present invention also provides a computer system. Please refer to Figure 10 , Figure 10 which is a schematic structural diagram of the computer system provided by the embodiment of the present invention.
[0191] As Figure 10 shown, the computer system includes the chip 1 as described in any of the foregoing embodiments.
[0192] It can be seen that in the technical solution provided by the embodiment of the present invention, a power consumption management unit is provided in the chip 1 to at least receive the core information transmitted by the functional unit when the functional unit is in the working state; and for the first functional unit in the low-power state, the core information received by it is latched, and when the first functional unit exits the low-power state, the latched core information can be transmitted to the first functional unit again. Since the core information is the information for controlling the normal operation of the functional unit when the core component structure is in the working state. Therefore, when the first functional unit exits the low-power state, the power consumption management unit transmits the core information to the first functional unit again, so that the normal operation of the first functional unit can be not affected. Since the functional unit is in the idle working state, even if there is no task to be processed at this time, the overall power consumption of the chip will increase due to the leakage current of each functional unit. The leakage current of the functional unit is related to the power supply situation of the functional unit. Therefore, in the embodiment of the present invention, the core information of the first functional unit in the low-power state is latched by using the power consumption management unit, which can reduce the power consumption of the first functional unit, reduce the power consumption of the chip, and at the same time, does not affect the normal operation of the first functional unit when it exits the low-power state.
[0193] The above describes multiple embodiment solutions provided by the embodiments of the present invention. Each optional manner introduced in each embodiment solution can be combined and cross-referenced with each other without conflict, so as to extend a variety of possible embodiment solutions, and these can all be regarded as the embodiment solutions disclosed and made public by the embodiments of the present invention.
[0194] Although the embodiments of the present invention are disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A chip, characterized in that: include: The functional unit includes a core component structure, wherein the core component structure is a structure that enables the functional unit to work normally; A power consumption management unit, configured to at least receive core information transmitted by the functional unit when the functional unit is in a working state, wherein the core information is information for controlling the normal operation of the functional unit by the core component structure in the working state; The power management unit is also used to latch the received core information for the first functional unit in a low power consumption state; And for sending the latched core information to the first functional unit for configuring the core component structure when the first functional unit exits the low power consumption state.
2. The chip according to claim 1, characterized in that: The functional units include: a first functional unit in a low power consumption state, and a second functional unit that is not in a low power consumption state; the first functional unit, the second functional unit, and the power consumption management unit are located in different power domains.
3. The chip according to claim 2, characterized in that: The first functional unit is located in a first power domain, the power consumption management unit is located in a second power domain, and the second functional unit is located in a third power domain; When the first functional unit is in a low power consumption state, the first power domain is powered off, and the second power domain and the third power domain remain powered on; When the first functional unit exits the low power consumption state, the first power domain is powered on, and the second power domain and the third power domain remain powered on.
4. The chip according to any one of claims 1 to 3, characterized in that: The functional unit also includes a non-core component structure; the power consumption management unit is used to receive at least the core information transmitted by the functional unit when the functional unit is in a working state, including: The core information and non-core information transmitted by the functional unit are received, wherein the non-core information is information generated during the normal working process of the functional unit when the non-core component structure is in the working state.
5. The chip according to claim 4, characterized in that: The power consumption management unit comprises a management register, and the management register is used for latching the received core information and non-core information for the first functional unit in the low power consumption state.
6. The chip according to claim 5, characterized in that: The core component structure includes an identifiable core component structure and an unidentifiable core component structure, and the non-core component structure includes an identifiable non-core component structure and an unidentifiable non-core component structure; The core information includes: the identifiable core information of the identifiable core component structure controlling the normal operation of the functional unit in the working state, and the unidentifiable core information of the unidentifiable core component structure controlling the normal operation of the functional unit in the working state; The non-core information includes: the identifiable non-core information generated by the identifiable non-core component structure when the functional unit is in the working state and the unidentifiable non-core information generated by the unidentifiable non-core component structure when the functional unit is in the working state and the unidentifiable non-core information generated by the unidentifiable non-core component structure when the functional unit is in the working state.
7. The chip according to claim 6, characterized in that: The management registers include: a first management register, a second management register, a third management register and a fourth management register; The first management register is used to latch the received identifiable core information of the identifiable core component structure for the first functional unit in the low power consumption state; The second management register is used to latch the received identifiable non-core information of the identifiable non-core component structure for the first functional unit in the low power consumption state; The third management register is used to latch the received unrecognizable core information of the unrecognizable core component structure for the first functional unit in the low power consumption state; The fourth management register is used to latch the received unrecognizable non-core information of the unrecognizable non-core component structure for the first functional unit in the low power consumption state.
8. The chip according to claim 7, characterized in that: The identifiable core component structure is a core configuration register, and the unidentifiable core component structure is a core state machine; the identifiable core information is core configuration information, and the unidentifiable core information is core state information; The power management unit is also used for latching received core information for the first functional unit in a low power consumption state, including: For the first functional unit in the low power consumption state, the received core configuration information of the core configuration register and the core state information of the core state machine are latched.
9. The chip according to claim 8, characterized in that Also includes: processor; The power management unit is further used to allocate the initial value of the identifiable core information to the identifiable core component structure of the connected functional unit and allocate the initial value of the identifiable non-core information to the identifiable non-core component structure of the connected functional unit based on the access address allocated by the chip when determining that the chip is powered on; and, when determining that the chip is powered on, allocating the initial value of the predefined unrecognizable core information to the unrecognizable core component structure of the connected functional unit, and allocating the initial value of the predefined unrecognizable non-core information to the unrecognizable non-core component structure of the connected functional unit; The power domain where the processor is located is the same as the power domain where the power consumption management unit is located.
10. The chip according to claim 9, characterized in that: Also includes: Chip power control module; The chip power control module is used to send a chip power signal when it is determined that the chip is performing task processing, so that the power consumption management unit is initialized based on the chip power signal. Or, when it is determined that the chip has completed task processing, a chip power-off signal is sent to power off the chip.
11. The chip according to claim 10, characterized in that: The power consumption management unit is further configured to generate a first power-off signal when detecting that the functional unit is a first functional unit in a low power consumption state, so that the power domain where the first functional unit is located is powered off based on the first power-off signal; The chip further comprises: The first power-on signal sending module is used to determine whether the first functional unit is included in the functional units used by the chip when performing task processing. If so, send a first power-on signal to the power consumption management unit corresponding to the first functional unit, so that the power domain where the first functional unit is located is powered on based on the first power-on signal.
12. The chip according to claim 10, characterized in that: Also includes: a first power domain control module, configured to determine whether the first functional unit is included in the functional units used by the chip when performing task processing, and if so, to send a second power-on signal to a power consumption management unit connected to the first functional unit so that the power domain where the first functional unit is located is powered on based on the second power-on signal; Or, when it is determined that the first functional unit completes task processing, a second power-off signal is generated to power off the power domain where the first functional unit is located based on the second power-off signal.
13. The chip according to claim 10, characterized in that: Also includes: At least one sideband signal group, used to connect the power management unit and the functional unit; A cross-power domain processing module, used for performing cross-power domain processing when information is transmitted between the functional unit and the power consumption management unit; The cross-power domain processing module includes at least one level conversion unit and at least one isolation unit; The information transmission direction of the sideband signal group is: when the information is transmitted from the power management unit to the functional unit, if the voltage of the power domain where the power management unit is located is different from the voltage of the power domain where the functional unit is located, the level conversion unit performs cross-power domain processing on the voltage of the power domain where the functional unit is located; Otherwise, no cross-power domain processing is performed; The information transmission direction of the sideband signal group is: when transmitted from the functional unit to the power consumption management unit, if the voltage of the power domain in which the power consumption management unit is located is different from the voltage of the power domain in which the functional unit is located, the isolation unit and the level conversion unit perform cross-power domain processing on the voltage of the power domain in which the functional unit is located; otherwise, the isolation unit performs cross-power domain processing on the voltage of the power domain in which the functional unit is located.
14. A task processing management method, characterized in that: A chip according to any one of claims 1 to 13, comprising: When the functional unit of the chip is in a working state, at least core information transmitted by the functional unit is received, wherein the core information is information of the core component structure of the functional unit in the working state, which controls the normal operation of the functional unit; And, for a first functional unit in a low power consumption state, latching the received core information; when the first functional unit exits the low power consumption state, sending the latched core information to the first functional unit for configuring the core component structure.
15. The task processing management method according to claim 14, characterized in that: When the functional unit is in a working state, at least receiving core information transmitted by the functional unit includes: The core information and non-core information transmitted by the functional unit are received, wherein the non-core information is information generated during the normal working process of the functional unit when the non-core component structure is in the working state.
16. The task processing management method according to claim 15, characterized in that: The core component structure includes an identifiable core component structure and an unidentifiable core component structure, and the non-core component structure includes an identifiable non-core component structure and an unidentifiable non-core component structure; The core information includes: the identifiable core information of the identifiable core component structure controlling the normal operation of the functional unit in the working state, and the unidentifiable core information of the unidentifiable core component structure controlling the normal operation of the functional unit in the working state; The non-core information includes: the identifiable non-core information generated by the identifiable non-core component structure when the functional unit is in the working state and the unidentifiable non-core information generated by the unidentifiable non-core component structure when the functional unit is in the working state and the unidentifiable non-core information generated by the unidentifiable non-core component structure when the functional unit is in the working state.
17. The task processing management method according to claim 16, characterized in that: The receiving the core information and non-core information transmitted by the functional unit includes: The first functional unit in the low power consumption state latches the received identifiable core information, identifiable non-core information, unidentifiable core information and unidentifiable non-core information.
18. A computer system, characterized in that: Comprising a chip as described in any one of claims 1-13.