A low-power FIFO module

Abstract

The present invention discloses a low-power FIFO module, which includes a FIFO memory and a FIFO controller. The FIFO memory includes a write unit, a storage unit, and a multiplexer. The FIFO controller includes a write pointer register, a read pointer register, a first adder and a second adder. The FIFO controller further includes a mux selection register and a third adder. The third adder increments the mux selection pointer signal output by the mux selection register by 1 only when there is valid data cached in the storage unit or when a new valid data is about to be cached while the storage unit outputs the last valid data, so that the multiplexer selects and outputs the data at the corresponding address from the storage unit according to the mux selection pointer signal when the read signal is high. The present invention solves the problem of invalid flips caused by outputting invalid data, thereby reducing power consumption.

Description

Technical Field

[0001] The present invention relates to a FIFO module within a chip, particularly a FIFO module with low power consumption characteristics. Background Art

[0002] A common FIFO module within a chip involves a first-in-first-out (FIFO) data storage and buffering mechanism, which is often used to cache data. For example Figure 1 , a traditional FIFO module 50 includes a FIFO memory 10 and a FIFO controller 20 for controlling the FIFO memory 10. Input data data_in (binary data) is input and cached from one end of the FIFO memory 10, and then output as output data data_out from the other end under the control of the FIFO controller 20. As the name implies, the data that enters the FIFO first will be output first. When the FIFO memory 10 is not full and the write signal push is high, the FIFO controller 20 outputs a write pointer signal wr_ptr to the FIFO memory 10 to store the input data data_in into the FIFO memory 10. When the FIFO memory 10 is not empty and the read signal pop is high, the FIFO controller 20 outputs a read pointer signal rd_ptr to the FIFO memory 10, and reads out the corresponding output data data_out from the FIFO memory 10 according to the read pointer signal rd_ptr for output.

[0003] Furthermore, as Figure 2 , Figure 2Taking a depth of 4 as an example, the configuration of the FIFO memory 10 is shown. The FIFO memory 10 includes a write unit 11, a storage unit 12, and a multiplexer 13. The write unit 11 receives an input data data_in, a write signal push, and a write pointer signal wr_ptr. When the write signal push is high, the input data data_in is cached at the corresponding address in the storage unit 12 according to the write pointer signal wr_ptr output by the write pointer register 21. Then, the write pointer register 21 increments the write pointer signal wr_ptr by 1 through the first adder 22. Specifically, the write unit 11 includes a decoder 14 and 4 parallel AND gates 15. The AND gates 15 are used to perform an AND calculation on the received input data data_in, write signal push, and the write pointer decoding signal output by the decoder 14 for the write pointer signal, so that the input data data_in is output according to the write pointer decoding signal, that is, output through the corresponding AND gate 15 and cached at the corresponding address in the storage unit 12. When the read signal pop is high, the multiplexer 13 selects the data at the corresponding address from the storage unit 12 according to the read pointer signal rd_ptr output by the read pointer register 24, that is, outputs the output data data_out. Then, the read pointer register 24 increments the read pointer signal rd_ptr by 1 through the second adder 25. Thus, the function of first-in, first-out of data is realized. Moreover, after the write pointer signal wr_ptr and the read pointer signal rd_ptr are updated, they will respectively generate a data full signal full and a data empty signal empty through the first comparator 26 and the second comparator 27. If the number of valid data cached in the storage unit 12 reaches 4, the data full signal full is pulled high. If the number of valid data is 0, the data empty signal empty is pulled high.

[0004] From the above control logic, it can be seen that after the last valid data in the storage unit 12 is output based on the high level of the read signal pop, the read pointer signal rd_ptr is incremented by 1. Since the valid data in the storage unit 12 is empty at this time, the output data data_out is the data pointed to by the current read pointer signal rd_ptr, and this data is not the real data to be output, but invalid data. That is, there is an invalid flip in the output data. As Figure 3 shown in the interface timing diagram, the data marked by the red circle is the invalid flip of the output data data_out under the action of each signal of push and pop. In actual operation, the invalid flip means a waste of chip power consumption.

[0005] Furthermore, there will be two extreme scenarios for the traditional FIFO module 50: In Scenario 1, data is continuously transmitted, that is, the data empty signal empty is always low, so there is no invalid data in the output data data_out and no invalid flips. In Scenario 2, only one data is transmitted each time, and after the transmission, the data empty signal empty is pulled high, so there will be one invalid data in the output data data_out, resulting in a total of twice as much invalid data, that is, twice as many invalid flips. It can be seen that the larger the data transmission bandwidth, the more data is continuously transmitted each time, and the closer it is to Scenario 1. Then, the invalid flip rate tends to 0%. On the contrary, the smaller the data transmission bandwidth, the fewer data is continuously transmitted each time, and the closer it is to Scenario 2. Then, the invalid flip rate tends to 100%. Here, the invalid flip rate is defined as the number of invalid flips divided by the number of valid flips. An invalid data output necessarily results in an invalid flip, and the flip during the output of valid data is called a valid flip.

[0006] As can be seen from the above, in application scenarios with large or small data transmission bandwidths (unless the theoretical maximum bandwidth is reached), there is a problem of invalid flips caused by the output of invalid data. Therefore, how to solve the problem of invalid data output is an urgent issue to be solved currently. Summary of the Invention

[0007] The object of the present invention is to provide a low-power FIFO module, which solves the problem of invalid flips caused by the output of invalid data, thereby reducing power consumption.

[0008] To achieve the above object, the present invention adopts the following technical solutions:

[0009] A low-power FIFO module includes a FIFO memory and a FIFO controller. The FIFO memory includes a write unit, a storage unit, and a multiplexer. The FIFO controller includes a write pointer register, a read pointer register, a first adder, and a second adder. The first adder is used to increment the write pointer signal output by the write pointer register by 1 based on the original write pointer signal when the write signal is high. The second adder is used to increment the read pointer signal output by the read pointer register by 1 based on the original read pointer signal when the read signal is high. In particular, the FIFO controller further includes a mux selection register and a third adder. The third adder is used to increment the mux selection pointer signal output by the mux selection register by 1 only when there is valid data cached in the storage unit or when a new valid data is about to be cached while the storage unit outputs the last valid data, so that the multiplexer selects the data at the corresponding address from the storage unit according to the mux selection pointer signal when the read signal is high.

[0010] The advantages of the present invention are:

[0011] By adding a mux selection register and a third adder in the FIFO controller, the present invention no longer outputs invalid data, avoids generating invalid flips, eliminates the problem of chip power consumption waste caused by invalid flips, and is applicable to both application scenarios with large data transmission bandwidth and those with small data transmission bandwidth. Moreover, the present invention has few newly added control logics, will not affect the total chip area, and will not affect the chip performance. Description of the Drawings

[0012] Figure 1 It is a block diagram of a traditional 4-depth FIFO module.

[0013] Figure 2 It is a control logic block diagram of a traditional 4-depth FIFO module.

[0014] Figure 3 It is an interface timing diagram of a traditional 4-depth FIFO module.

[0015] Figure 4 It is a control logic block diagram of the low-power FIFO module of the present invention.

[0016] Figure 5 It is an interface timing diagram of the low-power FIFO module of the present invention. Detailed Embodiment

[0017] Such as Figure 4As shown in the figure, the present invention proposes a low-power FIFO module 50', which is an improvement on the traditional FIFO module 50. Specifically, the low-power FIFO module 50' of the present invention includes a FIFO memory 10 and a FIFO controller 20' for controlling the FIFO memory 10. The FIFO memory 10 includes a write unit 11, a storage unit 12, and a multiplexer 13. The FIFO controller 20' includes a write pointer register 21, a read pointer register 24, a first adder 22, and a second adder 25. The first adder 22 is used to increment the write pointer signal wr_ptr output by the write pointer register 21 by 1 based on the original write pointer signal wr_ptr when the write signal push is high. The second adder 25 is used to increment the read pointer signal rd_ptr output by the read pointer register 24 by 1 based on the original read pointer signal rd_ptr when the read signal pop is high. Among them, the FIFO controller 20' further includes a mux selection register 30 and a third adder 40. The third adder 40 is used to receive the write signal push, the read signal pop, the write pointer signal wr_ptr output by the write pointer register 21, the read pointer signal rd_ptr output by the read pointer register 24, and the original mux selection pointer signal output by the mux selection register 30, so as to increment the mux selection pointer signal output by the mux selection register 30 only when there is valid data cached in the storage unit 12 or when the last valid data is output from the storage unit 12 and new valid data is about to be cached, so that the multiplexer 13 selects the data at the corresponding address from the storage unit 12 according to the mux selection pointer signal when the read signal pop is high, that is, outputs the output data data_out, which effectively prevents the output of invalid data.

[0018] The mux selection register 30 designed by the present invention decouples the multiplexer 13 from the read pointer register 24. The multiplexer 13 no longer selects the data at the corresponding address from the storage unit 12 according to the read pointer signal rd_ptr output by the read pointer register 24, but selects the output data from the storage unit 12 according to the mux selection pointer signal output by the mux selection register 30.

[0019] In actual implementation, when any of the following conditions is satisfied, the third adder 40 sends an instruction to increment by 1 to the mux selection register 30, so that the mux selection pointer signal output by the mux selection register 30 is incremented by 1:

[0020] Condition 1: There is no valid data cached in the storage unit 12 (i.e., the storage unit 12 is empty), and the write signal push is high;

[0021] Condition 2: The number of valid data cached in the storage unit 12 is 1, and the write signal push and the read signal pop are both high;

[0022] Condition 3: The number of valid data cached in the storage unit 12 is greater than 1, and the read signal pop is high.

[0023] In the present invention, the actually cached data in the storage unit 12 of the FIFO memory 10 is the valid data. When no data is cached in the storage unit 12 but an output operation is still performed, the output data is invalid data. A plurality of consecutive addresses are provided in the storage unit 12, and the input data input into the storage unit 12 is cached in the order of the addresses before and after, and the read operation is performed in accordance with the principle of first in first out of the data. The write pointer signal wr_ptr, the read pointer signal rd_ptr, and the mux selection pointer signal incrementing by 1 mean that the addresses they point to in the storage unit 12 move to the next address, which is a well-known technology in this field and will not be elaborated.

[0024] In the present invention, some contents in the module structure of the chip are represented in a simplified manner. For example, the slashes on the signal lines and the numbers thereon (such as Figure 2 、 Figure 4 the 2 or n in) represent the number of signal lines, that is, the bit width for representing the binary data transmitted.

[0025] In the present invention, the write unit 11 is used to receive the input data data_in, the write signal push, and the write pointer signal wr_ptr, and cache the input data data_in to the corresponding address in the storage unit 12 according to the write pointer signal wr_ptr when the write signal push is high.

[0026] Such as Figure 4 , the write unit 11 includes a decoder 14 and a plurality of AND gates 15 arranged in parallel. The AND gates 15 are used to perform an AND calculation on the received input data data_in, the write signal push, and the write pointer decoding signal output by the decoder 14 for the write pointer signal wr_ptr, so that the input data data_in is output through the corresponding AND gates 15 according to the write pointer decoding signal and cached to the corresponding address in the storage unit 12.

[0027] Such as Figure 4 , the FIFO controller 20' further includes a first comparator 26 and a second comparator 27. The first comparator 26 and the second comparator 27 are used to generate a data full signal full and a data empty signal empty respectively after the write pointer signal wr_ptr and the read pointer signal rd_ptr are updated, where: if the storage unit 12 is full of valid data, the data full signal full is high and the data empty signal empty is low; on the contrary, if there is no valid data in the storage unit 12, the data empty signal empty is high and the data full signal full is low.

[0028] In the present invention, the first adder 22, the second adder 25, the third adder 40, the first comparator 26 and the second comparator 27 are composed of well-known logic components such as AND gates and OR gates, which are well-known technologies. Their specific compositions are not limited and will not be elaborated here.

[0029] This new control logic of the present invention well solves the problem of invalid flips that occurred in the above-mentioned scenario 2.

[0030] Such as Figure 4 , Figure 4 Taking 4-depth as an example, the composition of the FIFO module 50' is shown. Four parallel AND gates 15 receive the input data data_in (binary data), the write signal push, and the write pointer decoding signal (the write pointer signal wr_ptr outputs the write pointer decoding signal after passing through the decoder 14), and perform AND calculations. Thus, when the write signal push is high, according to the address pointed to by the write pointer decoding signal, the input data data_in is cached into the storage unit 12 through the AND gate 15 corresponding to the address pointed to by this write pointer decoding signal. At this time, the write pointer signal wr_ptr output by the write pointer register 21 is incremented by 1 on the basis of the original write pointer signal wr_ptr through the first adder 22 (when the write signal push is high).

[0031] When the read signal pop is high, the read pointer signal rd_ptr output by the read pointer register 24 is incremented by 1 on the basis of the original read pointer signal rd_ptr through the second adder 25. And at this time, the third adder 40 receives the write signal push, the read signal pop, the write pointer signal wr_ptr output by the write pointer register 21, the read pointer signal rd_ptr output by the read pointer register 24, and the original mux selection pointer signal output by the mux selection register 30, and makes a judgment on whether to increment by 1. That is, only when there is valid data cached in the storage unit 12 at this time or when the storage unit 12 outputs the last valid data but is about to cache a valid data, the third adder 40 sends an instruction to increment by 1 to the mux selection register 30, that is, to increment the mux selection pointer signal output by the mux selection register 30 by 1, so that the multiplexer 13 selects the data at the corresponding address (the next address) from the storage unit 12 according to the mux selection pointer signal and outputs it (when the read signal pop is high). And at this time, there must be valid data cached in the storage unit 12. Therefore, it avoids the situation of invalid flips caused by outputting invalid data like the traditional FIFO module 50, and solves the problem of waste of chip power consumption.

[0032] In addition, similar to the traditional FIFO module 50, after the write pointer signal wr_ptr and the read pointer signal rd_ptr are updated, they will respectively generate a data full signal full and a data empty signal empty through the first comparator 26 and the second comparator 27. If the number of valid data cached in the storage unit 12 reaches 4, the data full signal full is pulled high. If the number of valid data is 0, the data empty signal empty is pulled high.

[0033] As Figure 5 , Figure 5 shown in the interface timing diagram of the FIFO module 50' of the present invention after improving the traditional FIFO module 50. Compared with Figure 3 , Figure 5 the output data data_out in [reference] no longer has invalid data, eliminating the invalid flips and avoiding the waste of chip power consumption.

[0034] Generally speaking, the data bit width is much larger than the pointer bit width. For example, the bit width of the input data is 128, while the pointer bit width of the 4-depth FIFO memory 10 is 2. Therefore, it can be seen that the power consumption saved by the third adder 40 and the mux selection register 30 is much greater than the power consumption generated by the third adder 40 and the mux selection register 30 themselves. So, as long as the actual bandwidth of data transmission is less than the theoretical bandwidth and the data is not a constant value, the power consumption can be reduced by the present invention. Moreover, the smaller the bandwidth and the greater the change in the input data, the better the power consumption reduction effect. In special cases, that is, if the actual bandwidth is equal to the theoretical bandwidth, since the total power consumption of the module is very large, the power consumption overhead caused by the third adder 40 and the mux selection register 30 added by the present invention is very small and can be ignored.

[0035] In summary, the present invention eliminates the waste of chip power consumption caused by invalid flips. In addition, the newly added devices of the present invention basically do not increase power consumption at high bandwidths and are suitable for application scenarios with large data transmission bandwidths. At low bandwidths, power consumption can be saved, so it is more suitable for application scenarios with small data transmission bandwidths. Moreover, the present invention has less newly added control logic, will not affect the total chip area, and will not affect the chip performance, making it suitable for promotion.

[0036] The above is the preferred embodiment of the present invention and the technical principles applied. For those skilled in the art, any obvious changes such as equivalent transformations and simple substitutions based on the technical solution of the present invention without departing from the spirit and scope of the present invention shall fall within the protection scope of the present invention.

Claims

1. A low-power FIFO module, comprising a FIFO memory and a FIFO controller. The FIFO memory includes a write unit, a storage unit, and a multiplexer. The FIFO controller includes a write pointer register, a read pointer register, a first adder, and a second adder. The first adder is configured to increment the write pointer signal output by the write pointer register by 1 based on the original write pointer signal when the write signal is high. The second adder is configured to increment the read pointer signal output by the read pointer register by 1 based on the original read pointer signal when the read signal is high. It is characterized in that, The FIFO controller further includes a mux selection register and a third adder. The third adder is configured to increment the mux selection pointer signal output by the mux selection register by 1 only when there is valid data cached in the storage unit or when a new valid data is to be cached while the storage unit outputs the last valid data, so that the multiplexer selects and outputs the data at the corresponding address from the storage unit according to the mux selection pointer signal when the read signal is high.

2. The low-power FIFO module according to claim 1, characterized in that, When any of the following conditions is satisfied, the third adder sends an instruction to increment the mux selection register by 1, so that the mux selection pointer signal output by the mux selection register is incremented by 1: Condition 1: There is no valid data cached in the storage unit and the write signal is high; Condition 2: The number of valid data cached in the storage unit is 1, and the write signal and the read signal are both high; Condition 3: The number of valid data cached in the storage unit is greater than 1, and the read signal is high.

3. The low-power FIFO module according to claim 2, wherein The write unit is configured to receive input data, a write signal, and a write pointer signal, and cache the input data to the corresponding address in the storage unit according to the write pointer signal when the write signal is high.

4. The low-power FIFO module according to claim 3, wherein The write unit includes a decoder and a plurality of parallel AND gates. The AND gates are configured to perform an AND operation on the received input data, the write signal, and the write pointer decoding signal output by the decoder through the write pointer, so that the input data is output through the corresponding AND gate according to the write pointer decoding signal and cached to the corresponding address in the storage unit.

5. The low-power FIFO module according to any one of claims 1 to 4, characterized in that The FIFO controller further includes a first comparator and a second comparator. The first comparator and the second comparator are configured to generate a data full signal and a data empty signal respectively after the write pointer signal and the read pointer signal are updated, where: if the storage unit is full of valid data, the data full signal is high; on the contrary, if there is no valid data in the storage unit, the data empty signal is high.

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