Linear equation set solver and solving method

Abstract

The invention provides a linear equation set solver and a solving method, and relates to the technical field of analog circuits. The system of linear equations solver comprises a control circuit, a voltage regulating circuit and a memristor array which are connected with one another, the control circuit obtains a target linear equation set; wherein the target linear equation set comprises a constant matrix and a coefficient matrix; the control circuit is used for adjusting parameters of the memristor array according to the coefficient matrix and adjusting parameters of the voltage regulation circuit according to the constant matrix and the coefficient matrix to obtain a target circuit formed by the adjusted memristor array and the adjusted voltage regulation circuit; and the control circuit obtains the voltage value of the voltage signal output by the adjusted memristor array on each column, forms a vector, and outputs the vector as a solving result of the target linear equation set. According to the mode, the solving efficiency of the linear equation set is improved.

Description

Technical Field

[0001] The present application relates to the technical field of analog circuits, and particularly to a linear equation solver and a solving method. Background Art

[0002] In the processes of open integrated circuit process research and development, mass production, etc., linear equations are the basic mathematical models of many practical problems. For example, in the production process, cost control is one of the keys to enterprise management. By establishing a linear equation system, it can help an enterprise determine the optimal production plan to minimize production costs. The core idea of a linear equation system is to obtain the specific values of variables by solving the equation system, so as to solve practical problems. Since the solving efficiency seriously affects the production capacity output, an efficient and rapid linear equation solving system is needed to meet the needs of practical applications.

[0003] Traditional linear equation solving systems are based on the von Neumann computer architecture. In this computing architecture where the memory is separated from the calculator, when performing solving calculations, data is frequently transferred between the processor and the memory, resulting in huge power consumption and delay. And traditional mathematical methods for solving linear equations, such as the elimination method, the inverse matrix method, the iterative method, etc., usually rely on circuits such as CPUs or GPUs to complete the calculation by instructions, and implement serial algorithms. Because iterative operations need to be repeatedly performed during the solving process, this problem becomes more serious when the scale of the coefficient matrix is huge.

[0004] Therefore, the prior art has the problem of low efficiency in solving linear equations. Summary of the Invention

[0005] The present application provides a linear equation solver and a solving method to solve the problem of low efficiency in solving linear equations existing in the prior art.

[0006] According to the first aspect of the present application, a linear equation solver is provided, including: a control circuit, a voltage regulating circuit, and a memristor array that are connected to each other;

[0007] The control circuit obtains a target linear equation system; wherein, the target linear equation system includes a constant matrix and a coefficient matrix;

[0008] The control circuit adjusts the parameters of the memristor array according to the coefficient matrix, and adjusts the parameters of the voltage regulating circuit according to the constant matrix and the coefficient matrix to obtain a target circuit composed of the adjusted memristor array and the adjusted voltage regulating circuit;

[0009] The control circuit obtains the voltage values of the voltage signals output by each column of the adjusted memristor array, forms a vector, and outputs it as the solution result of the target linear equation system.

[0010] Optionally, the memristor array includes m×n memristor cells;

[0011] The different memristor cells are connected by wires, and the conductance value of the memristor cell is G i，j ; where i ≤ m and j ≤ n; where i indicates that the memristor cell is located on the i-th row wire, and j indicates that the memristor cell is located on the j-th column wire.

[0012] Optionally, m = n.

[0013] Optionally, the memristor cell includes at least one memristor.

[0014] Optionally, when the number of the memristors is multiple, the different memristors can be connected by a preset connection method, and the preset connection method includes any one of the following: parallel connection method, series connection method, and series-parallel combination connection method.

[0015] Optionally, the voltage regulating circuit includes: m voltage regulating branches; where the output end of the i-th voltage regulating branch is connected to the input end of the i-th row wire.

[0016] Optionally, the voltage regulating branch includes a digital-to-analog converter and an amplifier connected in sequence;

[0017] The input end of the digital-to-analog converter is connected to the control circuit, and the output end of the amplifier is the output end of the voltage regulating branch.

[0018] According to a second aspect of the present application, a method for solving a system of linear equations is provided, which is applied to a control circuit in a system of linear equations solver, and includes:

[0019] Obtain a target system of linear equations; where the target system of linear equations includes a constant matrix and a coefficient matrix;

[0020] Adjust the parameters of the memristor array according to the coefficient matrix, and adjust the parameters of the voltage regulating circuit according to the constant matrix and the coefficient matrix to obtain a target circuit composed of the adjusted memristor array and the adjusted voltage regulating circuit;

[0021] Obtain the voltage values of the voltage signals output on each column of the adjusted memristor array, form a vector, and output it as the solution result of the target system of linear equations.

[0022] Optionally, the adjusting the parameters of the memristor array according to the coefficient matrix includes:

[0023] Adjust the conductance values of the respective memristor cells in the memristor array according to the respective coefficients in the coefficient matrix.

[0024] Optionally, adjusting the parameters of the voltage regulating circuit according to the constant matrix and the coefficient matrix includes:

[0025] Determining the voltage value of the voltage signal output by the voltage regulating circuit according to the constant matrix and the coefficient matrix.

[0026] According to the third aspect of the present application, a linear equation solving device is provided, which is applied to a control circuit in a linear equation solver and includes:

[0027] An acquisition module, configured to acquire a target linear equation set; wherein, the target linear equation set includes a constant matrix and a coefficient matrix;

[0028] An adjustment module, configured to adjust the parameters of the memristor array according to the coefficient matrix, and adjust the parameters of the voltage regulating circuit according to the constant matrix and the coefficient matrix, to obtain a target circuit composed of the adjusted memristor array and the adjusted voltage regulating circuit;

[0029] An acquisition and output module, configured to acquire the voltage values of the voltage signals output by the adjusted memristor array on each column, form a vector, and output the vector as the solution result of the target linear equation set.

[0030] A linear equation solver provided by the present application includes: a control circuit, a voltage regulating circuit, and a memristor array that are interconnected; the control circuit acquires a target linear equation set; wherein, the target linear equation set includes a constant matrix and a coefficient matrix; the control circuit adjusts the parameters of the memristor array according to the coefficient matrix, and adjusts the parameters of the voltage regulating circuit according to the constant matrix and the coefficient matrix, to obtain a target circuit composed of the adjusted memristor array and the adjusted voltage regulating circuit; the control circuit acquires the voltage values of the voltage signals output by the adjusted memristor array on each column, forms a vector, and outputs the vector as the solution result of the target linear equation set.

[0031] Compared with the existing serial algorithms, the present application realizes hardware parallel computing, that is, based on the memristor array, fast mapping of the coefficient matrix can be realized, and based on the memristor array and the voltage regulating circuit, fast mapping of the constant matrix can be realized. After the mapping is completed, the present application can quickly obtain the solution result by acquiring the voltage values of the voltage signals output by the adjusted memristor array on each column. Therefore, the present application improves the solving efficiency of the linear equation set.

[0032] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become easily understood through the following description. Description of the Drawings

[0033] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0034] Figure 1 A schematic structural diagram of a linear equation solver provided for an embodiment of this application;

[0035] Figure 2 A schematic structural diagram of another linear equation solver provided for an embodiment of this application;

[0036] Figure 3 A schematic structural diagram of yet another linear equation solver provided for an embodiment of this application;

[0037] Figure 4 A schematic flowchart of a method for solving a linear equation system provided for an embodiment of this application;

[0038] Figure 5 A schematic structural diagram of a device for solving a linear equation system provided for an embodiment of this application.

[0039] Through the above accompanying drawings, specific embodiments of this application have been shown, and there will be more detailed descriptions hereinafter. These drawings and textual descriptions are not intended to limit the scope of the concept of this application in any way, but to illustrate the concept of this application to those skilled in the art by referring to specific embodiments. Detailed Embodiments

[0040] Here, exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0041] Existing methods for solving linear equation systems usually adopt methods such as the elimination method, the inverse matrix method, and the iterative method, and usually rely on instructions for calculation using circuits such as CPUs or GPUs. The time complexity of the elimination method and the inverse matrix method is O(N3), that is, it has a cubic relationship with the number of unknowns in the equation. The time complexity of the iterative method is related to the setting of the initial value and the spectral radius, and there may be a situation of non-convergence. Implementing a serial algorithm using circuits such as CPUs or GPUs, when the number of variables is large, the corresponding time increases rapidly. Due to the serial nature, the increase in hardware has a very limited effect on improving the algorithm speed.

[0042] To solve the above technical problems, the overall inventive concept of this application is how to provide a method applied to the field of analog circuits for improving the efficiency of solving linear equation systems.

[0043] The technical solution of the present application and how the technical solution of the present application solves the above technical problems will be described in detail below with specific embodiments. These several specific embodiments below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0044] Figure 1 It is a schematic structural diagram of a linear equation solver provided by an embodiment of the present application. As Figure 1 shown, the linear equation solver of this embodiment includes: a control circuit 10, a voltage regulating circuit 20, and a memristor array 30 that are interconnected.

[0045] The control circuit 10 obtains the target linear equations; wherein, the target linear equations include a constant matrix and a coefficient matrix.

[0046] The linear equation solver in this embodiment is applicable to solving linear equations in the form of Gv = I, where G is a matrix of m'×n'.

[0047] Optionally, when m' is equal to n', the general solution of the target linear equations is solved by the equation solver, and the optimal solution can be determined according to the general solution. When m' is not equal to n', the particular solution of the target linear equations is solved by the equation solver, and the particular solution may include the optimal solution or may only have a relatively good solution. The equation solver in this embodiment can achieve the solution for different forms of target linear equations, improving the adaptability of the solution method.

[0048] This embodiment will be described below taking m' = n' as an example:

[0049] G is a matrix of m'×m' (the element in the i-th row and j-th column is G i，j ), each coefficient G in the coefficient matrix G i，j is greater than 0, or after the linear equations are transformed, each coefficient G in the coefficient matrix G i，j is greater than 0 (for example: when the coefficients of a certain unknown in all equations are negative, the coefficients of all such unknowns can be set to positive numbers, that is, all are set to the opposite numbers, etc.), v is a vector of m'×1 composed of unknowns to be solved (the j-th value is denoted as v out，j ), I is a constant matrix of m'×1, or called a coefficient vector, and the i-th value in the constant matrix I is denoted as I i .

[0050] In the embodiment of the present application, the target linear equations can be linear equations related to cost control in the process of open integrated circuit process research and development, mass production, etc., or can also be linear equations related to other aspects such as multi-factor analysis of variance in this process.

[0051] In many fields such as cost optimization, personalized recommendation, and production scheduling optimization, linear regression is a commonly used calculation process. However, limited by the von Neumann architecture, when traditional computers calculate linear equations, the calculation speed is slow, and the calculation time is related to the problem scale cubically. The linear equation solver in this application can be used as an accelerator to significantly improve the speed of linear regression, making the calculation time linearly related to the problem scale, and thus reducing the hardware cost of this embodiment under the same operation time and operation effect.

[0052] Among them, the dimension of the constant matrix is m′×1, and the specific value of m′ can be 2, 3, 5, 10, etc. Therefore, this application embodiment does not specifically limit the specific value of m′.

[0053] For example, the linear equation related to cost control is:

[0054]

[0055] Among them, is the coefficient matrix, is the constant matrix, where y1 represents the total cost of two production lines in the first case; y2 represents the total cost of two production lines in the second case; both the coefficient matrix and the constant matrix are known quantities, is the matrix composed of unknowns to be solved. x1 is the output of the products on the first production line, and x2 is the output of the products on the second production line. The products on different production lines can refer to the same type of products or different types of products.

[0056] In addition, linear equations can be used to solve problems such as circuit design, manufacturing process, motion analysis and optimization of enterprise internal control systems, and can also be applied in the computer field to solve various practical problems in image processing, computer vision, artificial intelligence, signal processing, and data analysis.

[0057] Furthermore, the specific values of the constant matrix and the coefficient matrix of the target linear equation, as well as the size of the matrix scale, can be adaptively configured according to actual needs. Therefore, this application embodiment does not specifically limit the specific values of the constant matrix and the coefficient matrix of the target linear equation, nor the size of the matrix scale.

[0058] The control circuit 10 adjusts the parameters of the memristor array 30 according to the coefficient matrix, and adjusts the parameters of the voltage regulating circuit 20 according to the constant matrix and the coefficient matrix to obtain a target circuit composed of the adjusted memristor array 30 and the adjusted voltage regulating circuit 20.

[0059] In this step of the embodiment of the present application, the mapping from the matrix to the hardware is realized, that is: the coefficient matrix is mapped to the parameters of the memristor array 30, and the constant matrix and the coefficient matrix are mapped to the parameters of the voltage regulating circuit 20, so as to realize the rapid acquisition of the unknowns to be solved.

[0060] The control circuit 10 obtains the voltage values of the voltage signals output by the adjusted memristor array 30 in each column, forms a vector, and outputs it as the solution result of the target linear equation system.

[0061] Compared with the existing serial algorithm, the linear equation system solver provided by the present application can provide an algorithm for automatically solving linear equation systems by using circuits. The algorithm can be parallelly computed by hardware, and thus the solution acceleration of specific linear equation systems can be completed.

[0062] Specifically, the hardware parallel computing implemented in this embodiment is as follows: based on the memristor array 30, the fast mapping of the coefficient matrix can be realized, and based on the memristor array 30 and the voltage regulating circuit 20, the fast mapping of the constant matrix can be realized. After the mapping is completed, the present application can quickly obtain the solution result by obtaining the voltage values of the voltage signals output by the adjusted memristor array 30 in each column. Therefore, the embodiment of the present application improves the solution efficiency of the linear equation system.

[0063] In addition, the linear equation system solver adopted in this embodiment can effectively reduce the time complexity, realize the integration of storage and computing, greatly save the operation energy consumption and time, and improve the reliability.

[0064] Based on the above embodiments, the technical solution of the present application will be described in more detail below in combination with several specific embodiments.

[0065] Embodiment 2:

[0066] Figure 2 It is a structural schematic diagram of another linear equation system solver provided by the embodiment of the present application. As Figure 2 shown, in another linear equation system solver, the memristor array 30 includes m×n memristor units.

[0067] Different memristor units are connected by wires, and the conductance value (or called transconductance coefficient) of the memristor unit is G i，j ; where, i≤m, and j≤n.

[0068] As Figure 2 shown, the conductance value of the memristor unit located on the first row of wires and the first column of wires is G 1，1 , the conductance value of the memristor unit located on the first row of wires and the second column of wires is G 1，2 , and the conductance value of the memristor unit located between the first row of wires and the nth column of wires is G1，n 。

[0069] Similarly, the conductance value of the memristor unit located on the wire in the second row and the wire in the first column is G 2，1 and the conductance value of the memristor unit located on the wire in the second row and the wire in the second column is G 2，2 and the conductance value of the memristor unit located on the wire in the second row and the wire in the nth column is G 2，n 。

[0070] By analogy, the conductance value of the memristor unit located on the wire in the mth row and the wire in the first column is G m，1 and the conductance value of the memristor unit located on the wire in the mth row and the wire in the second column is G m，2 and the conductance value of the memristor unit located on the wire in the mth row and the wire in the nth column is G m，n 。

[0071] Optionally, the number of memristor units is m×n; where m is greater than or equal to 2, n is greater than or equal to 2, and the memristor units are distributed in a matrix within the memristor array.

[0072] It should be understood that the specific values of m and n can be 10, 100, 200, etc. Therefore, the embodiments of the present application do not specifically limit the specific values of m and n. It should be noted that the larger the value of m, the more linear equations can be solved, and its adaptability is stronger.

[0073] By designing the value of m in the embodiments of the present application, the application range of the linear equation solver can be expanded.

[0074] Before solving the linear equations in this embodiment, a linear equation solver can be constructed first. During the construction of the linear equation solver, the memristor unit can ensure the accuracy of the mapping, and thus improve the solving efficiency while ensuring the mapping accuracy.

[0075] In a possible implementation, the memristor unit includes at least one memristor. A memristor can be an adjustable resistor or other forms of resistors. The embodiments of the present application do not specifically limit the number, type, etc. of the memristors. Further, the adjustable resistor can use a digital potentiometer.

[0076] In the case where the memristor unit includes multiple memristors, different states of the memristor can be realized by turning on and off the analog switch in this embodiment. In this embodiment, the resistance value of the digital potentiometer and the on and off of the analog switch can both be set by programming.

[0077] It should be understood that a memristor is a non-linear resistor with memory function. By controlling the change of current, etc., its resistance value can be changed. If the high resistance value is defined as "1" and the low resistance value is defined as "0", then this resistor can realize the function of storing data. In fact, it is a non-linear resistor with memory function.

[0078] In addition to the design method of adjustable resistors, the embodiments of the present application can also be implemented by combining resistors and switches. Specifically, in this embodiment, the conductance value of the memristor unit can be effectively adjusted by controlling whether the circuit where the switch is located is open or not, thereby improving the accuracy of adjustment.

[0079] In a possible implementation manner, when the number of memristors is multiple, different memristors can be connected in a preset connection manner, and the preset connection manner includes any one of the following: parallel connection manner, series connection manner, and series-parallel combination manner.

[0080] For example, for the series-parallel combination manner, there are three resistors with a single value of 3Ω each in the same memristor unit: resistor A, resistor B, and resistor C. Among them, after resistor A and resistor B are connected in series, they are combined with resistor C. In this embodiment, the on-off of the branch where resistor A and resistor B are located can be controlled by a analog switch, and the on-off of resistor C can also be controlled by the analog switch, finally providing multiple different resistance values: 2Ω, 3Ω, and 6Ω. Therefore, in this embodiment, based on multiple memristors, the effect of multiple resistance values can be achieved through the regulation of multiple analog switches.

[0081] When constructing the memristor unit in this embodiment, the memristor unit can be composed of a single or multiple memristors, and the memristors can be designed in series and / or in parallel. Taking the all-parallel design as an example: If the memristor includes two states of high resistance value and low resistance value, and all high resistance values are equal, and all low resistance values are equal, then the memristor unit composed of n memristors can represent n + 1 values; taking the all-series design as an example: If the memristor includes two states of high resistance value and low resistance value, and all high resistance values are extremely large, and all low resistance values show a two-fold increasing relationship, then the memristor unit composed of n memristors can represent n 2

[0082] In the case of all-parallel in the embodiments of the present application, the accurate mapping from the coefficients in the coefficient matrix to the memristor unit can be realized by controlling the conductance value of the memristor, or the accurate mapping from the coefficients in the coefficient matrix to the memristor unit can be realized by controlling the on-off of the memristor, thereby ensuring the accuracy of the solution result.

[0083] In a possible implementation manner, as Figure 2 shown, the voltage regulating circuit 20 includes: m voltage regulating branches; among them, the output end of the i-th voltage regulating branch is connected to the input end of the i-th row of wires.

[0084] In the embodiments of the present application, by providing m voltage regulation branches, an accurate mapping of the constant matrix can be achieved, thereby improving the accuracy of solving the linear equations.

[0085] In a possible implementation, the i-th voltage regulation branch includes a digital-to-analog converter DAC connected in sequence i and an amplifier Amp i . It should be understood that the voltage regulation branch is also called a digital-to-analog conversion circuit.

[0086] Specifically, as Figure 2 shown, the first voltage regulation branch 21 includes a first digital-to-analog converter DAC1 and a first amplifier Amp1 connected in sequence, the second voltage regulation branch includes a second digital-to-analog converter DAC2 and a second amplifier Amp2 connected in sequence, and the m-th voltage regulation branch includes an m-th digital-to-analog converter DAC m and an m-th amplifier Amp m .

[0087] All amplifiers are devices that amplify the corresponding voltage signals and are composed of one of electron tubes and transistors, a power transformer, and other electrical components. An amplifier is one of the most common and important units in a digital-to-analog conversion circuit. In the embodiments of the present application, no specific limitations are imposed on the model, parameters, etc. of the amplifier.

[0088] The input end of the digital-to-analog converter DAC i is connected to the control circuit 10, and the output end of the amplifier Ampi is the output end of the corresponding voltage regulation branch.

[0089] It should be understood that the amplifier is a non-inverting amplifier circuit or an inverting amplifier circuit. When m = n, in this embodiment, 2m wires are arranged in a form of m columns vertically and m rows horizontally. Among them, a memristor unit is connected between the i-th row wire and the j-th column wire, and the conductance value of this memristor unit is denoted as G i，j , let the voltage value of the j-th column wire be v out，j , and the voltage value of the i-th row wire be v in，i . One end of the i-th row wire is connected to the output end of the non-inverting or inverting amplifier circuit, and the amplification factor is A i , the input end of the amplifier is connected to the output end of the digital-to-analog converter DAC i , the output voltage of the digital-to-analog converter DAC i is v dac，i . Among them, the above amplification factor A i and the voltage value v in，i of the i-th row wire are both controllable quantities.

[0090] Through the above hardware design, the embodiments of the present application can construct an equation set circuit, thereby providing technical support for the subsequent solution of the target linear equation set.

[0091] After obtaining the target linear equation, the embodiments of the present application map the coefficients G in the coefficient matrix G i，j one by one to the corresponding memristor units. When the positive coefficient cannot be represented by the value space, the present embodiment can take the nearest value and calculate the sum of the transconductances ∑G on the i-th row wire in parallel i，j , and set the voltage value of the output voltage signal of the corresponding digital-to-analog converter DAC i to be v dac，i = I i / (A i ×∑G i，j ).

[0092] Optionally, the present embodiment gives the following example of the above nearest value: the coefficient assigned to the memristor unit is 1.115, but the memristor unit has a step size, which can be adjusted to 1.11 or 1.12. Therefore, the embodiments of the present application can select the nearest value according to the actual situation.

[0093] When the linear equation set solver is stable, the embodiments of the present application can use a voltage measuring device to measure the voltages at all v out，j locations, and the voltage value at this point is the solution variable. Further, the voltage measuring device can be a device in the control circuit 10 or an external device independent of the control circuit 10.

[0094] In the process of constructing the linear equation set solver in the present embodiment, through the design of each component in the linear equation set solver, the memristor unit can ensure the accuracy of the mapping, and thus while ensuring the mapping accuracy, the solution efficiency is improved. In addition, the linear equation set solver adopted in the present embodiment can effectively reduce the time complexity, realize the integration of storage and calculation, greatly save the operation energy consumption and time, and improve the reliability.

[0095] Embodiment 3:

[0096] Figure 3 is a schematic structural diagram of another linear equation set solver provided by the embodiments of the present application. As Figure 3 shown, the control circuit 10 can be the chip U, and the embodiments of the present application do not make specific limitations on the model and specific design of the chip U.

[0097] As Figure 3 shown, taking m = n = 3 as an example: the memristor array provided by the embodiments of the present application is in the form of 3×3. In the memristor array, the conductance value of the memristor unit located on the first row wire and the first column wire is G 1，1, the conductance value of the memristor unit located on the first-row wire and the second-column wire is G 1，2 , the conductance value of the memristor unit located on the first-row wire and the third-column wire is G 1，3 .

[0098] Similarly, the conductance value of the memristor unit located on the second-row wire and the first-column wire is G 2，1 , the conductance value of the memristor unit located on the second-row wire and the second-column wire is G 2，2 , the conductance value of the memristor unit located on the second-row wire and the third-column wire is G 2，3 .

[0099] Similarly, the conductance value of the memristor unit located on the third-row wire and the first-column wire is G 3，1 , the conductance value of the memristor unit located on the third-row wire and the second-column wire is G 3，2 , the conductance value of the memristor unit located on the third-row wire and the third-column wire is G 3，3 .

[0100] According to Kirchhoff's KCL law, the sum of the currents on the i-th row wire is 0, that is:

[0101] ∑G i，j (v out，j -v in，i ) = 0;

[0102] It can be transformed into ∑G i，j v out，j = v in,i ∑G i，j = v dac，i A i ∑G i，j = I i .

[0103] Combined with Figure 3 , the deformation process of the above formula is analyzed as follows:

[0104] When i = 1, ∑[G 1，j ×(v out，j -v in，1 )] = 0;

[0105] That is, G 1，1 (v out，1 -v in，1 ) + G 1，2 (v out，2 -v in，1 ) + G 1，3 (v out，3 -v in，1 ) = 0;

[0106] By transforming the above formula, it can be known that:

[0107] G 1，1 v out，1 +G 1，2 v out，2 +G 1，3 v out，3 =G 1，1 v in，1 +G 1，2 v in，1 +G 1，3 v in，1 ;

[0108] Continuing the transformation, it can be known that: ∑(G 1，j ×v out，j ) = ∑G 1，j ×v in，1 .

[0109] When i = 2, ∑[G 2，j ×(v out，j -v in，2 )] = 0;

[0110] That is, G 2，1 (v out，1 -v in，2 )+G 2，2 (v out，2 -v in，2 )+G 2，3 (v out，3 -v in，2 ) = 0;

[0111] By transforming the above formula, it is known that:

[0112] G 2，1 v out，1 +G 2，2 v out，2 +G 2，3 v out，3 =G 2，1 v in，2 +G 2，2 v in，2 +G 2，3 v in，2 ;

[0113] Continuing the transformation, it can be known that: ∑(G 2，j ×v out，j ) = ∑G 2，j ×v in，2 .

[0114] When i = 3, ∑[G 1，j ×(v out，j -v in，1 )] = 0;

[0115] That is, G 3，1 (v out，1 -v in，3 ) + G 3，2 (v out，2 -v in，3 ) + G 3，3 (v out，3 -v in，3 ) = 0;

[0116] By transforming the above formula, it can be known that:

[0117] G 3，1 v out，1 + G 3，2 v out，2 + G 3，3 v out，3 = G 3，1 v in，3 + G 3，2 v in，3 + G 3，3 v in，3 ;

[0118] Continuing to transform, it can be known that: ∑(G 3，j × v out，j ) = ∑G 3，j × v in，3 .

[0119] In the embodiments of the present application, if the coefficient matrix in the linear equation system is in the form of 3×3, each memristor in the memristor array corresponds to a coefficient respectively. If the coefficient matrix in the linear equation system is in the form of 2×2, the embodiments of the present application can adjust G 1，3 , G 2，3 , G 3，1 , G 3，2 , G 3，3 to 0.

[0120] In addition, the embodiments of the present application do not specifically limit the hardware structure of the linear equation system solver, and it can also be extended into other structural forms.

[0121] The embodiments of the present application can implement hardware parallel computing through the linear equation system solver, thereby completing the acceleration of the solution of a specific linear equation system and improving the solution efficiency of the linear equation system.

[0122] Embodiment 4:

[0123] Figure 4 is a schematic flow chart of a method for solving a linear equation system provided by the embodiments of the present application. As Figure 4 shown, the method for solving a linear equation system includes the following steps:

[0124] S10. Obtain a target linear equation set; wherein, the target linear equation set includes a constant matrix and a coefficient matrix.

[0125] S20. Adjust the parameters of the memristor array according to the coefficient matrix, and adjust the parameters of the voltage regulating circuit according to the constant matrix and the coefficient matrix, to obtain a target circuit composed of the adjusted memristor array and the adjusted voltage regulating circuit.

[0126] S30. Obtain the voltage values of the voltage signals output by each column of the adjusted memristor array, form a vector, and output it as the solution result of the target linear equation set.

[0127] The linear equation set solving method provided in this embodiment has a similar implementation principle and technical effect to the linear equation set solver provided in the above embodiment, and will not be elaborated here.

[0128] In a possible implementation manner, adjusting the parameters of the memristor array according to the coefficient matrix includes:

[0129] Adjust the conductance values of the respective memristor units in the memristor array according to the respective coefficients in the coefficient matrix.

[0130] In a possible implementation manner, adjusting the parameters of the voltage regulating circuit according to the constant matrix and the coefficient matrix includes:

[0131] Determine the voltage value of the voltage signal output by the voltage regulating circuit according to the constant matrix and the coefficient matrix.

[0132] The embodiments of the present application can implement hardware parallel computing through the linear equation set solving method, thereby completing the acceleration of the solution of a specific linear equation set and improving the solution efficiency of the linear equation set.

[0133] Embodiment 5:

[0134] Figure 5 It is a schematic structural diagram of a linear equation set solving device provided in an embodiment of the present application. The device in this embodiment can be in the form of software and / or hardware. As Figure 5 shown, the linear equation set solving device provided in this embodiment includes: an obtaining module 51, an adjusting module 52, and an obtaining and outputting module 53.

[0135] Wherein:

[0136] The obtaining module 51 is configured to obtain a target linear equation set; wherein, the target linear equation set includes a constant matrix and a coefficient matrix.

[0137] The adjusting module 52 is configured to adjust the parameters of the memristor array according to the coefficient matrix, and adjust the parameters of the voltage regulating circuit according to the constant matrix and the coefficient matrix, to obtain a target circuit composed of the adjusted memristor array and the adjusted voltage regulating circuit.

[0138] Obtain an output module 53, which is used to obtain the voltage values of the voltage signals output by the adjusted memristor array on each column, form a vector, and output it as the solution result of the target linear equation system.

[0139] In a possible implementation manner, the adjustment module 52 is further used for:

[0140] Adjust the conductance values of each memristor unit in the memristor array respectively according to the coefficients in the coefficient matrix.

[0141] In a possible implementation manner, the adjustment module 52 is further used for:

[0142] Determine the voltage value of the voltage signal output by the voltage regulation circuit according to the constant matrix and the coefficient matrix.

[0143] The linear equation system solving device provided in this embodiment can be used to execute the linear equation system solving method provided in any of the above method embodiments. The implementation principle and technical effects are similar, and will not be elaborated here.

[0144] It should be noted that the user information and data involved in this application (including but not limited to data for analysis, stored data, displayed data, etc.) are all information and data authorized by the user or fully authorized by all parties. And the collection, use, and processing of relevant data need to comply with the relevant laws, regulations, and standards of relevant countries and regions, and corresponding operation entrances are provided for users to choose to authorize or refuse.

[0145] That is to say, in the technical solution of this application, the collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved all comply with the provisions of relevant laws and regulations and do not violate public order and good customs.

[0146] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recorded in the disclosure of this application can be executed in parallel, sequentially, or in a different order, as long as the results expected by the technical solution disclosed in this application can be achieved. No limitation is imposed herein.

[0147] The above specific implementation manners do not constitute a limitation on the protection scope of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the principles of this application should be included within the protection scope of this application.

Claims

1. A linear equation system solver, characterized in that, Including: A control circuit, a voltage regulating circuit and a memristor array connected to each other; The control circuit obtains a target linear equation set; wherein, the target linear equation set includes a constant matrix and a coefficient matrix; The control circuit adjusts the parameters of the memristor array according to the coefficient matrix, and adjusts the parameters of the voltage regulating circuit according to the constant matrix and the coefficient matrix, to obtain a target circuit composed of the adjusted memristor array and the adjusted voltage regulating circuit; The control circuit obtains the voltage values of the voltage signals output on each column of the adjusted memristor array, forms a vector, and outputs the vector as the solution result of the target linear equation set.

2. The linear equation system solver according to claim 1, characterized in that, The memristor array includes m×n memristor units; The different memristor units are connected by wires, and the conductance value of the memristor unit is G i，j ; where i ≤ m and j ≤ n; where i indicates that the memristor unit is located on the i-th row wire, and j indicates that the memristor unit is located on the j-th column wire.

3. The linear equation system solver according to claim 2, characterized in that, m = n.

4. The linear equation system solver according to claim 2 or 3, characterized in that, The memristor unit includes at least one memristor.

5. The linear equation system solver according to claim 4, characterized in that, When the number of the memristors is multiple, different memristors can be connected by a preset connection method, and the preset connection method includes any one of the following: a parallel connection method, a series connection method, and a series-parallel combination connection method.

6. The linear equation system solver according to claim 2, characterized in that, The voltage regulating circuit includes: m voltage regulating branches; wherein, the output end of the i-th voltage regulating branch is connected to the input end of the i-th row of wires.

7. The linear equation system solver according to claim 6, characterized in that, The voltage regulating branch includes a digital-to-analog converter and an amplifier connected in sequence; The input end of the digital-to-analog converter is connected to the control circuit, and the output end of the amplifier is the output end of the voltage regulating branch.

8. A method for solving a linear equation system, characterized in that, A control circuit applied to a linear equation solver includes: Obtaining a target linear equation set; wherein, the target linear equation set includes a constant matrix and a coefficient matrix; Adjusting the parameters of the memristor array according to the coefficient matrix, and adjusting the parameters of the voltage regulating circuit according to the constant matrix and the coefficient matrix, to obtain a target circuit composed of the adjusted memristor array and the adjusted voltage regulating circuit; Obtaining the voltage values of the voltage signals output on each column of the adjusted memristor array, forming a vector, and outputting the vector as the solution result of the target linear equation set.

9. The method according to claim 8, characterized in that, The adjusting the parameters of the memristor array according to the coefficient matrix includes: Adjusting the conductance values of the respective memristor units in the memristor array respectively according to the respective coefficients in the coefficient matrix.

10. The method according to claim 8, characterized in that, The adjusting the parameters of the voltage regulating circuit according to the constant matrix and the coefficient matrix includes: Determining the voltage value of the voltage signal output by the voltage regulating circuit according to the constant matrix and the coefficient matrix.

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