Chamfering rule and OPC model determination method, system, equipment and medium
By determining the mapping relationship between chamfer parameters and dimensional parameters, the pattern distortion problem of OPC model after photoresist exposure imaging is solved, and the accuracy of the OPC model and the accuracy of the lithography preparation process are improved.
Patent Information
- Application Number
- CN202311761345.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-20
- Publication Date
- 2025-06-20
AI Technical Summary
After photoresist exposure imaging, the graphics are prone to distortion, and existing OPC models are difficult to accurately correct this effect, resulting in inconsistent graphics obtained on the silicon wafer with the design.
By obtaining multiple test figures with different size parameters, the chamfered shape corresponding to each test figure and its chamfered parameters are determined, and the mapping relationship between chamfered parameters and size parameters is established, thereby determining the chamfered rules in the OPC model.
The accuracy of the OPC model is improved, ensuring that the graphics obtained on the silicon wafer are consistent with the design, and improving the accuracy of the lithography preparation process.
Smart Images
Figure CN120181017A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and particularly to a method, system, device, and medium for determining a chamfering rule and an OPC model. Background Art
[0002] Light diffraction causes pattern distortion after lithographic exposure and imaging. By appropriately modifying the pattern on the mask to compensate for this effect, a pattern identical to the design can be obtained on the silicon wafer. This correction is called Optical Proximity Correction (OPC).
[0003] During the OPC correction process, the establishment of the OPC model is crucial. The correction of the mask pattern is based on the simulation of the OPC model and is achieved through a large number of iterations. Summary of the Invention
[0004] Based on this, it is necessary to provide a method, system, device, and medium for determining a chamfering rule and an OPC model.
[0005] To achieve the above object, in a first aspect, the present invention provides a method for determining a chamfering rule, which is characterized by including:
[0006] Obtain a plurality of test patterns, wherein the size parameters of the plurality of test patterns are different;
[0007] Determine the chamfered pattern corresponding to each test pattern and the chamfering parameters of the chamfered pattern;
[0008] Determine the mapping relationship between the chamfering parameters and the size parameters.
[0009] In one embodiment, the plurality of test patterns are arranged at intervals along a first direction;
[0010] The widths of the plurality of test patterns increase sequentially along the first direction, and / or the width spacing between adjacent test patterns along the first direction increases sequentially.
[0011] In one embodiment, the size parameters include width and / or width spacing. The determining the mapping relationship between the chamfering parameters and the size parameters includes:
[0012] According to the width of each test pattern in the first direction, determine the width interval of each test pattern in the first direction;
[0013] According to the chamfering parameters corresponding to the plurality of test patterns and the width intervals, determine the mapping relationship between the plurality of chamfering parameters and the plurality of width intervals;
[0014] And / or
[0015] Determine a plurality of first spacing intervals corresponding to the plurality of test patterns according to the width spacing in the first direction between every two adjacent ones of the plurality of test patterns;
[0016] Determine the mapping relationship between the plurality of chamfer parameters and the plurality of first spacing intervals according to the plurality of chamfer parameters corresponding to the plurality of test patterns and the plurality of first spacing intervals.
[0017] In one embodiment, the plurality of test patterns are arranged at intervals in a second direction perpendicular to the first direction;
[0018] The lengths of the plurality of test patterns increase in sequence in the second direction, and / or the length spacing between adjacent ones of the plurality of test patterns in the second direction increases in sequence.
[0019] In one embodiment, the dimension parameter includes length and / or length spacing, and determining the mapping relationship between the chamfer parameter and the dimension parameter includes:
[0020] Determine the length interval in the second direction of each test pattern according to the length of each test pattern in the second direction;
[0021] Determine the mapping relationship between the plurality of chamfer parameters and the plurality of length intervals according to the plurality of chamfer parameters corresponding to the plurality of test patterns and the length intervals;
[0022] and / or
[0023] Determine a plurality of second spacing intervals corresponding to the plurality of test patterns according to the length spacing in the second direction between every two adjacent ones of the plurality of test patterns;
[0024] Determine the mapping relationship between the plurality of chamfer parameters and the plurality of second spacing intervals according to the plurality of chamfer parameters corresponding to the plurality of test patterns and the plurality of second spacing intervals.
[0025] In one embodiment, determining the chamfered pattern corresponding to each test pattern and the chamfer parameter of the chamfered pattern includes:
[0026] Perform exposure and development processing on each test pattern to obtain a photolithography pattern corresponding to each test pattern;
[0027] Scan each photolithography pattern to obtain the chamfered pattern corresponding to each test pattern;
[0028] Determine the chamfer parameter of the chamfered pattern corresponding to each test pattern.
[0029] In one embodiment, the chamfered pattern is a contour map obtained by scanning the lithography pattern and extracting it.
[0030] In one embodiment, the chamfer parameters include the chamfer curvature radius of the chamfered pattern and the correction length of the chamfered pattern.
[0031] In a second aspect, the present invention provides a method for determining an OPC model, including:
[0032] Obtaining an initial OPC model;
[0033] Determining the chamfer parameters matching the initial OPC model according to the chamfer rules, where the chamfer rules are determined according to the determination method of the chamfer rules described in the first aspect;
[0034] Performing chamfer processing on the initial OPC model according to the chamfer parameters matching the initial OPC model to obtain a corrected OPC model.
[0035] In a third aspect, the present invention provides a system for determining chamfer rules, including:
[0036] An acquisition module for acquiring a plurality of test patterns, where the size parameters of the plurality of test patterns are different;
[0037] A chamfer module for determining the chamfered pattern corresponding to each test pattern and the chamfer parameters of the chamfered pattern;
[0038] A determination module for determining the mapping relationship between the chamfer parameters and the size parameters.
[0039] In one embodiment, the chamfer module includes:
[0040] A lithography unit for exposing and developing each test pattern to obtain the lithography pattern corresponding to each test pattern;
[0041] A scanning unit for scanning each lithography pattern to obtain the chamfered pattern corresponding to each test pattern;
[0042] A chamfer parameter measurement unit for determining the chamfer parameters of the chamfered pattern corresponding to each test pattern.
[0043] In one embodiment, the determination module includes:
[0044] A first determination unit for determining the width interval of each test pattern in the first direction according to the width of each test pattern in the first direction;
[0045] Determine the mapping relationship between multiple chamfer parameters and multiple width intervals according to the chamfer parameters and the width intervals corresponding to multiple test patterns;
[0046] and / or,
[0047] The first determination unit is configured to determine multiple first spacing intervals corresponding to multiple test patterns according to the width spacing in the first direction between every two adjacent test patterns among multiple test patterns;
[0048] Determine the mapping relationship between multiple chamfer parameters and multiple first spacing intervals according to the chamfer parameters and multiple first spacing intervals corresponding to multiple test patterns.
[0049] In one embodiment, the determination module further includes:
[0050] A second determination unit, configured to determine the length interval of each test pattern in the second direction according to the length of each test pattern in the second direction;
[0051] Determine the mapping relationship between multiple chamfer parameters and multiple length intervals according to the chamfer parameters and the length intervals corresponding to multiple test patterns;
[0052] and / or,
[0053] The second determination unit is configured to determine multiple second spacing intervals corresponding to multiple test patterns according to the length spacing in the second direction between every two adjacent test patterns among multiple test patterns;
[0054] Determine the mapping relationship between multiple chamfer parameters and multiple second spacing intervals according to the chamfer parameters and multiple second spacing intervals corresponding to multiple test patterns.
[0055] In a fourth aspect, the present invention provides a determination system for an OPC model, including:
[0056] A modeling module, configured to obtain an initial OPC model;
[0057] A chamfer parameter determination module, configured to determine chamfer parameters matching the initial OPC model according to chamfer rules;
[0058] A correction module, configured to perform chamfer processing on the initial OPC model according to the chamfer parameters matching the initial OPC model to obtain a corrected OPC model.
[0059] Fifth aspect, the present invention provides an electronic device, including at least one memory and at least one processor, wherein the memory stores one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the chamfering rule determination method as described in the first aspect.
[0060] Sixth aspect, the present invention provides a storage medium storing one or more computer instructions for implementing the chamfering rule determination method as described in the first aspect.
[0061] The chamfering rule and the determination method, system, device, and medium of the OPC model of the present invention determine the chamfering rule of the mapping relationship between chamfering parameters and dimension parameters. The chamfering rule can be applied to the establishment process of OPC model modeling, providing corresponding chamfering parameters for graphics of different dimensions in the OPC model, and improving the accuracy of the OPC model. Description of the Drawings
[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for description in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0063] Figure 1 It is a flowchart of the chamfering rule determination method provided in an embodiment.
[0064] Figure 2 It is a flowchart of determining the chamfered graphics corresponding to each test graphic and the chamfering parameters of the chamfered graphics provided in an embodiment.
[0065] Figure 3 It is a flowchart of determining the mapping relationship between chamfering parameters and dimension parameters provided in an embodiment.
[0066] Figure 4 It is a flowchart of determining the mapping relationship between chamfering parameters and dimension parameters provided in another embodiment.
[0067] Figure 5 It is a flowchart of determining the mapping relationship between chamfering parameters and dimension parameters provided in yet another embodiment.
[0068] Figure 6 It is a flowchart of determining the mapping relationship between chamfering parameters and dimension parameters provided in the fourth embodiment.
[0069] Figure 7 It is a schematic diagram of multiple test graphics provided in an embodiment.
[0070] Figure 8 Schematic diagram of a plurality of chamfered patterns corresponding to a plurality of test patterns provided in an embodiment.
[0071] Figure 9 Schematic diagram of a chamfered pattern provided in an embodiment.
[0072] Figure 10 Flowchart of a method for determining an OPC model provided in an embodiment.
[0073] Figure 11 Schematic diagram of an initial OPC model provided in an embodiment.
[0074] Figure 12 Schematic diagram of a corrected OPC model provided in an embodiment.
[0075] Figure 13 Block diagram of a system for determining a chamfering rule provided in an embodiment.
[0076] Figure 14 Block diagram of a system for determining an OPC model provided in an embodiment.
[0077] Figure 15 Block diagram of an electronic device provided in an embodiment. Detailed implementation manners
[0078] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0079] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.
[0080] The OPC model is to simulate the pattern formed on the wafer after the pattern designed on the photomask is projected based on information such as the relevant parameters of the optical system, the photoresist and film layer information parameters on the wafer, and the transmittance parameter of the photomask. The OPC model is crucial for the OPC correction process of the layout.
[0081] The OPC model is used for process simulation in the lithography preparation process of semiconductor devices. The OPC model can simulate the photoresist profile under the optimal process conditions, the photoresist profiles with energy offset and focus offset, the process variation bandwidth PV-band, the mask error enhancement factor MEEF, the photoresist imaging contrast, etc. Accurate OPC model prediction can accelerate the R & D speed of semiconductor devices.
[0082] The OPC model can be divided into two modules: the optical model and the photoresist model. The optical model can be simply understood as a fixed calculation process of the Fourier transform of the mask layout and the light intensity distribution on the wafer surface. The shape of the mask layout directly affects the OPC model. When manufacturing the mask, an electron beam exposure system is used. This process is affected by factors such as shot blur, photoresist resolution, and proximity effect, resulting in a rounded corner instead of an ideal right-angled shape at the corner, which is called the mask corner rounding effect.
[0083] When traditional OPC modeling is performed, the input mask layout is Manhattan-type (all edges are horizontal and vertical), and the chamfering (mask corner rounding) parameter of the mask layout is output as a fixed value / average value. However, the spot size of the actual mask manufacturing will switch according to the mask shape, resulting in different mask chamfers for different patterns.
[0084] The embodiments of the present disclosure will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure and should not be construed as limiting the present disclosure.
[0085] A method for determining a chamfering rule provided by an embodiment of the present disclosure, as Figure 1 shows a flowchart of the method for determining the chamfering rule of this exemplary embodiment. The method for determining the chamfering rule includes the following steps:
[0086] Step S10: Obtain a plurality of test patterns, where the size parameters of the plurality of test patterns are different.
[0087] Step S20: Determine the chamfered pattern corresponding to each test pattern and the chamfering parameter of the chamfered pattern.
[0088] Step S30: Determine the mapping relationship between the chamfering parameter and the size parameter.
[0089] The method for determining the chamfering rule of this embodiment determines the mapping relationship between the chamfering parameter and the size parameter, which can be applied to the establishment process of OPC model modeling, provides corresponding chamfering parameters for patterns of different sizes in the OPC model, and improves the accuracy of the OPC model.
[0090] In step S10, referring to Figure 7 , a plurality of test patterns 11 are designed on a design layout. The size parameters of the plurality of test patterns 11 are different, and the plurality of test patterns 11 are arranged at intervals. Each test pattern 11 is a square, a rectangle, or other regular pattern with right angles at the corners. The size parameters of the plurality of test patterns 11 are different.
[0091] In some embodiments, the size parameters include the width W and / or the width pitch S. For example, the widths of the plurality of test patterns 11 are different, or the width pitch S between adjacent test patterns 11 among the plurality of test patterns 11 is different.
[0092] Referring to Figure 7 , the plurality of test patterns 11 are arranged at intervals along the first direction D1. The widths of the plurality of test patterns 11 increase in sequence along the first direction D1, and / or the width pitch S between adjacent test patterns 11 along the first direction D1 increases in sequence along the first direction D1. For example, the widths W of the plurality of test patterns 11 can increase in sequence along the first direction D1. Or, the width pitch S between adjacent test patterns 11 increases in sequence along the first direction D1. Or, the widths W of the plurality of test patterns 11 increase in sequence along the first direction D1, and the width pitch S between adjacent test patterns 11 increases in sequence along the first direction D1.
[0093] In some examples, the plurality of test patterns 11 are arranged in several rows along the first direction D1. Along the first direction D1, the widths W of the test patterns 11 in the same row are the same, and the width pitch S between adjacent test patterns 11 in the same row increases in sequence.
[0094] In some examples, along the first direction, the width pitch S between adjacent test patterns 11 in the same row is the same, and the widths W of the test patterns 11 in the same row increase in sequence.
[0095] In some examples, along the first direction D1, the widths W of the test patterns 11 in the same row increase in sequence, and the width pitch S between adjacent test patterns 11 in the same row increases in sequence.
[0096] In some embodiments, the size parameters include the length H and / or the length pitch K. For example, the lengths H of the plurality of test patterns 11 are different, or the length pitch K between adjacent test patterns 11 among the plurality of test patterns 11 is different.
[0097] Referring to Figure 7 , the plurality of test patterns 11 are arranged at intervals along a second direction D2 perpendicular to the first direction D1; along the second direction D2, the lengths H of the plurality of test patterns 11 increase in sequence, and / or the length pitch K between adjacent test patterns 11 along the second direction D2 increases in sequence.
[0098] For example, the lengths of a plurality of test patterns 11 arranged along the second direction D2 can increase sequentially. Alternatively, the length spacing K between adjacent test patterns 11 along the second direction D2 can increase sequentially. Alternatively, the lengths of a plurality of test patterns 11 arranged along the second direction D2 increase sequentially, and the length spacing K between adjacent test patterns 11 along the second direction D2 increases sequentially.
[0099] In some examples, the test pattern 11 is a square, and one of the extending directions of two mutually perpendicular sides of the test pattern 11 can be used as the first direction D1, and the other extending direction of the two sides can be used as the second direction D2.
[0100] In some examples, the test pattern 11 is a rectangle, and the extending direction of the long side of the test pattern 11 can be used as the first direction D1, and the extending direction of the short side of the test pattern 11 can be used as the second direction D2.
[0101] In some examples, the test pattern 11 is a regular pattern with a right angle at the corner, and the extending direction of a pair of diagonals of the test pattern 11 can be used as the first direction D1, and the second direction D2 perpendicular to the first direction D1 is defined according to the first direction D1.
[0102] In some examples, a plurality of test patterns 11 are arranged in several columns along the second direction D2. The lengths H of the test patterns 11 in the same column are the same, and the length spacing K between adjacent test patterns 11 in the same column increases sequentially.
[0103] In some examples, the length spacing K between adjacent test patterns 11 in the same column is the same, and the lengths H of the test patterns 11 in the same column increase sequentially.
[0104] In some examples, the lengths H of the test patterns 11 in the same column increase sequentially, and the length spacing K between adjacent test patterns 11 in the same column increases sequentially.
[0105] In some embodiments, referring to Figure 7 , a plurality of test patterns 11 are arranged in several rows along the first direction D1, and the plurality of test patterns 11 are arranged at intervals along the first direction D1. At the same time, a plurality of test patterns 11 are arranged in several columns along the second direction D2 perpendicular to the first direction D1, and the plurality of test patterns 11 are arranged at intervals along the second direction D2.
[0106] As Figure 7 shown, a plurality of test patterns 11 can be designed on the design layout. The plurality of test patterns 11 are arranged in m rows along the first direction D1 and in n columns along the second direction D2 perpendicular to the first direction D1. The plurality of test patterns 11 are arranged at intervals along the first direction D1 and at intervals along the second direction D2. Among them, both m and n are positive integers greater than 1.
[0107] The test patterns 11 in the same row, the widths W of the test patterns 11 along the first direction D1 are W1, W2... Wm in sequence, and W1 - Wm increase in sequence. The width spacings S between adjacent test patterns 11 along the first direction D1 are S1, S2... Sm-1 in sequence and increase in sequence.
[0108] The test patterns 11 in the same column, the lengths H of the test patterns 11 along the second direction D2 are H1, H2... Hn in sequence, and H1 - Hn increase in sequence. The length spacings K between adjacent test patterns 11 along the second direction D2 are K1, K2... Kn-1 in sequence and increase in sequence.
[0109] In step S20, determine the chamfered patterns corresponding to each test pattern and the chamfer parameters of the chamfered patterns, as Figure 2 described, including the following steps:
[0110] Step S21: Expose and develop each test pattern to obtain the photolithographic pattern corresponding to each test pattern.
[0111] Step S22: Scan each photolithographic pattern to obtain the chamfered pattern corresponding to each test pattern.
[0112] Step S23: Determine the chamfer parameters of the chamfered pattern corresponding to each test pattern.
[0113] In step S21, referring to Figure 7 、 Figure 8 According to the designed layout after designing multiple test patterns 11, design the layout on a test reticle, and obtain multiple photolithographic patterns (not shown in the figure) on the test reticle. The multiple photolithographic patterns include the photolithographic pattern corresponding to each test pattern 11. Through the processes of exposure and development, rounded corners are formed at the corners of the photolithographic pattern.
[0114] In step S22, a scanning electron microscope (SEM) can be used to scan each photolithographic pattern to obtain the chamfered pattern 21 corresponding to each test pattern 11.
[0115] In some embodiments, referring to Figure 7 、 Figure 8 The chamfered pattern 21 is a contour map obtained by scanning and extracting the photolithographic pattern. Use a scanning electron microscope to scan multiple photolithographic patterns to obtain a scanned image, and then extract the contour map corresponding to each photolithographic pattern in the scanned image. For example, contour extraction software can be used to extract the contour map corresponding to each photolithographic pattern in the scanned image to obtain the chamfered pattern 21 corresponding to each test pattern 11.
[0116] In step S23, chamfering parameters C of the chamfered figure 21 corresponding to each test figure 11 are extracted. The chamfering parameters C include the chamfering curvature radius R of the chamfered figure 21 and the correction length L of the chamfered figure.
[0117] In some embodiments, referring to Figure 7 , Figure 8 , Figure 9 , the chamfering curvature radius R of the chamfered figure 21 includes at least the chamfering curvature radius of any point of the chamfered figure.
[0118] The correction length L of the chamfered figure 21 includes a first correction length L1 of the corner of the chamfered figure 21 relative to its corresponding test figure 11 along the first direction D1, and a second correction length L2 of the corner of the chamfered figure 21 relative to its corresponding test figure 11 along the second direction D2.
[0119] In some embodiments, each test figure 11 is a rectangle, and the chamfered figure 21 corresponding to each test figure 11 is an ellipse or an ellipse-like figure.
[0120] In step S30, the mapping relationship between the chamfering parameters C and the dimension parameters can be determined according to dimension parameters such as the width, length, and figure density of the test figure 11.
[0121] In some embodiments, the dimension parameter includes the width W. Determining the mapping relationship between the chamfering parameters C and the dimension parameters, as Figure 3 shown, includes:
[0122] Step S31: According to the width of each test figure in the first direction, determine the width interval of each test figure in the first direction.
[0123] Referring to Figure 7 , Figure 8 , Figure 9 , along the arrangement order in the first direction, using the width W of each test figure 11 and the width W of the test figure 11 preceding it as the value range, determine the width interval of each test figure 11 in the first direction D1.
[0124] For example, arrange m test patterns 11 along the first direction D1. The widths of the m test patterns 11 along the first direction D1 are W1, W2... Wm in sequence, and W1 - Wm increase in sequence. For the m test patterns 11, the width of the first test pattern 11 from left to right is W1, and there are no other test patterns 11 before the first test pattern D1. Then the width interval of the first test pattern 11 is [0, W1]. The width of the second test pattern 11 from left to right is W2. Then the width interval of the second test pattern 11 is [W1, W2]. Thus, according to the widths of the m test patterns 11, determine the width intervals [0, W1], [W1, W2]... [Wm - 1, Wm] of the m test patterns 11.
[0125] Step S32: Determine the mapping relationship between multiple chamfering parameters and multiple width intervals according to the chamfering parameters and width intervals corresponding to multiple test patterns.
[0126] Refer to Figure 7 、 Figure 8 、 Figure 9 . Arrange m test patterns 11 along the first direction D1 corresponding to m chamfered patterns 21. The chamfering parameters of the m chamfered patterns 21 are C1, C2... Cm respectively.
[0127] Establish a mapping relationship between the m chamfering parameters C corresponding to the m test patterns 11 and the m width intervals corresponding to the m test patterns 11. The m chamfering parameters C and the m width intervals are mapped in a one-to-one correspondence.
[0128] In some embodiments, the dimension parameter includes the width spacing S. Determine the mapping relationship between the chamfering parameter C and the dimension parameter. As Figure 4 shown, it includes:
[0129] Step S33: Determine multiple first spacing intervals corresponding to multiple test patterns according to the width spacing between every two adjacent test patterns among multiple test patterns in the first direction.
[0130] Refer to Figure 7 、 Figure 8 、 Figure 9 . According to the arrangement order along the first direction D1, take the width spacing S between each test pattern 11 and the test pattern 11 in its previous order in the first direction D1 and the width spacing S between the test pattern 11 in its subsequent order in the first direction D1 as the value range to determine the first spacing interval corresponding to each test pattern 11.
[0131] For example, arrange m test patterns 11 along the first direction D1. The width spacings S between m adjacent test patterns 11 along the first direction D1 are S1, S2, …, Sm-1 in increasing order. The width spacing between the first test pattern 11 and the second test pattern 11 is S1, and there is no other test pattern 11 in front of the first test pattern 11. Then, the first spacing interval corresponding to the first test pattern 11 is [0, S1]. The width spacing between the second test pattern 11 and the third test pattern 11 is S2. Then, the first spacing interval corresponding to the second test pattern 11 is [S1, S2]. Thus, according to the width spacings of the m test patterns 11, determine multiple first spacing intervals [0, S1], [S1, S2], …, [Sm-1, +∞] corresponding to the m test patterns 11.
[0132] Step S34: Determine the mapping relationship between multiple chamfer parameters and multiple first spacing intervals according to the chamfer parameters corresponding to multiple test patterns and the multiple first spacing intervals.
[0133] Refer to Figure 7 、 Figure 8 、 Figure 9 , arrange m test patterns 11 along the first direction D1 corresponding to m chamfered patterns 21. The chamfer parameters of the m chamfered patterns 21 are C1, C2, …, Cm respectively.
[0134] Establish a mapping relationship between the m chamfer parameters C corresponding to the m test patterns 11 and the m first spacing intervals corresponding to the m test patterns 11. The m chamfer parameters and the m first spacing intervals are mapped one-to-one.
[0135] In some embodiments, refer to Figure 7 、 Figure 8 、 Figure 9 , the dimension parameters include the width W and the width spacing S. Determine the mapping relationship between the chamfer parameter C and the dimension parameters, and execute steps S31 - S34. Establish a mapping relationship between the m chamfer parameters C corresponding to the m test patterns 11 and the m width intervals [0, W1], [W1, W2], …, [Wm-1, Wm] corresponding to the m test patterns 11, and establish a mapping relationship between the m chamfer parameters C corresponding to the m test patterns 11 and the m first spacing intervals [0, S1], [S1, S2], …, [Sm-1, +∞] corresponding to the m test patterns 11. In this embodiment, the mapping relationship between the chamfer parameter C and the width interval and the first spacing interval is shown in Table 1.
[0136] Table 1 Mapping relationship table of chamfer parameters and width intervals and first spacing intervals
[0137]
[0138] In some embodiments, the dimensional parameter includes a length H, and a mapping relationship between the chamfer parameter C and the dimensional parameter is determined, as Figure 5 shown, including:
[0139] Step S35: Determine the length intervals of each test pattern in the second direction according to the length of each test pattern in the second direction.
[0140] Referring to Figure 7 、 Figure 8 、 Figure 9 , along the arrangement order in the second direction D2, take the length H of each test pattern 11 and the length range of the test pattern 11 in front of it in the second direction D2 as the value range to determine the length interval corresponding to each test pattern 11.
[0141] For example, arrange n test patterns 11 along the second direction D2, and the lengths of the n test patterns along the second direction D2 are H1, H2... Hn in sequence, and H1 - Hn increase in sequence. According to the lengths of the n test patterns 11, determine multiple length intervals [0, H1], [H1, H2]... [Hn - 1, Hn] corresponding to the n test patterns 11.
[0142] Step S36: Determine the mapping relationship between multiple chamfer parameters and multiple length intervals according to the chamfer parameters and length intervals corresponding to multiple test patterns.
[0143] Referring to Figure 7 、 Figure 8 、 Figure 9 , arrange n test patterns 11 along the second direction D2 corresponding to n chamfered patterns 21, and the chamfer parameters of the n chamfered patterns are C1, C2... Cn respectively.
[0144] Establish a mapping relationship between the n chamfer parameters C corresponding to the n test patterns 11 and the n length intervals corresponding to the n test patterns 11, and the n chamfer parameters C and the n length intervals are mapped one-to-one.
[0145] In some embodiments, the dimensional parameter includes a length spacing K, and a mapping relationship between the chamfer parameter C and the dimensional parameter is determined, as Figure 6 shown, including:
[0146] Step S37: Determine multiple second spacing intervals corresponding to multiple test patterns according to the length spacing between every two adjacent test patterns in the second direction among multiple test patterns.
[0147] Referring to Figure 7 、 Figure 8 、 Figure 9, according to the arrangement order in the second direction D2, take the length spacing K between each test pattern 11 and the test pattern 11 preceding it in the second direction D2 and the length spacing K between the test pattern 11 and the test pattern 11 following it in the second direction D2 as the value range, and determine the corresponding second spacing interval for each test pattern 11.
[0148] For example, arrange n test patterns 11 in the second direction D2. The length spacings between adjacent test patterns 11 in the second direction D2 are K1, K2... Kn-1 in sequence and increase in sequence. According to the length spacings of the n test patterns, determine the multiple second spacing intervals [0, K1], [K1, K2]... [Kn-1, +∞] corresponding to the n test patterns 11.
[0149] Step S38: According to the chamfer parameters corresponding to the multiple test patterns and the multiple second spacing intervals, determine the mapping relationship between the multiple chamfer parameters and the multiple second spacing intervals.
[0150] Refer to Figure 7 、 Figure 8 、 Figure 9 , establish a mapping relationship between the n chamfer parameters C corresponding to the n test patterns 11 and the n second spacing intervals corresponding to the n test patterns 11. The n chamfer parameters C and the n second spacing intervals are mapped one-to-one.
[0151] In some embodiments, refer to Figure 7 、 Figure 8 、 Figure 9 , the dimension parameters include the length H and the length spacing K. Determine the mapping relationship between the chamfer parameter C and the dimension parameters, and execute steps S35 - S38. Establish a mapping relationship between the n chamfer parameters C corresponding to the n test patterns 11 and the n length intervals [0, H1], [H1, H2]... [Hn-1, Hn] corresponding to the n test patterns 11, and establish a mapping relationship between the n chamfer parameters C corresponding to the n test patterns 11 and the n second spacing intervals [0, K1], [K1, K2]... [Kn-1, +∞] corresponding to the n test patterns 11. In this embodiment, the mapping relationship between the chamfer parameter C and the width interval and the first spacing interval is shown in Table 2.
[0152] Table 2 Mapping relationship table of chamfer parameter and width interval, first spacing interval
[0153]
[0154] In some embodiments, the dimension parameters include the width W, the width spacing S, the length H, and the length spacing K. Determine the mapping relationship between the chamfer parameter C and the dimension parameters, and execute steps S31 - S38. Determine the mapping relationship between the chamfer parameter C and the width interval, length interval, first spacing region, and second spacing interval corresponding to the test pattern 11.
[0155] The method for determining the chamfering rule in this embodiment determines the mapping relationship between chamfering parameters and dimension parameters, which can be applied to the establishment process of OPC model modeling, provides corresponding chamfering parameters for graphics with different dimensions in the OPC model, and improves the accuracy of the OPC model.
[0156] According to an exemplary embodiment, this embodiment provides a method for determining an OPC model, as Figure 10 shows a flowchart of the method for determining the OPC model of this exemplary embodiment. The method for determining the OPC model includes the following steps:
[0157] Step S100: Obtain an initial OPC model.
[0158] Step S200: Determine the chamfering parameters matching the initial OPC model according to the chamfering rule.
[0159] Step S300: Perform chamfering processing on the initial OPC model according to the chamfering parameters matching the initial OPC model to obtain a corrected OPC model.
[0160] In step S110, as Figure 11 shown, the initial OPC model 100 includes a plurality of initial graphics 110. The dimensions of the plurality of initial graphics 110 are different, and each initial graphic 110 has a plurality of right-angle corners.
[0161] In step S120, the chamfering rule in this embodiment is determined according to the method for determining the chamfering rule in the above embodiment. The chamfering rule includes the mapping relationship between chamfering parameter C and dimension parameter. The corresponding dimension parameter in the chamfering rule is found according to the dimension of each initial graphic 110, and then the corresponding chamfering parameter C of each initial graphic 110 is determined.
[0162] In step S130, as Figure 12 shown, the initial graphic 110 is corrected according to the chamfering parameter C corresponding to the initial graphic 110 to obtain a corrected graphic 210. The corners of the corrected graphic 210 are rounded. The corrected OPC model 200 includes a plurality of corrected graphics 210.
[0163] The method for determining the OPC model in this embodiment, by determining the chamfering rule of chamfering parameters and dimension parameters, performs curve processing on the initial OPC model according to the chamfering rule, determines the corresponding chamfering parameters according to the dimensions of the initial graphics in the initial OPC model, and obtains a corrected OPC model after curve processing of each initial graphic of the initial OPC model. The graphic accuracy of the corrected OPC model is higher.
[0164] According to an exemplary embodiment, this embodiment provides a system for determining a chamfering rule, asFigure 13 As shown in Figure 13 , the chamfering rule determination system includes an acquisition module 310, a chamfering module 320, and a determination module 330. The acquisition module 310 is configured to acquire a plurality of test patterns, where the size parameters of the plurality of test patterns are different. The chamfering module 320 is configured to determine the chamfered patterns corresponding to each test pattern and the chamfering parameters of the chamfered patterns. The determination module 330 is configured to determine the mapping relationship between the chamfering parameters and the size parameters.
[0165] In some embodiments, as Figure 13 shown in Figure 13 , the chamfering module 320 includes a photolithography unit 321, a scanning unit 322, and a chamfering parameter measurement unit 323. The photolithography unit 321 is configured to perform exposure and development processes on each test pattern to obtain the photolithography pattern corresponding to each test pattern. The scanning unit 322 is configured to scan each photolithography pattern to obtain the chamfered pattern corresponding to each test pattern. The chamfering parameter measurement unit 323 is configured to determine the chamfering parameters of the chamfered patterns corresponding to each test pattern.
[0166] In some embodiments, as Figure 13 shown in Figure 13 , the determination module 330 includes a first determination unit 331. The first determination unit 331 is configured to determine the width interval of each test pattern in the first direction according to the width of each test pattern in the first direction; determine the mapping relationship between a plurality of chamfering parameters and a plurality of width intervals according to the chamfering parameters and the width intervals corresponding to the plurality of test patterns; and / or, the first determination unit 331 is configured to determine the plurality of first spacing intervals corresponding to the plurality of test patterns according to the width spacing between every two adjacent test patterns in the first direction among the plurality of test patterns; determine the mapping relationship between a plurality of chamfering parameters and a plurality of first spacing intervals according to the chamfering parameters and the plurality of first spacing intervals corresponding to the plurality of test patterns.
[0167] In some embodiments, as Figure 13 shown in Figure 13 , the determination module 330 further includes a second determination unit 332. The second determination unit 332 is configured to determine the length interval of each test pattern in the second direction according to the length of each test pattern in the second direction; determine the mapping relationship between a plurality of chamfering parameters and a plurality of length intervals according to the chamfering parameters and the length intervals corresponding to the plurality of test patterns; and / or, the second determination unit 332 is configured to determine the plurality of second spacing intervals corresponding to the plurality of test patterns according to the length spacing between every two adjacent test patterns in the second direction among the plurality of test patterns; determine the mapping relationship between a plurality of chamfering parameters and a plurality of second spacing intervals according to the chamfering parameters and the plurality of second spacing intervals corresponding to the plurality of test patterns.
[0168] According to an exemplary embodiment, this embodiment provides a determination system for an OPC model, as Figure 14As shown in the figure, the OPC model determination system includes a modeling module 410, a chamfer parameter determination module 420, and a correction module 430. The modeling module 410 is used to obtain an initial OPC model; the chamfer parameter determination module 420 is used to determine the chamfer parameters matching the initial OPC model according to the chamfer rules; the correction module 430 is used to perform chamfering on the initial OPC model according to the chamfer parameters matching the initial OPC model to obtain a corrected OPC model.
[0169] In addition, in the chamfer rule determination system and the OPC model determination system provided in some of the above embodiments, the terms "module" and "unit" used in this specification can be used to represent computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a "module" or "unit" can be, but is not limited to: a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. For example, a "module" or "unit" can execute from various computer-readable media on which various data structures are stored.
[0170] In the above embodiments provided by the present disclosure, it should be understood that the disclosed "module" or "unit" can be implemented in other ways. For example, the devices described above are merely illustrative. For example, the division of modules or units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple modules or units can be combined or integrated into another device, or some features can be ignored or not executed. And the described connections to each other can be through some interfaces, indirect coupling or communication connections of modules or units, which can be electrical, mechanical or other forms. The separately described units or modules may or may not be physically separated. Some or all of the units or modules can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present disclosure.
[0171] An exemplary embodiment of the present disclosure also provides an electronic device, such as Figure 15 As shown in the figure, the electronic device can be, for example, a mobile phone, a tablet computer, a laptop computer, etc. The electronic device includes at least one memory 501 and at least one processor 502. The memory 501 stores one or more computer instructions, wherein the one or more computer instructions are executed by the processor 502 to implement the chamfer rule determination method in any of the foregoing embodiments.
[0172] An exemplary embodiment of the present disclosure also provides a storage medium storing one or more computer instructions, and the one or more computer instructions are used to implement the chamfer rule determination method in any of the foregoing embodiments.
[0173] Those of ordinary skill in the art can understand that all or part of the processes in the above-described method embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a readable storage medium. When the computer program is executed, it can implement the processes of the method embodiments as described above. Among them, any reference to a memory or other medium used in the embodiments provided by the present disclosure may include at least one of non-volatile and volatile memories. Non-volatile memories may include read-only memory (ROM), floppy disks, flash memories, high-density embedded non-volatile memories, resistive random access memories (ReRAM), etc. Volatile memories may include random access memory (RAM) or external cache memories, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The processors involved in the embodiments provided by the present disclosure can be general-purpose processors, central processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.
[0174] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0175] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.
Claims
1. A method for determining a chamfering rule, characterized in that, Including: Obtain a plurality of test patterns, wherein the size parameters of the plurality of test patterns are different; Determine the chamfered pattern corresponding to each test pattern and the chamfering parameters of the chamfered pattern; Determine the mapping relationship between the chamfering parameters and the size parameters.
2. The method for determining a chamfering rule according to claim 1, characterized in that, The plurality of test patterns are arranged at intervals in a first direction; The widths of the plurality of test patterns increase sequentially in the first direction, and / or the width spacing between adjacent test patterns in the first direction increases sequentially.
3. The method for determining a chamfering rule according to claim 2, characterized in that, The size parameters include width and / or width spacing. Determining the mapping relationship between the chamfering parameters and the size parameters includes: According to the width of each test pattern in the first direction, determine the width interval of each test pattern in the first direction; According to the chamfering parameters corresponding to the plurality of test patterns and the width intervals, determine the mapping relationship between the plurality of chamfering parameters and the plurality of width intervals; and / or According to the width spacing between every two adjacent test patterns in the plurality of test patterns in the first direction, determine a plurality of first spacing intervals corresponding to the plurality of test patterns; According to the chamfering parameters corresponding to the plurality of test patterns and the plurality of first spacing intervals, determine the mapping relationship between the plurality of chamfering parameters and the plurality of first spacing intervals.
4. The method for determining a chamfering rule according to claim 2, characterized in that, The plurality of test patterns are arranged at intervals in a second direction perpendicular to the first direction; The lengths of the plurality of test patterns increase sequentially in the second direction, and / or the length spacing between adjacent test patterns in the second direction increases sequentially.
5. The method for determining a chamfering rule according to claim 4, characterized in that, The size parameters include length and / or length spacing. Determining the mapping relationship between the chamfering parameters and the size parameters includes: According to the length of each test pattern in the second direction, determine the length interval of each test pattern in the second direction; According to the chamfering parameters corresponding to the plurality of test patterns and the length intervals, determine the mapping relationship between the plurality of chamfering parameters and the plurality of length intervals; and / or According to the length spacing between every two adjacent test patterns in the plurality of test patterns in the second direction, determine a plurality of second spacing intervals corresponding to the plurality of test patterns; According to the chamfering parameters corresponding to the plurality of test patterns and the plurality of second spacing intervals, determine the mapping relationship between the plurality of chamfering parameters and the plurality of second spacing intervals.
6. The method for determining a chamfering rule according to any one of claims 1 - 5, characterized in that, Determining the chamfered pattern corresponding to each test pattern and the chamfering parameters of the chamfered pattern includes: Perform exposure and development processing on each test pattern to obtain a photolithography pattern corresponding to each test pattern; Scan each photolithography pattern to obtain the chamfered pattern corresponding to each test pattern; Determine the chamfering parameters of the chamfered pattern corresponding to each test pattern.
7. The method for determining a chamfering rule according to claim 6, characterized in that, The chamfered pattern is a contour pattern obtained by scanning the photolithography pattern and extracting it.
8. The method for determining a chamfering rule according to claim 7, characterized in that, The chamfering parameters include the chamfering curvature radius of the chamfered pattern and the correction length of the chamfered pattern.
9. A method for determining an OPC model, characterized in that, Including: Obtain an initial OPC model; Determine the chamfering parameters matching the initial OPC model according to the chamfering rule, where the chamfering rule is determined according to the determination method of any one of the chamfering rules in claims 1-8; Perform chamfering on the initial OPC model according to the chamfering parameters matching the initial OPC model to obtain a corrected OPC model.
10. A chamfering rule determination system, characterized in that Including: An acquisition module for acquiring a plurality of test patterns, where the size parameters of the plurality of test patterns are different; A chamfering module for determining the chamfered pattern corresponding to each test pattern and the chamfering parameters of the chamfered pattern; A determination module for determining the mapping relationship between the chamfering parameters and the size parameters.
11. The chamfering rule determination system according to claim 10, characterized in that The chamfering module includes: A lithography unit for exposing and developing each test pattern to obtain a lithography pattern corresponding to each test pattern; A scanning unit for scanning each lithography pattern to obtain the chamfered pattern corresponding to each test pattern; A chamfering parameter measurement unit for determining the chamfering parameters of the chamfered pattern corresponding to each test pattern.
12. The chamfering rule determination system according to claim 10, characterized in that The determination module includes: A first determination unit for determining the width interval of each test pattern in the first direction according to the width of each test pattern in the first direction; Determine the mapping relationship between the plurality of chamfering parameters and the plurality of width intervals according to the chamfering parameters corresponding to the plurality of test patterns and the width intervals; And / or, The first determination unit is used to determine a plurality of first spacing intervals corresponding to the plurality of test patterns according to the width spacing between every two adjacent test patterns in the plurality of test patterns in the first direction; Determine the mapping relationship between the plurality of chamfering parameters and the plurality of first spacing intervals according to the chamfering parameters corresponding to the plurality of test patterns and the plurality of first spacing intervals.
13. The chamfering rule determination system according to claim 12, characterized in that The determination module further includes: A second determination unit for determining the length interval of each test pattern in the second direction according to the length of each test pattern in the second direction; Determine the mapping relationship between the plurality of chamfering parameters and the plurality of length intervals according to the chamfering parameters corresponding to the plurality of test patterns and the length intervals; And / or, The second determination unit is used to determine a plurality of second spacing intervals corresponding to the plurality of test patterns according to the length spacing between every two adjacent test patterns in the plurality of test patterns in the second direction; Determine the mapping relationship between the plurality of chamfering parameters and the plurality of second spacing intervals according to the chamfering parameters corresponding to the plurality of test patterns and the plurality of second spacing intervals.
14. An OPC model determination system, characterized in that Including: A modeling module for acquiring an initial OPC model; A chamfering parameter determination module for determining the chamfering parameters matching the initial OPC model according to the chamfering rule; A correction module for performing chamfering on the initial OPC model according to the chamfering parameters matching the initial OPC model to obtain a corrected OPC model.
15. An electronic device, characterized in that Comprising at least one memory and at least one processor, the memory storing one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method for determining the chamfering rule according to any one of claims 1-8.
16. A storage medium, characterized in that The storage medium stores one or more computer instructions, and the one or more computer instructions are used to implement the method for determining the chamfering rule according to any one of claims 1-8.