Method for adjusting position and size of chip element

Abstract

The invention relates to a chip component position and size adjusting method, which comprises the following steps of: performing discretization processing according to a target size of each component in a to-be-arranged chip to obtain first discrete size data and second discrete size data of each component, according to the circuit topology of the to-be-arranged chip, the first discrete size data and the second discrete size data of each element and the target position data of each element, obtaining optimization index data and discrete performance data corresponding to each element; calculating the position gradient data of the optimization index data corresponding to each element relative to the target position data, obtaining the size gradient data of each element based on the discrete performance data corresponding to each element, and carrying out optimization processing according to the position gradient data and the size gradient data of each element, and obtaining the optimized target size data and target position data. By adopting the method, the efficiency of adjusting the position and the size of the chip element can be improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a method for adjusting the position and size of chip components. Background Art

[0002] In the process of integrated circuit design, the position and size of chip components will affect the performance of the chip. The above components refer to the basic units in the integrated circuit, and can also be called gate circuits; the components need to adjust their positions during the layout stage, and need to adjust the sizes of each component during the size adjustment stage, that is, the driving ability of the gate circuit. The layout will affect the performance of the integrated circuit in the wiring stage and the final stage. A good layout can make the electrical signals propagate along a more optimized path, thereby improving the performance and power consumption of the chip; moreover, a good layout rationalizes the distribution of integrated circuit components and reduces the possibility of subsequent wiring congestion caused by local congestion. For the component size, it represents the driving ability of the chip. A smaller driving ability means smaller power consumption and area consumption, but the performance in terms of timing and performance may be average. For the gate size of components with a larger driving ability, the power consumption and area consumption increase, but the advantages in timing and speed are obtained. Therefore, in order to meet the requirements of low power consumption and minimum area occupancy under the premise of meeting the timing target and the design rule target, it is necessary to comprehensively consider multiple targets to achieve a good optimization effect.

[0003] In the related art, the position adjustment and size adjustment of chip components are alternately performed multiple times to achieve the final design and optimization goals. Among them, after one round of layout is completed, the component size is optimized according to the timing information obtained from the optimized component position in the layout. After the component size is optimized, the previous layout may no longer be reasonable, including the possibility of component area increase causing position overlap, etc., so the position adjustment will be performed again. With the mutual alternate adjustments again and again, the chip indicators are continuously optimized.

[0004] However, the efficiency of the above method for adjusting the position and size of chip components is relatively low. Summary of the Invention

[0005] Based on this, it is necessary to provide a method for adjusting the position and size of chip components that can improve efficiency in view of the above technical problems.

[0006] In a first aspect, a method for adjusting the position and size of chip components is provided, including:

[0007] Performing discretization processing on the target size data of each component in the chip to be laid out, and obtaining the first discrete size data and the second discrete size data of each component;

[0008] According to the circuit topology of the chip to be placed, the first discrete size data and the second discrete size data of each component, and the target position data of each component, the optimization index data and the discrete performance data corresponding to each component are obtained, where the discrete performance data is intermediate data related to the target size data obtained during the process of obtaining the optimization index data;

[0009] Calculate the position gradient data of the optimization index data corresponding to each component with respect to the target position data;

[0010] Based on the discrete performance data corresponding to each component, obtain the size gradient data of the optimization index data corresponding to each component with respect to the target size data;

[0011] According to the position gradient data and the size gradient data of each component, optimize the target size data and the target position data of each component respectively to obtain the optimized target size data and target position data.

[0012] In one embodiment, the optimization index data includes wiring length data, timing data, load violation data, signal flip violation data, wiring density data, discretization loss data, and power consumption data;

[0013] According to the circuit topology of the chip to be placed, the first discrete size data and the second discrete size data of each component, and the target position data of each component, obtain the optimization index data corresponding to each component, including:

[0014] According to the circuit topology of the chip to be placed, obtain the directed acyclic graph data of the chip to be placed;

[0015] According to the target size data of each component, obtain the discretization loss data of each component;

[0016] According to the first discrete size data and the second discrete size data of each component and the power consumption mapping relationship corresponding to each component, obtain the power consumption data of each component;

[0017] According to the first discrete size data and the second discrete size data of each component, the target position data of each component, and the directed acyclic graph data, obtain the timing data, load violation data, and signal flip violation data of each component;

[0018] According to the target position data and the target size data of each component, obtain the wiring length data of each component;

[0019] According to the first discrete size data and the second discrete size data of each component and the target position data of each component, obtain the wiring density data of each component.

[0020] In one embodiment, based on the first discrete dimension data of each component, the second discrete dimension data, the target position data of each component, and the directed acyclic graph data, the timing data, load violation data, and signal flip violation data of each component are obtained, including:

[0021] According to the first discrete dimension data, the second discrete dimension data, and the pin capacitance mapping relationship, the received pin capacitance data corresponding to the component is obtained;

[0022] According to the directed acyclic graph data and the target position data of the component, the parasitic capacitance data corresponding to the component is determined;

[0023] According to the received pin capacitance data and the parasitic capacitance data of the component, the output capacitance data of the component is obtained;

[0024] Based on the output capacitance data and the timing delay model, the input delay data and impulse response data of the component are obtained;

[0025] According to the first discrete dimension data, the second discrete dimension data, the output capacitance data, the input voltage change rate, the impulse response data, and the non-linear delay model, the target in-gate delay data and signal flip data of the component are obtained;

[0026] According to the input delay data and the target in-gate delay data corresponding to the component, the timing data of the component is obtained;

[0027] According to the output capacitance data, the load violation data is obtained;

[0028] According to the signal flip data, the signal flip violation data is obtained.

[0029] In one embodiment, the dimension gradient data includes the power consumption dimension gradient data of the power consumption data of the component relative to the target dimension data of the component; the discrete performance data includes the first discrete power consumption data and the second discrete power consumption data;

[0030] In the process of obtaining the power consumption data of each component according to the first discrete dimension data, the second discrete dimension data of each component, and the power consumption mapping relationship corresponding to each component, it further includes: obtaining the first discrete power consumption data and the second discrete power consumption data of the component;

[0031] Based on the discrete performance data corresponding to each component, the dimension gradient data of the optimization index data corresponding to each component relative to the target dimension data is obtained, including:

[0032] According to the first discrete power consumption data and the second discrete power consumption data of the component, the power consumption dimension gradient data is obtained.

[0033] In one embodiment, the size gradient data includes density size gradient data of the wiring density data relative to the target size data of the components; the discrete performance data includes first discrete area data and second discrete area data;

[0034] Based on the discrete performance data corresponding to each component, obtaining the size gradient data of the optimization index data corresponding to each component relative to the target size data, including:

[0035] Obtaining the density size gradient data according to the first discrete area data, the second discrete area data, and the potential data.

[0036] In one embodiment, the size gradient data includes timing size gradient data of the timing data relative to the target size data of the components; the discrete performance data includes first discrete capacitance data, second discrete capacitance data, first discrete in-gate delay data, second discrete in-gate delay data, first discrete flip duration data, and second discrete flip duration data;

[0037] Based on the discrete performance data corresponding to each component, obtaining the size gradient data of the optimization index data corresponding to each component relative to the target size data, including:

[0038] Obtaining the first sub-timing size gradient data according to the first discrete capacitance data, the second discrete capacitance data, the receiving pin capacitance data, and the timing data;

[0039] Obtaining the second sub-timing size gradient data according to the first discrete in-gate delay data, the second discrete in-gate delay data, and the target in-gate delay data;

[0040] Obtaining the third sub-timing size gradient data according to the first discrete flip duration data, the second discrete flip duration data, and the signal flip data;

[0041] Obtaining the timing size gradient data according to the first sub-timing size gradient data, the second sub-timing size gradient data, and the third sub-timing size gradient data.

[0042] In one embodiment, according to the circuit topology of the chip to be laid out, the first discrete size data and the second discrete size data of each component, and the target position data of each component, obtaining the optimization index data corresponding to each component, including:

[0043] Obtaining a calibration factor, which is determined based on the ratio of the calibration index data and the external index data obtained during the calibration period;

[0044] Invoking an internal calculation engine to perform calculations based on the circuit topology of the chip to be laid out, the target size data of each component, and the target position data of each component to obtain initial index data;

[0045] Optimal index data is obtained based on the calibration factor and the initial index data.

[0046] In one embodiment, the target size data and target position data of each component are respectively optimized according to the position gradient data and size gradient data of each component to obtain the optimized target size data and target position data, including:

[0047] In the first cycle, the components with the number of layers less than the preset number of layers in the directed acyclic graph are determined as the components to be optimized, and the target size data and target position data of the components to be optimized are optimized according to the size gradient data and position gradient data of the components to be optimized to obtain the optimized target size data and target position data;

[0048] In the second cycle, the components with the number of layers greater than or equal to the preset number of layers in the directed acyclic graph are determined as the components to be optimized, and the target size data and target position data of the components to be optimized are optimized according to the size gradient data and position gradient data of the components to be optimized to obtain the optimized target size data and target position data.

[0049] In one embodiment, the process of optimizing the target size data of the components according to the size gradient data of each component to obtain the optimized target size data includes:

[0050] Determine the components whose gate sizes are to be optimized according to the size gradient data and size gradient threshold of each component;

[0051] Optimize the target size data of the components whose gate sizes are to be optimized to obtain the optimized target size data.

[0052] In one embodiment, the process of optimizing the target size data of the components according to the size gradient data of each component to obtain the optimized target size data includes:

[0053] Perform non-linear mapping processing on the size gradient data of each component according to the preset optimization space to obtain the mapped gradient data corresponding to each component;

[0054] Optimize each component according to the mapped gradient data to obtain the optimized target size data.

[0055] The above method for adjusting the positions and sizes of chip components discretizes according to the target sizes of the components in the chip to be laid out, obtaining the first discrete size data and the second discrete size data of each component. According to the circuit topology of the chip to be laid out, the first discrete size data, the second discrete size data, and the target position data of each component, the optimization index data and the discrete performance data corresponding to each component are obtained. Among them, the discrete performance data is the intermediate data related to the target size data obtained during the process of obtaining the optimization index data. Calculate the position gradient data of the optimization index data corresponding to each component with respect to the target position data. Based on the discrete performance data corresponding to each component, obtain the size gradient data of the optimization index data corresponding to each component with respect to the target size data. Optimize the target size data and the target position data of each component according to the position gradient data and the size gradient data of each component respectively, obtaining the optimized target size data and target position data. In this way, the target size data and the target position data of each component are simultaneously used as optimization variables for optimization adjustment. At the same time, the continuous target size data is discretized, interpolation processing is performed on the discrete performance data obtained based on the first discrete size data and the second discrete size data, the relevant performance data corresponding to the target size data is calculated, and then the optimization index data corresponding to each component is calculated. At the same time, using the intermediate data related to the target size data obtained during the calculation process, calculate the size gradient data of the optimization index data of the component with respect to the target size data, and then it is possible to backpropagate according to the size gradient data and the position gradient data simultaneously during the optimization process to optimize the target size data and the target position data of each component. In this way, during the integrated circuit design process, the positions and sizes of chip components can be adjusted simultaneously, avoiding the problem in related technologies that the positions and sizes of chip components need to be adjusted alternately with each other, resulting in low efficiency of adjusting the positions and sizes of chip components. Using the method provided in the above embodiments can improve the efficiency of adjusting the positions and sizes of chip components. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0057] Figure 1 FIG. is an application environment diagram of the method for adjusting the positions and sizes of chip components in an embodiment;

[0058] Figure 2 FIG. is a flowchart of the method for adjusting the positions and sizes of chip components in an embodiment;

[0059] Figure 3 Exemplary schematic diagram of the circuit topology of the chip to be processed in an embodiment;

[0060] Figure 4 Exemplary schematic diagram of the circuit topology in which component X drives two pins in an embodiment;

[0061] Figure 5 Structural block diagram of the chip component position and size adjustment device in an embodiment;

[0062] Figure 6 Internal structure diagram of a computer device in an embodiment. Detailed implementation manners

[0063] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0064] The chip component position and size adjustment method provided by the embodiments of the present application can be applied to an application environment as Figure 1 shown. Among them, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or placed in the cloud or other network servers. Among them, the terminal 102 can be, but is not limited to, various personal computers, laptop computers, smart phones, tablet computers, Internet of Things devices, and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart vehicle-mounted devices, etc. The portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc. The server 104 can be implemented by an independent server or a server cluster composed of multiple servers.

[0065] The terminal 102 performs discretization processing based on the target size data of each component in the chip to be laid out, and obtains the first discrete size data and the second discrete size data of each component; according to the circuit topology of the chip to be laid out, the first discrete size data, the second discrete size data of each component, and the target position data of each component, obtain the optimization index data and the discrete performance data respectively corresponding to each component, where the discrete performance data is intermediate data related to the target size data obtained during the process of obtaining the optimization index data; calculate the position gradient data of the optimization index data respectively corresponding to each component with respect to the target position data; based on the discrete performance data respectively corresponding to each component, obtain the size gradient data of the optimization index data respectively corresponding to each component with respect to the target size data; optimize the target size data and the target position data of each component respectively according to the position gradient data and the size gradient data of each component, and obtain the optimized target size data and target position data.

[0066] In an exemplary embodiment, please refer to Figure 2 , a method for adjusting the position and size of chip components is provided, and this method is applied to Figure 1 the terminal 102 in Figure 2 as an example for illustration. It can be understood that this method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. As

[0067] shown in

[0068] Step 202, perform discretization processing based on the target size data of each component in the chip to be laid out, and obtain the first discrete size data and the second discrete size data of each component.

[0069] During the integrated circuit layout design process, the size of components generally comes from a standard cell library with discrete selections; since there are only discrete component size timing, performance, power consumption, area, layout density, and design rule constraint information in the circuit standard library, in this embodiment, through the discretization method, the continuous target size data is converted into two discrete size data, and then the performance data corresponding to the first discrete size data and the second discrete size data is obtained, and then the performance of the continuous gate size data under various indicators is obtained through interpolation; at the same time, the interpolation data is differentiable, and the gradient data can be backpropagated to two adjacent target size data. In the embodiments of the present application, a component can also be referred to as a gate circuit. Exemplarily, perform ceiling processing on the target size data s to obtain the first discrete size data , and perform floor processing on the size data to obtain the second discrete size data

[0070] Step 204: According to the circuit topology of the chip to be placed, the first discrete size data and the second discrete size data of each component, and the target position data of each component, obtain the optimization index data and the discrete performance data corresponding to each component respectively. The discrete performance data is intermediate data related to the target size data obtained during the process of obtaining the optimization index data.

[0071] Please refer to Figure 3 , which is an exemplary schematic diagram of the circuit topology of a chip to be placed; as Figure 3 shown, (L) represents the chip layout, a rectangular area, and (C1), (C2), and (C3) are three components on the layout, namely a buffer, a register, and an AND gate circuit respectively; component (C1) has two pins, namely pin a and pin c, component (C2) has three pins, namely pin b, pin e, and pin d, and component (C3) has three pins, namely pin f, pin g, and pin h. In addition to the pins of each component, the chip also includes a peripheral input pin (PI1), an input pin (PI2), and an output pin (PO); Figure 3 The chip to be placed shown in total includes 11 pins. In the field of integrated circuit design technology, component pins can also be referred to as pins.

[0072] The circuit topology of the chip to be placed refers to the connection relationship between each component. Exemplarily, Figure 3 the circuit topology of the chip shown includes that pin c of component (C1) is respectively connected to pin e of component (C2) and pin f of component (C3).

[0073] Among them, the target position data refers to the coordinate position data of each component in the chip layout, and the size data refers to the physical size of the transistor corresponding to the component, including the channel length and the channel width. The size of the component directly affects the performance and power consumption of the component. Among them, at each stage of the component placement iteration, each component has a specific layout position in the layout, that is, the target position data of the component. As Figure 3 shown, it shows the relative layout of three components on the layout. At the same time, the position of each pin on the component is also fixed. For example, Figure 3 pin a on component (C1) in. Its position is constant relative to the component. The pin position data of each pin on each component can be obtained based on the target position data of each component; Exemplarily, the position data of each pin on the component is obtained by adding the position coordinates of the component to which the pin belongs and the position of the pin on the component (i.e., the offset coordinates); When calculating the optimization index data of the interconnect line length and the timing performance, the position data of each pin is required.

[0074] Exemplarily, the target size data and target position data of the component can be the target size data and target position data initialized in the chip layout stage; alternatively, exemplarily, the target size data and target position data of the component can be the optimized target size data and target position data obtained from the previous round of iterative optimization.

[0075] The method for adjusting the position and size of the chip component provided in this embodiment can be an iterative loop process, where steps 202 to 210 are executed multiple times until the iteration end condition is reached, and the final target size data and target position data are obtained.

[0076] In a possible implementation manner, the iteration end condition includes convergence judgment. Exemplarily, after the difference between the target size data and target position data obtained from two iterations is less than a preset difference, the iteration ends, and the currently obtained target size data and target position data are used as the final layout data, or the optimal target size data and target position data during multiple iterations are used as the final layout data. Exemplarily, the performance of the target size data and target position data obtained at the end of each iteration can be measured based on the sum value of the optimization index data corresponding to all components respectively.

[0077] In a possible implementation manner, the iteration end condition includes early stopping judgment. Exemplarily, during the iteration process, if the result deteriorates, oscillates, or other unreasonable situations occur, the iteration process is exited, and the optimal target size data and target position data during the previous iteration process are used as the final layout data. Exemplarily, when the sum value of the optimization index data corresponding to each component calculated based on the optimized target size data and target position data obtained during the current iteration process is less than a preset index threshold, the iteration process ends.

[0078] In a possible implementation manner, the iteration end condition includes the maximum number of iterations. After reaching the maximum number of iterations, the iteration ends, and the optimal target size data and target position data during the previous iteration process are used as the final layout data.

[0079] Among them, the optimization index data corresponding to each component respectively refers to various index data related to the size and / or position of the component, including but not limited to types such as timing, performance, design rule constraints, power consumption, area, and layout density.

[0080] In the process of calculating the optimization index data corresponding to the computing elements, since the target size data is continuous data, and the mapping relationship between the size data and the performance of the elements comes from the corresponding circuit standard library, and the circuit standard library generally uses discrete size data as an index, therefore, in this embodiment, the target size data of the elements is discretized, and the discrete performance data is obtained from the first discrete size data and the second discrete size data after discretization. Interpolation processing is performed based on the discrete performance data to obtain the relevant performance data corresponding to the target size data, and then the relevant performance data corresponding to the target position data is combined to obtain the optimization index data corresponding to each element respectively.

[0081] Step 206, calculate the position gradient data of the optimization index data corresponding to each element with respect to the target position data.

[0082] Among them, for each element, calculate the position gradient data of the optimization index data corresponding to the element with respect to the target position data of the element, for subsequent optimization of the target position data of the element based on the position gradient data.

[0083] Among them, the target position data of the element is a continuous variable. Exemplarily, the partial derivative of the optimization index data with respect to the target position data can be directly calculated to obtain the position gradient data.

[0084] Step 208, based on the discrete performance data corresponding to each element, obtain the size gradient data of the optimization index data corresponding to each gate circuit with respect to the target size data.

[0085] Among them, with the help of the discrete performance data obtained from the first discrete size data and the second discrete size data, the gradient of the optimization index data with respect to the target size data is obtained to adjust the size variable of the element by backpropagation.

[0086] Step 210, optimize the target size data and the target position data of each element according to the position gradient data and the size gradient data of each element respectively, to obtain the optimized target size data and the target position data.

[0087] Among them, for each element, optimize the target position data of the element based on the position gradient data of the element to obtain the optimized target position data, and optimize the target size data of the element based on the size gradient data of the element to obtain the optimized target size data.

[0088] The method for adjusting the positions and sizes of chip components provided by the above embodiments discretizes according to the target sizes of the components in the chip to be laid out, obtains the first discrete size data and the second discrete size data of each component, and based on the circuit topology of the chip to be laid out, the first discrete size data and the second discrete size data of each component, and the target position data of each component, obtains the optimization index data and the discrete performance data corresponding to each component, where the discrete performance data is intermediate data related to the target size data obtained during the process of obtaining the optimization index data; calculates the position gradient data of the optimization index data corresponding to each component with respect to the target position data, and based on the discrete performance data corresponding to each component, obtains the size gradient data of the optimization index data corresponding to each component with respect to the target size data, and optimizes the target size data and the target position data of each component according to the position gradient data and the size gradient data of each component respectively, to obtain the optimized target size data and target position data; in this way, the target size data and the target position data of each component are simultaneously used as optimization variables for optimization adjustment. At the same time, the continuous target size data is discretized, interpolation processing is performed on the discrete performance data obtained based on the first discrete size data and the second discrete size data, the relevant performance data corresponding to the target size data is calculated, and then the optimization index data corresponding to each component is calculated; at the same time, using the intermediate data related to the target size data obtained during the calculation process, the size gradient data of the optimization index data of the component with respect to the target size data is calculated, and then during the optimization process, the size gradient data and the position gradient data can be backpropagated simultaneously to optimize the target size data and the target position data of each component. In this way, during the integrated circuit design process, the positions and sizes of chip components can be adjusted simultaneously, avoiding the problem in the related art that the positions and sizes of chip components need to be adjusted alternately with each other, resulting in low efficiency of adjusting the positions and sizes of chip components. Using the method provided by the above embodiments can improve the efficiency of adjusting the positions and sizes of chip components.

[0089] In an exemplary embodiment, the optimization index data includes wiring length data, timing data, load violation data, signal flip violation data, wiring density data, discrete loss data, and power consumption data.

[0090] Among them, during the iterative optimization process, the above optimization index data serves as the target optimization function in the process of adjusting the positions and sizes of chip components, as shown in Formula 1:

[0091]

[0092] Among them, (x, y) represents the target position data of the component, and s represents the target size data of the component. Represents the wiring length function corresponding to the component, where net e represents an interconnect on the interconnect tree corresponding to the component, D(x,y;s) represents the wiring density data, Leak Power(s) represents the power consumption data, Loss(s,Round(s)) represents the discrete loss data, and t1WNS(x,y;s)+t2TNS(x,y;s) represents the timing data. Here, WNS(x,y;s) records the worst timing violation value; TNS(x,y;s) records the total timing violation value, which represents the most severe timing violation value of the timing violation, and SlewDRV(x,y;s) represents the signal transition violation data, and Load DRV(x,y;s) represents the load violation data. Among them, t1, t2, t3, t4, λ1, λ2, and λ3 are the weights of different objectives. It can be seen that the discrete loss data and the power consumption data only depend on the component size data and only propagate the gradient to the size variables of the component. The wiring length data, the timing data, the load violation data, the signal transition violation data, and the wiring density data depend on the component position data and the size data.

[0093] In this embodiment, the process of obtaining the optimized index data corresponding to each component according to the circuit topology of the chip to be placed, the first discrete size data and the second discrete size data of each component, and the target position data of each component includes steps A1 to A6, where:

[0094] Step A1: Obtain the directed acyclic graph data of the chip to be placed according to the circuit topology of the chip to be placed.

[0095] In this embodiment, the chip design is regarded as a set composed of components and interconnects. Each component has multiple pins, and the interconnects between components represent the signal transmission relationship between the pins. In the embodiment of the present application, the circuit topology of the chip is converted into a directed acyclic graph, where the nodes in the graph represent pins and the edges represent the signal transmission relationship between the pins. Among them, the signal transmission between pins is divided into two categories: one is the interconnect transmission, and the other is the internal component transmission. The signal transmission relationship between the pins inside each component is represented by an edge, and the edges between the pins of different components represent the interconnects. Exemplarily, please refer to Figure 3 , edge (D1) is the edge between component (C1) and component (C2), representing the signal transmission on the interconnect pin c→pin e; edge (D2) is the edge inside component (C2), representing the signal dependence relationship between the clock port and the output port of the register.

[0096] Then, flatten the directed acyclic graph and perform topological sorting to obtain the hierarchical directed acyclic graph data in list form. Exemplarily, please refer to Figure 3, the result after flattening is as follows: the first layer contains pin (PI1) and pin (PI2); the second layer includes pin a and pin b; the third layer is pin c; the fourth layer is pin e and pin f; the fifth layer is pin d; the sixth layer is pin g; the seventh layer is pin h; the eighth layer is pin (PO). It can be verified that this list meets the requirements of topological sorting, that is, if node n can be reached from any node m, then m must be ranked before n.

[0097] Step A2, according to the target size data of each component, obtain the discretization loss data of each component.

[0098] In order to keep the target size data discrete during the optimization process, in this embodiment, by setting the discretization loss data, the size variable is pushed towards its nearest discrete choice. Exemplarily, the discretization loss data can be expressed as Loss(s, Round(s)), where Loss is the loss function and Round is the rounding function.

[0099] Step A3, according to the first discrete size data, the second discrete size data of each component and the power consumption mapping relationship corresponding to each component, obtain the power consumption data of each component.

[0100] Among them, the power consumption data of the component refers to the leakage power consumption of the component, and the size of the power consumption data depends on the size of the component; Exemplarily, in this embodiment, through interpolation, the process of obtaining the power consumption data of the component under the target size data s is shown in Formula 2:

[0101]

[0102] Among them, Leak g (s g ) represents the power consumption data corresponding to component g, and is determined by the first discrete power consumption data and the second discrete power consumption data corresponding to the second discrete size data respectively. The first discrete power consumption data and the second discrete power consumption data can be determined according to the power consumption mapping relationship between the discrete component size data and the power consumption data in the circuit standard library. and the second discrete power consumption data can be determined according to the power consumption mapping relationship between the discrete component size data and the power consumption data in the circuit standard library.

[0103] In other examples, non - linear interpolation can also be used to obtain the power consumption data of the component under the target size data, or other methods can be adopted to obtain the power consumption data under the target size data according to the specific problem; subsequent other interpolation processes related to the target size data can also be replaced by non - linear interpolation or other methods, which will not be elaborated one by one.

[0104] In a possible implementation, the size gradient data includes power consumption size gradient data of the power consumption data of the component with respect to the target size data of the component; correspondingly, the discrete performance data includes first discrete power consumption data and second discrete power consumption data. In this implementation, based on the discrete performance data corresponding to each component, the size gradient data of the optimization index data corresponding to each component with respect to the target size data is obtained, including, for each component: obtaining the power consumption size gradient data according to the first discrete power consumption data and the second discrete power consumption data of the component.

[0105] Exemplarily, based on Equation 2, it can be deduced that the partial derivative of the power consumption data of the component with respect to the target size data can be obtained through the first discrete power consumption data and the second discrete power consumption data, and this process is as shown in Equation 3:

[0106]

[0107] As shown in Equation 3, subtracting the second discrete power consumption data from the first discrete power consumption data to obtain the power consumption size gradient data of the component.

[0108] In a possible implementation, the position gradient data includes power consumption position gradient data of the power consumption data with respect to the target position data of the component, where the partial derivative of the calculated power consumption data with respect to the target position data is used to obtain the power consumption position gradient data.

[0109] Step A4, obtaining the timing data, load violation data, and signal transition violation data of each component according to the first discrete size data, second discrete size data, target position data of each component, and directed acyclic graph data.

[0110] In a possible implementation, Step A4 further includes: performing Steps A401 to A408 for each component:

[0111] Step A401, obtaining the received pin capacitance data corresponding to the component according to the first discrete size data, second discrete size data, and pin capacitance mapping relationship.

[0112] Among them, components of the same type but different sizes have different pin capacitance values, and these values will affect the upstream load of the component, and this upstream load will change the upstream network delay, cell delay, rate of change propagation, etc., and ultimately affect the timing or design rule violation index.

[0113] In this implementation, the received pin capacitance data is obtained by interpolation as a function of the target size data s. Exemplarily, the process of obtaining the received pin capacitance data corresponding to the component is as shown in Equation 4:

[0114]

[0115] Among them, Cap i (s g ) represents the received pin capacitance data corresponding to component g, and is determined by the first discrete dimension data and the second discrete dimension data corresponding to the first discrete capacitance data and the second discrete capacitance data respectively. The first discrete capacitance data and the second discrete capacitance data can be determined according to the mapping relationship between the discrete component dimension data and the pin capacitance data in the circuit standard library; i represents the signal receiving pin of component g, and s g is the target dimension data of component g.

[0116] Among them, the received pin capacitance data of the component is determined based on the type and dimension of the component, and different components can correspond to different pin capacitance mapping relationships.

[0117] Step A402: Determine the parasitic capacitance data corresponding to the component according to the directed acyclic graph data and the target position data of the component.

[0118] Among them, in this embodiment, for each interconnect line in the directed acyclic graph data, that is, the connection line between components, a routing tree is used to connect all relevant pins to ensure the shortest length of the routing tree. This routing tree can also be called a Steiner Tree. The nodes of the routing tree include pins and transfer points, and the transfer points can also be called Steiner points. The edges of the routing tree represent the signal transmission relationship between the nodes. Exemplarily, please refer to Figure 3 , the interconnect line between pin c, pin e, and pin f forms a routing tree, where pin c is the root node, pin e and pin f are the leaf nodes, and the unmarked transfer position is a Steiner point. Exemplarily, in order to calculate the minimum routing tree, the FLUTE algorithm or other approximation algorithms can be used to obtain a chip layout optimization method suitable for timing-driven.

[0119] In a possible implementation manner, an improvement is made based on the FLUTE algorithm. The coordinates of the transfer point are associated with the coordinates of the relevant pins. When optimizing the associated pin coordinates, the coordinates of the transfer point are synchronously optimized, thereby opening the reverse gradient channel from routing to pin coordinates. Exemplarily, the transfer point is generally related to at least two component pins. During the optimization process, an association times threshold is set, and the transfer point is associated with the relevant pin coordinates according to the association times. For example, the association times threshold is 10. Please refer to Figure 3During the 1st to 10th iteration, the transfer point between pin c, pin e, and pin f is associated with pin c and is optimized for movement following the optimization direction of pin c. During the 11th to 20th iteration, it is associated with pin e and is optimized for movement following the optimization direction of pin e. During the 21st to 30th iteration, it is associated with pin f and is optimized for movement following the optimization direction of pin f.

[0120] At each node of the routing tree, the ground capacitance of the node is calculated using the position information of the node on the layout. For each edge of the routing tree, the resistance can be determined by the distance between the two connected nodes on the layout. Among them, the calculation processes of the ground capacitance and the resistance are approximated to the process of parasitic parameter extraction. In the embodiments of the present application, it is assumed that each unit length of the routing tree edge has a fixed resistance and capacitance, and the capacitance value of the edge is evenly distributed to the two endpoints of the edge.

[0121] Exemplarily, based on the target position data of the component and the coordinate data of the Steiner point corresponding to the component, parasitic capacitance data is obtained using a preset differentiable extraction model, which assumes a linear relationship between the Manhattan distance and the parasitic capacitance.

[0122] Step A403: Obtain the output capacitance data of the component according to the receiving pin capacitance data and the parasitic capacitance data of the component.

[0123] Among them, the receiving pin capacitance data and the parasitic capacitance data are added to obtain the output capacitance data of the component.

[0124] Step A404: Based on the output capacitance data and the timing delay model, obtain the input delay data and the impulse response data of the component.

[0125] Exemplarily, the timing delay model can adopt the Elmore timing delay model. Among them, the Elmore timing delay model can calculate the load, delay data, and impulse response data of each section of the interconnecting wire according to the output capacitance data of the component; based on the delay data of each interconnecting wire corresponding to the input pin of the component, the input delay data of the component is obtained.

[0126] Step A405: Obtain the target in-gate delay data and the signal flip data of the component according to the first discrete size data, the second discrete size data, the output capacitance data, the input voltage change rate, and the non-linear delay model.

[0127] Among them, the in-gate delay data refers to the delay data inside the component. Exemplarily, the non-linear delay model can adopt NLDM (Non-Linear Delay Model), which consists of piecewise linear lookup tables (LUTs). The index of the piecewise linear lookup table is the input voltage change rate and the output capacitance data.

[0128] Among them, the input voltage change rate refers to the change speed of the input signal voltage over time, usually expressed by the amount of voltage change per unit time (such as V / ns). In digital circuits, it reflects the conversion speed of the input signal from low level to high level or from high level to low level. In the non-linear delay model (NLDM), the input voltage change rate is one of the key parameters for calculating the gate delay. The delay not only depends on the output load but also is affected by the change speed of the input signal. A slower change rate will result in a greater delay, while a faster change rate may reduce the delay. The input voltage change rate is recursively defined and propagated layer by layer in the hierarchical directed acyclic graph throughout the chip design to ensure accurate delay calculation for each level of the circuit.

[0129] Among them, LUTs are part of the circuit process library and are determined by the type and size of the gate circuit; Exemplarily, it is carried out layer by layer through the hierarchical directed acyclic graph list structure. Taking the component layer as an example, the experimental delay data of the current component and the signal flip delay information of the component output pin are obtained through the signal flip delay of the input given externally to the circuit and the output capacitance data obtained in step A404 through the LUT query method; For the interconnect layer, based on the signal flip delay information of the component output pin obtained above and combined with the impulse response data obtained in step A405, the flip delay information at the end of the interconnect is calculated. By traversing layer by layer along the signal transmission direction, the delay data on each propagation directed edge in each level and the flip delay information of each node on the directed acyclic graph can be obtained; Furthermore, the target in-gate delay data and signal flip data of the component are obtained.

[0130] The target in-gate delay data and signal flip data of the component depend on the size data of the component; For the size data of a single discrete component, the models corresponding to the in-gate delay and signal flip data are differentiable functions themselves. Among them, the target in-gate delay data d ij (s g ) The first discrete in-gate delay data calculated through the NLDM LUT model, input voltage change rate, output capacitance data, first discrete size data, and second discrete size data and the second discrete in-gate delay data are obtained by interpolation; Exemplarily, this process is shown in Formulas 5, 6, and 7:

[0131]

[0132] where i is the input pin of component s g and j is the output pin of component s g LUT represents a non-linear delay model, islew represents the input voltage slew rate of component s g and oload represents the output capacitance data of component s g

[0133] where the signal slew data Slew can also be referred to as the output voltage slew rate of the component, and is obtained by interpolating the first discrete flip duration data and the second discrete flip duration data calculated from the first discrete dimension data and the second discrete dimension data. Exemplarily, this process is shown in Equation 8:

[0134]

[0135] where j is the output pin of component s g represents the first discrete flip duration data of component s g represents the second discrete flip duration data of component s g

[0136] Step A406: Obtain the timing data of the component according to the input delay data and the target in-gate delay data of the component.

[0137] where the input delay data of the component and the target in-gate delay data are added together to obtain the arrival time of the endpoint signals of each timing path corresponding to the component. If the value of this arrival time exceeds the predetermined clock period, it is considered that a timing violation has occurred, and the violation value needs to be accumulated to obtain the TNS (Total Negative Slack) value, and the most serious violation value among the violation values is recorded to obtain the WNS (Worst Negative Slack). The TNS and WNS are added together according to the preset weights to obtain the timing data of the component, which is used to measure the delay violation situation of the component in the current iteration process.

[0138] Step A407: Obtain the load violation data according to the output capacitance data.

[0139] where the output capacitance data of the component is compared with the preset load range in the circuit process library to determine whether a violation has occurred. If a violation has occurred, the output capacitance violation value is recorded to obtain the load violation data.

[0140] Step A408: Obtain the signal flip violation data according to the signal flip data.

[0141] ​​​​Among them, the signal flip data of the component is compared with the preset signal flip range in the circuit process library to determine whether a violation occurs. If a violation occurs, the signal flip violation value is recorded to obtain the signal flip violation data.

[0142] Exemplarily, the maximum value smoothing technique can be adopted in the process of calculating the timing data, load violation data and signal flip violation data of the component, so that the subsequent backpropagation optimization process can be more stable.

[0143] In a possible implementation manner, the size gradient data includes the timing size gradient data of the timing data relative to the target size data of the component; correspondingly, the discrete performance data includes the first discrete capacitance data, the second discrete capacitance data, the first discrete in-gate delay data, the second discrete in-gate delay data, the first discrete flip duration data and the second discrete flip duration data.

[0144] In this implementation manner, for each component, the size data of the component affects the timing data of the component through three aspects: output pin capacitance, in-gate delay, and output voltage change rate. Thus, in this embodiment, the timing size gradient data of the timing data relative to the target size data is divided into three channels, namely the first sub-timing size gradient data related to the output pin capacitance, the second sub-timing size gradient data related to the target in-gate delay data, and the third sub-timing size gradient data related to the signal flip data. Correspondingly, based on the discrete performance data respectively corresponding to each component, the process of obtaining the size gradient data of the optimization index data respectively corresponding to each component relative to the target size data includes steps B1 to B4, where:

[0145] Step B1, according to the first discrete capacitance data, the second discrete capacitance data, the receiving pin capacitance data and the timing data, obtain the first sub-timing size gradient data.

[0146] Among them, the differentiable receiving pin capacitance and the timing data are chained together, and the gradient is passed back from the timing target to the gate circuit size. Exemplarily, the process of obtaining the first sub-timing size gradient data is shown in Equation 9:

[0147]

[0148] Among them, represents the first timing size gradient data, T represents the timing data, pin i represents the receiving pin of component s g Cap i represents the receiving pin of component s g the capacitance data of the receiving pin i of.

[0149] Step B2: Obtain the second sub-timing dimension gradient data based on the first in-discrete-gate delay data, the second in-discrete-gate delay data, and the target in-gate delay data.

[0150] Among them, the target in-gate delay data is obtained by interpolation processing with the first in-discrete-gate delay data and the second in-discrete-gate delay data. Correspondingly, the reverse channel of the timing dimension gradient data regarding the component sg also includes the second sub-timing dimension gradient data obtained in the manner shown in Formula 10:

[0151]

[0152] Among them, represents the second sub-timing dimension gradient data.

[0153] Step B3: Obtain the third sub-timing dimension gradient data based on the first in-discrete-transition duration data, the second in-discrete-transition duration data, and the signal transition data.

[0154] Among them, the rate of change of the output voltage of the component can also be obtained by differentiable linear interpolation. Correspondingly, the reverse channel of the timing dimension gradient data regarding the component s g also includes the third sub-timing dimension gradient data obtained in the manner shown in Formula 11:

[0155]

[0156] Among them, represents the third sub-timing dimension gradient data.

[0157] Step B4: Obtain the timing dimension gradient data based on the first sub-timing dimension gradient data, the second sub-timing dimension gradient data, and the third sub-timing dimension gradient data.

[0158] Among them, due to the partial derivative chain rule, the entire timing dimension gradient data is the sum of the sub-timing dimension gradient data of the three channels of the output pin capacitance, the in-gate delay, and the rate of change of the output voltage. Exemplarily, the process of obtaining the timing dimension gradient data is as shown in Formula 12:

[0159]

[0160] Among them, represents the timing dimension gradient data.

[0161] In a possible implementation manner, the position gradient data includes the timing position gradient data of the timing data with respect to the target position data of the component, where the partial derivative of the calculated timing data with respect to the target position data is used to obtain the timing position gradient data.

[0162] Step A5: Obtain the wiring length data of each component according to the target position data and target size data of each component.

[0163] Exemplarily, based on the target position data and target size data of the component, calculate the exact coordinates of the input pins and output pins of each component; then calculate the Manhattan distance between the starting point and the ending point of the connection line based on the pin coordinates; estimate the winding length and the influence of vias on the wiring length according to the wiring rules of the wiring layer and the usage of vias, so as to obtain the wiring length data of each component.

[0164] In a possible implementation manner, the position gradient data includes the length position gradient data of the wiring length data with respect to the target position data of the component, wherein the length position gradient data is obtained by taking the partial derivative of the calculated wiring length data with respect to the target position data.

[0165] In a possible implementation manner, considering that the influence of the size of the component on the wiring length is much smaller than the influence of the position data of the component on the wiring length, therefore, in this implementation manner, the size gradient data does not include the gradient data of the wiring length data with respect to the target size data of the component, and no backpropagation channel is established for the wiring length and the size variable of the component.

[0166] Step A6: Obtain the wiring density data of each component according to the first discrete size data, the second discrete size data of each component and the target position data of each component.

[0167] Among them, the wiring density data of each component depends on the target position data and target size data of the component. In this embodiment, the component is modeled as a charge, the density penalty is modeled as the potential energy of the system, and the density gradient data is modeled as an electric field to push the component charges apart, and the electric field and the position layout of the chip are analogized; at the same time, the size variable of the component is modeled as a variable, which means that in the optimization process, the area of the component is also a variable, no longer a constant, and in the electrostatic-based layout, it means that the amount of charge changes.

[0168] In a possible implementation manner, Step A6 further includes Step A601 to Step A603, wherein:

[0169] Step A601: Obtain the component area data of the component according to the first difference size data, the second discrete size data of the component and the area mapping relationship.

[0170] Among them, for the component area, the component area data of the component under the target size data is obtained by using the linear interpolation method.

[0171] Exemplarily, the process of obtaining the component area data of the component is shown in Formula 13 below:

[0172]

[0173] Among them, Area g (s g ) represents the component area data corresponding to component g, which is determined by the first discrete dimension data and the second discrete dimension data corresponding to the first discrete area data and the second discrete area data respectively. The first discrete area data and the second discrete area data can be determined according to the area mapping relationship between the discrete component dimension data and area data in the circuit standard library.

[0174] Step A602: Obtain the potential data of the component according to the target position data and potential model of the component.

[0175] Among them, the potential data Φ(x g , y g ) of the component refers to the potential of component g at the position (x g , y g ). Among them, the potential model refers to the model obtained by modeling the component as a charge. The potential model is used to output the potential data corresponding to the component according to the target position data of the component on the layout.

[0176] Step A603: Obtain the wiring density data of the component according to the potential data and component area data of the component.

[0177] Among them, the potential data and component area data of the component are multiplied to obtain the wiring density data of the component.

[0178] Among them, the greater the wiring density data of the component, the higher the density penalty the component will receive during the optimization process, thereby suppressing the increase in the size of the component in these areas; effectively promoting the increase in the size of the component in the sparse areas, especially on the critical path, so that the size and position of the component can be adjusted simultaneously, exploring a more abundant search space, and thus discovering a better combined layout and size adjustment method.

[0179] In a possible implementation manner, the size gradient data includes the density size gradient data of the wiring density data with respect to the target size data of the component. Correspondingly, the discrete performance data includes the first discrete area data and the second discrete area data. In this implementation manner, the process of obtaining the size gradient data of the optimization index data corresponding to each component with respect to the target size data based on the discrete performance data corresponding to each component includes: obtaining the density size gradient data according to the first discrete area data, the second discrete area data, and the potential data.

[0180] Exemplarily, based on Equation 13, it can be deduced that the partial derivative of the component area data of a component with respect to the target dimension data can be obtained from the first discrete area data and the second discrete area data, as shown in Equation 14:

[0181]

[0182] Based on Equation 14, the process of obtaining the density dimension gradient data can be as shown in Equation 15:

[0183]

[0184] In a possible implementation manner, the position gradient data includes the density position gradient data of the wiring density data with respect to the target position data of the component, where the partial derivative of the target position data is obtained using the calculated wiring density data to obtain the density position gradient data.

[0185] In the method for adjusting the position and size of a chip component provided in the above embodiment, compared with the related art, in this embodiment, the optimization index data introduces multiple new optimization objectives, including timing data, load violation data, signal flip violation data, discretization loss data, and power consumption data, while retaining the original wiring length data and wiring density data of the integrated circuit layout; in order to optimize the component size and component position simultaneously, the above optimization objectives are used as functions of the size data and position data of the component, and through interpolation, the discrete size data is made differentiable, so that the gradients of the above optimization objectives with respect to the size data and position data of the component can be determined; with the help of these gradients, the gradient descent method can be used for optimization, which naturally fits with the non-linear global layout process.

[0186] In an exemplary embodiment, the process of obtaining the optimization index data corresponding to each component according to the circuit topology of the chip to be laid out, the first discrete size data and the second discrete size data of each component, and the target position data of each component includes steps C1 to C3, where:

[0187] Step C1, obtain a calibration factor. The calibration factor is determined based on the ratio of the calibration index data and the external index data obtained during the calibration period.

[0188] Step C2, call the internal calculation engine, and perform calculation processing based on the circuit topology of the chip to be laid out, the first discrete size data and the second discrete size data of each component, and the target position data of each component to obtain the initial index data.

[0189] Step C3, obtain the optimization index data according to the calibration factor and the initial index data.

[0190] Among them, the external metric data refers to the metric data measured using a circuit performance measurement tool. Exemplarily, the circuit performance measurement tool can be a measurement tool such as Synopsys PrimeTime, Cadence Tempus, or Siemens EDA (Mentor) Questa Timing Analysis. The initial metric data refers to the metric data calculated in this application through the circuit topology of the chip to be placed, the first discrete size data and the second discrete size data of each component, and the target position data of each component. The calibrated metric data refers to the metric data calculated by invoking the internal calculation engine during the calibration period. Among them, the calculation methods of the calibrated metric data and the initial metric data are the same. The differences are that the metric data is calculated in different iteration cycles and the data usage is different. Among them, the calibrated metric data refers to the metric data calculated in the calibration period and is used to compare with the external metric data to determine the calibration factor; the initial metric data refers to the metric data calculated in the optimization period. After being multiplied by the calibration factor, it is used to obtain the target optimization function value and the backpropagation gradient required for iterative optimization.

[0191] Exemplarily, the internal calculation engine can be an engine framework constructed based on the deep neural network learning framework Pytorch and can be implemented based on GPU (Graphics Processing Unit) hardware. Thanks to the GPU acceleration technology, the calculation process of the primary metric data is efficient and has low overhead, and can efficiently fuse to achieve the goal of layout and gate size optimization.

[0192] Taking the timing and design rule constraint objectives as an example, since the timing and design constraint rule analysis of components has been predefined in the circuit standard library, this application embodiment only focuses on the network analysis differences between different timers. This embodiment performs calibration based on multiplication on the circuit timing metrics, calibrating the forward timing data, the reverse timing size gradient data, and the timing position gradient data. Exemplarily, consider a simplified case, such as Figure 4 shown, component X drives a 2-pin (source pin a and target pin b) network. To calibrate the signal transition duration, this embodiment uses the external signal transition duration of the source pin a of the reference timer, and then calculates the timing data of the target pin b based on the calibrated signal transition duration calculated during the calibration period. If the calibrated signal transition duration calculated in this embodiment is 400 ps (femtoseconds), and the external signal transition duration reported by the reference timer is 600 ps, then the calibration factor for the signal transition data is 600 / 400 = 1.5; in the subsequent iterative optimization process, it is used to adjust the signal transition data of the component based on the calibration factor.

[0193] Similarly, external metric data such as timing data and output capacitance data that can be obtained through external measurements can be used to obtain calibration factors for the timing data and output capacitance data, so as to adjust the corresponding metric data during the iterative optimization process.

[0194] In a possible implementation, during the entire iterative process, there are multiple calibration cycles; during the iterative adjustment of the chip component positions and sizes, the calibration factors are updated multiple times to achieve a more accurate optimization effect.

[0195] This embodiment adopts a multiplicative calibration method, which can better capture the relationship between variables and metric data. First, the multiplicative calibration method reflects the sensitivity of the size data in the gradient, thus obtaining a more interpretable objective. Second, the multiplicative calibration method can still maintain a high accuracy even after undergoing multiple optimization iterations, avoiding the problem that the additive calibration method may cause a rapid deviation from the golden result; adopting the calibration method provided in this embodiment can improve the quality and stability of the differentiable framework.

[0196] In an exemplary embodiment, the process of optimizing the target size data and target position data of each component according to the position gradient data and size gradient data of each component respectively to obtain the optimized target size data and target position data includes:

[0197] Step D1, in the first cycle, the components with the number of layers less than the preset number of layers in the directed acyclic graph are determined as the components to be optimized, and the target size data and target position data of the components to be optimized are optimized according to the size gradient data and position gradient data of the components to be optimized, so as to obtain the optimized target size data and target position data.

[0198] Step D2, in the second cycle, the components with the number of layers greater than or equal to the preset number of layers in the directed acyclic graph are determined as the components to be optimized, and the target size data and target position data of the components to be optimized are optimized according to the size gradient data and position gradient data of the components to be optimized, so as to obtain the optimized target size data and target position data.

[0199] Among them, the first cycle and the second cycle refer to different iterative optimization cycles. Exemplarily, the first cycle refers to the odd iterative optimization cycle, and the second cycle refers to the even iterative optimization cycle; in this example, the target size data and target position data of the components on both sides of the preset number of layers are alternately optimized.

[0200] In this embodiment, the shallow or deep circuits with the number of layers less than or greater than the preset number of layers are alternately separated and optimized, so as to ensure the accuracy and reliability of the gradients obtained by the deep components; avoid the situation where the optimization quality of the deep layer decreases due to the optimization of the shallow layer when the sizes and positions of all components are optimized in parallel.

[0201] In an exemplary embodiment, the process of optimizing the target size data of components based on the size gradient data of each component to obtain the optimized target size data includes: determining the components with the gate size to be optimized according to the size gradient data and size gradient threshold of each component; optimizing the target size data of the components with the gate size to be optimized to obtain the optimized target size data.

[0202] In a possible implementation manner, the optimization metric data includes wiring length data, timing data, load violation data, signal flip violation data, wiring density data, discretization loss data, and power consumption data. The corresponding size gradient data of the components includes timing size gradient data, load violation size gradient data, signal flip violation size gradient data, wiring density size gradient data, discretization size gradient data, and power consumption size gradient data. The specific value of the size gradient data used to optimize the target size data is determined by weighted summation based on the timing size gradient data, load violation size gradient data, signal flip violation size gradient data, wiring density size gradient data, discretization size gradient data, and power consumption size gradient data.

[0203] Exemplarily, the specific values calculated for the size gradient data of each component are [-0.2, -0.5, -10.7, 0.0, …, 1.3]; where each value in the vector represents the size gradient data of a component. Sort the absolute values of the above values, and determine the components with the absolute value of the size gradient data greater than the size gradient threshold as the components with the gate size to be optimized. Quantize the absolute value of the size gradient data of the components with the gate size to be optimized to 1, that is, the size gradient data of the components with the gate size to be optimized is quantized to +1 or -1; the processed gradient data corresponding to the above size gradient data [-0.2, -0.5, -10.7, 0.0, …, 1.3] of each component is [0, 0, -1, 0, …, 0], and determine the components with non-zero values in the processed gradient data as the components with the gate size to be optimized. In this embodiment, for the components with the gate size to be optimized, determine whether the target size data of the component increases or decreases according to the positive or negative of the size gradient data.

[0204] Among them, for the components with the absolute value of the size gradient data less than the size gradient threshold, the size data is not adjusted during this optimization process.

[0205] In a possible implementation manner, the size gradient threshold is determined according to the size gradient data of the N components with larger absolute values among the size gradient data of each component in the current iteration process; thus, in each iteration optimization process, the size gradient data is adaptively adjusted according to the size conditions of each component in the current iteration process, so as to optimize the size data of different components in each round of iteration process and improve the robustness of the scheme.

[0206] In this application, the component that determines the gate size to be optimized according to the size gradient data provided in this embodiment is denoted as gradient clipping method 1. In this embodiment, by quantifying the size gradient data of each component based on the size gradient threshold, the continuous gradient data is converted into discrete component size change values, so as to ensure that the component size data can be optimized in a discrete space, and the gradient descent method originally used for continuous variable optimization is applied to the discrete problem of optimizing the discrete component size.

[0207] In an exemplary embodiment, the process of optimizing the target size data of the component according to the size gradient data of each component to obtain the optimized target size data includes: performing a non-linear mapping process on the size gradient data of each component according to a preset optimization space to obtain the mapped gradient data corresponding to each component; performing an optimization process on each component according to the mapped gradient data to obtain the optimized target size data.

[0208] Among them, the specific function of the non-linear mapping process is selected according to the actual problem. The main purpose of this embodiment is to compress the size gradient data into an interval range (i.e., the preset optimization space), so as to reduce the unstable influence on the optimization caused by the gradient value being too large or too small.

[0209] Compared with the method of determining the component of the gate size to be optimized according to the size gradient threshold in the previous embodiment, the method provided in this embodiment can retain the relative relationship between the size gradient data of each component.

[0210] Exemplarily, the process of performing a non-linear mapping process on the size gradient data of each component according to a preset optimization space to obtain the mapped gradient data corresponding to each component can be shown in Formula 16:

[0211] NoneLinear(x) = k2[Sigmoid(k1*x) - Sigmoid(k1*-x)], Formula 16

[0212] Among them, x is the input variable, that is, the size gradient data of the component, k1 is used to adjust the sensitivity of the final processing result to x, and k2 is used to express that the space range after compressing the input variable is (-k2, +k2). The Sigmoid function is a classic non-linear function. Exemplarily, the Sigmoid function can be called through the deep neural network learning tool PyTorch.

[0213] In this application, the method of performing a non-linear mapping process on the size gradient data of the component provided in this embodiment is denoted as gradient clipping method 2.

[0214] In a possible implementation manner, during the iterative optimization process, the optimization of the target size data of the component is alternately performed according to the first gradient clipping method and the second gradient clipping method, so that the entire iterative optimization process benefits from both gradient clipping methods, thereby improving the accuracy and reliability of the iterative optimization.

[0215] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the indications of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or steps or stages in other steps.

[0216] It can be understood that the term "based on" used in this application is used to describe one or more factors affecting the determination, and does not exclude other factors that may affect the determination. For example, the phrase "determine A based on B" means that the determination of A can be completely or at least partially based on factor B. That is to say, B is a factor affecting the determination of A, but it does not exclude that the determination of A is also based on C.

[0217] Based on the same inventive concept, the embodiments of this application also provide a chip component position and size adjustment device for implementing the chip component position and size adjustment method described above. The solution provided by this device to solve the problem is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the chip component position and size adjustment device provided below can refer to the limitations on the chip component position and size adjustment method in the above text, and will not be repeated here.

[0218] In an exemplary embodiment, as Figure 5 shown, a chip component position and size adjustment device is provided, including: an index calculation module 502, a gradient calculation module 504, and an iterative optimization module 506, where:

[0219] The index calculation module 502 is configured to perform discretization processing based on the target size data of each component in the chip to be laid out, obtain the first discrete size data and the second discrete size data of each component, and obtain the optimization index data and the discrete performance data respectively corresponding to each component according to the circuit topology of the chip to be laid out, the first discrete size data and the second discrete size data of each component, and the target position data of each component. The discrete performance data is intermediate data related to the target size data obtained during the process of obtaining the optimization index data.

[0220] The gradient calculation module 504 is configured to calculate the position gradient data of the optimization index data respectively corresponding to each component with respect to the target position data, and obtain the size gradient data of the optimization index data respectively corresponding to each component with respect to the target size data based on the discrete performance data respectively corresponding to each component.

[0221] The iterative optimization module 506 is configured to perform optimization processing on the target size data and the target position data of each component according to the position gradient data and the size gradient data of each component respectively, and obtain the optimized target size data and target position data.

[0222] In an exemplary embodiment, each module in the above chip component position and size adjustment device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or independent of it, or stored in the memory in the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to the above modules.

[0223] In an exemplary embodiment, the above chip component position and size adjustment device is implemented by a GPU.

[0224] In an exemplary embodiment, a computer device is provided. The computer device can be a terminal, and its internal structure diagram can be as Figure 6As shown in the figure. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the display unit, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner, and the wireless manner can be achieved through WIFI, a mobile cellular network, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a method for adjusting the position and size of chip components. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0225] Those skilled in the art can understand that Figure 6 the structure shown in the figure is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.

[0226] In one embodiment, a computer device is further provided, including a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above method embodiments are implemented.

[0227] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by the processor, the steps in the above method embodiments are implemented.

[0228] In one embodiment, a computer program product is provided, including a computer program. When the computer program is executed by the processor, the steps in the above method embodiments are implemented.

[0229] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memories can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0230] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0231] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for adjusting the position and size of a chip component, characterized in that: The method comprises: Performing discretization processing according to target size data of each component in the chip to be laid out, to obtain first discrete size data and second discrete size data of each of the components; According to the circuit topology of the chip to be laid out, the first discrete size data and the second discrete size data of each component and the target position data of each component, the optimization index data and the discrete performance data corresponding to each component are obtained, wherein the discrete performance data is the intermediate data related to the target size data obtained in the process of obtaining the optimization index data; Calculate the position gradient data of the optimization index data corresponding to each of the elements relative to the target position data; Based on the discrete performance data corresponding to each of the components, the size gradient data of the optimization index data corresponding to each of the components relative to the target size data is obtained; The target size data and target position data of each element are optimized according to the position gradient data and size gradient data of each element to obtain optimized target size data and target position data.

2. The method according to claim 1, characterized in that The optimization index data includes wiring length data, timing data, load violation data, signal flip violation data, wiring density data, discretization loss data and power consumption data; The step of obtaining optimization index data corresponding to each component according to the circuit topology of the chip to be laid out, the first discrete size data and the second discrete size data of each component, and the target position data of each component comprises: Obtaining directed acyclic graph data of the chip to be laid out according to the circuit topology of the chip to be laid out; Obtaining the discretized loss data of each of the components according to the target size data of each of the components; According to the first discrete size data of each component, the second discrete size data and the power consumption mapping relationship corresponding to each component, the power consumption data of each component is obtained; Obtaining the timing data, the load violation data, and the signal flip violation data of each of the components according to the first discrete size data and the second discrete size data of each of the components, the target position data of each of the components, and the directed acyclic graph data; Obtaining the wiring length data of each of the components according to the target position data and the target size data of each of the components; The wiring density data of each component is obtained according to the first discrete size data, the second discrete size data and the target position data of each component.

3. The method according to claim 2, characterized in that According to the first discrete size data, the second discrete size data, the target position data of each component and the directed acyclic graph data, the timing data, the load violation data and the signal flip violation data of each component are obtained, including: Obtaining receiving pin capacitance data corresponding to the component according to the mapping relationship between the first discrete size data, the second discrete size data and the pin capacitance; Determining parasitic capacitance data corresponding to the component according to the directed acyclic graph data and the target position data of the component; Obtaining output capacitance data of the component according to receiving pin capacitance data and parasitic capacitance data of the component; Based on the output capacitance data and the timing delay model, obtaining input delay data and pulse response data of the component; Obtaining target gate delay data and signal flip data of the element according to the first discrete size data, the second discrete size data, the output capacitance data, the input voltage change rate, the pulse response data and the nonlinear delay model; Obtaining timing data of the component according to the input delay data corresponding to the component and the target gate delay data; Obtaining the load violation data according to the output capacitance data; The signal inversion violation data is obtained according to the signal inversion data.

4. The method according to claim 2, characterized in that: The process of obtaining wiring density data of each component according to the first discrete size data, the second discrete size data and the target position data of each component comprises: Obtaining component area data of the component according to the first discrete size data, the second discrete size data and the area mapping relationship of the component; Obtaining electric potential data of the element according to the position data and the electric potential model of the element; The wiring density data is obtained based on the area data of the element and the potential data.

5. The method according to claim 1, characterized in that The size gradient data includes power consumption size gradient data of the power consumption data of the element relative to the target size data of the element; the discrete performance data includes first discrete power consumption data and second discrete power consumption data; In the process of obtaining the power consumption data of each component according to the first discrete size data, the second discrete size data of each component and the power consumption mapping relationship corresponding to each component, it also includes: obtaining the first discrete power consumption data and the second discrete power consumption data of the component; The step of obtaining the size gradient data of the optimization index data corresponding to each of the components relative to the target size data based on the discrete performance data corresponding to each of the components comprises: The power consumption dimension gradient data is obtained according to the first discrete power consumption data and the second discrete power consumption data of the component.

6. The method according to claim 4, characterized in that The size gradient data includes density size gradient data of the wiring density data relative to the target size data of the component; the discrete performance data includes first discrete area data and second discrete area data; The step of obtaining the size gradient data of the optimization index data corresponding to each of the components relative to the target size data based on the discrete performance data corresponding to each of the components comprises: The density size gradient data is obtained according to the first discrete area data, the second discrete area data and the potential data.

7. The method according to claim 3, characterized in that The size gradient data includes the timing size gradient data of the timing data relative to the target size data of the element; the discrete performance data includes the first discrete capacitance data, the second discrete capacitance data, the first discrete gate delay data, the second discrete gate delay data, the first discrete flipping time length data and the second discrete flipping time length data; The step of obtaining the size gradient data of the optimization index data corresponding to each of the components relative to the target size data based on the discrete performance data corresponding to each of the components comprises: Obtaining first sub-timing size gradient data according to the first discrete capacitance data, the second discrete capacitance data, the receiving pin capacitance data and the timing data; Obtaining second sub-time series size gradient data according to the first discrete gate intra-delay data, the second discrete gate intra-delay data and the target gate intra-delay data; Obtaining third sub-time series size gradient data according to the first discrete flip duration data, the second discrete flip duration data and the signal flip data; The temporal size gradient data is obtained according to the first sub-temporal size gradient data, the second sub-temporal size gradient data and the third sub-temporal size gradient data.

8. The method according to claim 2, characterized in that: The step of obtaining optimization index data corresponding to each of the components according to the circuit topology of the chip to be laid out, the first discrete size data and the second discrete size data of each of the components, and the target position data of each of the components comprises: Obtaining a calibration factor, wherein the calibration factor is determined based on a ratio of calibration index data obtained during a calibration period to external index data; Calling an internal calculation engine to calculate based on the circuit topology of the chip to be laid out, the target size data of each component and the target position data of each component to obtain initial indicator data; The optimized index data is obtained according to the calibration factor and the initial index data.

9. The method according to claim 1, characterized in that: The step of optimizing the target size data and target position data of each element according to the position gradient data and size gradient data of each element to obtain optimized target size data and target position data comprises: In the first cycle, the elements with a number of layers less than a preset number of layers in the directed acyclic graph are determined as elements to be optimized, and the target size data and target position data of the elements to be optimized are optimized according to the size gradient data and position gradient data of the elements to be optimized to obtain the optimized target size data and target position data; In the second cycle, the elements in the directed acyclic graph whose number of layers is greater than or equal to the preset number of layers are determined as elements to be optimized, and the target size data and target position data of the elements to be optimized are optimized according to the size gradient data and position gradient data of the elements to be optimized to obtain optimized target size data and target position data.

10. The method according to claim 1, characterized in that The process of optimizing the target size data of the component according to the size gradient data of each component to obtain the optimized target size data includes: Determining the element whose door size is to be optimized according to the size gradient data and the size gradient threshold of each of the elements; The target size data of the element whose door size is to be optimized is optimized to obtain optimized target size data.

11. The method according to claim 1, characterized in that: The process of optimizing the target size data of the component according to the size gradient data of each component to obtain the optimized target size data includes: Performing nonlinear mapping processing on the size gradient data of each of the components according to a preset optimization space to obtain mapped gradient data corresponding to each of the components; Each of the components is optimized according to the mapped gradient data to obtain the optimized target size data.

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