Display panel and driving method thereof

Abstract

The invention provides a display panel and a driving method thereof, a demultiplexing transistor in the display panel is connected to a corresponding data line and a corresponding demultiplexing line, and at least two demultiplexing transistors are connected to the same source line. A demultiplexing signal transmitted by the demultiplexing line is used for controlling the corresponding demultiplexing transistor to be switched on or switched off so as to control the corresponding source line and the corresponding data line to form a current path or a current open circuit, and the demultiplexing transistor comprises a first grid electrode connected to the corresponding demultiplexing line and a second grid electrode connected to the corresponding reset module; and the reset signal resets the corresponding second grid electrode through the reset module, so that the risk that the display frame is abnormal and the risk that the heat of the display panel is relatively high are reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a driving method thereof. Background Art

[0002] Demux (Demultiplexer) technology can decompose one signal channel into multiple signal channels to effectively reduce the number of lines, which is essential for the development of small-sized display panels.

[0003] However, when the demultiplexing signal acting on the Demux conducts from both sides to the middle, due to the large size of the transistors in the Demux, when the demultiplexing signal is transmitted to the transistors in the middle position, its attenuation is large, presenting a large trailing length of the demultiplexing signal. As a result, for at least two transistors connected to the same source line, when one transistor needs to be turned on, at least another transistor fails to be completely turned off, causing the data voltage to be wrongly charged to a column of sub-pixels corresponding to the transistor that fails to be completely turned off, resulting in abnormal display. Summary of the Invention

[0004] Embodiments of the present invention provide a display panel and a driving method thereof to solve the technical problem of abnormal display caused by the inability of the transistors in the Demux of the existing display panel to be turned off in time.

[0005] To solve the above technical problem, embodiments of the present invention provide a display panel, including:

[0006] Multiple sub-pixels;

[0007] Multiple data lines, the data lines being electrically connected to the corresponding multiple sub-pixels;

[0008] Multiple source lines, the source lines being used to transmit data signals;

[0009] Multiple demultiplexing transistors, the demultiplexing transistors being electrically connected to the corresponding data lines and corresponding demultiplexing lines, at least two of the demultiplexing transistors being electrically connected to the same source line, the demultiplexing signal transmitted by the demultiplexing line being used to control the corresponding demultiplexing transistor to be turned on or off, so as to control a current path or a current break to be formed between the corresponding source line and a corresponding data line, the demultiplexing transistor including a first gate and a second gate, the first gate being electrically connected to the corresponding demultiplexing line;

[0010] Multiple reset modules, the reset modules being connected to the second gate, and the reset modules being used to reset the second gate of the demultiplexing transistor according to a reset signal.

[0011] In some embodiments, the reset module includes:

[0012] A reset transistor, a gate of the reset transistor is electrically connected to a reset line for transmitting the reset signal, one of a source and a drain of the reset transistor is electrically connected to a power supply line, and the other of the source and the drain of the reset transistor is electrically connected to the corresponding second gate.

[0013] In some embodiments, a first amplitude of the demultiplexing signal is used to control conduction of the corresponding demultiplexing transistor, and a second amplitude of the demultiplexing signal is used to control cutoff of the corresponding demultiplexing transistor;

[0014] Wherein, gates of at least two reset transistors respectively corresponding to at least two demultiplexing transistors electrically connected to the same source line are electrically connected to the same reset line, and the reset signal is used to control conduction of the corresponding reset transistor when an amplitude of at least one of the corresponding at least two demultiplexing signals jumps from the first amplitude to the second amplitude.

[0015] In some embodiments, the reset signal includes a plurality of reset pulses, and time periods of the plurality of reset pulses respectively overlap at least partially with time periods of amplitudes of corresponding plurality of demultiplexing signals jumping from the first amplitude to the second amplitude on a time axis.

[0016] In some embodiments, a first amplitude of the demultiplexing signal is used to control conduction of the corresponding demultiplexing transistor, and a second amplitude of the demultiplexing signal is used to control cutoff of the corresponding demultiplexing transistor;

[0017] Wherein, gates of at least two reset transistors respectively corresponding to at least two demultiplexing transistors electrically connected to the same source line are electrically connected to different reset lines, and each reset signal is used to control conduction of the corresponding reset transistor when an amplitude of the corresponding demultiplexing signal jumps from the first amplitude to the second amplitude.

[0018] In some embodiments, the reset signal includes a first sub-reset signal, and a time period of the first sub-reset signal coincides with a time period when an amplitude of the corresponding demultiplexing signal is the second amplitude on a time axis; wherein, the first sub-reset signal in the reset signal is used to control conduction of the corresponding reset transistor.

[0019] In some embodiments, multiple display frames of the display panel include multiple first type frames and multiple second type frames, and the multiple demultiplexing signals include multiple first type demultiplexing signals and multiple second type demultiplexing signals;

[0020] Wherein, the multiple demultiplexing transistors include:

[0021] A plurality of first-type demultiplexing transistors, at least two of the first-type demultiplexing transistors corresponding to the same source line are used to be turned on in a time-sharing manner within the first-type frame according to the corresponding at least two first-type demultiplexing signals;

[0022] A plurality of second-type demultiplexing transistors, at least two of the second-type demultiplexing transistors corresponding to the same source line are used to be turned on in time-sharing within the second-type frame according to the corresponding at least two second-type demultiplexing signals.

[0023] In some embodiments, the polarity of the data signal transmitted by the source line in the first type of frame is opposite to that in the second type of frame.

[0024] In some embodiments, the same data line is electrically connected to a plurality of sub-pixels of the same color, and at least two data lines corresponding to the same source line are electrically connected to at least two sub-pixels of different colors respectively;

[0025] The color types of the sub-pixels corresponding to the plurality of first-type demultiplexing transistors and the color types of the sub-pixels corresponding to the plurality of second-type demultiplexing transistors are the same.

[0026] An embodiment of the present invention provides a method for driving a display panel, wherein the display panel comprises:

[0027] Multiple sub-pixels;

[0028] A plurality of data lines, wherein the data lines are electrically connected to the corresponding plurality of sub-pixels;

[0029] A plurality of source lines, wherein the source lines are used to transmit data signals;

[0030] A plurality of demultiplexing transistors, wherein the demultiplexing transistors are electrically connected to the corresponding data lines and the corresponding demultiplexing lines, at least two of the demultiplexing transistors are electrically connected to the same source line, and the demultiplexing transistors include a first gate and a second gate, and the first gate is electrically connected to the corresponding demultiplexing line;

[0031] A plurality of reset modules, each of which is electrically connected to the corresponding second gate;

[0032] The driving method of the display panel includes:

[0033] The demultiplexing signal transmitted by the demultiplexing line controls the corresponding demultiplexing transistor to change from on to off, so as to control the current path between the corresponding source line and the corresponding data line to change from a current disconnection, and the corresponding reset signal controls the resetting of the first gate of the demultiplexing transistor.

[0034] The present invention provides a display panel and a driving method thereof, wherein a demultiplexing transistor in the display panel is connected to a corresponding data line and a corresponding demultiplexing line, at least two demultiplexing transistors are connected to the same source line, and a demultiplexing signal transmitted by the demultiplexing line is used to control the corresponding demultiplexing transistor to be turned on or off so as to control the formation of a current path or a current disconnection between the corresponding source line and a corresponding data line. By setting the demultiplexing transistor to include a first gate connected to the corresponding demultiplexing line and a second gate connected to a corresponding reset module, the demultiplexing transistor that should have been turned off is controlled to be quickly turned off to reduce the risk of abnormal display image, and the risk of high heat of the display panel is also reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The present invention provides a display panel and a display device to which the display panel belongs.

[0036] Figure 2 , Figure 6 Schematic diagrams of connections among sub-pixels, source lines, data lines, etc. in a display panel provided by two embodiments of the present invention.

[0037] Figures 3 to 5 For the comparative examples of the present invention and Figure 2 An embodiment of the present invention provides a timing diagram of some signals in a display panel.

[0038] Figure 7 For the comparative examples of the present invention and Figure 6 An embodiment of the present invention provides a timing diagram of some signals in a display panel. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0040] The terms "first", "second", etc. in the present invention are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules that are not listed, or may optionally include other steps or modules that are inherent to these processes, methods, products or devices.

[0041] References to "embodiments" in this specification mean that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the invention. The appearances of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they separate or alternative embodiments mutually exclusive of other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0042] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0043] Embodiments of the present invention provide a display panel, and the display panel includes but is not limited to the following embodiments and combinations between the following embodiments.

[0044] In one embodiment, in combination with Figure 1 and Figure 2 as shown, the display panel 100 includes: a plurality of sub-pixels 301; a plurality of data lines (DL1 to DLm), the data lines being electrically connected to the corresponding plurality of sub-pixels 301; a plurality of source lines (S1 to SM), the source lines being used to transmit a data signal Data; a plurality of demultiplexing transistors (T1 to Tm), one of the demultiplexing transistors (T1 to Tm) being electrically connected to the corresponding data line (one of DL1 to DLm corresponding thereto) and the corresponding demultiplexing line (for example, one of CKA1, CKB1, CKA2, CKB2 corresponding thereto), at least two of the demultiplexing transistors (two of T1 to Tm) being electrically connected to the same source line (one of S1 to SM), the demultiplexing signal (for example, one of cka1, ckb1, cka2, ckb2) transmitted by the demultiplexing line being used to control the corresponding demultiplexing transistor (one of T1 to Tm) to be turned on or off, so as to control a current path or a current break to be formed between the corresponding source line (one of S1 to SM) and the corresponding data line (one of DL1 to DLm), the demultiplexing transistor including a first gate g1 and a second gate g2, the first gate g1 being electrically connected to the corresponding demultiplexing line; a plurality of reset modules 50, the reset modules 50 being connected to the second gate g2, and the reset modules 50 being used to reset the second gate g2 of the demultiplexing transistor according to a reset signal reset.

[0045] Specifically, as Figure 1As shown, the display panel 100 may further include a gate driving circuit 10 located on one side of a plurality of sub-pixels 301. The display device 200 may include the above-mentioned display panel 100. The display device 200 may further include a timing controller 401 and at least one source driver 402. The timing controller 401 and at least one source driver 402 may be integrated on the same chip or may be independently provided. The gate driving unit 101 in the gate driving circuit 10 may be electrically connected between the timing controller 401 and the corresponding plurality of sub-pixels 301 for outputting a gate signal Gate transmitted to the corresponding plurality of sub-pixels 301; each source driver 402 is electrically connected between the timing controller 401 and the corresponding plurality of sub-pixels 301 for outputting a data signal Data transmitted to the corresponding plurality of sub-pixels 301.

[0046] For ease of description, here, an example is given in which a plurality of sub-pixels 301 are arranged in an array of n rows and m columns (both n and m are positive integers).

[0047] As Figure 1 shown, the gate driving circuit 10 may at least include n levels of gate driving units 101. The gate driving circuit 10 (at least one gate driving unit 101 therein) is controlled by the timing controller 401 so that each gate driving unit 101 generates a corresponding gate signal Gate. The n levels of gate signals Gate are respectively transmitted to the n rows of sub-pixels 301 through n gate lines (GL1 to GLn). The n gate pulses respectively used to turn on the n rows of sub-pixels 301 among the n levels of gate signals may be arranged in sequence on the time axis to turn on the multiple rows of sub-pixels 301 in sequence.

[0048] The source driver 402 is controlled by the timing controller 401 to generate m data signals Data respectively output to the m columns of sub-pixels 301 through m data lines (DL1 to DLm). Each data signal Data may include n data voltages corresponding to the n sub-pixels 301 in the same column. When each row of sub-pixels 301 is turned on, the m data lines (DL1 to DLm) also receive the multiple data voltages corresponding to the multiple sub-pixels 301 in that row, so that the multiple data voltages act on the multiple sub-pixels 301 in that row, causing the multiple sub-pixels 301 in that row to emit light. And so on, all rows of sub-pixels 301 can be controlled to emit light in sequence to present a complete picture.

[0049] In order to save the number of pins of the source driver 402 and thus reduce the number of source drivers 402, in this embodiment, a plurality of demultiplexing transistors (T1 to Tm) are arranged between a plurality of source lines (S1 to SM) and a plurality of data lines (DL1 to DLm), and each source line is electrically connected to the corresponding at least two data lines (at least two of T1 to Tm) through at least two demultiplexing transistors (at least two of T1 to Tm), and the corresponding at least two demultiplexing signals (for example, cka1 and ckb1, or for example, cka2 and ckb2) are used to control at least two first gates g of the corresponding at least two demultiplexing transistors to control the at least two demultiplexing transistors to be turned on in time-sharing within a unit time, so as to control the corresponding source line to form a current path between the corresponding two data lines in time-sharing within a unit time.

[0050] It can be understood that the multiple demultiplexing transistors (T1 to Tm) in this embodiment also include a second gate g2, and the potential of the second gate g2 is controlled by the reset module 50. The reset module 50 is used to reset the second gate g2 according to the reset signal reset so that the demultiplexing transistor is turned off, so that at least two demultiplexing transistors electrically connected to the same source line (one of S1 to SM), when one of the demultiplexing transistors is turned on to form a current path between the source line and the corresponding data line (one of DL1 to DLm), the reset signal reset can control the potential of the second gate g2 of the remaining at least one demultiplexing transistor to turn off the demultiplexing transistor, thereby avoiding the current data voltage from being mistakenly transmitted to at least one data line corresponding to the "remaining at least one demultiplexing transistor", thereby reducing the risk of abnormal display screen.

[0051] At the same time, since multiple demultiplexing transistors (T1 to Tm) all have a dual-gate structure, that is, they include an independent first gate g1 and a second gate g2, the first gate g1 and the second gate g2 can be arranged in series. Since the two independent gates regulate the channel current, the off-state leakage current of the demultiplexing transistor can be significantly reduced, while the on-state current is enhanced, thereby improving the switching ratio. In this embodiment, it can be understood that the risk of excessive heat caused by the overlap of the effective potentials of the demultiplexing signal acting on the first gate g1 and the signal acting on the second gate g2 (such as the power supply signal vgl mentioned later) can be reduced.

[0052] In some embodiments, Figure 2As shown, the reset module 50 includes: a reset transistor (one of Tr1 to Trm), a gate of the reset transistor is electrically connected to a reset line Reset for transmitting the reset signal reset, one of a source and a drain of the reset transistor is electrically connected to a power supply line VGL, and the other of the source and the drain of the reset transistor is electrically connected to the corresponding second gate g2. Wherein, the reset signal reset controls the potential of the gate of the reset transistor (one of Tr1 to Trm), so that when the reset transistor is turned on, the power supply signal vgl transmitted by the power supply line VGL is transmitted to the second gate g2 of at least one demultiplexing transistor (one of T1 to Tm) to reset it, thereby turning off the demultiplexing transistor.

[0053] In some embodiments, in combination with Figures 2 to 5 As shown, a first amplitude a1 in the amplitudes of the demultiplexing signals (cka1, ckb1, cka2 or ckb2) is used to control conduction of the corresponding demultiplexing transistor (one of T1 to Tm), and a second amplitude a2 in the amplitudes of the demultiplexing signals is used to control cutoff of the corresponding demultiplexing transistor; gates of at least two of the demultiplexing transistors (at least two of T1 to Tm) respectively corresponding to at least two of the reset transistors (at least two of Tr1 to Trm) that are electrically connected to the same source line (one of S1 to SM) are electrically connected to the same reset line Reset; wherein, the reset signal reset is used to control conduction of the corresponding reset transistor when at least one of the amplitudes of at least two of the corresponding demultiplexing signals (such as cka1 and ckb1, or such as cka2 and ckb2) jumps from the first amplitude a1 to the second amplitude a2.

[0054] For ease of description, here, it is taken as an example that the same source line is electrically connected to corresponding two data lines through corresponding two demultiplexing transistors, the demultiplexing transistors and the reset transistors are in one-to-one correspondence, and the amplitude of each demultiplexing signal alternately includes a first amplitude a1 and a second amplitude a2. As Figures 3 to 5 shown, the source signal s1 transmitted by the source line S1 may alternately include a data voltage Vd1 corresponding to the data line DL1 and a data voltage Vd3 corresponding to the data line DL3, and the source signal s2 transmitted by the source line S2 may alternately include a data voltage Vd2 corresponding to the data line DL2 and a data voltage Vd4 corresponding to the data line DL4.

[0055] For example, the source line S1 is electrically connected to the data line DL1 through the demultiplexing transistor T1, and is also electrically connected to the data line DL3 through the demultiplexing transistor T2. The first gate g1 of the demultiplexing transistor T1 is electrically connected to the demultiplexing line CKA1, and the first gate g1 of the demultiplexing transistor T2 is electrically connected to the demultiplexing line CKB1. The second gate of the demultiplexing transistor T1 is electrically connected to the reset transistor Tr1, and the gate of the demultiplexing transistor T2 is electrically connected to the reset transistor Tr2.

[0056] In the comparative example provided by the present invention, the above-mentioned reset module 50 is not included. At this time, when the demultiplexing signal cka1' and the demultiplexing signal ckb1' are conducted from both sides to the middle, due to the large size of the demultiplexing transistor, the trailing lengths of the demultiplexing signal cka1' and the demultiplexing signal ckb1' are relatively large, that is, the time required for the amplitudes of the two to switch between the first amplitude a1 and the second amplitude a2 is longer. As a result, when the amplitude of the demultiplexing signal cka1' switches from the first amplitude a1 to the second amplitude a2, that is, when the demultiplexing transistor T1 is about to switch from the on state to the off state, the corresponding demultiplexing transistor T1 turns off slowly, causing the data voltage Vd3 corresponding to the data line DL3 currently transmitted by the source line S1 to be erroneously transmitted to the corresponding data line DL1, resulting in display anomalies.

[0057] In the embodiment provided by the present invention, the above-mentioned reset module 50 is included. As Figure 3 and Figure 5 shown, when the amplitude of the demultiplexing signal cka1 switches from the first amplitude a1 to the second amplitude a2, since the reset signal reset controls the reset transistor Tr1 to conduct, the power supply signal vgl can be transmitted to the second gate g2 of the demultiplexing transistor T1, thereby promoting the demultiplexing transistor T1 to turn off, and avoiding the data voltage Vd3 corresponding to the data line DL3 currently transmitted by the source line S1 from being erroneously transmitted to the corresponding data line DL1. Similarly, when the amplitude of the demultiplexing signal ckb1 switches from the first amplitude a1 to the second amplitude a2, since the reset signal reset controls the reset transistor Tr2 to conduct, the power supply signal vgl can be transmitted to the second gate g2 of the demultiplexing transistor T2, thereby promoting the demultiplexing transistor T2 to turn off, and avoiding the data voltage Vd1 corresponding to the data line DL1 currently transmitted by the source line S1 from being erroneously transmitted to the corresponding data line DL3.

[0058] Similarly, Figure 4 and Figure 5When the amplitude of the demultiplexing signal cka2 switches from the first amplitude a1 to the second amplitude a2, the reset signal reset controls the reset transistor Tr3 to conduct, and the power supply signal vgl promotes the demultiplexing transistor T3 to cut off; when the amplitude of the demultiplexing signal ckb2 switches from the first amplitude a1 to the second amplitude a2, the reset signal reset controls the reset transistor Tr4 to conduct, and the power supply signal vgl promotes the demultiplexing transistor T4 to cut off.

[0059] Specifically, as shown in Figures 2 to 5 the reset signal reset includes a plurality of reset pulses p, and the time periods of the plurality of reset pulses p at least partially overlap on the time axis with the time periods during which the amplitudes of the corresponding plurality of demultiplexing signals (such as cka1, ckb1, cka2, ckb2) jump from the first amplitude a1 to the second amplitude a2.

[0060] It can be understood that, for the demultiplexing transistors T1 and T2 connected to the same source line S1 in this embodiment, when the amplitude of the demultiplexing signal cka1 corresponding to one of them (for example, the demultiplexing transistor T1) jumps from the first amplitude a1 to the second amplitude a2, that is, when the demultiplexing transistor T1 is about to switch from the conducting state to the cut-off state, the reset signal reset acts on the second gate g2 of the demultiplexing transistor T1 with the corresponding reset pulse p at this time, at least enabling the demultiplexing transistor T1 to quickly switch to the cut-off state, and thereafter, since the amplitude of the demultiplexing signal cka1 is stabilized at the second amplitude a2, the cut-off state of the demultiplexing transistor T1 can be stabilized. At the same time, since the amplitude of the demultiplexing signal cka2 acting on the demultiplexing transistor T2 is stabilized at the first amplitude a1, the demultiplexing transistor T2 also only briefly cuts off and then immediately jumps to the conducting state, thereby reducing the risk of mischarging of the data voltage.

[0061] Similarly, when the amplitude of the demultiplexing signal ckb1 switches from the first amplitude a1 to the second amplitude a2, the reset signal reset is also the corresponding reset pulse p at this time, thereby controlling the reset transistor Tr2 to conduct, and the power supply signal vgl can be transmitted to the second gate g2 of the demultiplexing transistor T2 and the second gate g2 of the demultiplexing transistor T1, thereby promoting the demultiplexing transistor T2 to cut off. Although the demultiplexing transistor T1 instantaneously cuts off, thereafter, controlled by the first amplitude a1 of the demultiplexing signal ckb1 acting on its first gate g1, the demultiplexing transistor T1 will be stabilized in the conducting state.

[0062] Combined with the above discussion, it can be seen that the number of reset pulses p of the reset signal reset in one frame in this embodiment can be equal to the sum of the number of times the amplitudes of the plurality of demultiplexing signals jump from the first amplitude a1 to the second amplitude a2. Further, as shown in Figure 3 and Figure 4As shown, the start time of each reset pulse p can be the same as the end time of the corresponding first amplitude a1, and the end time of each reset pulse p can be the same as or earlier than the start time of the corresponding second amplitude a2, so as to avoid causing a delay in the turn-on of the demultiplexing transistor that should have been turned on due to being later than the start time of the corresponding second amplitude a2.

[0063] In some embodiments, different from Figures 2 to 5 As shown, in combination with Figure 6 and Figure 7 As shown, based on the above discussion about the first amplitude a1 transitioning to the second amplitude a2, in this embodiment, at least two of the reset transistors (at least two of Tr1 to Trm) respectively corresponding to at least two of the demultiplexing transistors (at least two of T1 to Tm) electrically connected to the same source line (one of S1 to SM) have their gates electrically connected to different reset lines Reset (at least the first reset line Reset1 and the second reset line Reset2); wherein, each reset signal reset (at least the first reset signal reset1 and the second reset signal reset2) is used to control the corresponding reset transistor (one of Tr1 to Trm) to turn on when the amplitude of the corresponding demultiplexing signal (one of cka1, ckb1, cka2, ckb2) transitions from the above first amplitude a1 to the above second amplitude a2.

[0064] The difference between this embodiment and the embodiment shown above Figures 2 to 5 is that in this embodiment, the multiple reset transistors (i.e., Tr1, Tr2) corresponding to the multiple demultiplexing transistors (i.e., T1, T2) connected to the same source line (such as S1) are respectively controlled by different reset signals reset (the first reset signal reset1 and the second reset signal reset2). When the amplitude of the corresponding demultiplexing signal (such as cka1) transitions from the first amplitude a1 to the second amplitude a2, one of the reset signals reset (such as the first reset signal reset1) only controls the corresponding one reset transistor (i.e., Tr1) to turn off, thus not affecting the on-state of the other reset transistors (i.e., Tr2).

[0065] Therefore, in combination with Figure 6 and Figure 7As shown, in this embodiment, for each of multiple reset transistors (i.e., Tr1 and Tr2) corresponding to the same source line (e.g., S1), a corresponding reset signal reset is separately set (for example, Tr1 is controlled by the first reset signal reset1, and Tr2 is controlled by the second reset signal reset2), and the waveforms of the multiple reset signals reset (including the first reset signal reset1 and the second reset signal reset2) corresponding to the multiple reset transistors corresponding to the same source line are different, so as to separately control the conduction periods of the multiple reset transistors (i.e., Tr1 and Tr2), reduce the risk that the demultiplexing transistor (i.e., T2 or T1) that should originally conduct is instantaneously cut off, improve the charging efficiency of the corresponding column of sub-pixels 301, and enhance the quality of the displayed image.

[0066] Specifically, as Figure 7 shown, each of the reset signals reset (each of the first reset signal reset1 and the second reset signal reset2) includes a first sub-reset signal (i.e., the corresponding reset pulse, for example, the first reset pulse p1 in the first reset signal reset1 and the second reset pulse p2 in the second reset signal reset2), and the period in which the first sub-reset signal is located coincides with the period in which the amplitude of the corresponding demultiplexing signal (one of cka1, ckb1, cka2, ckb2) is the second amplitude a2 on the time axis; wherein, the first sub-reset signal in the reset signal reset is used to control the corresponding reset transistor to conduct.

[0067] For example, for the source line S1, the period in which the first reset pulse p1 is located coincides with the period in which the amplitude of the corresponding demultiplexing signal cka1 is the second amplitude a2 on the time axis, so as to promote the reset transistor Tr1 to cut off at this time. At this time, since the amplitude of the demultiplexing signal ckb1 is the first amplitude a1, that is, the second reset signal reset2 is not the corresponding second reset pulse p2, the reset transistor Tr2 remains conducting; similarly, the period in which the second reset pulse p2 is located coincides with the period in which the amplitude of the corresponding demultiplexing signal ckb1 is the second amplitude a2 on the time axis, so as to promote the reset transistor Tr2 to cut off at this time. At this time, since the amplitude of the demultiplexing signal cka1 is the first amplitude a1, that is, the second reset signal reset1 is not the corresponding first reset pulse p1, the reset transistor Tr1 remains conducting.

[0068] Similarly, for the source line S2, the two demultiplexing signals (cka2 and ckb2) acting on its corresponding two reset transistors (Tr3 and Tr4) can be understood in the same way by referring to the discussion in the above text about the source line S1, its corresponding two reset transistors (Tr1 and Tr2), the corresponding two demultiplexing signals (cka1 and ckb2), and the corresponding two de - reset transistors (T1 and T2).

[0069] It should be noted that Figure 7 drawing the waveforms of cka1 and cka2 to be the same in [reference] does not limit them to be actually the same, and drawing the waveforms of ckb1 and ckb2 to be the same does not limit them to be actually the same. The aim is to indicate that Figure 7 the last two waveforms in [reference] can be the waveforms of cka1 and ckb1 respectively, or the waveforms of cka2 and ckb2 respectively, which is only used to illustrate the relative relationship of Figure 7 the aforementioned six signals in [reference].

[0070] It can be understood that taking the source line S1 as an example, during the period when the amplitude of its corresponding demultiplexing signal cka1 is the second amplitude a2, that is, during the period when the demultiplexing transistor T1 should be cutoff, the first reset signal reset1 is the corresponding first sub - reset signal (i.e., the first reset pulse p1), making the reset transistor Tr1 conductive, so that the power supply signal vgl is transmitted to the second gate g2 of the demultiplexing transistor T1. Therefore, it can promote the demultiplexing transistor T1 to be in the cutoff state, and during the entire period when the amplitude of the demultiplexing signal cka1 is the second amplitude a2, it can assist in stabilizing the cutoff state of the demultiplexing transistor T1.

[0071] In some embodiments, in combination with Figures 1 to 7As shown, the multiple frames of display screen of the display panel 100 include multiple first-type frames (for example, multiple odd-numbered frames), multiple second-type frames (for example, multiple even-numbered frames), and the multiple demultiplexed signals include multiple first-type demultiplexed signals (for example, including cka1, ckb1) and multiple second-type demultiplexed signals (for example, including cka2, ckb2); wherein the multiple demultiplexed transistors (Tr1 to Trm) include: multiple first-type demultiplexed transistors (for example, T1 and T2, T5 and T6, T9 and T10...), and the same source line (for example, S1) corresponds to At least two of the first-type demultiplexing transistors (i.e., T1 and T2) are used to be turned on in time-sharing within the first-type frame (i.e., odd-numbered frame) according to the corresponding at least two of the first-type demultiplexing signals (i.e., cka1 and ckb1); multiple second-type demultiplexing transistors (e.g., T3 and T4, T7 and T8, T11 and T12...), at least two of the second-type demultiplexing transistors corresponding to the same source line (e.g., S2) are used to be turned on in time-sharing within the second-type frame (i.e., even-numbered frame) according to the corresponding at least two of the second-type demultiplexing signals (i.e., cka2 and ckb2).

[0072] For example, in this embodiment, in an odd-numbered frame, two first-type demultiplexing transistors (i.e., two in a group of "T1 and T2", "T5 and T6", "T9 and T10"...) connected to source lines with odd numbers (e.g., one of S1, S3, S5...) are used for time-sharing conduction, so that each source line is electrically connected to the corresponding two data lines (i.e., two in a group of "DL1 or DL3", "DL5 or DL7", "DL9 or DL11"...) in a time-sharing manner; in an even-numbered frame, two first-type demultiplexing transistors (i.e., two in a group of "T3 and T4", "T7 and T8", "T11 and T12"...) connected to source lines with even numbers (e.g., one of S2, S4, S6...) are used for time-sharing conduction, so that each source line is electrically connected to the corresponding two data lines (i.e., two in a group of "DL2 or DL4", "DL6 or DL8", "T10 or DL12"...) in a time-sharing manner.

[0073] It can be understood that, taking the reset signal reset as an example, the embodiment sets the multiple demultiplexed signals to include multiple first-class demultiplexed signals (such as Figure 5Both ka1 and ckb1 in it only have their amplitudes alternately including a first amplitude a1 and a second amplitude a2 within the first type of frame, while their amplitudes are constantly the second amplitude a2 within the second type of frame), so as to control a corresponding part of the data lines corresponding to a part of the source lines to be able to receive the corresponding data signal Data within the first type of frame, so as to perform picture display; in addition, a plurality of demultiplexing signals are set to further include a plurality of second type demultiplexing signals that work in a time-sharing manner within the second type of frame and stop working within the first type of frame (such as Figure 5 Both ka2 and ckb2 in it only have their amplitudes alternately including a first amplitude a1 and a second amplitude a2 within the second type of frame, while their amplitudes are constantly the second amplitude a2 within the first type of frame), so as to control a corresponding other part of the data lines corresponding to a part of the source lines to be able to receive the corresponding data signal Data within the second type of frame, so as to perform picture display.

[0074] It can be seen from this that in this embodiment, the sub-pixels 301 of some columns are respectively controlled to perform picture display within the first type of frame and the second type of frame. When the refresh rate is high enough, even if there are differences in the color distributions of the multi-color sub-pixels 301 in the multi-columns of sub-pixels 301 that perform picture display within the first type of frame and the color distributions of the multi-color sub-pixels 301 in the multi-columns of sub-pixels 301 that perform picture display within the second type of frame, the human eye will not distinguish the multi-parts of sub-pixels 301 displayed successively, but perceives a complete frame of picture formed by superimposing the pictures of the first type of frame and the second type of frame within each cycle period. And because the light-emitting duration of each sub-pixel 301 within the first type of frame and the second type of frame is only half of the normal display, the power consumption of the display panel 100 is reduced.

[0075] In some embodiments, in combination with Figures 1 to 7 As shown, the polarities of the data signals transmitted by the source lines within the first type of frame and within the second type of frame are opposite. That is, within the first type of frame, the data voltages in the data signals transmitted by the source lines are all one of the positive polarity + and the negative polarity -; within the second type of frame, the data voltages in the data signals transmitted by the source lines are all the other of the positive polarity + and the negative polarity -. For example, within the first type of frame, the data voltages (Vd1 and Vd3) in the source signal s1 transmitted by the source line S1 and the data voltages (Vd2 and Vd4) in the source signal s2 transmitted by the source line S2 are all one of the positive polarity + and the negative polarity -; within the second type of frame, the data voltages (Vd1 and Vd3) in the source signal s1 transmitted by the source line S1 and the data voltages (Vd2 and Vd4) in the source signal s2 transmitted by the source line S2 are all the other of the positive polarity + and the negative polarity -.

[0076] Combined with the above discussion, it can be seen that in the first type of frame, since the two first type demultiplexing transistors (i.e., one of "T1 and T2", "T5 and T6", "T9 and T10" ...) connected to the source line with an odd number (e.g., one of S1, S3, S5 ...) are turned on in time sharing, the corresponding data line (i.e., one of "DL1 or DL3", "DL5 or DL7", "DL9 or DL11" ...) obtains data with a polarity of one of positive polarity + and negative polarity - (e.g., positive polarity +) in time sharing. Voltage; and in the second type of frame, since the two second type demultiplexing transistors (i.e., one of "T3 and T4", "T7 and T8", "T11 and T12"...) connected to the source lines with even numbers (e.g., one of S2, S4, S6...) are turned on in time sharing, the corresponding data lines (i.e., one of "DL2 or DL4", "DL6 or DL8", "T10 or DL12"...) obtain the data voltage of the other one of the positive polarity + and negative polarity - (e.g., negative polarity -) in time sharing.

[0077] Therefore, this embodiment controls some columns of sub-pixels 301 to display images with opposite polarities in the first frame and the second frame respectively. For the liquid crystal display device, the liquid crystal molecules can be deflected in opposite directions in the first frame and the second frame respectively, reducing the risk of liquid crystal deterioration.

[0078] In some embodiments, in combination Figures 1 to 7 As shown, the same data line (one of DL1 to DLm) is electrically connected to the multiple sub-pixels 301 of the same color (multiple red sub-pixels R, multiple green sub-pixels G or multiple blue sub-pixels B), and at least two data lines corresponding to the same source line (one of S1 to SM) are respectively electrically connected to at least two sub-pixels 301 of different colors (red sub-pixel R, green sub-pixel G or blue sub-pixel B); wherein the color types of the sub-pixels 301 corresponding to the multiple first-type demultiplexing transistors ("T1 and T2", "T5 and T6", "T9 and T10"...) and the color types of the sub-pixels 301 corresponding to the multiple second-type demultiplexing transistors ("T3 and T4", "T7 and T8", "T11 and T12"...) are the same, for example, all include red, blue, and green.

[0079] It can be understood that the same data line (one of DL1 to DLm) in this embodiment is electrically connected to multiple sub-pixels 301 of the same color. Since the grayscale value difference between adjacent quantum pixels 301 of the same color in the display screen is small, the fluctuation amplitude of the data signal Data can be reduced, thereby reducing power consumption. At the same time, at least two data lines corresponding to the same source line (one of S1 to SM) in this embodiment are respectively electrically connected to at least two sub-pixels of different colors, so that at least two sub-pixels 301 of different colors perform screen display within the first type of frame or the second type of frame, and the types of colors of the sub-pixels 301 corresponding to the source lines with odd numbers and the source lines with even numbers are the same, so that the types of colors of the sub-pixels 301 performing screen display within the first type of frame or the second type of frame are the same, improving the consistency of the display screen.

[0080] For example Figure 2 and Figure 6 As shown, in the horizontal direction, the colors of multiple columns of sub-pixels 301 can be arranged with "red, green, blue" as a repeating unit, and starting from the first demultiplexing transistor T1, every two consecutive first-type demultiplexing transistors and every two consecutive second-type demultiplexing transistors are divided into a group, and each group can be connected to four consecutive columns of sub-pixels 301. On this basis, in order to facilitate the uniformity of the number of colors of the sub-pixels 301 and the uniform setting of the numbers of both the first-type demultiplexing transistors and the second-type demultiplexing transistors, the number of columns of the sub-pixels 301 can be set to an integer multiple of 12.

[0081] The embodiment of the present invention provides a driving method for a display panel, which can be applied to, but not limited to, the above display panel 100. The driving method of the display panel includes, but is not limited to, the following embodiments and combinations between the following embodiments.

[0082] In some embodiments, the driving method of the display panel includes, but is not limited to, the following steps:

[0083] S1, when the demultiplexing signal transmitted by the demultiplexing line controls the corresponding demultiplexing transistor to change from conduction to cut-off, so as to control the current path between the corresponding source line and the corresponding data line to become an open circuit, the corresponding reset signal controls the second gate of the corresponding demultiplexing transistor to be reset.

[0084] As described above, for at least two demultiplexing transistors electrically connected to the same source line (one of S1 to SM), for example, when the amplitude of the demultiplexing signal cka1 switches from the first amplitude a1 to the second amplitude a2, the reset transistor Tr1 is controlled to conduct by the reset signal reset, so that the power supply signal vgl can be transmitted to the second gate g2 of the demultiplexing transistor T1, thereby promoting the demultiplexing transistor T1 to turn off, and avoiding the mistransmission of the data voltage Vd3 corresponding to the data line DL3 currently transmitted by the source line S1 to the corresponding data line DL1.

[0085] Of course, at the same time, it is also necessary for the gate driving circuit 10 to control multiple rows of sub-pixels 301 to be turned on in sequence. Meanwhile, the potential of the first gate g1 of the corresponding demultiplexing transistor is controlled by the demultiplexing signal, and the on-state of the reset transistor is controlled by the reset signal reset to further control the potential of the second gate g2 of the demultiplexing transistor, so as to achieve that the second gate g2 of each of the multiple demultiplexing transistors connected to the same source line is affected by the power supply signal vgl when it should be turned off, so that it quickly turns off and reduces the risk of mischarging of the data voltage.

[0086] The above has introduced in detail the display panel and its driving method provided by the embodiments of the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present invention; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: include: Multiple sub-pixels; A plurality of data lines, wherein the data lines are electrically connected to the corresponding plurality of sub-pixels; A plurality of source lines, wherein the source lines are used to transmit data signals; a plurality of demultiplexing transistors, wherein the demultiplexing transistors are electrically connected to the corresponding data lines and the corresponding demultiplexing lines, and at least two of the demultiplexing transistors are electrically connected to the same source line, and the demultiplexing signal transmitted by the demultiplexing line is used to control the corresponding demultiplexing transistor to be turned on or off, so as to control the formation of a current path or a current disconnection between the corresponding source line and a corresponding one of the data lines, and the demultiplexing transistor includes a first gate and a second gate, and the first gate is electrically connected to the corresponding demultiplexing line; A plurality of reset modules are provided, wherein the reset modules are connected to the second gate and are used for resetting the second gate of the demultiplexing transistor according to a reset signal.

2. The display panel according to claim 1, characterized in that: The reset module comprises: A reset transistor, wherein the gate of the reset transistor is electrically connected to a reset line for transmitting the reset signal, one of the source and the drain of the reset transistor is electrically connected to a power line, and the other of the source and the drain of the reset transistor is electrically connected to the corresponding second gate.

3. The display panel according to claim 2, characterized in that: A first amplitude of the amplitude of the demultiplexing signal is used to control the corresponding demultiplexing transistor to be turned on, and a second amplitude of the amplitude of the demultiplexing signal is used to control the corresponding demultiplexing transistor to be turned off; In which, the gates of at least two reset transistors corresponding to at least two demultiplexing transistors electrically connected to the same source line are electrically connected to the same reset line, and the reset signal is used to control the corresponding reset transistor to be turned on when the amplitude of at least one of the corresponding at least two demultiplexing signals jumps from the first amplitude to the second amplitude.

4. The display panel according to claim 3, characterized in that: The reset signal includes a plurality of reset pulses, and time periods of the plurality of reset pulses at least partially overlap with time periods of the amplitudes of the corresponding plurality of demultiplexed signals jumping from the first amplitude to the second amplitude on a time axis.

5. The display panel according to claim 2, characterized in that: A first amplitude of the amplitude of the demultiplexing signal is used to control the corresponding demultiplexing transistor to be turned on, and a second amplitude of the amplitude of the demultiplexing signal is used to control the corresponding demultiplexing transistor to be turned off; Among them, the gates of at least two reset transistors corresponding to at least two demultiplexing transistors electrically connected to the same source line are electrically connected to different reset lines, and each reset signal is used to control the corresponding reset transistor to be turned on when the amplitude of the corresponding demultiplexing signal jumps from the first amplitude to the second amplitude.

6. The display panel according to claim 5, characterized in that: The reset signal includes a first sub-reset signal, and the time period of the first sub-reset signal coincides with the time period of the corresponding demultiplexed signal when the amplitude is the second amplitude on the time axis; wherein the first sub-reset signal in the reset signal is used to control the corresponding reset transistor to be turned on.

7. The display panel according to any one of claims 1 to 6, characterized in that: The multiple frames of display pictures of the display panel include multiple first-type frames and multiple second-type frames, and the multiple demultiplexed signals include multiple first-type demultiplexed signals and multiple second-type demultiplexed signals; Wherein, the plurality of demultiplexing transistors include: A plurality of first-type demultiplexing transistors, at least two of the first-type demultiplexing transistors corresponding to the same source line are used to be turned on in a time-sharing manner within the first-type frame according to the corresponding at least two first-type demultiplexing signals; A plurality of second-type demultiplexing transistors, at least two of the second-type demultiplexing transistors corresponding to the same source line are used to be turned on in time-sharing within the second-type frame according to the corresponding at least two second-type demultiplexing signals.

8. The display panel according to claim 7, characterized in that: The polarity of the data signal transmitted by the source line in the first type of frame is opposite to that in the second type of frame.

9. The display panel according to claim 7, characterized in that: The same data line is electrically connected to a plurality of sub-pixels of the same color, and at least two data lines corresponding to the same source line are electrically connected to at least two sub-pixels of different colors respectively; The color types of the sub-pixels corresponding to the plurality of first-type demultiplexing transistors and the color types of the sub-pixels corresponding to the plurality of second-type demultiplexing transistors are the same.

10. A method for driving a display panel, characterized in that: The display panel comprises: Multiple sub-pixels; A plurality of data lines, wherein the data lines are electrically connected to the corresponding plurality of sub-pixels; A plurality of source lines, wherein the source lines are used to transmit data signals; A plurality of demultiplexing transistors, wherein the demultiplexing transistors are electrically connected to the corresponding data lines and the corresponding demultiplexing lines, at least two of the demultiplexing transistors are electrically connected to the same source line, and the demultiplexing transistors include a first gate and a second gate, and the first gate is electrically connected to the corresponding demultiplexing line; A plurality of reset modules, each of which is electrically connected to the corresponding second gate; The driving method of the display panel includes: The demultiplexing signal transmitted by the demultiplexing line controls the corresponding demultiplexing transistor to change from on to off, so as to control the current path between the corresponding source line and the corresponding data line to change from a current disconnection, and the corresponding reset signal controls the second gate of the corresponding demultiplexing transistor to be reset.

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