Display panel and display device

Abstract

The invention discloses a display panel and a display device, and relates to the technical field of display, the display panel comprises a plurality of data lines which are arranged along a first direction and extend along a second direction, and adjacent n data lines form a data line group; the multi-path gating circuit comprises n output ends, and n is a positive integer greater than or equal to 2; wherein one end of each data line in the data line group is electrically connected with one output end of the multi-path gating circuit, and the other end of each data line is connected with a capacitor. According to the display panel, the crosstalk problem between the data lines electrically connected with the same multi-path gating circuit is solved.

Description

[0001] This application is a divisional application of the application with the filing date of September 26, 2022, application number 202211176696.4, and invention creation name of "display panel and display device". Technical Field

[0002] The present invention relates to the field of display technologies, and more particularly, to a display panel and a display device. Background Art

[0003] Currently, display technologies have penetrated into all aspects of people's daily lives. Correspondingly, more and more materials and technologies are being used in display screens. As an important part of a display device, a display panel is used to implement the display function of the display device. Nowadays, the mainstream display screens mainly include liquid crystal display panels and organic light-emitting diode (OLED) display panels.

[0004] As a current-driven light-emitting device, organic light-emitting diodes have been increasingly used in high-performance displays. OLED display panels have many excellent characteristics such as self-luminescence, wide viewing angles, fast response speeds, high contrast ratios, wide color gamuts, low power consumption, thin panels, rich colors, flexible display capabilities, and a wide operating temperature range. An OLED display panel includes an anode and a cathode, as well as a hole transport layer, an organic light-emitting layer, and an electron transport layer disposed between the anode and the cathode. The anode provides hole injection, and the cathode provides electron injection. Under the drive of an external voltage, the holes and electrons injected from the cathode and the anode recombine in the organic light-emitting layer to form electron-hole pairs (i.e., excitons) in bound energy levels. The excitons radiatively de-excite to emit photons, generating visible light.

[0005] In the prior art, multiple data lines are provided on a display panel. After converging at the steps of the display panel, the data lines are pulled to a driving integrated circuit (IC). In order to reduce the number of traces at the steps, a multiplexer design is usually adopted. The multiplexer can receive a data signal through one trace and output the data signal to multiple data lines in a time-division manner. However, there is a serious problem of lateral crosstalk between multiple data lines connected to the same multiplexer, which affects the display.

[0006] In view of this, there is an urgent need to provide a display panel and a display device that can improve the problem of lateral crosstalk. Summary of the Invention

[0007] In view of this, the present invention provides a display panel and a display device for improving the problem of lateral crosstalk.

[0008] On the one hand, the present invention provides a display panel, including:

[0009] A plurality of data lines arranged along a first direction and extending along a second direction, and adjacent n data lines form a data line group;

[0010] A multiplexing circuit, the multiplexing circuit includes n output terminals, and n is a positive integer greater than or equal to 2;

[0011] Wherein, one end of the data lines in the data line group is electrically connected to one of the output terminals of the multiplexing circuit, and the other end is connected with a capacitor.

[0012] On the other hand, the present invention provides a display device, including the above display panel.

[0013] Compared with the prior art, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

[0014] In the present invention, a plurality of data lines in the data line group are electrically connected to the output terminals of the multiplexing circuit in one-to-one correspondence, the other end of each data line is connected with a capacitor, each data line is loaded with a plurality of sub-pixels, and a first power supply signal line for providing a high-potential signal for the sub-pixels is further provided in the display panel. The n output terminals of the multiplexing circuit respectively output data voltages to the plurality of data lines. When the line charging of one of the data lines is completed, at this time, this data line is in a floating state. When another data line is written with a signal, the signal on the first power supply signal line will fluctuate due to the coupling effect, and the signal fluctuation on the first power supply signal line will also couple to the data line in the floating state. In the prior art, the coupling jump of the charged data line is ΔV’ = C10 / C20, where C10 is the total capacitance of the charged data line and the first power supply signal line, and C20 is the total capacitance of the charged data line. After adding a capacitor to the other end of the data line in the present invention, the coupling jump of the charged data line is ΔV = C10 / (C20 + C), where C10 is the total capacitance of the charged data line and the first power supply signal line, C20 is the total capacitance of the charged data line, and C is the capacitor added to the data line. Compared with the coupling jump ΔV’ of the related technology, after adding the capacitor, the numerator is the same, but the denominator becomes larger, so the coupling jump ΔV in the present invention is reduced, thereby improving the lateral crosstalk and enhancing the display performance.

[0015] Of course, it is not necessary for any product implementing the present invention to simultaneously achieve all the above-mentioned technical effects.

[0016] Through the following detailed description of the exemplary embodiments of the present invention with reference to the accompanying drawings, other features and advantages of the present invention will become clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments of the present invention, and together with the description are used to explain the principles of the present invention.

[0018] Figure 1 is a schematic plan view of a display panel in the related art;

[0019] Figure 2 is a schematic plan view of a display panel provided by the present invention;

[0020] Figure 3 is a pixel driving circuit diagram provided by the present invention;

[0021] Figure 4 is a cross-sectional view of a pixel in the present invention;

[0022] Figure 5 is another schematic plan view of a display panel provided by the present invention;

[0023] Figure 6 is another schematic plan view of a display panel provided by the present invention;

[0024] Figure 7 is another schematic plan view of a display panel provided by the present invention;

[0025] Figure 8 is another schematic plan view of a display panel provided by the present invention;

[0026] Figure 9 is another schematic plan view of a display panel provided by the present invention;

[0027] Figure 10 is another schematic plan view of a display panel provided by the present invention;

[0028] Figure 11 is another schematic plan view of a display panel provided by the present invention;

[0029] Figure 12 is a schematic plan view of a display device provided by an embodiment of the present invention. Detailed Embodiments

[0030] Now, various exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that: Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present invention.

[0031] The following description of at least one exemplary embodiment is merely illustrative in nature and in no way serves as a limitation on the present invention or its application or use.

[0032] Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered as part of the specification.

[0033] In all of the examples shown and discussed herein, any specific values should be construed as merely exemplary and not as a limitation. Thus, other examples of the exemplary embodiments may have different values.

[0034] It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

[0035] In view of the fact that in an organic self-luminous display panel of the related art, a multiplexer receives a data signal through a trace and outputs the data signal to multiple data lines in a time-division manner, but there is a serious problem of lateral crosstalk between multiple data lines connected to the same multiplexer, the inventor has conducted the following research on the related art. Refer to Figure 1 , Figure 1 is a schematic plan view of a display panel in the related art. Figure 1 The display panel 00 in includes a display area AA' and a non-display area BB' surrounding the display area AA'. A driving chip IC' is provided in the lower border of the non-display area BB'. The driving chip IC' provides signals during display. A multiplexing circuit 1' is also provided in the lower border. The input end of the multiplexing circuit 1' is electrically connected to the driving chip IC'. The multiplexing circuit 1' has two output ends, and each output end is electrically connected to a data line DATA'. A plurality of sub-pixels 2' are loaded on each data line DATA'. After adopting the multiplexing circuit 1', its charging method is changed from direct charging to line charging, that is, a signal is first written to the data line DATA', and then the data line DATA' writes the signal to the sub-pixels. For each sub-pixel 2' of the organic self-luminous display panel, its driving circuit also requires a high-potential signal line PVDD'. Figure 1Two data lines DATA1' and DATA2' electrically connected to the same multiplexing circuit 1'. Of course, the display panel 00 also has scan lines (not shown in the figure). During display, the scan lines scan line by line, and the driving chip IC' sends data voltages to the multiplexing circuit 1'. The two output terminals of the multiplexing circuit 1' respectively output data voltages to the data lines DATA1' and DATA2'. When the line charging of the data line DATA1' is completed, the data line DATA1' is in a floating state at this time. When a signal is written to the data line DATA2', the signal on the high-potential signal line PVDD' will fluctuate due to the coupling effect, and the signal fluctuation on the high-potential signal line PVDD' will be coupled to the floating data line DATA1', resulting in a serious problem of horizontal crosstalk between multiple data lines connected to the same multiplexer.

[0036] In view of this, the present invention provides a display panel and a display device to improve the serious problem of horizontal crosstalk between multiple data lines connected to the same multiplexer. The specific embodiments of the display panel will be described in detail below.

[0037] Referring to Figure 2 、 Figure 3 and Figure 4 , Figure 2 is a schematic plan view of a display panel provided by the present invention, Figure 3 is a pixel driving circuit diagram provided by the present invention, Figure 4 is a cross-sectional view of a pixel in the present invention. Figure 2 The display panel 000 in

[0038] Specifically, Figure 2 the display panel 000 in Figure 2 includes a display area AA and a non-display area BB surrounding the display area AA. Figure 2 Only the case where the non-display area BB completely surrounds the display area AA is shown. Of course, the non-display area BB can also partially surround the display area AA, such as a water-drop screen, which is not specifically limited here. The non-display area BB includes an upper border and a lower border arranged oppositely along the second direction Y. The driving chip IC is usually bonded in the lower border. The driving chip IC provides signals during display. The multiplexing circuit 100 is also provided in the lower border. The input terminal of the multiplexing circuit 100 is electrically connected to the driving chip IC. Figure 2FIG. schematically shows a case where the multiplexing circuit 100 has one input terminal and two output terminals, that is, the ratio of the input terminal to the output terminal is 1:2, and each output terminal is electrically connected to a data line 300. A plurality of data lines 300 are arranged along the first direction X and extend along the second direction Y. Figure 2 In, two adjacent data lines 300 form a data line group 30. A plurality of sub-pixels 200 are loaded on each data line 300. One end of the data lines 300 in the data line group 30 is electrically connected to an output terminal of the multiplexing circuit 100, and the other end is connected to a capacitor C. Figure 2 The data line group 30 in includes data line 3001 and data line 3002. Of course, the multiplexing circuit 100 can also have one input terminal and four output terminals, that is, the ratio of the input terminal to the output terminal is 1:4, or the multiplexing circuit 100 can have one input terminal and six output terminals, that is, the ratio of the input terminal to the output terminal is 1:6.

[0039] It can be understood that the display panel 000 also has scan lines extending along the first direction X and arranged in the second direction Y, which are not shown in the figure. The scan lines and the data lines 300 intersect to define the area of the sub-pixels 200.

[0040] For the pixel driving circuit of each sub-pixel 200, each sub-pixel 200 in the display area AA of the display panel 000 includes a pixel circuit, which can be referred to Figure 3 , Figure 3It is a pixel circuit structure diagram provided by the present invention. The pixel circuit can be 7T1C, including: a transistor M1, whose control terminal is electrically connected to the light-emitting signal input terminal, the first terminal is electrically connected to the first power supply signal terminal PVDD, and the second terminal is electrically connected to the first terminal of the driving transistor M; a transistor M2, whose control terminal is electrically connected to the second scan signal input terminal S2, the first terminal is electrically connected to the data signal input terminal Vdata, and the second terminal is electrically connected to the first terminal of the driving transistor M; a driving transistor M, whose control terminal is electrically connected to the second terminal of the transistor M4, the first terminal is electrically connected to the second terminal of the transistor M1 and the second terminal of the transistor M2; a transistor M3, whose control terminal is electrically connected to the second scan signal input terminal S2, the first terminal is electrically connected to the second terminal of the transistor M4 and the second terminal of the storage capacitor Cst, and the second terminal is electrically connected to the second terminal of the driving transistor M and the first terminal of the transistor M5; a transistor M4, whose control terminal is electrically connected to the first scan signal input terminal S1, the first terminal is electrically connected to the reference voltage signal input terminal Vref, and the second terminal is electrically connected to the control terminal of the driving transistor M; a transistor M5, whose control terminal is electrically connected to the light-emitting signal input terminal Emit, the first terminal is electrically connected to the second terminal of the driving transistor M and the second terminal of the transistor M3, and the second terminal is electrically connected to the anode of the light-emitting element O; a transistor M6, whose control terminal is electrically connected to the second scan signal input terminal, the first terminal is electrically connected to the reference voltage signal input terminal Vref, and the second terminal is electrically connected to the first terminal of the light-emitting element O; a light-emitting element O, whose first terminal is electrically connected to the second terminal of the transistor M5 and the second terminal of the transistor M6, and the second terminal is electrically connected to the second power supply signal terminal PVEE; a storage capacitor Cst, whose first terminal is electrically connected to the first power supply signal terminal PVDD, and the second terminal is electrically connected to the control terminal of the driving transistor M, the first terminal of the transistor M3, and the second terminal of the transistor M4. The first power supply signal terminal PVDD here is connected to Figure 2 the first power supply signal line 400 in Figure 2 . The first power supply signal line 400 extends along the second direction Y and is arranged in the first direction X to transmit a high-potential signal to each pixel circuit.

[0041] The display panel 000 of this embodiment can be an organic light-emitting display panel. The organic light-emitting display panel includes an anode and a cathode, and a light-emitting layer provided between the anode and the cathode. The light-emitting layer can include a hole transport layer, an organic light-emitting layer, and an electron transport layer. The anode provides hole injection, and the cathode provides electron injection. Under the drive of an external voltage, the holes and electrons injected from the cathode and the anode recombine in the organic light-emitting layer to form electron-hole pairs (i.e., excitons) in the bound energy level. The excitons radiatively de-excite to emit photons, generating visible light. It should be noted that Figure 4 in Figure 4 , the sub-pixel 200 is the sub-pixel 200 closest to the upper border. Figure 4The cross-sectional view therein also shows the capacitor C. In this embodiment, the display panel 000 includes: a substrate substrate 91; a thin-film transistor 20 located on one side of the substrate substrate 91; a light-emitting device 30A located on the side of the thin-film transistor 20 away from the substrate substrate 91; the light-emitting device 30A includes an anode layer 310, a light-emitting layer 320 located on the side of the anode away from the substrate substrate 91, and a cathode 330 located on the side of the light-emitting layer 320 away from the substrate substrate 91. The thin-film transistor 20 drives the light-emitting device 30A to emit light for display. Figure 4 Also shown therein are a buffer layer 92, a first insulating layer 93, a second insulating layer 94, a third insulating layer 95, a fourth insulating layer 96, a planarization layer 97, and a pixel definition layer 98. The thin-film transistor 20 includes a second metal layer M12 (source and drain), and a first metal layer M13 is provided between the anode layer 310 and the second metal layer M12. Optionally, the thin-film transistor is located on the buffer layer 92. Figure 4 Only the structure of the top-gate thin-film transistor is taken as an example for the description. The thin-film transistor 20 includes a semiconductor active layer 201 located on the buffer layer 92. The semiconductor active layer 201 includes a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions. The region between the source region and the drain region is a channel region where no impurities are doped. The semiconductor active layer 201 can be formed by crystallizing amorphous silicon to change amorphous silicon into polycrystalline silicon. In order to crystallize amorphous silicon. The first metal layer M11 (gate) is located on the gate insulating layer. The gate can include a single layer or multiple layers of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), or chromium (Cr), or alloys such as aluminum (Al): neodymium (Nd) alloy, molybdenum (Mo): tungsten (W) alloy. The first metal layer M12 has a source and a drain, and the source and the drain are respectively electrically connected (or bonded) to the source region and the drain region of the active layer 201 through contact holes. The contact holes are formed by selectively removing the insulating layer. Optionally, Figure 4 Also shown therein is a packaging layer 50 located on the side of the light-emitting device 30A away from the substrate substrate 91. Optionally, the packaging layer 50 is a laminated structure of an inorganic packaging layer, an organic packaging layer, and an inorganic packaging layer. Of course, the specific structure in the packaging layer 50 is not limited in the present invention. The packaging layer 50 can have multiple inorganic packaging layers and multiple organic packaging layers to form good protection for the light-emitting device 30A in the display area AA. In the present invention, a capacitor C is connected to the other end of the data line 300. Optionally, one of the two plates of the capacitor C can be provided on the first metal layer M13, that is, on the same layer as the data line 300. In this way, when manufacturing the data line 300, as long as the length of the data line 300 is extended, the first plate C001 of the capacitor C can be obtained. The second plate C002 of the capacitor C can be provided on the capacitor metal layer MC, on the same layer as the capacitor metal layer MC, which is convenient for manufacturing.

[0042] It can be understood that after adopting the multiplexing circuit 100, its charging method is changed from direct charging to line charging, that is, signals are first written to the data line 300, and then the data line 300 writes signals to the sub-pixel 200. For each sub-pixel 200 of the organic self-luminous display panel 000, its driving circuit also requires a high-potential signal line. Figure 2 For two data lines 3001 and 3002 electrically connected to the same multiplexing circuit 100 in the [description]. During display, the scanning line scans row by row, the driving chip IC sends data voltage to the multiplexing circuit 100, and two output terminals of the multiplexing circuit 100 respectively output data voltage to the data line 3001 and the data line 3002. When the line charging of the data line 3001 is completed, at this time the data line 3001 is in a floating state. When signals are written to the data line 3002, signal fluctuations will occur on the first power signal line 400 due to the coupling effect, and the signal fluctuations on the first power signal line 400 will couple to the floating data line 3001. In the present invention, capacitors C are connected to the other ends of the data lines 300. In the related art, the coupling jump of the charging data line DATA’ is ΔV’ = C10 / C20, where C10 is the total capacitance C of the charging data line DATA’ and the first power signal line PVDD’, and C20 is the total capacitance of the charging data line DATA’. After the capacitor C is electrically connected to the other end of the data line 300 in the present invention, the coupling jump of the charging data line 300 is ΔV = C10 / (C20 + C), where C10 is the total capacitance of the charging data line 300 and the first power signal line 400, C20 is the total capacitance of the charging data line 300, and C is the capacitor C added on the data line 300. Compared with the coupling jump ΔV’ of the related art, after adding the capacitor C, the numerator is the same, but the denominator becomes larger, so the coupling jump ΔV in the present invention decreases, thereby improving the lateral crosstalk and enhancing the display performance.

[0043] In some alternative embodiments, continue to refer to Figure 2 that the capacitors C connected to different data lines 300 are all equal.

[0044] It can be understood that in the same data line group 30, capacitors C are connected to the ends (the ends far from the multiplexing circuit 100) of each data line 300. Optionally, refer to Figure 4, one of the two plates of the capacitor C can be disposed on the first metal layer M13, i.e., the same layer as the data line 300. Thus, when manufacturing the data line 300, the first plate C001 of the capacitor C can be obtained by simply extending the length of the data line 300. The second plate C002 of the capacitor C can be disposed on the capacitor metal layer MC, on the same layer as the capacitor metal layer MC, which is convenient for manufacturing. In this embodiment, the capacitors C connected to different data lines 300 are all equal. Optionally, the sizes of the two plates of the capacitor C can be set to be the same. In this way, the two plates of the capacitor C can be etched using the same process during manufacturing, which is convenient for manufacturing.

[0045] In some alternative embodiments, referring to Figure 5 , Figure 5 is a schematic plan view of another display panel provided by the present invention. The first plate C001 of the capacitor C is connected to the data line 300, and the second plate C002 of the capacitor C is connected to a fixed potential V.

[0046] It can be understood that the first plate C001 of the capacitor C can be directly electrically connected to the data line 300 by extending the data line 300, while the second plate C002 of the capacitor C needs to be connected to a fixed potential V. Figure 5 In

[0047] In some alternative embodiments, referring to Figure 6 , Figure 6 is a schematic plan view of another display panel provided by the present invention. Each multiplexing circuit 100 includes first to nth output terminals. The capacitors C corresponding to the ith output terminals of different multiplexing circuits 100 are connected to the same fixed potential V, where i is a positive integer greater than 1 and less than n.

[0048] Optionally, n can be a positive integer such as 2, 4, 6, etc. The quantity of n is not specifically limited herein. Figure 6Only taking the example that each multiplexing circuit 100 includes the first to the second output terminals, the first output terminal is electrically connected to the first data line 3001, the other end of the first data line 3001 is connected to the first capacitor C1, the second output terminal is electrically connected to the second data line 3002, and the other end of the second data line 3002 is connected to the second capacitor C2. Each multiplexing circuit 100 includes the first to the nth output terminals, and the capacitors C corresponding to the ith output terminals of different multiplexing circuits 100 are connected to the same fixed potential V. The capacitors C corresponding to the first output terminals of multiple multiplexing circuits 100 are all connected to the same fixed potential V, the capacitors C corresponding to the second output terminals of multiple multiplexing circuits 100 are all connected to the same fixed potential V... The capacitors C corresponding to the ith output terminals of multiple multiplexing circuits 100 are all connected to the same fixed potential V. In this way, the number of fixed potentials V can be reduced, that is, the number of signal lines for transmitting the fixed potential V in the upper frame is reduced. On the one hand, the material cost and manufacturing cost caused by setting the signal lines can be reduced, and the occupied space of the signal lines in the upper frame can also be reduced, meeting the requirements of a narrow frame.

[0049] In some alternative embodiments, with continued reference to Figure 6 , n = 2, the multiplexing circuit 100 includes the first output terminal and the second output terminal. The capacitors C corresponding to the first output terminals of different multiplexing circuits 100 are connected to the first fixed potential V1, and the capacitors C corresponding to the second output terminals of different multiplexing circuits 100 are connected to the second fixed potential V2; V1 = V2.

[0050] Figure 6 In

[0051] It can be understood that the capacitors C corresponding to the first output terminals of different multiplexing circuits 100 are connected to a first fixed potential V1, and the capacitors C corresponding to the second output terminals of different multiplexing circuits 100 are connected to a second fixed potential V2, and V1 = V2. Here, the functions of the first fixed potential V1 and the second fixed potential V2 are to stabilize the potentials of the data lines 3001 and 3002. It should be noted that the capacitance values of the first capacitor C1 and the second capacitor C2 affect the lateral crosstalk effect, and whether the first fixed potential V1 and the second fixed potential V2 are equal does not affect the lateral crosstalk effect. In this embodiment, V1 = V2, which can reduce the number of potentials transmitted to the signal lines.

[0052] In some alternative embodiments, with continued reference to Figure 6 , n = 2, the multiplexing circuit 100 includes a first output terminal and a second output terminal. The capacitors C corresponding to the first output terminals of different multiplexing circuits 100 are connected to a first fixed potential V1, and the capacitors C corresponding to the second output terminals of different multiplexing circuits 100 are connected to a second fixed potential V2; V1 ≠ V2.

[0053] Figure 6 In [[reference]], the capacitors C corresponding to the first output terminals of the four multiplexing circuits 100 are all connected to the first fixed potential V1, and the capacitors C corresponding to the second output terminals of the four multiplexing circuits 100 are all connected to the second fixed potential V2. In this way, the number of fixed potentials V is only 2, that is, the number of signal lines transmitting the fixed potential V in the upper frame is greatly reduced, and the number of signal lines is reduced to 2. On the one hand, it can reduce the material cost and manufacturing cost caused by setting the signal lines. Moreover, since there are only 2 signal lines, the occupied space of the signal lines in the upper frame can be reduced, meeting the requirements of a narrow frame.

[0054] It can be understood that the capacitors C corresponding to the first output terminals of different multiplexing circuits 100 are connected to a first fixed potential V1, and the capacitors C corresponding to the second output terminals of different multiplexing circuits 100 are connected to a second fixed potential V2, and V1 = V2. Here, the functions of the first fixed potential V1 and the second fixed potential V2 are to stabilize the potentials of the data lines 3001 and 3002. It should be noted that the capacitance values of the first capacitor C1 and the second capacitor C2 affect the lateral crosstalk effect, and whether the first fixed potential V1 and the second fixed potential V2 are equal does not affect the lateral crosstalk effect. In this embodiment, V1 is not equal to V2, which can further stabilize the potentials of the data lines 3001 and 3002.

[0055] In some alternative embodiments, with reference to Figure 7 , Figure 7It is a schematic plan view of another display panel provided by the present invention. The multiplexing strobe circuit 100 includes a first transistor T1 and a second transistor T2. Among them, the control terminal of the first transistor T1 is electrically connected to the first signal line CHK1, the first pole of the first transistor T1 is electrically connected to the data signal terminal S, and the second pole of the first transistor T1 is electrically connected to the first data line 3001 in the data line group 30; the control terminal of the second transistor T2 is electrically connected to the second signal line CHK2, the first pole of the second transistor T2 is electrically connected to the data signal terminal S, and the second pole of the second transistor T2 is electrically connected to the second data line 3002 in the data line group 30.

[0056] Specifically, each multiplexing strobe circuit 100 has a first transistor T1 and a second transistor T2. The first poles (i.e., source poles) of the first transistor T1 and the second transistor T2 are both connected to the same data signal terminal S, that is, the input end of the multiplexing strobe circuit 100. The control terminal (i.e., gate) of the first transistor T1 is electrically connected to the first signal line CHK1, the second pole (i.e., drain) of the first transistor T1 is electrically connected to the first data line 3001 in the data line group 30, the control terminal (i.e., gate) of the second transistor T2 is electrically connected to the second signal line CHK2, and the second pole of the second transistor T2 is electrically connected to the second data line 3002 in the data line group 30. That is, the control terminals of the first transistor T1 and the second transistor T2 are respectively controlled to conduct or not through the first signal line CHK1 and the second signal line CHK2. For example, when data needs to be written to the data line 3001, the first signal line CHK1 controls the gate of the first transistor T1 to conduct, and the data voltage is written to the data line 3001. At this time, the second signal line CHK2 controls the gate of the second transistor T2 to close, and no data voltage is written to the data line 3002; similarly, when data needs to be written to the data line 3002, the second signal line CHK2 controls the gate of the second transistor T2 to conduct, and the data voltage is written to the data line 3002. At this time, the first signal line CHK1 controls the gate of the first transistor T1 to close, and no data voltage is written to the data line 3001. The present invention realizes the separate data writing of the data lines 300 in the data line group 30 through the multiplexing strobe circuit 100, and can reduce the number of pads on the driving chip IC.

[0057] In some alternative embodiments, refer to Figure 8 , Figure 8It is a schematic plan view of another display panel provided by the present invention. n = 4. The multiplexing gate circuit 100 includes the 1st to 4th output terminals. The capacitors C corresponding to the 1st output terminals of different multiplexing gate circuits 100 are connected to the third fixed potential V3. The capacitors C corresponding to the 2nd output terminals of different multiplexing gate circuits 100 are connected to the fourth fixed potential V4. The capacitors C corresponding to the 3rd output terminals of different multiplexing gate circuits 100 are connected to the fifth fixed potential V5. The capacitors C corresponding to the 4th output terminals of different multiplexing gate circuits 100 are connected to the sixth fixed potential V6; V3 = V4 = V5 = V6.

[0058] In this embodiment, the ratio of the number of input terminals to the number of output terminals of the multiplexing gate circuit 100 is 1:4, that is, one input and four outputs, and it can be electrically connected to 4 adjacent data lines 300. The capacitors C connected to the 4 data lines 300 are respectively the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. The capacities of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 may be equal or unequal, which will not be elaborated here.

[0059] Figure 8 Only two multiplexing gate circuits 100 are schematically shown. The first capacitors C1 corresponding to the 1st output terminals of the two multiplexing gate circuits 100 are both connected to the first fixed potential V1. The second capacitors C2 corresponding to the 2nd output terminals of the two multiplexing gate circuits 100 are both connected to the second fixed potential V2. The third capacitors C3 corresponding to the 3rd output terminals of the two multiplexing gate circuits 100 are both connected to the second fixed potential V3. The fourth capacitors C4 corresponding to the 4th output terminals of the two multiplexing gate circuits 100 are both connected to the second fixed potential V4. In this way, the number of fixed potentials V is only 4, that is, the number of signal lines for transmitting the fixed potential V in the upper border is greatly reduced, and the number of signal lines is reduced to 4. On the one hand, it can reduce the material cost and manufacturing cost caused by setting the signal lines, and since there are only 4 signal lines, it can reduce the occupied space of the signal lines in the upper border and meet the requirements of a narrow border.

[0060] It can be understood that the first capacitor C1 corresponding to the first output terminal of different multiplexing circuits 100 is connected to the third fixed potential V3, the second capacitor C2 corresponding to the second output terminal of different multiplexing circuits 100 is connected to the fourth fixed potential V4, the third capacitor C3 corresponding to the third output terminal of different multiplexing circuits 100 is connected to the fifth fixed potential V5, and the fourth capacitor C4 corresponding to the fourth output terminal of different multiplexing circuits 100 is connected to the sixth fixed potential V6. The functions of the third fixed potential V3, the fourth fixed potential V4, the fifth fixed potential V5, and the sixth fixed potential V6 are to stabilize the potentials of the first data line 3001, the second data line 3002, the third data line 3003, and the fourth data line 3004. It should be noted that the capacitance of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 affects the lateral crosstalk effect. Whether the third fixed potential V3, the fourth fixed potential V4, the fifth fixed potential V5, and the sixth fixed potential V6 are equal or not does not affect the lateral crosstalk effect. In this embodiment, V3 = V4 = V5 = V6, which can reduce the number of potentials transmitted to the signal line.

[0061] In some alternative embodiments, with continued reference to Figure 8 , n = 4, the multiplexing circuit 100 includes the first to the fourth output terminals. The capacitor corresponding to the first output terminal of different multiplexing circuits 100 is connected to the third fixed potential V3, the capacitor corresponding to the second output terminal of different multiplexing circuits 100 is connected to the fourth fixed potential V4, the capacitor corresponding to the third output terminal of different multiplexing circuits 100 is connected to the fifth fixed potential V5, and the capacitor corresponding to the fourth output terminal of different multiplexing circuits 100 is connected to the sixth fixed potential V6; at least two of V3, V4, V5, and V6 are not equal.

[0062] Figure 8 Only two multiplexing circuits 100 are schematically shown in . The first capacitor C1 corresponding to the first output terminal of the two multiplexing circuits 100 is connected to the first fixed potential V1, the second capacitor C2 corresponding to the second output terminal of the two multiplexing circuits 100 is connected to the second fixed potential V2, the third capacitor C3 corresponding to the third output terminal of the two multiplexing circuits 100 is connected to the second fixed potential V3, and the fourth capacitor C4 corresponding to the fourth output terminal of the two multiplexing circuits 100 is connected to the second fixed potential V4. In this way, the number of fixed potentials V is only 4, that is, the number of signal lines transmitting the fixed potential V in the upper border is greatly reduced, and the number of signal lines is reduced to 4. On the one hand, it can reduce the material cost and manufacturing cost due to the setting of signal lines, and since there are only 4 signal lines, it can reduce the occupied space of the signal lines in the upper border and meet the requirements of a narrow border.

[0063] It can be understood that the first capacitor C1 corresponding to the first output terminal of different multiplexing circuits 100 is connected to the third fixed potential V3, the second capacitor C2 corresponding to the second output terminal of different multiplexing circuits 100 is connected to the fourth fixed potential V4, the third capacitor C3 corresponding to the third output terminal of different multiplexing circuits 100 is connected to the fifth fixed potential V5, and the fourth capacitor C4 corresponding to the fourth output terminal of different multiplexing circuits 100 is connected to the sixth fixed potential V6. The functions of the third fixed potential V3, the fourth fixed potential V4, the fifth fixed potential V5, and the sixth fixed potential V6 are to stabilize the potentials of the first data line 3001, the second data line 3002, the third data line 3003, and the fourth data line 3004. It should be noted that the capacitance values of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 affect the lateral crosstalk effect. Whether the third fixed potential V3, the fourth fixed potential V4, the fifth fixed potential V5, and the sixth fixed potential V6 are equal or not does not affect the lateral crosstalk effect. In this embodiment, at least two of V3, V4, V5, and V6 are not equal. Optionally, V3≠V4=V5=V6, or V3=V4≠V5=V6, or V3=V4=V5≠V6, or V3≠V4≠V5=V6, or V3=V4=V5≠V6, or V3≠V4≠V5≠V6. Details are not described herein again. In this embodiment, at least two of V3, V4, V5, and V6 are not equal, which can stabilize the potentials of the data line 3001, the data line 3002, the data line 3003, and the data line 3004.

[0064] In some alternative embodiments, referring to Figure 9 , Figure 9 is a schematic plan view of another display panel provided by the present invention. Figure 9The multi-way selection circuit 100 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. Among them, the control terminal of the third transistor T3 is electrically connected to the third signal line CHK3, the first pole of the third transistor T3 is electrically connected to the data signal terminal S, and the second pole of the third transistor T3 is electrically connected to the first data line 3001 in the data line group 30; the control terminal of the fourth transistor T4 is electrically connected to the fourth signal line CHK4, the first pole of the fourth transistor T4 is electrically connected to the data signal terminal S, and the second pole of the fourth transistor T4 is electrically connected to the second data line 3002 in the data line group 30; the control terminal of the fifth transistor T5 is electrically connected to the fifth signal line CHK5, the first pole of the fifth transistor T5 is electrically connected to the data signal terminal S, and the second pole of the fifth transistor T5 is electrically connected to the third data line 3003 in the data line group 30; the control terminal of the sixth transistor T6 is electrically connected to the sixth signal line CHK6, the first pole of the sixth transistor T6 is electrically connected to the data signal terminal S, and the second pole of the sixth transistor T6 is electrically connected to the fourth data line 3004 in the data line group 30.

[0065] Figure 9 Among them, the ratio of the number of input terminals to the number of output terminals of the multi-way selection circuit 100 is 1:4, that is, one input and four outputs, and it can be electrically connected to four adjacent data lines 300. The capacitors C connected to the four data lines 300 are the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 respectively. The capacitances of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can be equal or unequal, which will not be elaborated here.

[0066] Specifically, each multiplexing circuit 100 includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6. The first poles (i.e., source electrodes) of the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all connected to the same data signal terminal S, which is also the input terminal of the multiplexing circuit 100. The control terminal (i.e., gate) of the third transistor T3 is electrically connected to the third signal line CHK3, and the second pole (i.e., drain) of the third transistor T3 is electrically connected to the first data line 3001 in the data line group 30. The control terminal (gate) of the fourth transistor T4 is electrically connected to the fourth signal line CHK4, and the second pole (drain) of the fourth transistor T4 is electrically connected to the second data line 3002 in the data line group 30. That is, the control terminals of the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are controlled to conduct or not through the third signal line CHK3, the fourth signal line CHK4, the fifth signal line CHK5, and the sixth signal line CHK6 respectively. For example, when data needs to be written to the data line 3001, the third signal line CHK3 controls the gate of the third transistor T3 to conduct, and the data voltage is written to the data line 3001. At this time, the fourth signal line CHK4 controls the gate of the fourth transistor T4 to close, the fifth signal line CHK5 controls the fifth transistor T5 to close, and the sixth signal line CHK6 controls the sixth transistor T6 to close, so that no data voltage is written to the data line 3002, no data voltage is written to the data line 3003, and no data voltage is written to the data line 3004. Similarly, when data needs to be written to the data line 3002, the fourth signal line CHK4 controls the gate of the fourth transistor T4 to conduct, and the data voltage is written to the data line 3002. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to close, the fifth signal line CHK5 controls the fifth transistor T5 to close, and the sixth signal line CHK6 controls the sixth transistor T6 to close, so that no data voltage is written to the data line 3001, no data voltage is written to the data line 3003, and no data voltage is written to the data line 3004. When data needs to be written to the data line 3003, the fifth signal line CHK5 controls the gate of the fifth transistor T5 to conduct, and the data voltage is written to the data line 3003. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to close, the fourth signal line CHK4 controls the fourth transistor T4 to close, and the sixth signal line CHK6 controls the sixth transistor T6 to close, so that no data voltage is written to the data line 3001, no data voltage is written to the data line 3002, and no data voltage is written to the data line 3004;When data needs to be written to the data line 3004, the sixth signal line CHK6 controls the gate of the sixth transistor T6 to conduct, and the data voltage is written to the data line 3004. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to turn off, the fourth signal line CHK4 controls the fourth transistor T4 to turn off, and the fifth signal line CHK5 controls the fifth transistor T5 to turn off. No data voltage is written to the data line 3001, no data voltage is written to the data line 3002, and no data voltage is written to the data line 3003. The present invention realizes data writing to the data lines 300 in the data line group 30 respectively through the multiplexing circuit 100, and can reduce the number of pads on the driving chip IC.;

[0067] In some alternative embodiments, with continued reference to Figure 9 , Figure 9 the display panel 000 further includes a plurality of sub-pixels 200 arranged in an array. The first data line 3001 and the third data line 3003 in each data line group 30 are electrically connected to the sub-pixels 200 in the odd-numbered columns, and the second data line 3002 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in the even-numbered columns.

[0068] Specifically, each data line 300 is correspondingly electrically connected to the sub-pixels 200 in the same column to transmit the data voltage to the sub-pixels 200 in this column.

[0069] Figure 9When data needs to be written to the data line 3001, the third signal line CHK3 controls the gate of the third transistor T3 to conduct, and the data voltage is written to the data line 3001. The sub-pixels 200 in the first column are charged. At this time, the fourth signal line CHK4 controls the gate of the fourth transistor T4 to turn off, the fifth signal line CHK5 controls the fifth transistor T5 to turn off, and the sixth signal line CHK6 controls the sixth transistor T6 to turn off. No data voltage is written to the data line 3002, no data voltage is written to the data line 3003, no data voltage is written to the data line 3004, and the sub-pixels 200 in the 2nd to 4th columns are not charged. Similarly, when data needs to be written to the data line 3002, the fourth signal line CHK4 controls the gate of the fourth transistor T4 to conduct, and the data voltage is written to the data line 3002. The sub-pixels 200 in the 2nd column are charged. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to turn off, the fifth signal line CHK5 controls the fifth transistor T5 to turn off, and the sixth signal line CHK6 controls the sixth transistor T6 to turn off. No data voltage is written to the data line 3001, no data voltage is written to the data line 3003, no data voltage is written to the data line 3004, and the sub-pixels 200 in the 1st column, the 3rd column, and the 4th column are not charged. When data needs to be written to the data line 3003, the fifth signal line CHK5 controls the gate of the fifth transistor T5 to conduct, and the data voltage is written to the data line 3003. The sub-pixels 200 in the 3rd column are charged. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to turn off, the fourth signal line CHK4 controls the fourth transistor T4 to turn off, and the sixth signal line CHK6 controls the sixth transistor T6 to turn off. No data voltage is written to the data line 3001, no data voltage is written to the data line 3002, no data voltage is written to the data line 3004, and the sub-pixels 200 in the 1st column, the 2nd column, and the 4th column are not charged. When data needs to be written to the data line 3004, the sixth signal line CHK6 controls the gate of the sixth transistor T6 to conduct, and the data voltage is written to the data line 3004. The sub-pixels 200 in the 4th column are charged. At this time, the third signal line CHK3 controls the gate of the third transistor T3 to turn off, the fourth signal line CHK4 controls the fourth transistor T4 to turn off, and the fifth signal line CHK5 controls the fifth transistor T5 to turn off. No data voltage is written to the data line 3001, no data voltage is written to the data line 3002, no data voltage is written to the data line 3003, and the sub-pixels 200 in the 1st column, the 2nd column, and the 3rd column are not charged.

[0070] In some alternative embodiments, referring to Figure 10 and Figure 11 , Figure 10 is a schematic plan view of another display panel provided by the present invention. Figure 11It is a schematic plan view of another display panel provided by the present invention. Figure 10 and Figure 11 In Figure 11 , the display panel 000 further includes a plurality of sub-pixels 200 arranged in an array. For each data line group 30, the first data line 3001 and the second data line 3002 are electrically connected to the sub-pixels 200 in the same column, and the third data line 3003 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in the same column. Moreover, the first data line 3001 and the third data line 3003 are electrically connected to the sub-pixels 200 in odd rows, and the second data line 3002 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in even rows; or in each data line group 30, the first data line 3001 and the third data line 300 are electrically connected to the sub-pixels 200 in even rows, and the second data line 3002 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in odd rows.

[0071] In this embodiment, Figure 10 and Figure 11 in Figure 11 , the ratio of the number of input ends to the number of output ends of the multiplexing circuit 100 is 1:4, that is, one input and four outputs, and it can be electrically connected to four adjacent data lines 300. The capacitors C connected to the four data lines 300 are respectively the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. The capacities of the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can be equal or not equal, which will not be elaborated here. In this embodiment, a double-gate arrangement design is adopted at the same time. Figure 10 Taking Figure 10 as an example, in Figure 10 , for each data line group 30, the first data line 3001 and the second data line 3002 are electrically connected to the sub-pixels 200 in the same column, and the third data line 3003 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in the same column. Moreover, the first data line 3001 and the third data line 3003 are electrically connected to the sub-pixels 200 in odd rows, and the second data line 3002 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in even rows. The same data line 300 only transmits data voltage to the sub-pixels 200 in odd rows or even rows, so that the charging time of the sub-pixels 200 can be increased, and the display performance can be improved. Figure 11 Taking Figure 11 as an example, in Figure 11 , in each data line group 30, the first data line 3001 and the third data line 300 are electrically connected to the sub-pixels 200 in even rows, and the second data line 3002 and the fourth data line 3004 are electrically connected to the sub-pixels 200 in odd rows. The same data line 300 only transmits data voltage to the sub-pixels 200 in odd rows or even rows, so that the charging time of the sub-pixels 200 can be increased, and the display performance can be improved.

[0072] In some alternative embodiments, continue to refer to Figure 2, the data signal terminals S connected to the input ends of different multiplexing circuits 100 are different.

[0073] Figure 2 Among them, the four multiplexing circuits 100 are respectively connected to the data signal terminal S1, the data signal terminal S2, the data signal terminal S3, and the data signal terminal S4. These four data signal terminals S can be four pads on the driving chip IC. Different data voltages are provided to the multiple multiplexing circuits 100 through the driving chip IC, so as to realize displays with different brightnesses.

[0074] In some alternative embodiments, please refer to Figure 12 , Figure 12 Figure 12 is a schematic plan view of a display device provided by an embodiment of the present invention. The display device 0000 provided in this embodiment includes the display panel 000 provided in the above embodiment. Figure 12 This embodiment only takes a mobile phone as an example to illustrate the display device 0000. It can be understood that the display device 0000 provided by the embodiments of the present invention can be other display devices 0000 with a display function, such as a computer, a television, a vehicle-mounted display device, etc. The present invention does not make specific limitations thereto. The display device 0000 provided by the embodiments of the present invention has the beneficial effects of the display panel 000 provided by the embodiments of the present invention. For specific descriptions of the display panel 000, reference can be made to the above embodiments, and details are not described herein again.

[0075] As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following beneficial effects:

[0076] In the present invention, multiple data lines in the data line group are electrically connected to the output ends of the multiplexing circuit one by one. A capacitor is connected to the other end of each data line, and multiple sub-pixels are loaded on each data line. A first power signal line for providing a high-potential signal to the sub-pixels is further provided in the display panel. The n output ends of the multiplexing circuit respectively output data voltages to the multiple data lines. When the line charging of one of the data lines is completed, the data line is in a floating state at this time. When a signal is written to another data line, the signal on the first power signal line will fluctuate due to the coupling effect, and the signal fluctuation on the first power signal line will also couple to the floating data line. In the prior art, the coupling jump of the charged data line is ΔV’ = C10 / C20, where C10 is the total capacitance of the charged data line and the first power signal line, and C20 is the total capacitance of the charged data line. After adding a capacitor to the other end of the data line in the present invention, the coupling jump of the charged data line is ΔV = C10 / (C20 + C), where C10 is the total capacitance of the charged data line and the first power signal line, C20 is the total capacitance of the charged data line, and C is the capacitor added to the data line. Compared with the coupling jump ΔV’ of the related art, after adding the capacitor, the numerator is the same, but the denominator becomes larger, so the coupling jump ΔV in the present invention decreases. Therefore, the lateral crosstalk can be improved and the display performance can be enhanced.

[0077] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for the purpose of illustration and not for the purpose of limiting the scope of the present invention. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, Comprising: Multiple data lines arranged along a first direction and extending along a second direction, and adjacent n data lines form a data line group; A multiplexing circuit, the multiplexing circuit includes n output terminals, and n is a positive integer greater than or equal to 2; Wherein, one end of the data lines in the data line group is electrically connected to one of the output terminals of the multiplexing circuit, and the other end is connected with a capacitor; The first electrode plate of the capacitor is connected to the data line, and the second electrode plate of the capacitor is connected to a fixed potential.

2. The display panel according to claim 1, characterized in that, The capacitors connected to different data lines are all equal.

3. The display panel according to claim 1, characterized in that, The multiplexing circuit includes the 1st to the nth output terminals, and the capacitors corresponding to the ith output terminal of different multiplexing circuits are connected to the same fixed potential, where i is a positive integer greater than 1 and less than n.

4. The display panel according to claim 1, characterized in that, In one multiplexing circuit, the fixed potentials to which the capacitors corresponding to different output terminals are connected have the same voltage value.

5. The display panel according to claim 4, characterized in that, n = 2, the multiplexing circuit includes the 1st output terminal and the 2nd output terminal, the capacitors corresponding to the 1st output terminal of different multiplexing circuits are connected to a first fixed potential V1, and the capacitors corresponding to the 2nd output terminal of different multiplexing circuits are connected to a second fixed potential V2; V1 = V2.

6. The display panel according to claim 3, characterized in that, n = 2, the multiplexing circuit includes the 1st output terminal and the 2nd output terminal, the capacitors corresponding to the 1st output terminal of different multiplexing circuits are connected to a first fixed potential V1, and the capacitors corresponding to the 2nd output terminal of different multiplexing circuits are connected to a second fixed potential V2; V1 ≠ V2.

7. The display panel according to claim 5 or 6, characterized in that, The multiplexing circuit includes a first transistor and a second transistor, wherein, The control terminal of the first transistor is electrically connected to a first signal line, the first pole of the first transistor is electrically connected to a data signal terminal, and the second pole of the first transistor is electrically connected to the 1st data line in the data line group; The control terminal of the second transistor is electrically connected to a second signal line, the first pole of the second transistor is electrically connected to the data signal terminal, and the second pole of the second transistor is electrically connected to the 2nd data line in the data line group.

8. The display panel according to claim 4, characterized in that, n = 4, the multiplexing circuit includes the 1st to the 4th output terminals, the capacitors corresponding to the 1st output terminal of different multiplexing circuits are connected to a third fixed potential V3, the capacitors corresponding to the 2nd output terminal of different multiplexing circuits are connected to a fourth fixed potential V4, the capacitors corresponding to the 3rd output terminal of different multiplexing circuits are connected to a fifth fixed potential V5, and the capacitors corresponding to the 4th output terminal of different multiplexing circuits are connected to a sixth fixed potential V6; V3 = V4 = V5 = V6.

9. The display panel according to claim 3, characterized in that, n = 4, the multiplexing circuit includes the 1st to the 4th output terminals, the capacitors corresponding to the 1st output terminal of different multiplexing circuits are connected to a third fixed potential V3, the capacitors corresponding to the 2nd output terminal of different multiplexing circuits are connected to a fourth fixed potential V4, the capacitors corresponding to the 3rd output terminal of different multiplexing circuits are connected to a fifth fixed potential V5, and the capacitors corresponding to the 4th output terminal of different multiplexing circuits are connected to a sixth fixed potential V6; At least two of V3, V4, V5 and V6 are not equal.

10. The display panel according to claim 9, characterized in that, The multiplexing circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein the control terminal of the third transistor is electrically connected to a third signal line, the first pole of the third transistor is electrically connected to a data signal terminal, and the second pole of the third transistor is electrically connected to the first data line in the data line group; the control terminal of the fourth transistor is electrically connected to a fourth signal line, the first pole of the fourth transistor is electrically connected to the data signal terminal, and the second pole of the fourth transistor is electrically connected to the second data line in the data line group; the control terminal of the fifth transistor is electrically connected to a fifth signal line, the first pole of the fifth transistor is electrically connected to the data signal terminal, and the second pole of the fifth transistor is electrically connected to the third data line in the data line group; the control terminal of the fifth transistor is electrically connected to a sixth signal line, the first pole of the sixth transistor is electrically connected to the data signal terminal, and the second pole of the sixth transistor is electrically connected to the fourth data line in the data line group.

11. The display panel according to claim 10, characterized in that, The display panel further includes a plurality of sub-pixels arranged in an array. In each data line group, the first data line and the third data line are electrically connected to the sub-pixels in the odd-numbered columns, and the second data line and the fourth data line are electrically connected to the sub-pixels in the even-numbered columns.

12. The display panel according to claim 10, characterized in that, The display panel further includes a plurality of sub-pixels arranged in an array. In each data line group, the first data line and the second data line are electrically connected to the sub-pixels in the same column, the third data line and the fourth data line are electrically connected to the sub-pixels in the same column, and the first data line and the third data line are electrically connected to the sub-pixels in the odd-numbered rows, and the second data line and the fourth data line are electrically connected to the sub-pixels in the even-numbered rows; or in each data line group, the first data line and the third data line are electrically connected to the sub-pixels in the even-numbered rows, and the second data line and the fourth data line are electrically connected to the sub-pixels in the odd-numbered rows.

13. The display panel according to claim 1, characterized in that, The data signal terminals connected to the input ends of different multiplexing circuits are different.

14. The display panel according to claim 1, wherein The first electrode plate is provided on the same layer as the data line.

15. The display panel according to claim 1, wherein The display panel further includes a substrate. The second electrode plate is located on the side of the first electrode plate close to the substrate.

16. A display device, wherein A display panel as claimed in claims 1 to 15 is included.

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