Formation method of semiconductor structure
By forming a core layer and a mask side wall on the first dielectric layer of the semiconductor structure, the problem of insufficient graphics partition accuracy in the prior art is solved, the quality of the trench and the isolation effect are improved, and the performance of the semiconductor structure is improved.
Patent Information
- Application Number
- CN202311761897.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-19
- Publication Date
- 2025-06-20
AI Technical Summary
In the existing semiconductor structure formation method, the accuracy of pattern partitions needs to be improved, resulting in poor quality and isolation effect of the trench, which affects the performance of the semiconductor structure.
By forming a core layer on the top of the first dielectric layer, forming a mask side wall on the side wall of the core layer, and then removing the core layer, the mask side wall is formed by self-aligning multiple patterning to improve its dimensional accuracy and position alignment accuracy, thereby forming a plurality of spaced-distributed trenches in the first dielectric layer.
The quality of the trench and the isolation effect of trenches in different regions are improved, and the performance of the semiconductor structure is enhanced.
Smart Images
Figure CN120184013A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. Background Art
[0002] With the rapid development of the semiconductor integrated circuit (IC) industry, semiconductor technology has continuously advanced towards smaller process nodes driven by Moore's Law, enabling integrated circuits to develop in the direction of smaller volume, higher circuit precision, and higher circuit complexity.
[0003] In the semiconductor manufacturing process, forming a metal interconnect structure is crucial to achieve connections between electronic components. Generally, this involves etching trenches to accommodate the metal interconnect structure. To isolate the trenches from each other, a barrier layer needs to be introduced before etching to divide the etching positions in a preset etching window, so as to achieve the partition of the trenches and accurately define the positions of the trenches.
[0004] However, the current accuracy of achieving pattern isolation needs to be improved. Summary of the Invention
[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.
[0006] To solve the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, including: providing a substrate, on which a first dielectric layer is formed at the top; forming a core layer on the top of the first dielectric layer; forming a mask sidewall on the sidewall of the core layer; removing the core layer; after removing the core layer, etching the first dielectric layer within a preset etching window, where the preset etching window spans the mask sidewall along a first direction, so that the mask sidewall divides the etching positions in the preset etching window and forms a plurality of trenches spaced apart from each other in the first dielectric layer.
[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0008] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a core layer is formed on the top of a first dielectric layer; a mask sidewall is formed on the sidewall of the core layer; after removing the core layer, the first dielectric layer in a preset etching window is etched, and the preset etching window crosses the mask sidewall along a first direction, so that the mask sidewall divides the etching position in the preset etching window, and forms a plurality of spaced grooves in the first dielectric layer; by forming a core layer on the top of the first dielectric layer, then forming a mask sidewall on the sidewall of the core layer, and then removing the core layer, the mask sidewall is formed by self-aligned multiple patterning (for example, self-aligned double patterning), so that the size accuracy and position alignment accuracy of the mask sidewall are higher, and accordingly, when etching the first dielectric layer in the preset etching window, the mask sidewall divides the etching position in the preset etching window, so that the quality of the formed grooves is improved by the mask sidewall, and the grooves in different regions can be better isolated, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0010] Figures 5 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0011] At present, the performance of semiconductor structures still needs to be improved. Now, combined with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures needs to be improved are analyzed.
[0012] Figures 1 to 4 The present invention is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure. Specifically, Figures 1 to 3 is a cross-sectional view along a direction perpendicular to the extension direction of the gate structure, Figure 4 yes Figure 3 Top view of the .
[0013] refer to Figure 1 , providing a substrate 10, on which a gate structure and a source-drain doping layer (not marked) are formed, and a dielectric layer (not marked) covering the gate structure and the source-drain doping layer is also formed on the substrate 10.
[0014] refer to Figure 2 A barrier material layer 11 is formed on the top of the dielectric layer, and multiple ion implantations are performed on specific positions of different regions of the barrier material layer 11 , so that the barrier material layer 11 doped with ions serves as a barrier layer 12 .
[0015] refer to Figure 3 andFigure 4 After forming the barrier layer 12, the remaining barrier material layer 11 is removed by a wet etching process.
[0016] As Figure 4 shown, Figure 4 The boxes of different contour types in it are used to represent the barrier layer 12 formed by different ion implantations. For example, the solid-line box represents the barrier layer 12 formed by the first ion implantation, and the dashed-line boxes with different densities respectively represent the barrier layer 12 formed by the second ion implantation and the third ion implantation.
[0017] After removing the remaining barrier material layer 11, the subsequent process further includes: etching the dielectric layer within a preset etching window, where the preset etching window extends across the barrier layer 12 in a direction parallel to the extension direction of the gate structure, so that the barrier layer 12 divides the etching positions in the preset etching window, and multiple grooves spaced apart are formed in the dielectric layer.
[0018] The grooves are used to provide spatial positions for forming the target layer. For example, the target layer can be the zeroth interconnect layer (M0).
[0019] The barrier layer 12 is formed by ion implanting the barrier material layer 11. In order to improve the etching selectivity between the barrier material layer 11 and the barrier layer 12 during the process of removing the remaining barrier material layer 11, the remaining barrier material layer 11 is removed by a wet etching process.
[0020] However, currently in the method for forming a semiconductor structure, as the pattern feature size in semiconductor processes continues to shrink, it means that the space between the barrier layers 12 is getting smaller and smaller, which easily leads to poor removal effect of the wet method on the remaining barrier material layer 11 at positions where the barrier layers 12 are closely spaced, and it is easy to have residues of the barrier material layer 11, thereby resulting in poor morphology of the formed barrier layer 12, and further affecting the quality of the subsequently formed grooves.
[0021] In addition, due to the need for multiple ion implantations in different regions, the number of masks used is relatively large, increasing the complexity of the process. Moreover, by forming the target pattern multiple times through multiple masks, multiple photolithography processes need to be adopted accordingly (refer to Figure 4 , where different line types represent the patterns formed in different steps), then the alignment accuracy between multiple photolithography processes is difficult to control, which will further magnify the problem of overlay shift, resulting in inaccurate positions of the formed barrier layer, and further leading to low position accuracy of the subsequently formed grooves, and even possibly the problem of groove connection, correspondingly resulting in connection problems of the target layer formed in the grooves (for example, the problem of short circuit in the zeroth interconnect layer).
[0022] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on the top of which a first dielectric layer is formed; forming a core layer on the top of the first dielectric layer; forming a mask sidewall on the sidewall of the core layer; removing the core layer; after removing the core layer, etching the first dielectric layer within a preset etching window, the preset etching window spanning across the mask sidewall along a first direction, so that the mask sidewall divides the etching position in the preset etching window, and forming a plurality of grooves spaced apart from each other in the first dielectric layer.
[0023] In the method for forming a semiconductor structure provided by the embodiment of the present invention, a core layer is formed on the top of the first dielectric layer; a mask sidewall is formed on the sidewall of the core layer; after removing the core layer, the first dielectric layer within a preset etching window is etched, the preset etching window spanning across the mask sidewall along a first direction, so that the mask sidewall divides the etching position in the preset etching window, and forming a plurality of grooves spaced apart from each other in the first dielectric layer; by forming a core layer on the top of the first dielectric layer, then forming a mask sidewall on the sidewall of the core layer, and then removing the core layer, a mask sidewall is formed by means of self-aligned multiple patterning (for example, self-aligned double patterning), such that the dimensional accuracy and alignment accuracy of the position of the mask sidewall are higher. Correspondingly, when etching the first dielectric layer within the preset etching window, the mask sidewall divides the etching position in the preset etching window, thereby improving the quality of the formed grooves by the mask sidewall and enabling better isolation of the grooves in different regions, thus improving the performance of the semiconductor structure.
[0024] In order to make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.
[0025] Figures 5 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.
[0026] Refer to Figure 5 , Figure 5 which is a cross-sectional view along a second direction, the second direction being perpendicular to the extending direction of the gate structure.
[0027] Provide a substrate 500, on which a gate structure 501 extending along a first direction is formed, and source / drain doping layers 502 are formed in the substrate 500 on both sides of the gate structure 501.
[0028] The substrate 500 is used to provide a process platform for subsequent process steps.
[0029] In this embodiment, the substrate 500 is used to form a field-effect transistor. As an example, the substrate 500 is used to form a fin field-effect transistor.
[0030] In this embodiment, the substrate 500 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
[0031] The gate structure 501 is used to adjust or control the channel current of the field-effect transistor. In this embodiment, the gate structure 501 is a metal gate structure. In other embodiments, the gate structure may also be a polysilicon gate structure.
[0032] It should be noted that, as an example, after source / drain doping layers 502 are formed on both sides of the dummy gate structure, the dummy gate structure can be removed, and the gate structure 501 can be formed at the original position of the dummy gate structure.
[0033] The source / drain doping layers 502 are used as the source region or the drain region to provide carriers during device operation.
[0034] The gate structure 501 extends in a first direction. Correspondingly, the source / drain doping layers 502 are located on both sides of the gate structure 501 in a second direction, and the first direction is perpendicular to the second direction.
[0035] Continuing to refer to Figure 5 , a first dielectric layer 510 is further formed on the top of the substrate 500.
[0036] The first dielectric layer 510 is used to provide a process basis for forming trenches subsequently. The trenches are used to provide a spatial position for forming a target layer. For example, the target layer can be a zero interconnect layer or a back-end interconnect layer.
[0037] Specifically, the first dielectric layer 510 is used to provide a process basis for forming a metal interconnect structure located in the trenches subsequently.
[0038] In this embodiment, the first dielectric layer 510 covers the source / drain doping layers 502 and the gate structure 501.
[0039] Specifically, the first dielectric layer 510 includes: a first sub-dielectric layer 511 covering the sidewalls of the gate structure 501, a second stop layer 512 covering the gate structure 501 and the first sub-dielectric layer 511, and a second sub-dielectric layer 515 covering the second stop layer 512.
[0040] The first sub-dielectric layer 511 is used to isolate each semiconductor structure, prevent leakage current from occurring between devices, and also used to support other structures formed thereon.
[0041] Correspondingly, the first sub-dielectric layer 511 is made of an insulating material, and the material of the first sub-dielectric layer 511 includes one or more of silicon nitride, silicon carbide, silicon oxide, silicon carbonitride, silicon carbon oxynitride, and titanium oxide.
[0042] The second sub-dielectric layer 515 functions as a transfer layer when forming the zeroth interconnect layer (M0) subsequently.
[0043] The second sub-dielectric layer 515 is made of an insulating material, and the material of the second sub-dielectric layer 515 includes one or more of silicon nitride, silicon carbide, silicon oxide, silicon carbonitride, silicon carbon oxynitride, and titanium oxide.
[0044] When forming a trench on top of the gate structure 501 subsequently, the second stop layer 512 functions to define the process stop position.
[0045] The material of the second stop layer 512 includes one or more of silicon nitride, silicon carbide, silicon oxide, silicon carbonitride, silicon carbon oxynitride, titanium nitride, and titanium oxide.
[0046] It should be noted that different materials are selected for the second stop layer 512 and the second sub-dielectric layer 515, and different materials are selected for the second stop layer 512 and the first sub-dielectric layer 511.
[0047] In this embodiment, the material of the first sub-dielectric layer 511 is silicon oxide, the material of the second stop layer 512 is silicon nitride, and the material of the second sub-dielectric layer 515 is silicon oxide.
[0048] Reference Figure 6 , Figure 6 is a cross-sectional view based on Figure 5 of.
[0049] In this embodiment, the method for forming the semiconductor structure further includes: forming a first stop layer 561 on top of the first dielectric layer 510, and forming a second dielectric layer 562 on top of the first stop layer 561.
[0050] In the process of forming a mask structure subsequently, there is a height difference between different types of mask structures. While transferring the pattern of the mask structure, the second dielectric layer 562 can reduce the influence of the height difference between different types of mask structures on the pattern transfer effect and improve the uniformity of pattern transfer.
[0051] The material of the second dielectric layer 562 is an insulating material, and the material of the second dielectric layer 562 includes one or more of silicon nitride, silicon carbide, silicon oxide, silicon carbonitride, silicon carbon oxynitride, and titanium oxide. In this embodiment, the material of the second dielectric layer 562 is silicon oxide.
[0052] During the process of transferring the pattern of the mask structure, the first stop layer 561 serves to define the process stop position, which can further reduce the influence of the height difference between different types of mask structures on the pattern transfer effect and improve the uniformity of pattern transfer.
[0053] The material of the first stop layer 561 includes one or more of silicon nitride, silicon carbide, silicon oxide, silicon carbonitride, silicon carbon oxynitride, titanium nitride, and titanium oxide.
[0054] It should be noted that the first stop layer 561 and the second sub-dielectric layer 515 are made of different materials, and the first stop layer 561 and the second dielectric layer 562 are made of different materials.
[0055] In this embodiment, the material of the first stop layer 561 is titanium nitride.
[0056] In this embodiment, forming the second dielectric layer 562 and the first stop layer 561 on the top of the substrate 500 can reduce the influence brought by the height difference between different mask structures while transferring the mask structure pattern, which is convenient for achieving better effects when forming trenches subsequently.
[0057] Continue to refer to Figure 6 and, in combination with reference to Figure 7 and Figure 8 , Figure 7 and Figure 8 are cross-sectional views based on Figure 6 On the top of the first dielectric layer 510, a core layer 520 is formed.
[0058] The core layer 520 provides a process basis for forming mask sidewalls subsequently.
[0059] The material of the core layer 520 includes amorphous silicon or a dopant of amorphous silicon, and the doping elements include arsenic, carbon, phosphorus, germanium, etc. As an example, the material of the core layer 520 is amorphous silicon.
[0060] It should be noted that, as an example, the shape of the projection of the core layer 520 on the surface of the substrate 500 is oval. In other embodiments, the shape of the projection of the core layer on the substrate surface can also be square.
[0061] In this embodiment, the extending direction of the gate structure 501 is the first direction, and the direction perpendicular to the first direction is the second direction. The size of the core layer 520 in the second direction is greater than or equal to the preset size of the zero-th interconnection layer, and the size of the core layer 520 in the second direction is less than or equal to the sum of the preset size of the zero-th interconnection layer and twice the spacing between adjacent zero-th interconnection layers, that is, the size of the core layer 520 in the second direction is less than or equal to the spacing of the next adjacent zero-th interconnection layer.
[0062] As an example, the size of the core layer 520 in the second direction is greater than the preset size of the zero-th interconnection layer, which is beneficial to ensuring that the zero-th interconnection layer can be completely blocked.
[0063] The size of the core layer 520 in the second direction is less than or equal to the spacing of the next adjacent zero-th interconnection layer, which is beneficial to reducing the influence between adjacent core layers 520, so as to form a mask sidewall with better topography in subsequent processes.
[0064] Specifically, the size of the core layer 520 in the second direction is 10 nanometers to 100 nanometers.
[0065] In this embodiment, the size of the core layer 520 in the second direction should not be too large or too small. If the size of the core layer 520 in the second direction is too large, it is easy to make the size of the mask sidewall formed on the sidewall of the core layer 520 in subsequent processes smaller, so that the size of the formed blocking layer is smaller, and then it is easy to increase the risk of not being able to completely block the zero-th interconnection layer; if the size of the core layer 520 in the second direction is too small, it is easy to cause poor connection of the mask sidewalls 530 on the sidewalls of adjacent core layers 520 in subsequent processes, and it is easy to increase the risk of not being able to completely block the zero-th interconnection layer. Therefore, the size of the core layer 520 in the second direction is 10 nanometers to 100 nanometers.
[0066] It should also be noted that the size of the core layer 520 in the first direction is determined by the size of the groove formed subsequently in the first direction, and the size of the core layer 520 in the first direction can be adjusted according to process requirements, which has a certain degree of flexibility.
[0067] The step of forming the core layer 520 on the top of the first dielectric layer 510 includes: referring to Figure 6 , forming a core material layer 521 on the top of the first dielectric layer 510; referring to Figure 7 and Figure 8 , patterning the core material layer 521 to form the core layer 520 located on the top of the first dielectric layer 510.
[0068] The core material layer 521 provides a process basis for forming the core layer 520 subsequently.
[0069] Specifically, the steps of patterning the core material layer 521 include: as Figure 7 shown, a third mask layer is formed on the core material layer 521, and the third mask layer includes a first planarization layer (not labeled), a first anti-reflection coating (not labeled), and a patterned first photoresist layer (not labeled) stacked from bottom to top; as Figure 8 shown, using the patterned first photoresist layer as a mask, the first anti-reflection coating, the first planarization layer, and the core material layer 521 are etched in sequence to pattern the core material layer 521 into the core layer 520.
[0070] As an example, the first planarization layer is a spin-on carbon (SOC) layer, and the first anti-reflection coating is a silicon-containing anti-reflection coating (Si-ARC). By using the third mask layer with a stacked structure, the accuracy of patterning the core material layer 521 is improved.
[0071] The process of patterning the core layer 520 includes a dry etching process (for example, an anisotropic dry etching process).
[0072] By patterning the core material layer 521 to form the core layer 520, the process difficulty is reduced.
[0073] In this embodiment, after forming the core layer 520, it further includes: removing the remaining third mask layer.
[0074] Refer to Figures 9 to 12 , Figures 9 to 11 is a cross-sectional view based on Figure 8 , Figure 12 is Figure 11 a top view of
[0075] In this embodiment, the method of forming the semiconductor structure further includes: forming a mask sidewall 530 on the sidewall of the core layer 520.
[0076] Subsequently, the first dielectric layer in the preset etching window is etched, and the mask sidewall 530 is used as a barrier layer when etching the first dielectric layer, so as to realize the segmentation of the trench through the mask sidewall 530.
[0077] The material of the mask sidewall 530 includes: one or more of silicon nitride, silicon carbide, silicon oxide, silicon carbonitride, silicon carbon oxynitride, and titanium oxide. As an example, the material of the mask sidewall 530 is silicon nitride.
[0078] In this embodiment, by first forming the core layer 520 and then forming the mask sidewall 530 on the sidewalls of the core layer 520, the process steps can be simplified and the number of photomasks used can be reduced. Moreover, the mask sidewall 530 is formed by self-aligned multiple patterning (e.g., self-aligned double patterning), so that the dimensional accuracy of the mask sidewall 530 and the alignment accuracy of the position are higher, thereby facilitating the control of the size and position of the trench.
[0079] Specifically, in the step of forming the mask sidewall 530 on the sidewalls of the core layer 520, the mask sidewall 530 is an annular structure, and the mask sidewall 530 includes a first mask sidewall 531 located on the sidewalls of both sides of the core layer 520 along the first direction Y (as Figure 12 shown), and a second mask sidewall 532 located on the sidewalls of both sides of the core layer 520 along the second direction X (as Figure 12 shown). Figure 12 shown).
[0080] By forming the annular mask sidewall 530, the first mask sidewall 531 and the second mask sidewall 532 are formed simultaneously, and both the first mask sidewall 531 and the second mask sidewall 532 can divide the etching position in the preset etching window in the first direction, thereby improving the efficiency of forming the barrier layer.
[0081] More specifically, in the step of forming the mask sidewall 530 on the sidewalls of the core layer 520, the mask sidewall 530 at least covers the sidewalls of both sides of the core layer 520 along the second direction X, and the adjacent mask sidewalls 530 in the second direction X are in contact with each other.
[0082] The adjacent mask sidewalls 530 in the second direction X being in contact with each other can form an integral mask sidewall 530 between adjacent core layers 520, and the contacting mask sidewalls 530 can play a role in separating the trench formed between adjacent core layers 520 in the first direction.
[0083] It should be noted that the distance between adjacent core layers 520 in the second direction is less than or equal to the size of the core layer 520 in the second direction. Therefore, along the direction parallel to the surface of the substrate, the thickness of the mask sidewall 530 in the second direction should be greater than half of the size of the core layer 520 in the second direction to ensure that the sidewalls of the adjacent mask sidewalls 530 in the second direction are directly connected. Therefore, along the direction parallel to the surface of the substrate 500, the thickness of the mask sidewall 530 is 5 nanometers to 50 nanometers.
[0084] In this embodiment, along the normal direction of the substrate 500, the height of the mask sidewall is 10 nanometers to 100 nanometers.
[0085] In this embodiment, the step of forming the mask sidewall 530 on the sidewall of the core layer 520 includes: referring to Figure 9 , forming a mask sidewall material layer 533 that conformally covers the core layer 520 and the first dielectric layer 510; referring to Figures 10 to 12 , removing the mask sidewall material layer 533 on the top of the core layer 520 and the top of the first dielectric layer 510, and retaining the mask sidewall material layer 533 located on the sidewall of the core layer 520 as the mask sidewall 530.
[0086] Specifically, the process of removing the mask sidewall material layer 533 on the top of the core layer 520 and the top of the first dielectric layer 510 includes a dry etching process (e.g., an anisotropic dry etching process).
[0087] In this embodiment, the etching gas used in the dry etching process includes a fluorine-containing gas.
[0088] Specifically, the process parameters of the dry etching process include: the etching gas includes one or more of CF4, CH2F2, C4F6, SF6, and NF3, the process pressure is 5 mTorr to 100 mTorr, the process temperature is 20 °C to 80 °C, the power is 100 W to 1000 W, and the bias voltage is 100 V to 300 V.
[0089] In this embodiment, the dry etching process adopted has better etching ability for fine patterns.
[0090] Continuing to refer to Figures 9 to 12 , before removing the mask sidewall material layer 533 on the top of the core layer 520 and the top of the first dielectric layer 510, it further includes: using a lithography process to form a first mask layer 541 on the mask sidewall material layer 533 on the side of the core layer 520.
[0091] Correspondingly, using the first mask layer 541 as a mask, etching and removing the mask sidewall material layer 533 on the top of the core layer 520 and the top of the first dielectric layer 510, retaining the mask sidewall material layer 533 located on the sidewall of the core layer 520 as the mask sidewall 530, and retaining the remaining mask sidewall material layer 533 on the side of the core layer 520 as the second mask layer 542.
[0092] The second mask layer 542 serves as a pattern transfer layer in the subsequent process of forming the trench.
[0093] It should be noted that the mask sidewall material layer 533 on the sidewall of the core layer 520 serves as the mask sidewall 530. The height of the mask sidewall 530 along the normal direction of the substrate 500 is the height of the core layer 520, and the height of the second mask layer 542 along the normal direction of the substrate 500 is the thickness of the mask sidewall material layer 533 along the normal direction of the substrate 500. Therefore, along the normal direction of the substrate 500, the height of the second mask layer 542 is less than the height of the mask sidewall 530.
[0094] It should also be noted that the first mask layer 541 is formed by a lithography process, and the mask sidewall material layer 533 on the side of the core layer 520 is etched to form the first mask layer 541, that is, the second mask layer 542 is formed by a lithography-etching process, and the mask sidewall 530 is formed by a self-aligned double patterning process, which can meet the requirements of forming mask structures with different pattern complexities and different sizes. Moreover, both the mask sidewall 530 and the second mask layer 542 are formed through the mask sidewall material layer 533, thus simplifying the process steps.
[0095] In this embodiment, before forming the first mask layer 541 on the mask sidewall material layer 533 on the side of the core layer 520, it further includes: forming a second planarization layer (not labeled) and a second anti-reflection coating on the mask sidewall material layer 533; the first mask layer 541 is correspondingly formed on the second anti-reflection coating.
[0096] As an example, the second planarization layer is a spin-on carbon (SOC) layer, and the second anti-reflection coating is a silicon-containing anti-reflection coating (Si-ARC). By using a stacked structure composed of the second planarization layer, the second anti-reflection coating, and the first mask layer 541 to pattern the mask sidewall material layer 533, the patterning accuracy of the mask sidewall material layer 533 can be improved.
[0097] In addition, for the convenience of illustration, Figure 12 different coatings are used in [the figure] to distinguish the first mask sidewall 531, the second mask sidewall 532, and the second mask layer 542.
[0098] Refer to Figure 13 Figure 13 [the figure] is a top view. In this embodiment, after forming the mask sidewall 530 and the second mask layer 542, the method for forming the semiconductor structure further includes: removing the core layer 520.
[0099] When forming trenches in subsequent processes, the dielectric layer under the core layer 520 also needs to be etched to form trenches, so the core layer 520 needs to be removed.
[0100] Specifically, the process of removing the core layer 520 includes a dry etching process.
[0101] In this embodiment, the etching gas used in the dry etching process includes fluorine-containing gas.
[0102] Specifically, the process parameters of the dry etching process include: the etching gas includes one or more of CF4, CH2F2, C4F6, SF6, and NF3, the process pressure is 5 mTorr to 100 mTorr, the process temperature is 20 °C to 80 °C, the power is 100 W to 1000 W, and the bias voltage is 100 V to 300 V.
[0103] In this embodiment, the dry etching process has a higher selective etching ratio, and the removal of the core layer 520 is more thorough, correspondingly improving the quality of the subsequently formed trenches.
[0104] Continue to refer to Figure 13 , after removing the core layer 520, the method for forming the semiconductor structure further includes: etching the first dielectric layer 510 within a preset etching window A, where the preset etching window A extends across the mask sidewall 530 along the first direction Y, so that the mask sidewall 530 divides the etching positions within the preset etching window A, and a plurality of spaced trenches 550 are formed in the first dielectric layer 510.
[0105] The trenches 550 are used to provide a spatial position for forming the target layer. In this embodiment, the target layer is the zero-th interconnect layer. In other embodiments, the target layer may also be a back-end interconnect layer (i.e., the metal interconnect layer in the back-end process).
[0106] It should be noted that when etching the first dielectric layer 510 within the preset etching window A, the mask sidewall 530 acts as a barrier layer, thereby being able to divide the etching positions within the preset etching window A. Among them, by using the mask sidewall 530 to divide the etching positions within the preset etching window A, the length of the preset etching window A along the first direction Y is greater than the length of the trench 550 along the first direction Y, thereby improving the process window of the etching process.
[0107] In this embodiment, the size of the preset etching window along the second direction X is determined according to the size of the subsequently formed target layer along the second direction X.
[0108] In this embodiment, in the step of etching the first dielectric layer 510 within the preset etching window A, the preset etching windows A are arranged in sequence along the second direction X and respectively extend across the first mask sidewall 531 and the second mask sidewall 532.
[0109] Correspondingly, in the step of etching the first dielectric layer 510 within the preset etching window A, the preset etching window A also extends across the second mask layer 542 in the first direction, so that the second mask layer 542 divides the etching positions within the preset etching window A.
[0110] It should be noted that Figure 12 only a part of the preset etching window A is schematically shown, and the number of preset etching windows is not limited to 5.
[0111] It should also be noted that in the step of etching the first dielectric layer 510 within the preset etching window A, the trench 550 exposes either the source / drain doping layer 502 or the gate structure 501, or exposes the source / drain doping layer 502 and the gate structure 501 respectively.
[0112] In this embodiment, the case where the trench 550 exposes the source / drain doping layer 502 is taken as an example for illustration.
[0113] Specifically, a first stop layer 561 is formed on the top of the first dielectric layer 510, and a second dielectric layer 562 is located on the top of the first stop layer 561. Correspondingly, the step of forming the trench 550 further includes: etching the second dielectric layer 562 with the top surface of the first stop layer 561 as the stop position to expose the top surface of the first stop layer 561; after exposing the top surface of the first stop layer 561, etching the first stop layer 561 and the first dielectric layer 510.
[0114] In this embodiment, after etching the first stop layer 561 and the first dielectric layer 510, the trench 550 exposes the source / drain doping layer 502.
[0115] It should be noted that during the process of etching the first dielectric layer 510, the first stop layer 561 and the second sub-dielectric layer 515 can be etched with the top surface of the second stop layer 512 as the stop position to expose the top surface of the second stop layer 512; after exposing the top surface of the second stop layer 512, the second stop layer 512 and the first sub-dielectric layer 511 are etched to expose the top surface of the gate structure 501 and expose the source / drain doping layer 502, so as to further improve the depth uniformity of the trench 550 exposing the source / drain doping layer 502 and reduce the damage to the source / drain doping layer 502.
[0116] It should also be noted that in some other embodiments, when forming a trench exposing the top surface of the gate structure in the first dielectric layer, correspondingly, the step of forming the trench located on the top surface of the gate structure further includes: using the top surface of the first stop layer as the stopping position, etching the second dielectric layer to expose the top surface of the first stop layer; after exposing the top surface of the first stop layer, using the top surface of the second stop layer as the stopping position, etching the first stop layer and the second sub-dielectric layer to expose the top surface of the second stop layer; after exposing the top surface of the second stop layer, etching the second stop layer to expose the top surface of the gate structure.
[0117] By using the top surface of the first stop layer as the stopping position, the depth uniformity of the trench exposing the gate structure is improved, and the damage to the gate structure is reduced.
[0118] In this embodiment, the method for forming the semiconductor structure further includes: forming a target layer (not shown in the figure) in the trench 550.
[0119] Specifically, the target layer is an interconnect layer. The interconnect layer is usually a metal material, and it is easier to etch the dielectric material. Moreover, the metal material is filled in the trench 550 to reduce the probability of damage to the interconnect layer, thereby facilitating the improvement of the quality of the interconnect layer.
[0120] As an example, the target layer is a zero-th interconnect layer (not shown in the figure).
[0121] The zero-th interconnect layer is used to connect the source-drain doping layers, and the zero-th interconnect layer plays a role in transmitting signals, thereby realizing the electrical connection between the source-drain doping layers and other structures.
[0122] The material of the zero-th interconnect layer includes W, Co, or Ru, etc.
[0123] In other embodiments, the target layer can also be a back-end interconnect layer in the back-end-of-line (BEOL) process.
[0124] It should be noted that the method for forming the semiconductor structure described in the embodiments of the present invention can be used to form any type of device structure, including planar transistor devices, fin field-effect transistor (FinFET) devices, or gate-all-around (GAAFET) devices.
[0125] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that: Provide a substrate, on the top of which a first dielectric layer is formed; Form a core layer on the top of the first dielectric layer; Form a mask sidewall on the sidewalls of the core layer; Remove the core layer; After removing the core layer, etch the first dielectric layer within a preset etching window that extends across the mask sidewall in a first direction, so that the mask sidewall divides the etching positions within the preset etching window and forms a plurality of grooves spaced apart from each other in the first dielectric layer.
2. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of forming a mask sidewall on the sidewalls of the core layer, the mask sidewall is an annular structure, which includes a first mask sidewall located on the two sidewalls of the core layer along the first direction and a second mask sidewall located on the two sidewalls of the core layer along a second direction, and the first direction is perpendicular to the second direction; In the step of etching the first dielectric layer within a preset etching window, the preset etching windows are arranged in sequence along the second direction and respectively extend across the first mask sidewall and the second mask sidewall.
3. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of forming a mask sidewall on the sidewalls of the core layer, the mask sidewall at least covers the two sidewalls of the core layer along the second direction, and adjacent mask sidewalls in the second direction are in contact with each other.
4. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of forming a mask sidewall on the sidewalls of the core layer includes: forming a mask sidewall material layer that conformally covers the core layer and the first dielectric layer; Remove the mask sidewall material layer on the top of the core layer and the top of the first dielectric layer, and retain the mask sidewall material layer located on the sidewalls of the core layer as the mask sidewall.
5. The method for forming a semiconductor structure according to claim 4, characterized in that, Before removing the mask sidewall material layer on the top of the core layer and the top of the first dielectric layer, it further includes: using a photolithography process to form a first mask layer on the mask sidewall material layer on the side of the core layer; Using the first mask layer as a mask, remove the mask sidewall material layer on the top of the core layer and the top of the first dielectric layer, and retain the remaining mask sidewall material layer on the side of the core layer as a second mask layer; In the step of etching the first dielectric layer within a preset etching window, the preset etching window also extends across the second mask layer in the first direction, so that the second mask layer divides the etching positions within the preset etching window.
6. The method for forming a semiconductor structure according to claim 4, characterized in that, The process of removing the mask sidewall material layer on the top of the core layer and the top of the first dielectric layer includes a dry etching process.
7. The method for forming a semiconductor structure according to claim 6, characterized in that, The process parameters of the dry etching process include: the etching gas includes one or more of CF4, CH2F2, C4F6, SF6, and NF3, the process pressure is 5 mTorr to 100 mTorr, the process temperature is 20 °C to 80 °C, the power is 100 W to 1000 W, and the bias voltage is 100 V to 300 V.
8. The method for forming a semiconductor structure according to claim 1, characterized in that, Before forming the core layer, the method for forming the semiconductor structure further includes: forming a first stop layer on the top of the first dielectric layer; Form a second dielectric layer on the top of the first stop layer.
9. The method for forming a semiconductor structure according to any one of claims 1 to 8, characterized in that, In the step of providing a substrate, a gate structure extending in a first direction is formed on the substrate, source / drain doping layers are formed in the substrate on both sides of the gate structure, and the first dielectric layer covers the source / drain doping layers and the gate structure; In the step of etching the first dielectric layer within a preset etching window, the trench exposes either the source / drain doping layer or the gate structure, or exposes the source / drain doping layer and the gate structure respectively; The method for forming the semiconductor structure further includes: forming a zero-th interconnection layer within the trench.
10. The method for forming a semiconductor structure according to claim 9, characterized in that, The first dielectric layer includes: a first sub-dielectric layer covering the sidewalls of the gate structure, a second stop layer covering the gate structure and the first sub-dielectric layer, and a second sub-dielectric layer covering the second stop layer.
11. The method for forming a semiconductor structure according to any one of claims 1 to 8, characterized in that, In the step of forming a mask sidewall on the sidewalls of the core layer, the material of the mask sidewall includes one or more of silicon nitride, silicon carbide, silicon oxide, silicon carbonitride, silicon carbon oxynitride, and titanium oxide.
12. The method for forming a semiconductor structure according to any one of claims 1 to 8, characterized in that, Along the direction parallel to the surface of the substrate, the thickness of the mask sidewall is 5 nanometers to 50 nanometers.
13. The method for forming a semiconductor structure according to any one of claims 1 to 8, characterized in that,Along the normal direction of the substrate, the height of the mask sidewall is 10 nanometers to 100 nanometers.
14. The method for forming a semiconductor structure according to any one of claims 1 to 8, wherein, The dimension of the core layer in a second direction is greater than or equal to a preset dimension of the zero-th interconnection layer, and the dimension of the core layer in the second direction is less than or equal to the sum of the preset dimension of the zero-th interconnection layer and twice the spacing between adjacent zero-th interconnection layers, and the first direction is perpendicular to the second direction.
15. The method for forming a semiconductor structure according to any one of claims 1 to 8, wherein, The step of forming the core layer includes: forming a core material layer on the top of the first dielectric layer; Patterning the core material layer to form the core layer located on the top of the first dielectric layer.
16. The method for forming a semiconductor structure according to any one of claims 1 to 8, wherein, The process for removing the core layer includes a dry etching process.
17. The method for forming a semiconductor structure according to claim 16, wherein, The process parameters of the dry etching process include: the etching gas includes one or more of CF4, CH2F2, C4F6, SF6, and NF3, the process pressure is 5 millitorr to 100 millitorr, the process temperature is 20 degrees Celsius to 80 degrees Celsius, the power is 100 watts to 1000 watts, and the bias voltage is 100 volts to 300 volts.