Device manufacturing method and semiconductor device

Abstract

The present disclosure provides a device manufacturing method and a semiconductor device. The device manufacturing method includes: synchronously forming a first conductive member and a first heat conductive member in a first chip, wherein the first conductive member and the first heat conductive member are electrically isolated; synchronously forming a second conductive member and a second heat conductive member in a second chip, wherein the second conductive member and the second heat conductive member are electrically isolated; and joining the first chip and the second chip to make the first heat conductive member and the second heat conductive member in thermal communication and form a heat conductive channel.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a method for fabricating an apparatus and a semiconductor apparatus. Background Technology

[0002] Semiconductor devices typically generate heat during operation, causing their temperature to rise. If the semiconductor device cannot be cooled in time, it will operate in a high-temperature environment for a long time, leading to performance degradation or malfunction.

[0003] Therefore, there is a need to dissipate heat from semiconductor devices. Summary of the Invention

[0004] One of the purposes of this disclosure is to provide a method for fabricating an apparatus and a semiconductor device.

[0005] According to a first aspect of this disclosure, a method for preparing an apparatus is provided, comprising:

[0006] A first conductive element and a first thermally conductive element are formed simultaneously in a first chip, wherein the first conductive element and the first thermally conductive element are electrically isolated;

[0007] A second conductive element and a second thermally conductive element are simultaneously formed in the second chip, wherein the second conductive element and the second thermally conductive element are electrically isolated; and

[0008] The first chip and the second chip are joined together so that the first thermal conductive element and the second thermal conductive element are in thermal communication and form a thermal conductive channel.

[0009] In some embodiments, simultaneously forming a first conductive element and a first thermally conductive element in a first chip includes:

[0010] Multiple first through-holes are formed in a first preset layer of the first chip, and conductive and thermally conductive materials are filled in the multiple first through-holes to simultaneously form the first conductive portion of the first conductive element and the first thermally conductive portion of the first thermally conductive element; and / or

[0011] One or more first wirings are formed on the second preset layer of the first chip to simultaneously form the second conductive portion of the first conductive element and the second thermally conductive portion of the first thermally conductive element, wherein the one or more first wirings extend in a plane perpendicular to the thickness direction.

[0012] In some embodiments, simultaneously forming the second conductive element and the second thermally conductive element in the second chip includes:

[0013] Multiple second vias are formed in the third preset layer of the second chip, and conductive and thermally conductive materials are filled in the multiple second vias to simultaneously form the third conductive portion of the second conductive element and the third thermally conductive portion of the second thermally conductive element; and / or

[0014] One or more layers of second wiring are formed on the fourth preset layer of the second chip to simultaneously form the fourth conductive portion of the second conductive element and the fourth thermally conductive portion of the second thermally conductive element, wherein the one or more layers of second wiring extend in a plane perpendicular to the thickness direction.

[0015] In some embodiments, joining the first chip and the second chip includes:

[0016] A bonding layer is formed on a first side of the first chip and / or a second side of the second chip, and the first chip and the second chip are bonded through the bonding layer, wherein the first side of the first chip is adjacent to the second side of the second chip, and the first thermal conductive element and the second thermal conductive element are thermally connected via bonding pads in the bonding layer.

[0017] In some embodiments, a portion of the surface of one of the first chip and the second chip adjacent to the other is exposed to the environment to form an exposure portion, wherein a thermally conductive element in the chip having the exposure portion is partially located in the exposure portion to be partially exposed to the environment.

[0018] In some embodiments, the method of preparing the device further includes:

[0019] A third heat-conducting element is formed on the exposed surface of the exposed portion, wherein the third heat-conducting element is in thermal communication with a heat-conducting element in the chip having the exposed portion.

[0020] In some embodiments, the method of preparing the device further includes:

[0021] The location of hot spots in the first chip and / or the second chip is determined by thermal simulation, and the location of the first heat-conducting component and the second heat-conducting component is determined based on the location of the hot spots by thermal simulation, so that the heat conduction channel can conduct heat to the hot spots.

[0022] According to a second aspect of this disclosure, a semiconductor device is provided, comprising:

[0023] A first chip includes a patterned first functional layer, a first portion of which is configured to serve as a first conductive element, and a second portion of which is configured to serve as a first thermal conductive element, wherein the first conductive element is electrically isolated from the first thermal conductive element.

[0024] A second chip, bonded to one side of the first chip, includes a patterned second functional layer. A first portion of the patterned second functional layer is configured to function as a second conductive element, and a second portion of the patterned second functional layer is configured to function as a second thermal conductive element. The second conductive element and the second thermal conductive element are electrically isolated.

[0025] The first heat-conducting component and the second heat-conducting component are thermally connected to form a heat-conducting channel.

[0026] In some embodiments, the first thermally conductive element and the first electrically conductive element are formed simultaneously, and the second thermally conductive element and the second electrically conductive element are formed simultaneously.

[0027] In some embodiments, the first functional layer includes a first substrate, a first device layer, and a first wiring layer stacked sequentially in the thickness direction, and the second functional layer includes a second substrate, a second device layer, and a second wiring layer stacked sequentially in the thickness direction.

[0028] The second wiring layer is disposed face-to-face with the first substrate, or the second substrate is disposed face-to-face with the first substrate.

[0029] In some embodiments, the first thermally conductive element includes a first thermally conductive portion and / or a second thermally conductive portion, and the second thermally conductive element includes a third thermally conductive portion and / or a fourth thermally conductive portion.

[0030] The first thermally conductive portion fills the first via, and the first via is formed in at least one of the first substrate, the first device layer, and the first wiring layer.

[0031] The first wiring layer includes one or more first wiring layers extending in a plane perpendicular to the thickness direction, wherein at least a portion of the one or more first wiring layers is configured to serve as the second heat-conducting portion.

[0032] The third thermally conductive portion fills the second via, which is formed in at least one of the second substrate, the second device layer, and the second wiring layer.

[0033] The second wiring layer includes one or more layers of second wiring extending in a plane perpendicular to the thickness direction, wherein at least a portion of the one or more layers of second wiring is configured to serve as the fourth heat-conducting portion.

[0034] In some embodiments, a portion of the surface of one of the first chip and the second chip adjacent to the other is exposed to the environment to form an exposure portion, wherein a thermally conductive element in the chip having the exposure portion is partially located in the exposure portion to be partially exposed to the environment.

[0035] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0036] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0037] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0038] Figure 1 A schematic diagram of the temperature distribution before and after proper chip layout is shown in an example.

[0039] Figure 2 A schematic diagram of heat dissipation for a chip is shown in one example;

[0040] Figure 3 A schematic flowchart of a method for fabricating an apparatus according to an exemplary embodiment of the present disclosure is shown;

[0041] Figure 4 A schematic diagram showing the simultaneous formation of a first conductive portion and a first thermally conductive portion according to an exemplary embodiment of the present disclosure is shown;

[0042] Figure 5 A schematic diagram of the simultaneous formation of a third conductive portion and a third thermally conductive portion according to an exemplary embodiment of the present disclosure is shown;

[0043] Figure 6 A schematic diagram of the simultaneous formation of a second conductive portion and a second thermally conductive portion according to an exemplary embodiment of the present disclosure is shown;

[0044] Figure 7 A schematic diagram of the simultaneous formation of a second conductive portion and a second thermally conductive portion according to another exemplary embodiment of the present disclosure is shown;

[0045] Figure 8 A schematic diagram of the simultaneous formation of a fourth conductive portion and a fourth thermally conductive portion according to an exemplary embodiment of the present disclosure is shown;

[0046] Figure 9 A schematic diagram of the simultaneous formation of a fourth conductive portion and a fourth thermally conductive portion according to another exemplary embodiment of the present disclosure is shown;

[0047] Figure 10 A schematic diagram of the structure of a semiconductor device according to an exemplary embodiment of the present disclosure is shown;

[0048] Figure 11A schematic diagram of the structure of a semiconductor device according to another exemplary embodiment of the present disclosure is shown;

[0049] Figure 12 A schematic diagram of the structure of a semiconductor device according to yet another exemplary embodiment of the present disclosure is shown;

[0050] Figure 13 A schematic diagram of the process for constructing a heat conduction channel by thermal simulation according to an exemplary embodiment of the present disclosure is shown.

[0051] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts having the same function, and repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0052] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, the disclosed invention is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components. Detailed Implementation

[0053] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0054] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. Those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and are not exhaustive.

[0055] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0056] Three-dimensional integrated chips offer advantages such as high density, high performance, and small size, making them widely used in various modern electronic devices. However, as the number of stacked structures increases in three-dimensional integrated chips, the thermal resistance between internal hotspots and the external surface increases significantly, hindering effective heat dissipation. This causes heat generated during chip operation to easily accumulate internally, potentially leading to overheating, performance degradation, and reduced reliability.

[0057] In some examples, the components within a chip can be strategically arranged to ensure even distribution of hotspots and reduce thermal coupling. Figure 1 Figures (a) and (b) show schematic diagrams of chip temperature before and after optimized chip layout, respectively. Figure 1 (c) in the middle is related to Figure 1 The grayscale diagram corresponding to (a) in the image. Figure 1 (d) in the context is related to Figure 1 The grayscale diagram corresponding to (b) in the image. While this method can alleviate the problem of excessively high local temperatures caused by overly concentrated hotspots to some extent, heat from each hotspot area still tends to accumulate inside the chip, resulting in poor heat dissipation. Alternatively, in some examples, such as... Figure 2 As shown, thermal interface materials (TIMs) 3, integrated heat sinks 4, and heat sinks 5 can be used on the ball grid array (BGA) substrate 1 and silicon substrate 2 of the chip to reduce the thermal resistance from the chip to the boundary, thereby assisting in heat dissipation at the chip surface. However, this method of heat dissipating heat from the chip surface by additionally introducing TIM materials, heat sinks, and heat sinks is difficult to effectively handle the heat accumulated inside the chip. Alternatively, in some examples, microfluidic technology can be used to create channels for coolant flow inside or around the chip, using the flowing coolant to cool the chip. However, this method introduces additional microfluidic fabrication technology, which is difficult and costly.

[0058] To address the aforementioned issues, this disclosure provides a device fabrication method that simultaneously forms corresponding heat-conducting components to construct heat conduction channels while forming the conductive components of the chip. This eliminates the need for additional process steps to separately form the heat-conducting components, saving device fabrication costs while effectively reducing heat accumulation, decreasing thermal resistance, and improving the chip's heat dissipation capabilities.

[0059] In one exemplary embodiment of this disclosure, such as Figures 3 to 4 , Figures 6 to 7 , Figures 10 to 12 As shown, the device fabrication method may include:

[0060] In step S110, the first conductive element 130 and the first heat-conducting element 140 in the first chip 100 are formed simultaneously.

[0061] The first conductive element 130 and the first heat-conducting element 140 formed simultaneously can be electrically isolated to avoid short circuits in related circuits.

[0062] In some embodiments, such as Figure 4 , Figures 10 to 12As shown, the first heat-conducting element 140 may include a first heat-conducting portion 141 extending in the thickness direction, so that heat can be conducted in the thickness direction via the first heat-conducting portion 141. Correspondingly, the first electrical conductive element 130 formed synchronously with the first heat-conducting element 140 may also include a first electrical conductive portion 131 extending in the thickness direction.

[0063] In some embodiments, such as Figure 4 As shown, the simultaneous formation of the first conductive element 130 and the first thermal conductive element 140 in the first chip 100 may include: forming a plurality of first through holes 120 in the first preset layer 110 of the first chip 100, and filling the plurality of first through holes 120 with conductive and thermally conductive materials to simultaneously form the first conductive portion 131 of the first conductive element 130 and the first thermally conductive portion 141 of the first thermal conductive element 140.

[0064] Specifically, such as Figure 4 As shown in (a), the simultaneous formation of the first conductive element 130 and the first heat-conducting element 140 in the first chip 100 may include:

[0065] Step S111: A patterned first anti-etching layer 10 is formed on the first preset layer 110 of the first chip 100 using photolithography.

[0066] Specifically, an anti-etching material can be deposited on the first preset layer 110. Then, an electron beam exposure or ion beam exposure followed by development can be used to form a patterned first anti-etching layer 10 on the first preset layer 110 of the first chip 100. Alternatively, the pattern of the first mask can be transferred to the anti-etching material using a photolithography process based on the first mask to form a patterned first anti-etching layer 10. In this way, the first conductive portion 131 of the first conductive element 130 and the first thermally conductive portion 141 of the first thermally conductive element 140 can be formed simultaneously based on the first mask without having to set different masks for the formation of the first conductive portion 131 and the first thermally conductive portion 141, thus reducing the fabrication difficulty and saving fabrication costs.

[0067] Furthermore, such as Figure 4 As shown in (b), the simultaneous formation of the first conductive element 130 and the first heat-conducting element 140 in the first chip 100 may further include:

[0068] In step S112, the first preset layer 110 is etched under the protection of the first anti-etching layer 10 to form a plurality of first vias 120.

[0069] In some embodiments, such as Figure 4 (b) Figures 10 to 12 As shown, the first preset layer 110 can be, for example, the first substrate 160 of the first chip 100. Wherein, as... Figure 4 (b) Figure 10 and Figure 12 As shown, only the first substrate 160 can be etched to form the first via 120 formed on the first substrate 160. Alternatively, as... Figure 4 (b) and Figure 11 As shown, the first substrate 160 and the first device layer 170 of the first chip 100 can be etched sequentially to form a first via 120 opened in the first substrate 160 and the first device layer 170.

[0070] In some embodiments, such as Figure 4 (b) and Figure 11 As shown, the first preset layer 110 may be, for example, the first wiring layer 180 of the first chip 100. The first wiring layer 180 may be etched to form a first via 120 formed in the first wiring layer 180.

[0071] Furthermore, such as Figure 4 As shown in (c), the simultaneous formation of the first conductive element 130 and the first heat-conducting element 140 in the first chip 100 may further include:

[0072] In step S113, conductive and thermally conductive materials are filled into the plurality of first through holes 120 to simultaneously form the first conductive portion 131 of the first conductive element 130 and the first thermally conductive portion 141 of the first thermally conductive element 140.

[0073] Among these, conductive and thermally conductive materials can include, for example, metallic materials. Metallic materials typically have high thermal and electrical conductivity. Using metallic materials to form corresponding thermal conductive components can effectively improve the heat dissipation performance of the chip, eliminating the need to introduce additional thermally conductive materials to form the components and reducing device manufacturing costs.

[0074] In some embodiments, such as Figure 6 , Figure 7 and Figure 11 As shown, the first thermally conductive element 140 may include a second thermally conductive portion 142 extending in a plane parallel to or coinciding with the main plane of the first chip 100, or in other words, the first thermally conductive element 140 may include a second thermally conductive portion 142 extending in a plane perpendicular to the thickness direction, such that heat can be conducted through the second thermally conductive portion 142 in the plane perpendicular to the thickness direction. Correspondingly, the first conductive element 130, formed synchronously with the first thermally conductive element 140, may also include a second conductive portion 132 extending in a plane perpendicular to the thickness direction. In some embodiments, the second thermally conductive portion 142 may be in thermal communication with the first thermally conductive portion 141. Figure 11 As shown, the second heat-conducting portion 142 can be configured to be thermally connected to a plurality of first heat-conducting portions 141.

[0075] In some embodiments, such as Figures 6 to 7 As shown, the simultaneous formation of the first conductive element 130 and the first thermal conductive element 140 in the first chip 100 may include: forming one or more first wiring layers on the second preset layer 150 of the first chip 100 to simultaneously form the second conductive portion 132 of the first conductive element 130 and the second thermal conductive portion 142 of the first thermal conductive element 140, wherein the one or more first wiring layers may extend in a plane perpendicular to the thickness direction.

[0076] Specifically, in some embodiments, such as Figure 6 As shown in (a) to (c), forming one or more first wiring layers on the second preset layer 150 of the first chip 100 using photolithography may include:

[0077] Step S114: A conductive and thermally conductive material 30 in the form of a continuous thin film is deposited on the second preset layer 150.

[0078] Step S115: A patterned second anti-etching layer 40 is formed on the conductive and thermally conductive material 30 using a photolithography process;

[0079] Step S116: Etch the portion of the conductive and thermally conductive material 30 that is not covered by the second anti-etching layer 40 to form one or more layers of first wiring.

[0080] In this configuration, a portion of one or more layers of the first wiring can be configured as a second conductive portion 132, and another portion can be configured as a second thermally conductive portion 142. Thus, the second conductive portion 131 and the second thermally conductive portion 142 can be formed simultaneously.

[0081] In one specific example, the second resist layer 40 may be formed solely of photoresist, or it may also be formed of a material such as deposited silicon nitride. In some embodiments, step S115 may include depositing a resist material on the conductive and thermally conductive material 30, and using a photolithography process based on the second mask to transfer the pattern of the second mask onto the resist material to form a patterned second resist layer 40. Considering that the remaining second resist layer 40 after etching to form one or more layers of the first wiring in step S116 may affect subsequent processes, in some embodiments, the remaining second resist layer 40 may also be removed.

[0082] Alternatively, in other embodiments, such as Figure 7 As shown in (a) to (c), forming one or more first wiring layers on the second preset layer 150 of the first chip 100 using photolithography may include:

[0083] Step S117: A patterned photoresist layer 50 is formed on the second preset layer 150 of the first chip 100 using a photolithography process;

[0084] Step S118: Deposit a continuous thin film of conductive and thermally conductive material 30;

[0085] Step S119: A lift-off process is used to remove the photoresist layer 50 and the conductive and thermally conductive material 30 thereon, so that the remaining conductive and thermally conductive material 30 forms one or more layers of first wiring, so as to simultaneously form the second conductive portion 132 of the first conductive element 130 and the second thermally conductive portion 142 of the first thermally conductive element 140.

[0086] Step S117 may include depositing photoresist material on the second preset layer 150, and transferring the pattern of the second mask onto the photoresist material using a photolithography process based on the second mask to form a patterned photoresist layer 50.

[0087] In some embodiments using the second mask described above, it is not necessary to set different masks for the formation of the second conductive part 132 and the second thermally conductive part 142. The second conductive part 132 of the first conductive element 130 and the second thermally conductive part 142 of the first thermally conductive element 140 can be formed simultaneously through the second mask, which reduces the difficulty of device fabrication and saves fabrication costs.

[0088] In some embodiments, the second preset layer 150 may be, for example, the first substrate 160 of the first chip 100, such that one or more first wiring layers may be formed on the first substrate 160. Alternatively, in some embodiments, such as Figures 6 to 7 , Figures 10 to 12 As shown, the second preset layer may be, for example, the first device layer 170 of the first chip 100, and the first device layer 170 may be located above the first substrate 160. Thus, one or more first wiring layers may be formed on the first device layer 170. The one or more first wiring layers may be at least a part of the first wiring layer 180 of the first chip 100.

[0089] like Figure 3 , Figure 5 , Figures 8 to 12 As shown, the method for preparing the device disclosed herein may further include:

[0090] In step S120, the second conductive element 230 and the second heat-conducting element 240 in the second chip 200 are formed simultaneously.

[0091] The second conductive element 230 and the second heat-conducting element 240 formed simultaneously can be electrically isolated to avoid short circuits in related circuits.

[0092] In some embodiments, such as Figure 5 , Figures 8 to 12As shown, the second heat-conducting element 240 may include a third heat-conducting portion 241 extending in the thickness direction, so that heat can be conducted in the thickness direction via the third heat-conducting portion 241. Correspondingly, the second electric conductive element 230 formed synchronously with the second heat-conducting element 240 may also include a third electric conductive portion 231 extending in the thickness direction.

[0093] In some embodiments, such as Figure 5 As shown, the simultaneous formation of the second conductive element 230 and the second thermal conductive element 240 in the second chip 200 may include: forming a plurality of second through holes 220 in the third preset layer 210 of the second chip 200, and filling the plurality of second through holes 220 with conductive and thermally conductive materials to simultaneously form the third conductive portion 231 of the second conductive element 230 and the third thermally conductive portion 241 of the second thermal conductive element 240.

[0094] Specifically, such as Figure 5 As shown in (a), the simultaneous formation of the second conductive element 230 and the second heat-conducting element 240 in the second chip 200 may include:

[0095] Step S121: A patterned third anti-etching layer 20 is formed on the third preset layer 210 of the second chip 200 using photolithography.

[0096] Specifically, an anti-etching material can be deposited on the third preset layer 210. Then, an electron beam lithography or ion beam lithography followed by development can be used to form a patterned third anti-etching layer 20 on the third preset layer 210 of the second chip 200. Alternatively, the pattern of the third mask can be transferred to the anti-etching material using a photolithography process based on the third mask to form a patterned third anti-etching layer 20. In this way, the third conductive portion 231 of the second conductive element 230 and the third thermally conductive portion 242 of the second thermally conductive element 240 can be formed simultaneously based on the third mask, without the need to set different masks for the formation of the third conductive portion 231 and the third thermally conductive portion 241, reducing the fabrication difficulty and saving fabrication costs.

[0097] Furthermore, such as Figure 5 As shown in (b), the second conductive element 230 and the second heat-conducting element 240 in the second chip 200, which are formed synchronously, may further include:

[0098] In step S122, the third preset layer 210 is etched under the protection of the third anti-etching layer 20 to form a plurality of second vias 220.

[0099] In some embodiments, such as Figure 5 (b) Figures 10 to 12As shown, the third preset layer 210 can be, for example, the second substrate 260 of the second chip 200. Specifically, only the second substrate 260 can be etched to form the second via 220 formed on the second substrate 260. Alternatively, as... Figure 5 (b) Figure 12 As shown, the second substrate 260 and the second device layer 270 can be etched to form a second via 220 formed in the second substrate 260 and the second device layer 270.

[0100] In some embodiments, such as Figure 5 (b) Figures 10 to 12 As shown, the third preset layer 210 may be, for example, the second wiring layer 280 of the second chip 200. The second wiring layer 280 may be etched to form a second via 220 formed in the second wiring layer 280.

[0101] Furthermore, such as Figure 5 As shown in (c), the second conductive element 230 and the second heat-conducting element 240 in the second chip 200, which are formed synchronously, may further include:

[0102] In step S123, conductive and thermally conductive materials are filled into the plurality of second through holes 220 to simultaneously form the third conductive portion 231 of the second conductive element 230 and the third thermally conductive portion 241 of the second thermally conductive element 240.

[0103] In some embodiments, such as Figures 8 to 12 As shown, the second heat-conducting element 240 may include a fourth heat-conducting portion 242 extending in a plane parallel to or coinciding with the main plane of the second chip 200, or in other words, the second heat-conducting element 240 may include a fourth heat-conducting portion 242 extending in a plane perpendicular to the thickness direction, so that heat can be conducted through the fourth heat-conducting portion 242 in the plane perpendicular to the thickness direction. Correspondingly, the second conductive element 230, formed synchronously with the second heat-conducting element 240, may also include a fourth conductive portion 232 extending in a plane perpendicular to the thickness direction. In some embodiments, the fourth heat-conducting portion 242 may be in thermal communication with the third heat-conducting portion 241. Figures 10 to 12 As shown, the fourth heat-conducting portion 242 can be configured to be thermally connected to a plurality of third heat-conducting portions 241.

[0104] In some embodiments, such as Figures 8 to 9 As shown, the simultaneous formation of the second conductive element 230 and the second heat-conducting element 240 in the second chip 200 may include: forming one or more layers of second wiring on the fourth preset layer 250 of the second chip 200 to simultaneously form the fourth conductive portion 232 of the second conductive element 230 and the fourth heat-conducting portion 242 of the second heat-conducting element 240, wherein the one or more layers of second wiring may extend in a plane perpendicular to the thickness direction.

[0105] Specifically, in some embodiments, such as Figure 8 As shown in (a) to (c), forming one or more layers of second wiring on the fourth preset layer 250 of the second chip 200 using photolithography may include:

[0106] Step S124: Deposit a continuous thin film of conductive and thermally conductive material 60 on the fourth preset layer 250;

[0107] Step S125: A patterned fourth anti-etching layer 70 is formed on the conductive and thermally conductive material 60 using a photolithography process;

[0108] Step S126: Etch the portion of the conductive and thermally conductive material 60 that is not covered by the fourth anti-etching layer 70 to form one or more layers of second wiring.

[0109] In this configuration, a portion of one or more layers of the second wiring can be configured as a fourth conductive portion 232, and another portion can be configured as a fourth thermally conductive portion 242. Thus, the fourth conductive portion 232 and the fourth thermally conductive portion 242 can be formed simultaneously.

[0110] In one specific example, the fourth resist layer 70 may be formed solely of photoresist, or it may also be formed of a material such as deposited silicon nitride. In some embodiments, step S125 may include depositing a resist material on the conductive and thermally conductive material 70, and using a photolithography process based on the fourth mask to transfer the pattern of the fourth mask onto the resist material to form a patterned fourth resist layer 70. Considering that the remaining fourth resist layer 70 after etching to form one or more layers of second wiring in step S126 may affect subsequent processes, in some embodiments, the remaining fourth resist layer 70 may also be removed.

[0111] Alternatively, in other embodiments, such as Figure 9 As shown in (a) to (c), forming one or more layers of second wiring on the fourth preset layer 250 of the second chip 200 using photolithography may include:

[0112] Step S127: A patterned photoresist layer 80 is formed on the fourth preset layer 250 of the second chip 200 using photolithography.

[0113] Step S128: Deposit a continuous thin film of conductive and thermally conductive material 60;

[0114] Step S129: A stripping process is used to remove the photoresist layer 80 and the conductive and thermally conductive material 60 thereon, so that the remaining conductive and thermally conductive material 80 forms one or more layers of second wiring, so as to simultaneously form the fourth conductive portion 232 of the second conductive element 230 and the fourth thermally conductive portion 242 of the second thermally conductive element 240.

[0115] Step S127 may include depositing photoresist material on the fourth preset layer 250, and may use photolithography to transfer the pattern of the fourth mask onto the photoresist material based on the fourth mask to form a patterned photoresist layer 80.

[0116] In some embodiments using the fourth mask described above, it is not necessary to set different masks for the formation of the fourth conductive part 232 and the fourth thermally conductive part 242. The fourth conductive part 232 of the second conductive element 230 and the fourth thermally conductive part 242 of the second thermally conductive element 240 can be formed simultaneously through the fourth mask, which reduces the difficulty of device fabrication and saves fabrication costs.

[0117] In some embodiments, the fourth preset layer 250 may be, for example, the second substrate 260 of the second chip 200, such that one or more second wiring layers may be formed on the second substrate 260. Alternatively, in some embodiments, such as Figures 8 to 9 , Figures 10 to 12 As shown, the fourth preset layer 250 can be the second device layer 270 of the second chip 200, and the second device layer 270 can be located on the second substrate 260. Thus, one or more second wiring layers can be formed on the second device layer 270. The one or more second wiring layers can be at least a part of the second wiring layer 280 of the second chip 200.

[0118] like Figure 3 , Figures 10 to 12 As shown, the method for preparing the device disclosed herein may further include:

[0119] In step S130, the first chip 100 and the second chip 200 are joined together so that the first heat-conducting element 140 and the second heat-conducting element 240 are in thermal communication and form a heat-conducting channel.

[0120] In some embodiments, bonding the first chip 100 and the second chip 200 may include forming a bonding layer 410 on at least one of a first side of the first chip 100 and a second side of the second chip 200, wherein the first side of the first chip 100 and the second side of the second chip 200 may be face-to-face adjacent to each other, and the first thermal conductive element 140 of the first chip 100 and the second thermal conductive element 240 of the second chip 200 may be thermally connected via bonding pads 411 in the bonding layer 410. In a specific example, a hybrid bonding process may be used to bond the first chip 100 and the second chip 200 to improve the package integration of the first chip 100 and the second chip 200, and a corresponding bonding layer 410 may be formed between the first side of the first chip 100 and the second side of the second chip 200.

[0121] In some embodiments, in order to improve the bonding effect and make the connection between the first chip 100 and the second chip 200 more stable, thereby improving the performance of the prepared semiconductor device, bonding materials can be deposited on the first side of the first chip 100 and the second side of the second chip 200 respectively to form a bonding layer 410 to bond the first chip 100 and the second chip 200.

[0122] In some embodiments, the first conductive element 130 of the first chip 100 and the second conductive element 230 of the second chip 200 can be electrically connected via corresponding bonding pads in the bonding layer 410. The bonding pads 411 used to achieve the electrical connection between the first conductive element 130 and the second conductive element 230 and the bonding pads 411 used to achieve the thermal connection between the first thermal conductive element 140 and the second thermal conductive element 240 can be electrically isolated to avoid short circuits.

[0123] In some embodiments, such as Figures 10 to 12 As shown, a portion of the surface of one of the first chip 100 and the second chip 200 adjacent to the other is exposed to the environment to form an exposure portion 420. Alternatively, the area of ​​the first chip 100 may be unequal to the area of ​​the second chip 200, such that a portion of the larger of the first chip 100 and the second chip 200 forms an exposure portion 420 exposed to the environment relative to the smaller of the two. A heat-conducting element in the chip having the exposure portion 420 may be partially located within the exposure portion 420 to be partially exposed to the environment, allowing heat to be transferred from the exposure portion 420 to the environment via a heat-conducting channel. In a specific example, the area of ​​the first chip 100 may be larger than the area of ​​the second chip 200, and the first chip 100 may form an exposure portion 420 exposed to the environment relative to the second chip 200, wherein a first heat-conducting element 140 (e.g., a first heat-conducting portion 141 and / or a second heat-conducting portion 142) may be partially located within the exposure portion 420 to be partially exposed to the environment. Alternatively, in another specific example, the area of ​​the second chip 200 may be larger than the area of ​​the first chip 100. The second chip 200 may have an exposed portion 420 relative to the first chip 100, exposed to the environment. A second heat-conducting element 240 (e.g., a third heat-conducting portion 241 and / or a fourth heat-conducting portion 242) may be partially located in the exposed portion 420, so as to be partially exposed to the environment. In this way, heat in the first chip 100 or the second chip 200 can be transferred in a timely manner from the heat-conducting element of the exposed portion 420 to the outside of the first chip 100 and the second chip 200, which can effectively reduce the possibility of heat accumulation in the first chip 100 or the second chip 200, reduce the thermal resistance of the fabricated device, and improve the heat dissipation effect of the device.

[0124] To further improve the heat dissipation effect of semiconductor devices, in some embodiments, such as Figures 10 to 12As shown, a third heat-conducting element 430 may also be formed on the exposed surface of the exposed portion 420, wherein the third heat-conducting element 430 is in thermal communication with a heat-conducting element in the chip having the exposed portion 420. For example, when the first chip 100 has an exposed portion 420 exposed relative to the second chip 200, the third heat-conducting element 430 may be in thermal communication with the first heat-conducting element 140; or, when the second chip 200 has an exposed portion 420 exposed relative to the first chip 100, the third heat-conducting element 430 may be in thermal communication with the second heat-conducting element 240.

[0125] In some cases, the heat distribution within the individual chips of a semiconductor device is often uneven during operation; for example, regions closer to the device's location within the chip typically generate more heat. Figures 10 to 12 The hot spot area 440 is shown. To maximize the heat conduction of the heat in the hot spot area 440 via the heat conduction channel, in some embodiments, the location of the hot spot area 440 in the first chip 100 and / or the second chip 200 can be determined through thermal simulation. Based on the location of the hot spot area 440, the locations of the first heat conductor 140 and the second heat conductor 240 can also be determined through thermal simulation. This ensures that the heat conduction channel formed by the thermal connection of the first heat conductor 140 and the second heat conductor 240 can effectively conduct heat from the hot spot area 440, reducing heat accumulation in the hot spot area 440. Thus, by determining the location of the hot spot area 440 through thermal simulation and using this location to determine the position of the heat conductor within the chip, a heat conduction channel capable of transferring heat from the hot spot area 440 is constructed, improving heat dissipation efficiency.

[0126] In some embodiments, the hot spot area 440 of the chip can be evenly distributed by making reasonable arrangements of the first chip 100 and / or the second chip 200, for example, avoiding the concentration of working devices in the same area, thereby reducing the thermal coupling of the chip and lowering the local maximum temperature on the chip, and thus making the temperature distribution of the chip more uniform.

[0127] like Figures 10 to 12As shown, a third heat-conducting element 430 can be arranged at the location of the heat-conducting channel exposed to the environment to allow for rapid heat dissipation after heat transfer. Considering that the arrangement of the third heat-conducting element 430 affects the construction of the heat-conducting channel, for example, the layout of the first and second chips is usually pre-designed, and the available locations for arranging the third heat-conducting element 430 are limited, it is necessary to comprehensively consider the available locations of the third heat-conducting element 430 to construct a heat-conducting channel for transferring heat from the hot spot area. Specifically, in some embodiments, the location of the third heat-conducting element 430 can be determined, and the locations of the first heat-conducting element 140 and the second heat-conducting element 240 can be determined based on the location of the third heat-conducting element 430 and the location of the hot spot area to construct a heat-conducting channel with an optimized path, thereby further improving the heat dissipation efficiency of the device.

[0128] In a specific example, such as Figure 13 As shown, the method for preparing the device disclosed herein may further include:

[0129] Step S210: Obtain the logic design and layout of the first chip 100 and the second chip 200;

[0130] Step S220: Determine the location of the hot spot area inside at least one of the first chip 100 and the second chip 200 through thermal simulation;

[0131] Step S230: Determine the position where the third heat-conducting component 430 can be arranged based on the layout of the first chip 100 and the second chip 200.

[0132] Step S240: Design a heat conduction channel based on the location of the hot spot area and the location where the third heat conduction component 430 can be arranged;

[0133] Step S250: Insert the designed heat conduction channel into the layout of the first chip 100 and the second chip 200;

[0134] In step S260, thermal simulation is used to determine whether the first chip 100 and the second chip 200 meet the preset thermal simulation requirements. If they do, step S270 is executed to carry out the subsequent device fabrication according to the designed heat conduction channel. Otherwise, the process returns to step S240 and the heat conduction channel is redesigned.

[0135] In this way, corresponding heat conduction channels can be flexibly constructed through thermal simulation, and heat conduction channels can be effectively constructed under different chip stacking structures to improve the heat dissipation effect of the device.

[0136] In a specific example, thermal simulation is used to determine whether the first chip 100 and the second chip 200 meet the preset thermal simulation requirements. For example, it can be determined whether the chip temperature is less than or equal to the preset temperature.

[0137] In some embodiments, step S240 may include determining the optimal placement position closest to the hot spot region among the possible placement positions of the third heat conductor 430 based on the location of the hot spot region, determining an optimal path based on the location of the hot spot region and the optimal placement position of the third heat conductor 430, and designing a heat conduction channel based on the optimal path.

[0138] In a specific example, a thermal conductive channel connecting the hot spot area and the third thermal conductive element 430 can be constructed by selecting appropriate metal components from the Process Design Kit (PDK). The optimized path, for example, can be the shortest path connecting the hot spot area and the third thermal conductive element 430 that can be constructed using the metal components in the PDK without affecting the original chip layout. By determining the optimized path to construct the corresponding thermal conductive channel, the efficiency of heat conduction from the hot spot area of ​​the chip to the outside is significantly improved, allowing heat to be released to the outside in a shorter time, thereby keeping the chip operating at a lower operating temperature and avoiding performance degradation and failure caused by overheating. In some embodiments, appropriate metal components can be pre-selected to form a preset thermal conductive channel, and thermal simulation can be used to predict the heat transfer situation inside the chip under the preset thermal conductive channel. Based on the heat transfer situation, the position and interconnection of the metal components can be optimized to ensure optimal heat dissipation.

[0139] Metal components may include, for example, at least one of through-silicon vias (TSVs), metal vias, metal wiring, thermal pads, bonding pads, package balls, and metal bumps. Metal components typically have high thermal conductivity. By creating thermal channels using metal components, heat inside the chip can be quickly conducted to the outside, thereby effectively reducing the temperature of hot spots, reducing the chip's thermal resistance, and improving heat dissipation capabilities.

[0140] Thus, based on the results of thermal simulation and in conjunction with the device fabrication methods described in some of the above embodiments, corresponding semiconductor devices (such as...) can be fabricated. Figures 10 to 12 The semiconductor device 300 shown.

[0141] In some embodiments, at least a portion of the selected metal components can be configured to form as follows: Figures 10 to 12 The first heat-conducting element 140 and / or the second heat-conducting element 240 shown.

[0142] According to another aspect of this disclosure, a semiconductor device 300 is also provided, such as Figures 10 to 12 As shown, the semiconductor device 300 may include a first chip 100 and a second chip 200, wherein the second chip 200 may be attached to one side of the first chip 100.

[0143] The first chip 100 may include a patterned first functional layer, wherein a first portion of the patterned first functional layer may be configured as a first conductive element, and a second portion of the patterned first functional layer may be configured as a first thermal conductive element 140, the first conductive element being electrically isolated from the first thermal conductive element 140. For the sake of simplicity and clarity, the thermal conductive path... Figures 10 to 12 The first conductive element in the first chip 100 and the second conductive element in the second chip 200 are not shown.

[0144] In some embodiments, the first portion and the second portion of the patterned first functional layer may be formed simultaneously, or the first thermal conductive element 140 and the first electrical conductive element may be formed simultaneously, so that the first thermal conductive element 140 can be formed simultaneously based on the steps of the existing first chip 100 fabrication process without introducing additional process steps.

[0145] In some embodiments, the first heat-conducting element 140 may include a first heat-conducting portion 141, wherein the first heat-conducting portion 141 may extend in the thickness direction to conduct heat in the thickness direction. Alternatively, in some embodiments, the first heat-conducting element 140 may include a second heat-conducting portion 142 extending in a plane perpendicular to the thickness direction to conduct heat in the plane perpendicular to the thickness direction.

[0146] like Figures 10 to 12 As shown, the first functional layer may include a first substrate 160, a first device layer 170, and a first wiring layer 180 stacked sequentially in the thickness direction. In some embodiments, a first thermally conductive portion 141 may fill within a first via 120, and the first via 120 may be formed in at least one of the first substrate 160, the first device layer 170, and the first wiring layer 180. Figure 10 and Figure 12 In the example shown, the first via 120 can be formed in the first substrate 160, and a vertical silicon via located in the first substrate 160 can be formed, for example, by filling it with a suitable conductive and thermally conductive material. Figure 11In the example shown, the first via 120 can be formed in the first substrate 160 and the first device layer 170. By filling with a corresponding conductive and thermally conductive material, a vertical silicon via can be formed, for example, in the first substrate 160 and the first device layer 170. Furthermore, the first via 120 can also be formed in the first wiring layer 180. By filling with a corresponding conductive and thermally conductive material, a metal via can be formed, for example, in the first wiring layer 180. In a specific example, the location of the first via 120 in the first chip 100 can be determined in advance, for example, through thermal simulation, to determine the location of the first thermally conductive portion 141 in the first chip 100. In some embodiments, the first conductive portion of the first conductive element can also be filled within the corresponding first via, wherein the first conductive portion and the first thermally conductive portion 141 can be electrically isolated.

[0147] In some embodiments, the first wiring layer 180 may include one or more first wirings extending in a plane perpendicular to the thickness direction, wherein at least a portion of the one or more first wirings may be configured to serve as a second thermally conductive portion 142 of the first thermally conductive element 140. For example, a portion of the one or more first wirings may be configured to serve as the second thermally conductive portion 142 of the first thermally conductive element 140, and another portion may be configured to serve as a second conductive portion of the second conductive element, wherein the second thermally conductive portion 142 may be electrically isolated from the second conductive portion. Alternatively, the first wiring layer 180 may also include one or more conductive wirings extending in a plane perpendicular to the thickness direction to serve as the second conductive portion of the second conductive element, wherein the conductive wirings may be electrically isolated from the first wirings.

[0148] The second chip 200 may include a patterned second functional layer, wherein a first portion of the patterned second functional layer may be configured as a second conductive element, and a second portion of the patterned second functional layer may be configured as a second thermal conductive element 240, wherein the second conductive element may be electrically isolated from the second thermal conductive element 240. The second thermal conductive element 240 of the second chip 200 may be thermally connected to the first thermal conductive element 140 of the first chip 100 to form a thermally conductive channel, thereby facilitating heat conduction between the first chip 100 and the second chip 200 and reducing heat accumulation.

[0149] In some embodiments, the first and second portions of the patterned second functional layer may be formed simultaneously, or the second thermal conductive element 240 and the second conductive element may be formed simultaneously, so that the second thermal conductive element 240 can be formed simultaneously based on the steps of the existing second chip 200 fabrication process without introducing additional process steps.

[0150] In some embodiments, the second heat-conducting element 240 may include a third heat-conducting portion 241, wherein the third heat-conducting portion 241 may extend in the thickness direction to conduct heat in the thickness direction. Alternatively, in some embodiments, the second heat-conducting element 240 may include a fourth heat-conducting portion 242 extending in a plane perpendicular to the thickness direction to conduct heat in the plane perpendicular to the thickness direction.

[0151] like Figures 10 to 12 As shown, the second functional layer may include a second substrate 260, a second device layer 270, and a second wiring layer 280 stacked sequentially in the thickness direction. Wherein, as... Figure 10 and Figure 11 As shown, the second wiring layer 280 can be disposed face-to-face with the first substrate 160, or, as... Figure 12 As shown, the second substrate 260 can be disposed face-to-face with the first substrate 160.

[0152] In some embodiments, the third thermally conductive portion 241 may fill within the second via 220, which may be formed in at least one of the second substrate 260, the second device layer 270, and the second wiring layer 280. Figure 10 and Figure 11 In the example shown, the second via 220 can be formed in the second wiring layer 280, and a metal via located in the second wiring layer 280 can be formed, for example, by filling it with a suitable conductive and thermally conductive material. Figure 12 In the example shown, the second via 220 can be formed in the second substrate 260 and the second device layer 270, and a vertical silicon via can be formed, for example, in the second substrate 260 and the second device layer 270 by filling it with a corresponding conductive and thermally conductive material. In another example, the second via 220 can also be formed in the second substrate 260, and a vertical silicon via can be formed, for example, in the second substrate 260 by filling it with a corresponding conductive and thermally conductive material. In a specific example, the location of the second via 220 in the second chip 200 can be determined in advance by, for example, thermal simulation, to determine the location of the third thermally conductive portion 241 in the second chip 200. In some embodiments, the third conductive portion of the second conductive element can also be filled in the corresponding second via, wherein the third conductive portion and the third thermally conductive portion can be electrically isolated.

[0153] In some embodiments, the second wiring layer 280 may include one or more layers of second wiring extending in a plane perpendicular to the thickness direction, wherein at least a portion of the one or more layers of second wiring may be configured as a fourth thermally conductive portion 242 of the second thermally conductive element 240. For example, a portion of the one or more layers of second wiring may be configured as a fourth thermally conductive portion 242 of the second thermally conductive element 240, and another portion may be configured as a fourth conductive portion of the second conductive element, wherein the fourth thermally conductive portion 242 may be electrically isolated from the fourth conductive portion. Alternatively, the second wiring layer 280 may also include one or more layers of conductive wiring extending in a plane perpendicular to the thickness direction to serve as a fourth conductive portion of the second conductive element, wherein the conductive wiring may be electrically isolated from the second wiring.

[0154] To improve the heat dissipation of the device, the heat conduction channel can be partially exposed to the environment. For example, a portion of the first heat conduction element 140 and / or the second heat conduction element 240 can be exposed to the environment to transfer heat from the first chip 100 and the second chip 200 to the environment via the heat conduction channel. In some embodiments, one end of the heat conduction channel can be located on the surface of the first chip 100 or the second chip 200 exposed to the environment, so that heat can be transferred from the surface exposed to the environment via the heat conduction channel. For example, one end of the first heat conduction element 140 can be located on the surface of the first chip 100 exposed to the environment, and the other end can be used to thermally communicate with the second heat conduction element 240, so that heat in the first chip 100 and the second chip 200 can be transferred from the exposed surface of the first chip 100 via the heat conduction channel. Alternatively, one end of the second heat conduction element 240 can be located on the surface of the second chip 200 exposed to the environment, and the other end can be used to thermally communicate with the first heat conduction element 140, so that heat in the first chip 100 and the second chip 200 can be transferred from the exposed surface of the second chip 200 via the heat conduction channel. In some embodiments, a corresponding heat dissipation device or heat-conducting component may be arranged at the location where the heat conduction channel is exposed to the environment, so as to further promote the heat in the heat conduction channel to be transferred to the environment outside the chip, thereby further improving the heat dissipation effect.

[0155] In order to allow the heat in the first chip 100 and the second chip 200 to be dissipated in a timely manner outside the first chip 100 and the second chip 200, in some embodiments, such as Figures 10 to 12 As shown, one of the first chip 100 and the second chip 200 may be exposed to the environment relative to the other on a surface adjacent to the other, forming an exposed portion 420. Alternatively, the areas of the first chip 100 and the second chip 200 may be unequal, such that the chip with the larger area is exposed to the environment relative to the chip with the smaller area, forming the exposed portion 420. A heat-conducting element in the chip having the exposed portion 420 may be partially located within the exposed portion 420, allowing heat to be transferred away from the exposed portion 420 via a heat-conducting channel.

[0156] In some embodiments, the area of ​​the first chip 100 may be larger than the area of ​​the second chip 200. The first chip 100 may have an exposed portion 420 that is exposed relative to the second chip 200. For example, at least one of the first substrate 160, the first device layer 170, and the first wiring layer 180 may have an exposed portion 420. The first thermally conductive element 140 (e.g., the first thermally conductive portion 141 and / or the second thermally conductive portion 142) may be partially located in the exposed portion 420 to be partially exposed to the environment. Alternatively, in some embodiments, such as... Figures 10 to 12 As shown, the second chip 200 may have an exposed portion 420 relative to the first chip 100. For example, at least one of the second substrate 260, the second device layer 270, and the second wiring layer 280 may have an exposed portion 420. A second thermally conductive element 240 (e.g., a third thermally conductive portion 241 and / or a fourth thermally conductive portion 242) may be partially located in the exposed portion 420 to be partially exposed to the environment.

[0157] In this way, the heat in the first chip 100 or the second chip 200 can be transferred from the heat-conducting element of the exposed part 420 to the outside of the first chip 100 and the second chip 200 in a timely manner, which can effectively reduce the possibility of heat accumulation in the first chip 100 or the second chip 200, reduce the thermal resistance of the device and improve the heat dissipation effect of the device.

[0158] To further improve the heat dissipation effect of the semiconductor device 300, in some embodiments, the semiconductor device 300 of this disclosure may further include a third heat-conducting element 430 located on the exposed surface of the exposed portion 420, wherein the third heat-conducting element 430 can be thermally connected to the heat-conducting element in the chip having the exposed portion 420. The exposed portion 420 provides more arrangement space for the third heat-conducting element 430, thereby allowing for more flexible construction of heat dissipation channels with the third heat-conducting element 430, improving process flexibility. The third heat-conducting element 430 may, for example, include thermal pads and heat dissipation devices connected to the thermal pads to dissipate heat in the heat conduction channels into the environment, thereby further improving the heat dissipation effect.

[0159] In some implementations, the semiconductor device 300 may further include a bonding layer 410, wherein the bonding layer 410 is located between the first chip 100 and the second chip 200 and can be configured to bond the first chip 100 and the second chip 200 to improve the package integration of the semiconductor device 300, wherein the first thermal conductive element 140 and the second thermal conductive element 240 can be thermally connected via bonding pads 411 in the bonding layer 410.

[0160] In some embodiments, the heat conduction channel formed by the first heat-conducting element 140 and the second heat-conducting element 240 can be configured to transfer heat from the hot spot region 440 in the first chip 100 and / or the second chip 200, wherein the hot spot region 440 can be determined according to the layout of the first chip 100 and the second chip 200. Figures 10 to 12 As shown, when the hot spot region 440 is located within the first chip 100, one end of the first heat-conducting element 140 can be configured to be close to the hot spot region 440, and the other end of the first heat-conducting element 140 can be configured to be in thermal communication with the second heat-conducting element 240. This allows heat from the hot spot region 440 of the first chip 100 to be conducted through the first heat-conducting element 140 and the second heat-conducting element 240, reducing heat accumulation in the hot spot region 440 of the first chip 100 and effectively improving the device's heat dissipation capacity. Similarly, when the hot spot region 440 is located within the second chip 200, one end of the second heat-conducting element 240 can be configured to be close to the hot spot region 440, and the other end of the second heat-conducting element 240 can be configured to be in thermal communication with the first heat-conducting element 140. This allows heat from the hot spot region 440 of the second chip 200 to be conducted through the first heat-conducting element 140 and the second heat-conducting element 240, reducing heat accumulation in the hot spot region 440 of the second chip 200 and effectively improving the device's heat dissipation capacity.

[0161] exist Figures 10 to 12 In the example shown, the heat at the hot spot area 440 of the first chip 100 can be conducted to the bonding layer 410 via the first thermal conductive element 140, then to the second thermal conductive element 240 via the bonding pads 411 of the bonding layer 410, and then to the third thermal conductive element 430 via the second thermal conductive element 240, thereby conducting the heat at the hot spot area 440 to the external environment and realizing heat exchange.

[0162] Furthermore, the semiconductor device 300 disclosed herein can also be fabricated by the device fabrication method described above.

[0163] In the technical solution disclosed herein, corresponding heat-conducting components are formed simultaneously with the conductive components of the chip to construct heat conduction channels. This eliminates the need for additional process steps to separately form heat-conducting components, saving on device fabrication costs while effectively reducing heat accumulation, decreasing thermal resistance, and improving chip heat dissipation. Furthermore, it effectively lowers the chip's operating temperature, thus effectively solving the chip overheating problem, improving chip performance stability, and extending chip lifespan. According to some embodiments of this disclosure, no additional heat dissipation equipment (such as heat sinks, fans, etc.) is required; heat conduction channels can be constructed based on the internal metal components of the chip. This allows the chip to maintain high heat dissipation efficiency while retaining a miniaturized and highly integrated design, meeting the stringent size and weight requirements of modern electronic devices.

[0164] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “high,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, enabling embodiments of this disclosure described herein to operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0165] In the specification and claims, when an element is described as being "on top of," "attached to," "connected to," "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0166] As used herein, the term “exemplary” means “serving as an example, instance, or illustration” and not as a “model” to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, this disclosure is not limited to any theory expressed or implied as given in the field of art, background art, summary of invention, or detailed description.

[0167] As used herein, the term "substantially" means any minor variation resulting from design or manufacturing defects, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in the actual implementation.

[0168] Furthermore, terms such as “first,” “second,” etc., may be used in this document for reference purposes only and are therefore not intended to be restrictive. For example, unless the context clearly indicates otherwise, the words “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence.

[0169] It should also be understood that when the term “including / contains” is used herein, it indicates the presence of the indicated feature, whole, step, operation, unit and / or component, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units and / or components and / or combinations thereof.

[0170] In this disclosure, the term “provide” is used broadly to cover all ways of obtaining an object, and therefore “provide an object” includes, but is not limited to, “purchasing,” “preparing / manufacturing,” “arranging / setting up,” “installing / assembling,” and / or “ordering” an object.

[0171] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0172] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0173] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A method of device fabrication, comprising: The device manufacturing method comprises: synchronously forming a first conductive member and a first heat conductive member in a first chip, wherein the first conductive member and the first heat conductive member are electrically isolated; synchronously forming a second conductive member and a second heat conductive member in a second chip, wherein the second conductive member and the second heat conductive member are electrically isolated; and bonding the first chip and the second chip to make the first heat conductive member and the second heat conductive member in thermal communication and form a heat conductive channel, wherein the synchronously forming the first conductive member and the first heat conductive member in the first chip comprises: forming a plurality of first through holes in a first preset layer of the first chip, and filling the plurality of first through holes with a conductive and heat conductive material to synchronously form a first conductive part of the first conductive member and a first heat conductive part of the first heat conductive member; and / or forming one or more layers of first wiring on a second preset layer of the first chip to synchronously form a second conductive part of the first conductive member and a second heat conductive part of the first heat conductive member, wherein the one or more layers of first wiring extend in a plane perpendicular to a thickness direction, wherein the synchronously forming the second conductive member and the second heat conductive member in the second chip comprises: forming a plurality of second through holes in a third preset layer of the second chip, and filling the plurality of second through holes with a conductive and heat conductive material to synchronously form a third conductive part of the second conductive member and a third heat conductive part of the second heat conductive member; and / or forming one or more layers of second wiring on a fourth preset layer of the second chip to synchronously form a fourth conductive part of the second conductive member and a fourth heat conductive part of the second heat conductive member, wherein the one or more layers of second wiring extend in a plane perpendicular to a thickness direction.

2. The method of claim 1, wherein the device is prepared by, The bonding the first chip and the second chip comprises: forming a bonding layer on a first side of the first chip and / or a second side of the second chip, and bonding the first chip and the second chip through the bonding layer, wherein the first side of the first chip is adjacent to the second side of the second chip, and the first heat conductive member and the second heat conductive member are in thermal communication via a bonding pad in the bonding layer.

3. The method of claim 1, wherein the device is prepared by, A part of a surface of one of the first chip and the second chip adjacent to the other is exposed to the environment to form an exposed part, wherein a heat conductive member in the chip having the exposed part is partially located in the exposed part to be partially exposed to the environment.

4. The method of claim 3, wherein the device is prepared by, The device manufacturing method further comprises: forming a third heat conductive member on an exposed surface of the exposed part, wherein the third heat conductive member is in thermal communication with the heat conductive member in the chip having the exposed part.

5. The method of claim 1, wherein the device is prepared by, The device manufacturing method further comprises: determining a location of a hot spot region in the first chip and / or the second chip through thermal simulation, and determining a location of the first heat conductive member and the second heat conductive member based on the location of the hot spot region through thermal simulation, so that the heat conductive channel conducts heat of the hot spot region.

6. A semiconductor device, characterized by comprising: The semiconductor device comprises: The first chip includes a patterned first functional layer, a first portion of the patterned first functional layer is configured to serve as a first electrically conductive member, a second portion of the patterned first functional layer is configured to serve as a first thermally conductive member, wherein the first electrically conductive member is electrically isolated from the first thermally conductive member; The second chip is bonded on one side of the first chip, the second chip includes a patterned second functional layer, a first portion of the patterned second functional layer is configured to serve as a second electrically conductive member, a second portion of the patterned second functional layer is configured to serve as a second thermally conductive member, wherein the second electrically conductive member is electrically isolated from the second thermally conductive member, The first thermally conductive member is in thermal communication with the second thermally conductive member and forms a thermally conductive channel, the first thermally conductive member is synchronously formed with the first electrically conductive member, and the second thermally conductive member is synchronously formed with the second electrically conductive member.

7. The semiconductor device according to claim 6, wherein The first functional layer includes a first substrate, a first device layer and a first wiring layer stacked in a thickness direction, and the second functional layer includes a second substrate, a second device layer and a second wiring layer stacked in the thickness direction, The second wiring layer is arranged face-to-face with the first substrate, or the second substrate is arranged face-to-face with the first substrate.

8. The semiconductor device according to claim 7, wherein The first thermally conductive member includes a first thermally conductive portion and / or a second thermally conductive portion, and the second thermally conductive member includes a third thermally conductive portion and / or a fourth thermally conductive portion, The first thermally conductive portion is filled in a first via, and the first via is formed in at least one of the first substrate, the first device layer and the first wiring layer, The first wiring layer includes one or more layers of first wirings extending in a plane perpendicular to the thickness direction, and at least part of the one or more layers of first wirings is configured to serve as the second thermally conductive portion, The third thermally conductive portion is filled in a second via, and the second via is formed in at least one of the second substrate, the second device layer and the second wiring layer, The second wiring layer includes one or more layers of second wirings extending in a plane perpendicular to the thickness direction, and at least part of the one or more layers of second wirings is configured to serve as the fourth thermally conductive portion.

9. The semiconductor device according to claim 6, wherein A portion of a surface of one of the first chip and the second chip adjacent to the other is exposed to the environment to form an exposed portion, and a thermally conductive member in the chip having the exposed portion is partially located in the exposed portion to be partially exposed to the environment.

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