Method of packaging semiconductor die

Abstract

A method of packaging a semiconductor die is provided. The method includes a first step of providing a substrate and a plurality of semiconductor dies spaced apart on the substrate, the substrate having exposed surfaces between the dies. Thereafter, a film is applied to the substrate to cover the plurality of semiconductor dies and the exposed substrate surface with a film layer, where each die includes a top surface and at least one side surface, and where the film layer extends across the top surface of the die and along the side surface. Subsequently, the film is removed from the top surface of the die while the film remains intact on the side surfaces of the die. Thereafter, a plasma etches the top surface of the die, and removes the film from the side surfaces of the die. The semiconductor die is thinned for a variety of end applications.

Description

Technical Field

[0001] The present invention relates to methods for encapsulating semiconductor die (e.g., preparing die assemblies for encapsulation). The present invention also relates to methods for thinning semiconductor die, such as after a die-to-wafer bonding process. The present invention also relates to semiconductor die assemblies (e.g., hybrid bonded semiconductor die assemblies), and plasma etching systems for encapsulating semiconductor die (e.g., preparing semiconductor die for encapsulation and / or performing semiconductor die thinning). Background Art

[0002] Thermal compression, fusion, and hybrid bonding techniques are used in the fabrication of CMOS image sensors and advanced packaging applications, such as for preparing semiconductor die for 3D stacking. In hybrid bonding applications, different types or the same type of semiconductor die from different wafers are attached (i.e., bonded) to a substrate (e.g., a target wafer) through dielectric-to-dielectric and metal-to-metal connections, such that multiple semiconductor die can be assembled together in a single package.

[0003] Die-to-wafer bonding is a preferred method for hybrid bonding because it enables a relatively high placement accuracy of semiconductor die compared to wafer-to-wafer bonding and other similar techniques. It is also a process that enables a good level of control over the yield of the bonded wafers because only known good die are selected for bonding. Before transferring the die as individual die supported on a carrier tape or a carrier wafer in a ring or a frame to a target wafer that already contains die (which can be of the same or different types), the die are typically separated by plasma scribing the wafer through a mask.

[0004] The limitations of available pick-and-place tools impose restrictions on the size and shape of the semiconductor die to be transferred. Specifically, the die to be transferred must have sufficient thickness (i.e., height above the substrate plane) to be grasped and moved. Typically, thinner semiconductor die packages are specified for the final product, and thus excess semiconductor die material must be removed to thin the die (i.e., reduce the thickness) before etching.

[0005] One solution to the problem is to create a reconstructed wafer where the gaps between individual die are filled with a thick dielectric film. Although current plasma enhanced chemical vapor deposition (PECVD) SiO2 films can fill gaps up to about 40 μm deep, at least an equal amount of SiO2 will also cover the surface of the die. To provide a smooth horizontal top surface of the die, the SiO2 and silicon need to be ground and then chemically mechanically polished. Typically, the thickness of the die must be significantly reduced, and thus the process uses a large amount of dielectric filling material and is extremely costly.

[0006] A method for thinning a semiconductor die, for example, during or after a die-to-wafer bonding process, is needed that preserves the integrity of the semiconductor die and is cost-effective in the process. Summary of the Invention

[0007] In a first aspect of the present invention, a method of encapsulating a semiconductor die is provided. The method includes the steps of providing a substrate and a plurality of semiconductor dies spaced apart on the substrate, the substrate having an exposed surface between the dies. The method further includes the step of applying a film to the substrate to cover the plurality of semiconductor dies and the exposed substrate surface with a film layer, wherein each die includes a top surface and at least one side surface, and wherein the film layer extends across the top surface of the die and along the side surfaces. The method further includes the step of removing the film from the top surface of the die while keeping the film intact on the side surfaces of the die. The method further includes the step of plasma etching the top surface of the die. The method includes the additional step of removing the film from the side surfaces of the die.

[0008] The method advantageously provides a method of encapsulating a semiconductor die in which the die is thinned with high precision. For example, the claimed method can have a particular use after a die-to-wafer bonding process on a target wafer where the die to be placed on the target wafer is thick. Compared to some prior art methods, the claimed method avoids using excessive materials, such as the materials required for depositing a dielectric layer for polishing. Under the claimed method, the etching of the semiconductor die is almost completely anisotropic in the vertical direction due to the use of a film layer that provides selective passivation of the die sidewalls during the main etching. The high integrity of the semiconductor die sidewalls is maintained. In the application of the claimed method, an extremely smooth (i.e., having a minimum surface roughness of ∼1 nm) horizontal semiconductor top surface is provided. Additionally, the method enables the silicon etching thinning step to be performed at a relatively high etching rate of about 1 - 10 μm / minute, which is relatively fast compared to methods such as chemical mechanical polishing.

[0009] The claimed encapsulation method can include methods of 3D integration or 2.5D integration. The encapsulation method can include a method of thinning semiconductor dies in a vertical die stack. The method can be repeated for each die added to the stack. Alternatively, the encapsulation method can include a method of thinning semiconductor dies in a horizontal die stack.

[0010] The shape of a semiconductor die can generally be substantially cuboid. The side surfaces of the semiconductor die can be substantially perpendicular to the central horizontal plane of the substrate. The top surface of the die can be substantially horizontal, i.e., parallel to the central horizontal plane of the substrate. The exposed surface can be substantially horizontal, i.e., parallel to the central horizontal plane of the substrate.

[0011] The film can include a polymer. Alternatively, the film can include another material that has a high etch selectivity to the thinning etch process, in other words, the etch rate of the other material is much slower than that of Si and it can be removed without etching Si.

[0012] The semiconductor die can include an unmasked silicon die.

[0013] The film layer can directly cover the top surface of the die without any intermediate layer.

[0014] The film can be applied by plasma enhanced chemical vapor deposition.

[0015] The plasma deposition process can produce conformal deposition over the die and the substrate.

[0016] The film can be applied using a plasma formed from a fluorocarbon gas.

[0017] Fluorocarbon gas may be particularly suitable as a process gas for plasma deposition of polymers because it forms a large amount of fluorine and carbon and can be easily polymerized.

[0018] The fluorocarbon gas can include C4F8. Alternatively, the fluorocarbon gas can include C5F8 or C4F6 or a mixture of the above gases.

[0019] The film can be applied conformally, in other words, having substantially the same thickness everywhere. The film can be applied at least in the vertical and lateral directions with respect to the central horizontal plane of the substrate so as to cover the top surface and the side surfaces of the die.

[0020] The method can further include removing the film from the exposed substrate surface while removing the film from the top surface of the die.

[0021] The film can be removed from the top surface of the die by anisotropic plasma etching.

[0022] "Anisotropic" etching should be understood to mean etching in a direction perpendicular to the exposed surface of the substrate. The film can be removed from the top surface of the die by performing anisotropic plasma etching in a direction perpendicular to the central horizontal plane of the substrate. Thus, the film is removed only where the plasma ions contact the semiconductor die assembly in the vertical direction. A high level of directionality ensures that the film remains on the side surfaces of the die while etching from the top surface.

[0023] A high level of etching directionality can be provided by creating a charge bias (i.e., a potential difference) between (i) the semiconductor die assembly and its surrounding components and (ii) the plasma. This charge bias can be created by supplying RF power to at least one support component (e.g., an electrostatic chuck) of the semiconductor die assembly. The alternating current can cause a negative electric potential to be established on the semiconductor die assembly and the support component, which then attracts positive ions towards the semiconductor die assembly. To create a suitable charge bias, it may be necessary to supply more than 200 W (e.g., more than 300 W) of RF power (i.e., "RF bias power").

[0024] A plasma formed from SF6 gas can be used to remove the film from the top surface of the die.

[0025] SF6 gas can be particularly suitable as a process gas for plasma etching of polymer films because it can be selectively used to etch both silicon and polymer films. As described above, using the RF bias power supplied to one or more components (e.g., an electrostatic chuck) supporting the semiconductor die assembly can create a high level of directionality for plasma etching of polymer films. Additionally, using a relatively low pressure can minimize ion collisions to achieve almost vertical ion bombardment of the semiconductor die assembly.

[0026] Alternatively, the plasma can be formed from another gas (e.g., NF3 or CF4 gas).

[0027] The film can be removed from the side surfaces of the die by isotropic plasma ashing. "Isotropic" plasma ashing will be understood to mean not completely directional. Plasma ashing without any specific directionality can be a particularly effective way to remove all remaining polymers from the semiconductor die assembly.

[0028] An oxygen-based ashing chemical (such as O2 or O2 / Ar) can be used to remove the film from the side surfaces of the die.

[0029] Oxygen-containing gases are particularly suitable for removing polymer films from the side surfaces of the die because CO and CO2 can be formed.

[0030] A film layer can be applied over substantially the entire substrate.

[0031] A film layer can be applied such that there are no uncovered portions of the substrate or die.

[0032] The film layer can extend along each side surface of the die.

[0033] Thus, the film can remain intact on each side surface of the die while etching the top surface of the die.

[0034] The maximum thickness of the film layer can be less than 5 μm.

[0035] The maximum thickness of the film layer can be less than 2 μm, such as less than 1 μm.

[0036] The film layer can have a substantially constant average thickness, where the maximum thickness variation compared to the average thickness is less than 20%.

[0037] The maximum thickness variation can be less than 10%, such as less than 5%.

[0038] The film can be applied to the substrate in a single deposition step.

[0039] The top surface of the die can be etched until the thickness between the exposed surface of the substrate and the top surface of each die is less than a user-defined threshold thickness.

[0040] The threshold thickness can be 20 μm.

[0041] The threshold thickness can be 10 μm.

[0042] The threshold thickness can be application-specific and can be preset by the user using a controller prior to performing the method.

[0043] A cyclic etch process similar to the process described in the applicant's patent US9842772 can be used to etch the top surface of the die. The cyclic process can help maintain a smooth surface and also provide high selectivity to SiO2 when exposed through vias in silicon. Alternatively, if protection of buried SiO2 features is not required, for example, a single-step process can be used to etch the top surface of the die.

[0044] A plasma formed from SF6 gas can be used to etch the top surface of the die.

[0045] The plurality of semiconductor dies can include at least one die of a first type and at least one die of a second type, and the method can include a previous step of attaching at least one of the first type of die to the substrate to provide the plurality of semiconductor dies spaced apart on the substrate, where at least one of the second type of die is pre-bonded to the substrate. Alternatively, the dies can be of the same type and bonded to a target substrate that has been selected and removed from a different wafer.

[0046] The plurality of semiconductor die can include at least one die transferred from a first wafer to a substrate and a plurality of additional die supported on the substrate, and the method can include a previous step of attaching the at least one die to the substrate, wherein the plurality of additional die are pre-bonded on the substrate. The die can be attached in a stacked form. The die can be stacked in a suitable configuration, such as in a vertical stack or a horizontal stack. A plurality of dynamic random access memory (DRAM) die can be stacked.

[0047] The method can include a step of performing die-to-wafer bonding to provide a substrate and the plurality of semiconductor die spaced apart on the substrate.

[0048] The substrate can include a semiconductor material.

[0049] The substrate can include a dielectric material.

[0050] The substrate can include a tape or be supported on a tape.

[0051] The method can further include a subsequent step of applying a packaging material to the substrate to encapsulate the substrate and the die.

[0052] The plurality of semiconductor die can be included in a top layer of a plurality of vertical die stacks. Alternatively, the plurality of semiconductor die can be included in a plurality of horizontal die stacks, wherein the film layer extends across the top surface of the die and along a plurality of outward-facing side surfaces (i.e., exposed outer surfaces) of the die.

[0053] In a second aspect, a method of thinning semiconductor die is provided. The method includes the step of applying a continuous film layer over a plurality of unmasked die supported on a substrate to cover the upper surface and each side surface of the die. The method includes the step of plasma etching the film layer while the film layer remains covering the side surfaces to expose the upper surface of each of the plurality of unmasked die. The method includes the step of plasma etching the exposed upper surface of the die. The method includes the step of plasma ashing the film layer remaining on the side surfaces of the die such that the film layer is completely removed.

[0054] The plurality of unmasked die can be included in a top layer of a plurality of vertical die stacks, with two or more die present in each stack, wherein the continuous film layer covers the upper surface of the plurality of unmasked die in the top layer and the side surfaces of each die in each stack.

[0055] The method may further include the steps of: transferring additional unmasked die to each stack to form a plurality of new unmasked die in a new top layer; and thereafter: applying a new continuous film layer over the plurality of new unmasked die, wherein the new continuous film layer covers the upper surfaces of the die in the new top layer and the side surfaces of each die in each stack; plasma etching the new film layer while the new film layer remains covering the side surfaces to expose the upper surfaces of each die in the new top layer; plasma etching the exposed upper surfaces of the die; and plasma ashing the new film layer remaining on the side surfaces of the die such that the new film layer is completely removed.

[0056] In a third aspect of the invention, there is provided a semiconductor die assembly comprising a substrate and a plurality of semiconductor die processed according to the method of the first or second aspect, wherein the plurality of semiconductor die includes at least two different types of die bonded to the substrate.

[0057] In a fourth aspect of the invention, there is provided a semiconductor die assembly comprising a substrate and a plurality of semiconductor die processed according to the method of the first or second aspect, wherein each of the plurality of semiconductor die has a thickness of less than 15 μm.

[0058] In a fifth aspect of the invention, there is provided a plasma etching apparatus configured to perform the method according to the first or second aspect. The plasma etching apparatus includes a chamber. The plasma etching apparatus further includes a plasma generator associated with the chamber and configured to generate plasma from at least one gas received in the chamber. The plasma etching apparatus further includes a substrate support configured to support a substrate assembly including a substrate and a plurality of semiconductor die spaced apart on the substrate, the substrate support being arranged relative to the chamber such that in use, the plasma contacts the substrate assembly. The plasma etching apparatus further includes a controller configured to cause the apparatus to perform plasma deposition to cover the substrate assembly with a film layer and then perform plasma etching to partially remove the film layer such that the top surfaces of the semiconductor die are exposed, and then perform plasma etching to reduce the thickness of the plurality of semiconductor die, and then perform plasma ashing to completely remove the film layer. Description of the Drawings

[0059] Embodiments of the invention will now be described, by way of example only, with reference to the schematic drawings:

[0060] Figure 1 is a side view of a semiconductor die assembly prior to die thinning, according to an example embodiment of the invention;

[0061] Figure 2 is Figure 1 Side view of a semiconductor die assembly after film deposition;

[0062] Figure 3 is Figure 1 and 2 Side view of a semiconductor die assembly after partial etching of the film;

[0063] Figure 4 is Figures 1-3 Side view of a semiconductor die assembly after die etching;

[0064] Figure 5 is Figures 1-4 Side view of a semiconductor die assembly after complete etching of the film;

[0065] Figure 6 Flowchart of a die thinning method according to an exemplary embodiment of the present invention;

[0066] Figure 7 is Figure 4 Side view of a semiconductor die assembly in which the polymer layer on the sidewall has partially collapsed;

[0067] Figure 8 is for performing Figure 6 Side view of a plasma etching apparatus for the method. Detailed Description

[0068] In an exemplary embodiment of the present invention, a semiconductor die assembly 1 is provided, the semiconductor die assembly including two semiconductor dies 3, 5 positioned side by side and bonded to a substrate 7( Figure 1 ). For illustrative purposes, the assembly 1 includes two dies, however, in other embodiments, there may be multiple dies (e.g., more than 50 or more than 100 dies) attached to the substrate. The dies are positioned on the substrate 7 with a gap 6 therebetween such that a portion 8 of the upper surface 10 of the substrate 7 is exposed ("exposed portion 8"). In embodiments where there are more than two dies, the dies may be evenly arranged on the substrate. In the present embodiment, the substrate 7 is unsupported. In alternative embodiments, the substrate 7 may be supported on a support structure (e.g., a film or a base wafer in a frame).

[0069] In an example embodiment, the substrate 7 comprises a 300 mm wafer. In an alternative embodiment, the substrate may alternatively comprise a tape (i.e., die are located on the tape). In an example embodiment, the die are square in a top view and have four side surfaces 23. Each die 3, 5 comprises a semiconductor layer 9 over a dielectric layer 11, which semiconductor layer is formed of silicon in the example embodiment. The dielectric layer 11 of each die 3, 5 is in contact with an interface layer 13 on the wafer 7. In an example embodiment of the present invention, the dielectric layer 11 of each die comprises a lower dielectric surface 15, which lower dielectric surface comprises bond pad openings (not shown) for hybrid bonding the die 3, 5 to the upper interface surface 17 of the interface layer 13 of the wafer 7.

[0070] The die 3, 5 of the semiconductor die assembly 1 have been attached to the wafer 7 after a die-to-wafer bonding process using a pick-and-place robot (not shown). Each of the die 3, 5 has a thickness t of approximately 40 μm between the top surface 12 of the die and the upper interface surface 17 of the interface layer 13 of the wafer 7. The pick-and-place process and machinery are known in the art and are not described in detail herein. For precise placement by a pick-and-place robot, a die thickness of approximately 30 μm or greater is required. However, for many applications, for practical reasons (e.g., to enable integration in various end products with different space constraints) as well as for economic reasons, a significantly smaller thickness is desirable. Depending on the intended end use, the thickness may need to be slightly or significantly reduced.

[0071] To thin the die 3, 5, a die thinning method as described herein is employed.

[0072] In an initial step 103, a film layer 19 ( Figure 2)Cover the die 3, 5, and the wafer 7. The film layer provides a passivation layer, i.e., a protective layer covering the surfaces of each silicon die 3, 5. In an exemplary embodiment, the film layer 19 comprises a polymer formed of fluorine and carbon. However, other passivation materials (e.g., other polymeric materials) may be suitable as an alternative. In an exemplary embodiment, the film layer 19 is deposited by plasma deposition using inductively coupled plasma (ICP) etching equipment known in the art. Another etching equipment may be suitable as an alternative, such as a PECVD chamber or an RIE chamber. The equipment (described in more detail below) generates plasma from a fluorocarbon gas (e.g., C4F8). The plasma deposition is carried out in the sub / main chamber of the equipment (the equipment will be described in more detail below) for a period of about 40 - 80 seconds at a relatively high pressure of about 80 - 120 mTorr. The equipment of the exemplary embodiment receives two C4F8 gas flows (i.e., a primary gas flow and a secondary gas flow) into the chamber through two separate inlets. The gas is fed at a flow rate of about 100 - 300 sccm. In an alternative embodiment, a single chamber of a similar equipment may be fed with a single gas supply. In an exemplary embodiment, two plasma generators in the form of ICP sources generate two plasmas (which are then mixed) by electromagnetic induction at an ICP power of about 500 - 2000 W from two corresponding gas feeds.

[0073] An AC voltage of 13.56 MHz (i.e., high-frequency "RF bias power") is applied to the support assembly of the semiconductor die assembly 1 (as described in more detail below with reference to Figure 7 ). In the positive cycle, electrons are attracted to the support assembly, while in the negative cycle, cations are attracted to the support assembly. However, since electrons travel faster, a negative DC potential is established on the support assembly. This creates a charge bias (i.e., a charge difference / potential difference) between the semiconductor die assembly 1 and the plasma. The negative DC potential then attracts cations to the semiconductor die assembly 1 on the support assembly, and the cations are deposited as a carbon- and fluorine-containing polymer layer 19. Using a relatively high pressure creates scattering, which helps to make the deposition more uniform.

[0074] By applying RF bias power to the support assembly, the charge difference can be controlled, and thus the rate of polymer deposition can be controlled. It has been found that an RF bias power of about 450 - 550 W is suitable for polymer deposition.

[0075] The polymer layer 19 is deposited to a thickness of approximately 1 μm (not shown to scale) and is applied as a substantially uniform layer, i.e., having a substantially constant thickness across the semiconductor die assembly 1. The high-pressure deposition step is isotropic, where positively charged plasma ions flow towards all outer surfaces of the semiconductor die assembly 1 as part of the plasma flow within the chamber. The polymer layer 19 is deposited in a single application. It has been found that a thickness of 0.5 - 1.5 μm is optimal for providing a film layer that is thick enough to successfully passivate the sides of the semiconductor layer during plasma etching while being thin enough to be applied in a single application.

[0076] The polymer layer 19 completely covers each die and also completely covers the exposed portion 8 of the upper surface 10 of the substrate 7. The polymer layer thus provides a continuous passivation layer covering the die assembly. In an embodiment in which there are multiple dies attached to the substrate, the exposed portion may include several smaller exposed portions of the upper surface of the substrate between and around the dies.

[0077] In an example embodiment, the polymer layer 19 extends across the entire top surface 12 of each die and along each side surface 23 of each of the dies 3, 5. The thickness of the polymer layer 19 across the top surface 12 of the dies 3, 5 is substantially the same as the thickness of the polymer layer 19 along the side surfaces 23 of the dies 3, 5 and is substantially the same as the thickness of the polymer layer 19 across the exposed portion 8 of the upper surface 10 of the substrate 7. In an alternative embodiment, the thickness of the polymer layer 19 along the side surfaces 23 may be slightly less than the thickness of the polymer layer 19 across the top surface 12 of the dies 3, 5 and / or the exposed portion 8 of the upper surface 10 of the substrate 7. However, as long as the polymer layer provides a continuous barrier (i.e., no gaps), a passivation effect can still be provided.

[0078] In a subsequent step, the polymer layer 19 is removed from the top surface 12 of each of the dies 3, 5 and the exposed portion 8 between the dies 3, 5 while keeping the polymer layer 19 intact on the side surfaces 23 of the dies Figure 3) Thus, the side surfaces of the die are kept passivated while the top surface 12 of the die is exposed. In an exemplary embodiment, the polymer layer 19 is removed by plasma etching using the same plasma etching equipment. The equipment (described in more detail below) generates plasma from SF6 gas. The polymer plasma etching is carried out in the chamber of the equipment for a period of about 120 - 160 seconds at a relatively low pressure of about 5 - 20 mTorr. A dual-input SF6 gas flow (i.e., a primary gas flow and a secondary gas flow) is fed into the chamber at a low flow rate of about 150 - 250 sccm. The dual ICP plasma source generates two plasmas, which are then mixed by electromagnetic induction at an ICP power of about 500 - 2000 W. An RF bias power of about 250 - 350 W has been found suitable for polymer etching.

[0079] In an exemplary embodiment, the etching of the polymer from the top surface 12 of the die and from the exposed portion 8 between the dies 3, 5 is carried out simultaneously, where the etching is oriented along a vertical axis (i.e., an axis perpendicular to the central horizontal plane of the substrate 7). Since the etching is directional / anisotropic, the polymer on the side surface 23 of the die is not affected and remains in place. The directionality is achieved by using a low-pressure SF6 gas and RF bias power during the etching. In contrast, the deposition of the film uses a high-pressure C4F8 gas and RF bias power.

[0080] The removal of the polymer layer from the top surface of the die is monitored by spectroscopy and continues until the spectral line at 300 nm suddenly drops sharply before leveling off, indicating that the horizontal top surface of the die has been cleared of the polymer (and thus also implying the removal of the layer from the exposed portion 8).

[0081] In a subsequent step, the top surface 12 of the silicon dies 3, 5 is plasma-etched to thin the dies ( Figure 4 )。In an exemplary embodiment, the dies are thinned by plasma etching using the same plasma etching equipment that has been used for polymer deposition and polymer etching (but in principle the polymer layer can be deposited in another tool after dicing). Similar to the polymer etching of the die top surface, SF6 gas is fed into the equipment chamber in a dual manner. The etching rate of the Si die is faster than that of the polymer layer, which means that the die can be thinned while the polymer layer remains intact on the sidewalls of the die. The Si etching step uses a higher SF6 flow rate of about 500 - 1000 sccm and a slightly higher pressure to increase the etching rate.

[0082] In an exemplary embodiment of the present invention, buried features in the form of through-silicon vias (TSVs - not shown in the figure) are present in the semiconductor layer 9 of the die. The TSVs include Cu pillars covered by a dielectric layer of SiO2. Si plasma etching is performed in a cyclic manner at a medium to low pressure of about 20 - 40 mTorr (to increase the SiO2 selectivity). The etching is performed by an alternating sequence in which RF bias power is applied for one second and then removed (i.e., RF bias power is turned off) for two seconds. The process continues until a target silicon thickness t' is reached, where the etching ends on a smooth Si surface (alternatively, the etching can end when the TSVs are exposed). During the etching, the film layer 19 remaining on the side surfaces 23 of the dies 3, 5 protects the sides of the dies 3, 5 from unwanted etching. Thus, due to the protective passivation layer, the plasma etching of silicon is anisotropic. In other words, the etching is oriented in the vertical direction. The achieved thickness reduction can vary as needed (a reduction of several microns to tens or hundreds of microns). In an alternative embodiment without TSVs or other buried features, the cyclic etching process can be omitted to support a single-step process, since SiO2 selectivity is not of particular concern.

[0083] In a subsequent step, the polymer layer 19 is removed from the side surfaces 23 of each of the dies 3, 5 such that the polymer is completely removed from the semiconductor die assembly 1, leaving the thinned dies 3, 5 bonded to the wafer 7 ( Figure 5 ). In the exemplary embodiment, the polymer layer 19 is removed from the side surfaces 23 by plasma ashing performed using the same plasma etching equipment. The equipment (described in more detail below) generates plasma from an oxygen-containing gas. The plasma ashing is performed in the chamber of the equipment at a relatively low pressure of about 5 - 15 mTorr. A dual-input oxygen gas flow (i.e., a primary gas flow and a secondary gas flow) is fed into the chamber at a flow rate of about 100 - 400 sccm. A dual ICP plasma source generates the plasma, which is then mixed by electromagnetic induction at an ICP power of about 2 - 5 kW. A low RF bias power of about 0 - 50 W has been found to be suitable for polymer ashing. Anisotropic ashing is performed, and all remaining polymer is removed.

[0084] The final polymer stripping is timed, but in another embodiment, an optical end-point signal can be used to monitor.

[0085] In the exemplary embodiment, the semiconductor die assembly is maintained at a constant temperature, for example, about 1 - 10 degrees Celsius for the deposition and etching steps, and slightly warmer (due to the higher ICP power) but less than 50 degrees Celsius for the ashing step.

[0086] The described die thinning method provides a more compact semiconductor die assembly and prepares dies 3, 5 for packaging, for example, using advanced packaging techniques. In summary ( Figure 6 ), the method includes a first step 103 of providing a semiconductor die assembly; a second step 105 of applying a film to a substrate 7 to cover the semiconductor die and an exposed portion 8 with a film layer, where the film layer extends across the top surface of the die and along the side surfaces; a third step 107 of removing the film from the top surface of the die while keeping the film intact on the side surfaces of the die; a fourth step 109 of plasma etching the top surface of the die; and a fifth step 111 of removing the film from the side surfaces of the die. Thus, a processed die assembly is provided having a die thinned from an original thickness of about 40 μm to a height suitable for packaging for various final applications (e.g., thinned to half or less of the original height, e.g., thinned to a quarter or less of the original height).

[0087] The process can be adjusted as needed. In some cases, during Si etching, the film layer 19 on the side surfaces of the die may partially collapse ( Figure 7 ). When the film layer collapses over the semiconductor layer 9, the semiconductor layer is partially obscured in a top view, and the Si etching rate decreases near the obscured region 25. Thus, the Si thickness adjacent to the film layer is greater than the open area of the die. To avoid this from happening, the film deposition and the semiconductor layer and film etching parameters can be changed. Alternatively or additionally, the method can include an additional step of stripping and redepositing the film layer as an intermediate step.

[0088] In an exemplary embodiment, all method steps are performed using a plasma etching device 301 (such as Rapier XE TM ( Figure 8 )). In an alternative embodiment, the method steps can be performed using individual modules on a cluster tool or using a series of different tools or other devices.

[0089] The plasma etching device 301 includes a first chamber 303 disposed above a second larger chamber 305. A first plasma generator 308 in the form of a cylindrical ICP source 309 connected to a first RF (13.56 MHz) power supply 311 is arranged on the periphery of the first chamber and is configured to excite electrons in the gas in the first chamber by generating a changing magnetic field to induce an electric field. A first gas inlet 307 feeds a first process gas into the first chamber 303, where a primary plasma is generated by electromagnetic induction, and subsequently ions are generated.

[0090] The DC coil 313 is used to control the shape of the plasma exiting the first chamber 303. The Faraday shield 315 reduces capacitive coupling from the ICP source, even though it is primarily inductively coupled.

[0091] The plasma flows into the second chamber 305, where the plasma contacts the semiconductor die assembly 1 supported on the electrostatic chuck 317.

[0092] The semiconductor die assembly 1 is carried on a tape 321 held in a frame 323. In an exemplary embodiment, the edges of the semiconductor die assembly 1 are protected by a wafer edge protection (WEP) device 319. A baffle 325 above the electrostatic chuck 317 is arranged to control the gas flow near the semiconductor die assembly.

[0093] The second gas inlet 327 is disposed in a ring arrangement at the top of the second chamber 305 and is arranged to feed a second process gas into the second chamber. A second plasma generator 329 connected to a second RF (13.56 MHz) power supply 331 provides a second cylindrical ICP source. The coaxial source helps to increase the etch rate towards the edges of the semiconductor die assembly. The second plasma generator 329 is arranged at the periphery of the second chamber and is configured to generate a secondary plasma from the second process gas at the periphery of the second chamber 305. The two plasmas are mixed in the chamber and provide a more uniformly distributed plasma above the semiconductor die assembly. The gas flow through the chamber is assisted by a pump 333 and a valve 335. A separate power supply 337 (also at 13.56 MHz, but frequencies from 2 - 20 MHz can be used) provides RF bias power on the electrodes (i.e., the support associated with the semiconductor die assembly).

Claims

1. A method for packaging a semiconductor die, the method comprising the following steps: providing a substrate and a plurality of semiconductor dies spaced apart on the substrate, the substrate having exposed surfaces between the dies; applying a film to the substrate to cover the plurality of semiconductor dies and the exposed substrate surface with a film layer, wherein each die includes a top surface and at least one side surface, and wherein the film layer spans the top surface of the die and extends along the side surface; removing the film from the top surface of the die while leaving the film intact on the side surfaces of the die; plasma etching the top surface of the die; The film is removed from the side surfaces of the die. The method of claim 1 , wherein the membrane comprises a polymer.

3. The method of claim 1 or 2, wherein the semiconductor die comprises an unmasked silicon die.

4. A method according to claim 1 or 2, wherein the film is applied by plasma enhanced chemical vapour deposition.

5. A method according to claim 1 or 2, wherein the film is applied using a plasma formed from a fluorocarbon gas.

6. The method according to claim 1 or 2, wherein the film is applied at least in a vertical direction and a lateral direction relative to a central horizontal plane of the substrate.

7. The method of claim 1 or 2, further comprising removing the film from the exposed substrate surface simultaneously with removing the film from the top surface of the die.

8. The method of claim 1 or 2, wherein the film is removed from the top surface of the die by anisotropic plasma etching.

9. The method of claim 1 or 2, wherein the film is removed from the top surface of the die using a plasma formed from SF6 gas.

10. The method of claim 1 or 2, wherein the film is removed from the side surface of the die by isotropic plasma ashing.

11. The method of claim 1 or 2, wherein an oxygen-based ashing chemistry is used to remove the film from the side surfaces of the die.

12. The method of claim 1 or 2, wherein the film layer is applied over substantially the entire substrate.

13. The method of claim 1 or 2, wherein the film layer extends along each side surface of the die.

14. The method according to claim 1 or 2, wherein the maximum thickness of the film layer is less than 5 μm.

15. The method of claim 1 or 2, wherein the film layer has a substantially constant average thickness, wherein a maximum thickness variation from the average thickness is less than 20%.

16. The method of claim 1 or 2, wherein the film is applied to the substrate in a single deposition step.

17. The method of claim 1 or 2, further comprising the intermediate steps of stripping the film to completely remove the film layer, and reapplying the film to the substrate to cover the plurality of semiconductor dies and the exposed substrate surface with a replacement film layer.

18. The method according to claim 1 or 2, wherein: The top surfaces of the dies are etched until a thickness of each die between the exposed surface of the substrate and the top surface of the die is less than a user-defined threshold thickness. The method of claim 18 , wherein the threshold thickness is 20 μm.

20. The method of claim 18, wherein the threshold thickness is 10 μm.

21. A method according to claim 1 or 2, wherein the plurality of semiconductor dies include at least one first type of die and at least one second type of die, and the method includes a previous step of attaching at least one of the first type of die to the substrate to provide the plurality of semiconductor dies spaced apart on the substrate, wherein at least one of the second type of die is pre-bonded on the substrate.

22. The method of claim 1 or 2, wherein the substrate comprises a semiconductor material.

23. The method of claim 1 or 2, wherein the substrate comprises a dielectric material.

24. The method of claim 1 or 2, wherein the substrate is a tape or is supported on a tape.

25. The method of claim 1 or 2, further comprising the subsequent step of applying an encapsulation material to the substrate to encapsulate the substrate and the die.

26. The method of claim 1 or 2, wherein the plurality of semiconductor dies are included in a top layer of a plurality of vertical die stacks.

27. The method of claim 1 or 2, wherein the plurality of semiconductor dies are included in a plurality of horizontal die stacks, wherein the film layer spans the top surfaces of the dies and extends along a plurality of outward facing side surfaces of the dies.

28. A method for thinning a semiconductor die, the method comprising the following steps: applying a continuous film layer over a plurality of unmasked dies supported on a substrate to cover an upper surface and each side surface of the dies; plasma etching the film layer to expose the upper surface of each of the plurality of unmasked dies while the film layer remains covering the side surfaces; plasma etching the exposed upper surface of the die; Plasma ashing is performed on the film layer remaining on the side surface of the die so that the film layer is completely removed.

29. The method of claim 28, wherein the plurality of unmasked dies are included in a top layer of a plurality of vertical die stacks, with two or more dies present in each stack, wherein the continuous film layer covers the upper surfaces of the plurality of unmasked dies in the top layer and the side surfaces of each die in each stack.

30. The method according to claim 29, further comprising the steps of: transferring another unmasked die to each stack to form a plurality of new unmasked dies included in a new top layer; and after: applying a new continuous film layer over the plurality of new unmasked dies, wherein the new continuous film layer covers the top surfaces of the dies in the new top layer and the side surfaces of each die in each stack; plasma etching the new film layer to expose the upper surface of each die in the new top layer while the new film layer remains covering the side surfaces; plasma etching the exposed upper surface of the die; Plasma ashing is performed on the new film layer remaining on the side surface of the die so that the new film layer is completely removed.

31. A semiconductor die assembly comprising a substrate and a plurality of semiconductor dies processed according to the method of any one of claims 1 to 30, wherein the plurality of semiconductor dies comprises at least two different types of dies bonded to the substrate.

32. A semiconductor die assembly comprising a substrate and a plurality of semiconductor dies processed according to the method of any one of claims 1 to 30, wherein each of the plurality of semiconductor dies has a thickness of less than 15 μm.

33. A plasma etching apparatus, configured to perform the method according to any one of claims 1 to 30, the plasma etching apparatus comprising: Chamber; a plasma generator connected to the chamber and configured to generate plasma from at least one gas received in the chamber; a substrate support configured to support a substrate assembly comprising a substrate and a plurality of semiconductor dies spaced apart on the substrate, the substrate support being arranged relative to the chamber such that, in use, the plasma contacts the substrate assembly; as well as A controller configured to cause the apparatus to perform plasma deposition to cover the substrate assembly with a film layer, and then perform plasma etching to partially remove the film layer to expose the top surface of the semiconductor die, and then perform plasma etching to reduce the thickness of the plurality of semiconductor dies, and then perform plasma ashing to completely remove the film layer.

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