Package substrate and manufacturing method thereof

Abstract

A package substrate and a manufacturing method thereof are provided, the package substrate includes a circuit structure formed on one side of a core board body having a core layer, and the other side of the core board body is used as a ball mounting side to reduce the number of layers of the package substrate, so that the total thickness of the package substrate is beneficial to thinning.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging technology, and more particularly to a packaging substrate that can meet the thinning requirements and a manufacturing method thereof. Background Art

[0002] With the vigorous development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in form, and in terms of function, they are developed in the direction of high performance, high functionality and high speed. Therefore, in order to meet the requirements of high integration and miniaturization of semiconductor devices, in the packaging process, packaging substrates with designs such as thinning, low warpage degree, and high-density wiring are often used.

[0003] However, in the existing manufacturing methods of packaging substrates, there is a risk of damage to the conditions of the board thickness in the existing equipment, thus restricting its processing ability for thinner substrates. Therefore, when producing packaging substrates that meet the designs such as thinning and low warpage degree, special-purpose equipment with special specifications needs to be set up, resulting in difficult reduction of production costs.

[0004] Therefore, how to overcome the problems of the above-mentioned existing technologies has actually become an urgent issue to be solved at present. Summary of the Invention

[0005] The object of the present invention is to provide a packaging substrate and a manufacturing method thereof to solve at least one of the above problems.

[0006] In view of the defects of the above-mentioned existing technologies, the present invention provides a packaging substrate, including: a core board body, including a core layer having opposite first and second sides, a plurality of through holes communicating the first and second sides of the core layer, insulating layers formed on opposite sides and in the through holes of the core layer, via holes formed in the insulating layers of the through holes and corresponding to each through hole, hollow conductive columns formed in each via hole, plugging materials formed in the hollow conductive columns, and wiring layers formed on the insulating layers of the first and second sides and electrically connecting the conductive columns, wherein the wiring layer formed on the insulating layer of the first side has a plurality of ball mounting pads; a dielectric layer formed on the insulating layer of the first side of the core layer, burying the wiring layer on the first side of the core board body in the dielectric layer; and a circuit structure provided on the insulating layer of the second side of the core layer and electrically connecting the wiring layer on the second side of the core board body.

[0007] The present invention also provides a method for manufacturing an encapsulation substrate, including: providing a plurality of core substrates, wherein each core substrate includes a core layer having opposite first and second sides, a plurality of through holes communicating the first and second sides of the core layer, insulating layers formed on opposite sides of the core layer and in the through holes, through holes formed in the insulating layers of the through holes and corresponding to each through hole, hollow conductive columns formed in each through hole, plugging materials formed in the hollow conductive columns, and wiring layers formed on the insulating layers of the first and second sides and electrically connecting the conductive columns, wherein the wiring layer formed on the insulating layer of the first side has a plurality of ball mounting pads; bonding the insulating layers on the first sides of the core layers respectively on opposite sides of a carrier, wherein the carrier laminates the core substrate through a dielectric layer, such that the wiring layer on the first side of the core substrate is buried in the dielectric layer; forming a circuit structure on the insulating layer on the second side of the core layer and electrically connecting the circuit structure to the wiring layer on the second side of the core substrate; and removing the carrier to expose the dielectric layer.

[0008] In a specific embodiment of the foregoing encapsulation substrate and its manufacturing method, the material of the insulating layer is the same as that of the plugging material.

[0009] In a specific embodiment of the foregoing encapsulation substrate and its manufacturing method, the thickness of the insulating layers formed on opposite sides of the core layer and on the wall surfaces of the through holes ≥ 50 μm.

[0010] In a specific embodiment of the foregoing encapsulation substrate, the dielectric layer is formed with a plurality of openings penetrating the dielectric layer to expose the ball mounting pads on the first side of the core substrate. Correspondingly, in a specific embodiment of the foregoing manufacturing method of the encapsulation substrate, it further includes, after removing the carrier, forming a plurality of openings penetrating the dielectric layer to expose the ball mounting pads on the first side of the core substrate, so that the dielectric layer serves as a solder mask.

[0011] In a specific embodiment of the foregoing encapsulation substrate and its manufacturing method, it further includes forming a solder mask layer on the circuit structure.

[0012] In a specific embodiment of the foregoing encapsulation substrate, the dielectric layer is formed with a plurality of openings penetrating the dielectric layer to expose the ball mounting pads on the first side of the core substrate; and a solder mask layer formed on the dielectric layer. Correspondingly, in a specific embodiment of the foregoing manufacturing method of the encapsulation substrate, it further includes, after removing the carrier, forming a plurality of openings penetrating the dielectric layer to expose the ball mounting pads on the first side of the core substrate; and forming a solder mask layer on the dielectric layer, so that the ball mounting pads are exposed outside the dielectric layer and the solder mask layer.

[0013] In a specific embodiment of the foregoing encapsulation substrate and its manufacturing method, the core substrate further includes a bonding layer formed on the surfaces of opposite first and second sides of the core layer and on the surfaces of the through holes to be located between the core layer and the insulating layer.

[0014] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the bonding layer is an organic coating or an inorganic coating.

[0015] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the material forming the organic coating is a polymer.

[0016] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the polymer is selected from at least one of the group consisting of polyoxymethylene, polyamide, and parylene.

[0017] In a specific embodiment of the foregoing packaging substrate and its manufacturing method, the material forming the inorganic coating includes silica sand with a diameter of 20 to 50 microns and a roughness Ra of 1 to 200 microns.

[0018] As can be seen from the above, in the packaging substrate and its manufacturing method of the present invention, the first side of the core layer is mainly used as the ball-planting side to reduce the number of layers of the packaging substrate. Therefore, compared with the prior art, the total thickness of the packaging substrate is beneficial to be thinned.

[0019] Furthermore, through the ball grid array design on the first side of the core layer, the core board body has the conventional ball-planting side pad size, conductive column spacing, and the diameter of the perforation. Therefore, regardless of how the wiring of the circuit structure is designed, the substrate with perforations can be made into the core board body for use in a BGA-specification packaging substrate, thus saving process time.

[0020] In addition, through the design of the core layer with high hardness in the present invention, the problem of warping of the packaging substrate can be effectively avoided.

[0021] In addition, in the present invention, by using the first side of the core layer as the ball-planting side and directly contacting the solder balls with the circuit board thereon, the conduction path can be shortened to reduce signal loss. Brief Description of the Drawings

[0022] Figures 1A to 1H It is a schematic cross-sectional view of the first embodiment of the manufacturing method of the packaging substrate of the present invention.

[0023] Figure 1H-1 It is a schematic cross-sectional view of the packaging substrate with a bonding layer of the first embodiment of the present invention.

[0024] Figures 2A to 2D It is a schematic cross-sectional view of the second embodiment of the manufacturing method of the packaging substrate of the present invention.

[0025] Figure 2D-1 It is a schematic cross-sectional view of the packaging substrate with a bonding layer of the second embodiment of the present invention.

[0026] The reference numerals are as follows:

[0027] 1,2 Encapsulation Substrate

[0028] 1a Core Board Body

[0029] 10 Core Layer

[0030] 10a First Side

[0031] 10b Second Side

[0032] 100 Perforation

[0033] 101 Crack

[0034] 11 Insulation Layer

[0035] 110 Through Hole

[0036] 12 Conductive Layer

[0037] 13 Plugging Material

[0038] 14a, 14b Wiring Layer

[0039] 140 Ball Mounting Pad

[0040] 15 Conductive Column

[0041] 16 Circuit Structure

[0042] 160 Dielectric Layer

[0043] 161 Circuit Layer

[0044] 17, 27 Solder Mask Layer

[0045] 170, 270, 720 Opening

[0046] 22 Bonding Layer

[0047] 7 Carrier

[0048] 70 Board Body

[0049] 71 Copper Foil

[0050] 72 Dielectric Layer

[0051] 8 Substrate. Detailed Implementation Modes

[0052] The following illustrates the implementation modes of the present invention through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0053] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented. Therefore, they do not have technical substantive significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper", "first", "second", "one", etc. cited in this specification are only for the convenience of clear narration and are not used to limit the scope under which the present invention can be implemented. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope under which the present invention can be implemented.

[0054] Figures 1A to 1H It is a schematic cross-sectional view of the first embodiment of the manufacturing method of the encapsulation substrate 1 of the present invention.

[0055] As Figure 1A shown, a core layer 10 is provided, which has opposite first side 10a and second side 10b. A plurality of through holes 100 communicating the first side 10a and the second side 10b are formed in the core layer 10, and insulating layers 11 are formed on opposite sides and in the through holes 100 of the core layer 10.

[0056] In this embodiment, the core layer 10 is made of a high-hardness dielectric material, such as glass, ceramic, silicon carbide (SiC), AlO2, or a highly rigid composite material with a modulus of 50 to 100 GPa. In addition, the first side 10a and the second side 10b of the core layer 10 can be penetrated by means such as laser ablation, hydrofluoric acid (HF) etching, plasma etching, mechanical drilling, etc. to form a plurality of through holes 100.

[0057] Furthermore, the insulating layer 11 can be an ink material formed by filling methods such as injection, plugging, or coating. For example, after injecting a paste-like ink material into the through holes 100, it is heated for several hours to crosslink the molecules in the ink material and evaporate the solvent. After the ink is cured, it is polished and leveled with a ceramic roller to remove the excess ink protruding from the core layer 10 and make the ink evenly coated on the surfaces of opposite sides of the core layer 10.

[0058] In addition, the ink material is mainly composed of epoxy ink composites, which have physical properties such as a viscosity of 25 to 55 Pa·s, a glass transition temperature (Tg) of 145 to 180 °C, and / or a Young's modulus ≥ 3 GPa. Further, the epoxy ink composites can be cured by heating at 180 °C for 2 hours to form the insulating layer 11.

[0059] Therefore, the manufacturing method of the present invention can reduce the consumption costs of the process and materials by injecting ink to fill the through holes 100 of the core layer 10.

[0060] As Figure 1B shown, a plurality of through holes 110 corresponding to each of the through holes 100 are formed in the insulating layer 11 of each of the through holes 100 by means such as laser or mechanical drilling. And a conductive layer 12 is formed on the insulating layers 11 on opposite sides of the core layer 10 and in each of the through holes 110. Among them, the conductive layer 12 can be a metal layer such as copper material, etc., for use as a barrier and a seed layer.

[0061] In this embodiment, the through hole 100 is in a straight cylindrical shape, and the through hole 110 is in a double conical hole shape such as a hourglass shape. It should be understood that the through hole 100 and the through hole 110 can also be other hole shapes. In addition, the insulating layer 11 wraps the core layer 10, so the depth of the through hole 110 is greater than that of the through hole 100, and the aperture of the through hole 110 is smaller than that of the through hole 100.

[0062] Furthermore, the thickness of the insulating layers 11 on opposite sides of the core layer 10 should be ≥ 50 μm, and after the through holes 110 are formed, the thickness of the insulating layer 11 on the wall surface of the through hole 100 should also be maintained at ≥ 50 μm.

[0063] As Figure 1C shown, a plugging material 13 is formed in the through holes 110 to make a substrate 8.

[0064] In this embodiment, the plugging material 13 can be an ink material formed by filling methods such as injection, plugging, or coating. For example, after the plugging material 13 is formed in the through holes 110 and the ink is cured, the surface is polished and leveled again with a ceramic roller to remove the excess ink protruding from the conductive layer 12 on the surface of the conductive layer 12 on opposite sides of the core layer 10 and in the through holes 110, so that the ink only fills the through holes 110 and does not cover the surface of the conductive layer 12.

[0065] Furthermore, the ink material can also be composed of an epoxy ink composite, and has physical properties such as a viscosity of 25 to 55 Pa·s, a glass transition temperature (Tg) of 145 to 180 °C, and / or a Young's modulus ≥ 3 GPa. That is to say, the plugging material 13 can be the same material as the insulating layer 11. Therefore, by injecting ink (plugging material 13) to fill the through holes 110, the consumption costs of the process and materials can be reduced.

[0066] As Figure 1DAs shown, a patterning wiring process is performed through the conductive layer 12 on the insulating layer 11 to respectively form a wiring layer 14a and 14b on the insulating layer 11 on the first side 10a and the second side 10b of the core layer 10, and the conductive layer 12 in the through hole 110 serves as a hollow conductive column 15 to form a core board body 1a.

[0067] In this embodiment, the adhesion between the ink serving as the insulating layer 11, the core layer 10, and the conductive layer 12 is excellent, which can reduce the risk of delamination or crack generation and increase the stability and reliability of the core board body 1a. Furthermore, the wiring layers 14a and 14b are formed on the insulating layer 11, and after the cured ink is polished and leveled, it ensures good surface flatness to facilitate the formation of a wiring pattern with a fine line width / line pitch (L / S).

[0068] As Figure 1E shown, the core board body 1a is respectively bonded to opposite sides of a carrier 7, wherein the core board body 1a is bonded to the carrier 7 with its first side 10a.

[0069] In this embodiment, the carrier 7 is a double capacity bonding material, such as a copper clad laminate (CCL), and the core board body 1a is respectively pressed on the copper foils 71 on both sides of its board body 70 through a dielectric layer 72, so that the wiring layer 14a on the first side 10a of the core board body 1a is buried in the dielectric layer 72. In one embodiment, the dielectric layer 72 is polybenzoxazole (PBO), polyimide (PI), a prepreg with glass fiber (PP), or other dielectric materials.

[0070] Therefore, in the production process of the packaging substrate 1 of this embodiment, through the design of the carrier 7, a patterning circuit build-up operation is carried out in a symmetric manner subsequently, which helps to improve the yield of the fine line width / fine line pitch (L / S).

[0071] Furthermore, if a thinner substrate 8 is used, with the configuration of the carrier 7, it is not only beneficial for handling or transportation in the process, but also can double the output.

[0072] As Figure 1F shown, a patterning circuit build-up operation is carried out in a symmetric manner to form a circuit structure 16 electrically connecting the wiring layer 14b on the second side 10b of each core board body 1a. Then, a solder mask layer 17 is formed on the circuit structure 16.

[0073] In this embodiment, the circuit structure 16 includes at least one dielectric layer 160 disposed on the core board 1a and at least one circuit layer 161 formed on the dielectric layer 160 and electrically connected to the wiring layer 14b. For example, the build-up process is adopted to fabricate the circuit structure 16 with two dielectric layers 160 and two circuit layers 161 as in this embodiment by electroplating a metal (such as copper) or other means.

[0074] Furthermore, the dielectric layer 160 is made of Ajinomoto Build-up Film (ABF) material or other dielectric materials, and the circuit layer 161 is made of copper, such as adopting the Redistribution layer (RDL) specification.

[0075] In addition, a part of the surface of the circuit layer 161 is exposed outside the solder mask layer 17 to serve as an electrical contact pad. For example, a plurality of openings 170 exposing the circuit layer 161 are formed on the solder mask layer 17.

[0076] In addition, the circuit structure 16 and the core board 1a have a total of four layers of wiring. The line width / line pitch (L / S) of the three layers of configuration from the outermost circuit layer 161 to the wiring layer 14b on the second side 10b are respectively, for example, 5 / 5, 8 / 10, and 15 / 15 micrometers (um), and the wiring layer 14a on the first side 10a includes a plurality of ball pads 140. It should be understood that the number of wiring layers of the circuit structure 16 can be determined according to requirements and is not limited to the above two layers.

[0077] As Figure 1G shown, the board body 70 of the carrier 7 is removed to retain the copper foil 71 on the dielectric layer 72.

[0078] In this embodiment, the first side 10a of the core board 1a serves as the ball mounting side, and the second side 10b serves as the build-up side. For example, the width of the wiring layer 14a (ball pad 140) on the first side 10a is greater than, less than, or equal to the width of the via hole 100.

[0079] As Figure 1H shown, the copper foil 71 is first removed to expose the dielectric layer 72, and then a plurality of openings 720 exposing the wiring layer 14a (ball pad 140) are formed on the dielectric layer 72.

[0080] In this embodiment, the dielectric layer 72 can be used for solder mask, so there is no need to form another solder mask layer.

[0081] Therefore, for the packaging substrate 1 and its manufacturing method in this embodiment, by mainly using the first side 10a of the core layer 10 as the ball mounting side, the number of layers of the packaging substrate 1 is reduced. Therefore, compared with the prior art, the total thickness of the packaging substrate 1 is beneficial to be thinned.

[0082] Furthermore, through the ball grid array design on the first side 10a of the core layer 10, the core board body 1a has conventional ball-planting side pad sizes, conductive post 15 spacings, and via 100 diameters. Therefore, regardless of how the wiring of the circuit structure 16 is designed, the substrate 8 with vias 100 and through holes 110 can be fabricated into the core board body 1a for use in the BGA-specification packaging substrate 1, thus saving process time.

[0083] In addition, through the design of the core layer 10 with high hardness, the problem of warping of the packaging substrate 1 can be effectively avoided.

[0084] In addition, by using the first side 10a of the core layer 10 as the ball-planting side and directly contacting the circuit board with solder balls (not shown) thereon, the conduction path can be shortened to reduce signal loss.

[0085] Figures 2A to 2D It is a cross-sectional schematic view of the second embodiment of the manufacturing method of the packaging substrate 2 of the present invention. The difference between this embodiment and the first embodiment lies in the configuration of the solder mask layer, so the same parts will not be elaborated hereinafter.

[0086] As Figure 2A shown, in the process shown in Figure 1F , only the circuit structure 16 is fabricated, and the solder mask layer 17 is not formed on the circuit structure 16.

[0087] As Figure 2B shown, the board body 70 of the carrier 7 is removed to retain the copper foil 71 on the dielectric layer 72.

[0088] As Figure 2C shown, the copper foil 71 is removed first to expose the dielectric layer 72, and then a plurality of openings 720 exposing the wiring layer 14a (ball-planting pads 140) are formed on the dielectric layer 72.

[0089] As Figure 2D shown, a solder mask layer 17, 27 is respectively formed on the circuit structure 16 and the dielectric layer 72.

[0090] In this embodiment, part of the surface of the circuit layer 161 exposes the solder mask layer 17, and the wiring layer 14a (ball-planting pads 140) exposes the solder mask layer 27. For example, a plurality of openings 270 exposing the wiring layer 14a (ball-planting pads 140) are formed on the solder mask layer 27, and the openings 270 correspond to the openings 720 of the dielectric layer 72 shown in Figure 2C , and a plurality of openings 170 exposing the circuit layer 161 are formed on the solder mask layer 17, making the exposed surface of the circuit layer 161 serve as an electrical contact pad.

[0091] Therefore, for the encapsulation substrate 2 and its manufacturing method of the present embodiment, by using the first side 10a of the core layer 10 as the ball-planting side, the number of layers of the encapsulation substrate 2 is reduced. Therefore, compared with the prior art, the total thickness of the encapsulation substrate 2 is beneficial to be thinned.

[0092] Furthermore, through the ball grid array design on the first side 10a of the core layer 10, the core board body 1a has the conventional ball-planting side pad size, the pitch of the conductive posts 15, and the diameter of the perforations 100. Therefore, regardless of how the wiring of the circuit structure 16 is designed, the substrate 8 with the perforations 100 and the vias 110 can be made into the core board body 1a for use in the BGA-specification encapsulation substrate 1, thus saving the process time.

[0093] In addition, through the design of the core layer 10 with high hardness, the problem of warping of the encapsulation substrate 2 can be effectively avoided.

[0094] In addition, by using the first side 10a of the core layer 10 as the ball-planting side and directly contacting the circuit board with solder balls (not shown) thereon, the conduction path can be shortened to reduce the signal loss.

[0095] In some specific embodiments, according to the above two embodiments, in order to improve the adhesion of the surface of the core layer 10 and the wall surface of the perforations 100, a bonding layer 22 can be formed on the opposite sides of the core layer 10 and the wall surface of the perforations 100 as required, and then the insulating layer 11 is bonded through the bonding layer 22.

[0096] Furthermore, the bonding layer 22 can be an organic coating formed through a chemical process. For example, organic polymers such as polyphenylene oxide (PPO), polyamide, or poly-dimethylbenzene (PD) are deposited. Further, a thinner organic coating can be formed through a chemical vapor deposition (CVD) method to improve the isolation, anti-corrosion, and protection of the surface of the high-rigidity core layer 10. Its thickness is, for example, 1 nanometer to 100 micrometers, and the organic coating can penetrate into the cracks 101 to limit the expansion of the cracks 101, as Figure 1H-1 and Figure 2D-1 shown, the bonding layer 22 of the organic coating penetrates into the cracks 101 of the core layer 10 and reduces the dielectric constant (Dk) of the core layer 10 to 2.5 to 5 (1 GHz), such as 2.5, 2.65, 2.7, 2.8, 2.9, 3.0, 3.2, 3.5, 3.7, 4.0, 4.2, 4.5, 4.7, and 5.0 (1 GHz).

[0097] On the other hand, the bonding layer 22 can also be an inorganic coating formed by a physical process to form Van der Waals force. For example, sandblasting with silica sand having a diameter of 20 to 50 micrometers and a roughness Ra of 1 to 200 micrometers can not only remove oxides and impurities on the core layer 10, but also increase the surface area of the core layer 10, thus helping to improve the adhesion of the insulating layer 11 formed on the core layer 10 of the high-hardness material. Therefore, in a specific embodiment, the bonding layer 22 is formed by silica sand having a diameter of 20 to 50 micrometers and a roughness of 1 to 200 micrometers.

[0098] The present invention also provides a packaging substrate 1, 2, comprising: a core board body 1a, a dielectric layer 72, and a circuit structure 16.

[0099] The core board body 1a includes a core layer 10 having opposite first and second sides 10a and 10b. A plurality of through holes 100 communicating the first side 10a and the second side 10b are formed in the core layer 10, and insulating layers 11 are formed on opposite sides of the core layer 10 and on the wall surfaces of the through holes 100. A plurality of through holes 110 corresponding to each of the through holes 100 are formed in the insulating layer 11 on the wall surface of the through hole 100, so that hollow conductive columns 15 are formed in the through holes 110, and plugging materials 13 are formed in the conductive columns 15. Wiring layers 14a and 14b electrically connected to the conductive columns 15 are respectively formed on the insulating layers 11 of the first side 10a and the second side 10b, and the wiring layer 14a on the insulating layer 11 of the first side 10a has a plurality of ball pads 140.

[0100] The dielectric layer 72 is formed on the insulating layer 11 of the first side 10a of the core layer 10, so that the wiring layer 14a on the first side 10a of the core board body 1a is embedded in the dielectric layer 72.

[0101] The circuit structure 16 is disposed on the insulating layer 11 of the second side 10b of the core layer 10 and is electrically connected to the wiring layer 14b on the second side 10b of the core board body 1a.

[0102] In one embodiment, the material of the insulating layer 11 is the same as that of the plugging material 13.

[0103] In one embodiment, the thickness of the insulating layers 11 formed on opposite sides of the core layer 10 and on the wall surfaces of the through holes 100 is ≥50 μm.

[0104] In one embodiment, the dielectric layer 72 is formed with a plurality of openings 720 penetrating the dielectric layer 72 to expose the ball pads 140 on the first side 10a of the core board body 1a, so that the dielectric layer 72 serves as a solder mask.

[0105] In one embodiment, the encapsulation substrates 1, 2 further include a solder mask layer 17 formed on the circuit structure 16.

[0106] In one embodiment, the dielectric layer 72 is formed with a plurality of openings 720 that penetrate the dielectric layer 72 to expose the ball pads 140 on the first side 10a of the core board body 1a; and a solder mask layer 27 is formed on the dielectric layer 72 to expose the ball pads 140 outside the dielectric layer 72 and the solder mask layer 27.

[0107] In one embodiment, the core board body 1a further includes a bonding layer 22 formed on the surfaces of the opposite first side 10a and second side 10b of the core layer 10 and the surface of the perforation 100 to be located between the core layer 10 and the insulating layer 11.

[0108] In one embodiment, the bonding layer 22 is an organic coating or an inorganic coating.

[0109] In one embodiment, the material forming the organic coating is a polymer, and the thickness of the organic coating is, for example, 1 nanometer to 100 micrometers.

[0110] In one embodiment, the polymer is selected from at least one of the group consisting of polyoxymethylene, polyamide, and parylene.

[0111] In one embodiment, the material forming the inorganic coating includes silica sand with a diameter of 20 to 50 micrometers and a roughness Ra of 1 to 200 micrometers.

[0112] In summary, for the encapsulation substrate and its manufacturing method of the present invention, mainly by using the first side of the core layer as the ball-planting side, the number of layers of the encapsulation substrate is reduced, so the total thickness of the encapsulation substrate is beneficial to be thinned.

[0113] Furthermore, by the ball grid array design on the first side of the core layer, the core board body has conventional ball-planting side pad sizes, conductive column spacings, and perforation diameters. Therefore, regardless of how the wiring of the circuit structure is designed, the substrate with perforations and vias can be made into the core board body for use in BGA-specification encapsulation substrates, thus saving process time.

[0114] In addition, the present invention can effectively avoid the problem of warping of the encapsulation substrate by the design of the core layer with high hardness.

[0115] In addition, the present invention uses the first side of the core layer as the ball-planting side to directly contact the circuit board with solder balls thereon, thereby shortening the conduction path and reducing signal loss.

[0116] The above embodiments are used to illustrate the principles and effects of the present invention by way of example, rather than to limit the present invention. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the protection of the rights of the present invention shall be as set forth in the claims.

Claims

1. A packaging substrate, characterized in that: include: A core board body, comprising a core layer having a first side and a second side opposite to each other, a plurality of through-holes connecting the first side and the second side of the core layer, an insulating layer formed on opposite sides of the core layer and in the through-holes, a through-hole formed in the insulating layer of the through-holes and corresponding to each of the through-holes, a hollow conductive column formed in each of the through-holes, a plugging material formed in the hollow conductive column, and a wiring layer formed on the insulating layer on the first side and the second side and electrically connected to the conductive column, wherein the wiring layer formed on the insulating layer on the first side has a plurality of ball pads; A dielectric layer is formed on the insulating layer on the first side of the core layer, so that the wiring layer on the first side of the core board is buried in the dielectric layer; and The circuit structure is arranged on the insulating layer on the second side of the core layer and is electrically connected to the wiring layer on the second side of the core board body.

2. The packaging substrate according to claim 1, wherein: The material of the insulating layer is the same as that of the plugging material.

3. The packaging substrate according to claim 1, wherein: The thickness of the insulating layer formed on the opposite sides of the core layer and on the wall surface of the through hole is ≥50 μm.

4. The packaging substrate according to claim 1, wherein: The dielectric layer is formed with a plurality of openings penetrating through the dielectric layer to expose the ball-planting pads on the first side of the core board body, so that the dielectric layer can be used as solder mask.

5. The packaging substrate according to claim 1, wherein: The packaging substrate also includes a solder mask formed on the circuit structure.

6. The packaging substrate according to claim 1, wherein: The dielectric layer is formed with a plurality of openings penetrating the dielectric layer to expose the ball-planting pad on the first side of the core board; and a solder mask layer is formed on the dielectric layer to expose the dielectric layer and the solder mask layer outside the ball-planting pad.

7. The packaging substrate according to claim 1, wherein: The core board also includes a bonding layer formed on the surfaces of the first side and the second side opposite to the core layer and the surface of the perforation so as to be located between the core layer and the insulating layer.

8. The packaging substrate according to claim 7, wherein: The bonding layer is an organic coating or an inorganic coating.

9. The packaging substrate according to claim 8, wherein: The material forming the organic coating is a polymer.

10. The packaging substrate according to claim 9, wherein: The polymer is at least one selected from the group consisting of polyoxyxylene, polyamide and polyparaxylene.

11. The packaging substrate according to claim 8, wherein: The material forming the inorganic coating includes silica sand with a diameter of 20 to 50 micrometers and a roughness Ra of 1 to 200 micrometers.

12. A method for manufacturing a packaging substrate, characterized in that: include: A plurality of core boards are provided, wherein each of the core boards comprises a core layer having a first side and a second side opposite to each other, a plurality of through holes connecting the first side and the second side of the core layer, an insulating layer formed on opposite sides of the core layer and in the through holes, a through hole formed in the insulating layer of the through hole and corresponding to each of the through holes, a hollow conductive column formed in each of the through holes, a plugging material formed in the hollow conductive column, and a wiring layer formed on the insulating layer on the first side and the second side and electrically connected to the conductive column, wherein the wiring layer formed on the insulating layer on the first side has a plurality of ball pads; The core board is pressed on two opposite sides of a carrier by dielectric layers, so that the wiring layer on the first side of the core board is buried in the dielectric layer; forming a circuit structure on the insulating layer on the second side of the core layer, and electrically connecting the circuit structure to the wiring layer on the second side of the core board; and The carrier is removed to expose the dielectric layer.

13. The method for manufacturing a packaging substrate according to claim 12, wherein: The material of the insulating layer is the same as that of the plugging material.

14. The method for manufacturing a packaging substrate according to claim 12, wherein: The thickness of the insulating layer formed on the opposite sides of the core layer and on the wall surface of the through hole is ≥50 μm.

15. The method for manufacturing a packaging substrate according to claim 12, wherein: The manufacturing method further comprises, after removing the carrier, forming a plurality of openings penetrating the dielectric layer to expose the ball-planting pads on the first side of the core board, so that the dielectric layer can be used as solder mask.

16. The method for manufacturing a packaging substrate according to claim 12, wherein: The manufacturing method also includes forming a solder resist layer on the circuit structure.

17. The method for manufacturing a packaging substrate according to claim 12, wherein: The method further comprises, after removing the carrier, forming a plurality of openings penetrating the dielectric layer to expose the ball pad on the first side of the core board; and forming a solder mask on the dielectric layer to expose the dielectric layer and the solder mask outside the ball pad.

18. The method for manufacturing a packaging substrate according to claim 12, wherein: The core board also includes a bonding layer formed on the surfaces of the first side and the second side opposite to the core layer and the surface of the perforation so as to be located between the core layer and the insulating layer.

19. The method for manufacturing a packaging substrate according to claim 12, wherein: The bonding layer is an organic coating or an inorganic coating.

20. The method for manufacturing a packaging substrate according to claim 19, wherein: The material forming the organic coating is a polymer.

21. The method for manufacturing a packaging substrate according to claim 20, wherein: The polymer is at least one selected from the group consisting of polyoxyxylene, polyamide and polyparaxylene.

22. The method for manufacturing a packaging substrate according to claim 19, wherein: The material forming the inorganic coating includes silica sand with a diameter of 20 to 50 micrometers and a roughness Ra of 1 to 200 micrometers.

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