A high-density stacked packaging structure and packaging method integrating capacitor and PMIC chip

Abstract

The present invention discloses a high-density stacked packaging structure and packaging method for integrated capacitors and PMIC chips. The packaging structure embeds a PMIC chip and an LSI chip into two layers of plastic encapsulation, each with TSV (through-hole vias). A capacitor circuit and an intermediate redistribution layer are fabricated between the two layers of plastic encapsulation, forming a double-layer plastic encapsulation through-hole interposer. Redistribution layers are fabricated on both sides of the double-layer plastic encapsulation through-hole interposer. The top layer connects an HBM chip and a SOC chip, and the bottom layer is soldered to a substrate. Balls are implanted at the bottom of the substrate, and heat sinks are embedded in the two layers of plastic encapsulation. The heat sinks are connected to the heat dissipation channels of the substrate to conduct heat, and a heat dissipation cover is provided on the substrate. This packaging method utilizes plastic encapsulation through-holes and plastic encapsulation embedded chip technology to form a high-density 3D stacked package. The PMIC chip, capacitor, and processor are vertically connected, shortening the connection path and addressing voltage and current shortages, power shortages, and heat dissipation issues associated with high-performance processors.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and more particularly to a high-density stacked packaging structure with integrated capacitors and PMIC chips and a packaging method. Background Art

[0002] Traditional processors, PMIC chips (Power Management ICs), and capacitors are connected horizontally through a PCB. This creates a long connection path, high resistance, and high losses, resulting in low voltage and significant parasitic effects, making it difficult to meet the high voltage and current requirements of high-performance processors.

[0003] High-performance processors often combine an HBM (High Bandwidth Memory) chip and a System on Chip (SOC) chip in a heterogeneous chip package. However, when integrating these high-performance processors with a power management microcontroller (PMIC) chip, the high power density and rapid current dynamics can lead to significant localized hotspots. Traditional packaging materials, such as organic substrates, have limited thermal conductivity, making efficient heat dissipation difficult, impacting system stability and lifespan. Summary of the Invention

[0004] In order to solve the above problems, the present invention provides a high-density stacked packaging structure and packaging method that integrates capacitors and PMIC chips. By vertically connecting the PMIC chip with the capacitor and the processor, the connection path is shortened, the resistance and connection loss are reduced, thereby increasing the voltage and current, and increasing the power. The heat sink is reasonably arranged and combined with a heat dissipation cover to effectively solve the heat dissipation problem and meet the requirements of high-performance processors.

[0005] According to one aspect of the present invention, a high-density stacked packaging structure integrating a capacitor and a PMIC chip is provided, comprising:

[0006] substrate;

[0007] Heterogeneous chips, including HBM chips and SOC chips;

[0008] A double-layer plastic-sealed through-hole interposer, wherein the double-layer plastic-sealed through-hole interposer is bonded to the substrate, and the heterogeneous chip is bonded to the double-layer plastic-sealed through-hole interposer;

[0009] The double-layer plastic-sealed through-hole interposer includes a bottom plastic-sealed through-hole embedded chip layer, a middle redistribution layer, and a top plastic-sealed through-hole embedded chip layer, which are arranged in sequence from bottom to top. A PMIC chip is arranged in the bottom plastic-sealed through-hole embedded chip layer, an LSI chip is arranged in the top plastic-sealed through-hole embedded chip layer, and a capacitor circuit is arranged inside the middle redistribution layer. Both the PMIC chip and the LSI chip have TSV through-holes. The LSI chip is interconnected with the middle redistribution layer and the heterogeneous chip through the two ends of the TSV through-hole, and the LSI chip is interconnected with the capacitor circuit. The PMIC chip is interconnected with the substrate and the middle redistribution layer through the two ends of the TSV through-hole, and the PMIC chip is interconnected with the capacitor circuit.

[0010] Therefore, the PMIC chip (PMIC, Power Management IC) and LSI chip (LSI, Large Scale Integrated circuit) are embedded in two layers of plastic packaging respectively, and the capacitor circuit and the middle redistribution layer are made in the upper and lower plastic packaging layers. Through TSV (Through Silicon Via) technology is used to realize vertical interconnection between the HBM chip (or SOC chip) and the LSI chip, capacitor circuit, PMIC chip, and substrate, shortening the connection path, reducing circuit and connection losses, increasing voltage and current, and improving power.

[0011] Preferably, a top redistribution layer is provided on top of the double-layer plastic-encapsulated through-hole interposer. The LSI chip is interconnected with the top redistribution layer and the heterogeneous chip in sequence through TSV vias. A bottom redistribution layer is provided at the bottom of the double-layer plastic-encapsulated through-hole interposer. The bottom redistribution layer is bonded to the substrate via a first solder ball. The PMIC chip is interconnected with the bottom redistribution layer and the substrate in sequence through TSV vias. Thus, by forming redistribution layers on both sides of the double-layer plastic-encapsulated through-hole interposer, wiring paths can be optimized, chip integration can be increased, high-density packaging can be achieved, and chip performance can be improved.

[0012] Preferably, tall copper pillars are provided in both the bottom and top plastic-encapsulated through-hole embedded chip layers. Both sides of the middle redistribution layer are interconnected with the tall copper pillars to achieve vertical interconnection between the heterogeneous chip and the substrate. The heterogeneous chip is then vertically interconnected with the capacitor circuit via the tall copper pillars. Thus, the tall copper pillars enable vertical interconnection between the HBM chip and the SOC chip and the substrate, as well as between the HBM chip and the SOC chip and the capacitor circuit, simplifying the packaging process, improving integration, and enhancing packaging reliability.

[0013] Preferably, the packaging structure further includes a heat dissipation cover having a top cover and dams around the top cover, the top cover being mounted on the heterogeneous chip, and the dams being mounted on the substrate, thereby dissipating heat through the heat dissipation cover.

[0014] Preferably, heat sinks are placed within both the double-layer plastic-encapsulated through-hole interposer and the substrate. One end of the substrate's heat sink connects to the heat sink of the double-layer plastic-encapsulated through-hole interposer, while the other end connects to the cofferdam of the heat dissipation cover. Thus, heat sinks are embedded within both plastic-encapsulated layers, connecting to the heat sink within the substrate to form a heat conduction channel. Heat can be transferred to the heat dissipation cover, effectively solving the heat dissipation problem and meeting the requirements of high-performance processors.

[0015] According to another aspect of the present invention, a packaging method is provided for preparing the high-density stacked packaging structure of the integrated capacitor and the PMIC chip, the method comprising:

[0016] Providing a temporary carrier, a substrate, a heterogeneous chip, an LSI chip, and a PMIC chip, wherein the heterogeneous chip includes an HBM chip and a SOC chip;

[0017] sputtering a metal seed layer onto a temporary carrier;

[0018] Fabricate the bottom plastic-encapsulated through-hole embedded chip layer: mount the PMIC chip on the metal seed layer and plastic-encapsulate the PMIC chip to form a bottom plastic-encapsulated layer;

[0019] Fabricate the middle redistribution layer: Process a capacitor circuit above the bottom plastic layer. The capacitor circuit is interconnected with the PMIC chip. A middle redistribution layer is formed above the bottom plastic layer. The middle redistribution layer covers the capacitor circuit.

[0020] Making a top plastic-encapsulated through-hole embedded chip layer: mounting an LSI chip on the middle redistribution layer, interconnecting the LSI chip with the capacitor circuit, and plastic-encapsulating the LSI chip to form a top plastic-encapsulated layer, exposing the TSV through-holes of the LSI chip;

[0021] The HBM chip and the SOC chip are mounted on the top plastic layer and then encapsulated to form an upper plastic layer. The HBM chip and the SOC chip are vertically interconnected with the LSI chip, the capacitor circuit, and the PMIC chip.

[0022] Remove the temporary carrier and metal seed layer to expose the TSV through-holes of the PMIC chip, forming a double-layer plastic-encapsulated through-hole interposer with the heterogeneous chip mounted;

[0023] Mount the double-layer plastic-encapsulated through-hole interposer on the substrate.

[0024] Furthermore, a top redistribution layer is fabricated above the top layer of chip buried in the plastic encapsulation through-holes, and the LSI chip is interconnected with the top redistribution layer and the heterogeneous chip in sequence through TSV through-holes; a bottom redistribution layer is fabricated at the bottom of the bottom layer of chip buried in the plastic encapsulation through-holes, and the PMIC chip is interconnected with the bottom redistribution layer and the substrate in sequence through TSV through-holes.

[0025] Furthermore, before mounting the PMIC chip, tall copper pillars are first made on the metal seed layer, the bottom plastic packaging layer covers the tall copper pillars, and the tall copper pillars are interconnected with the middle redistribution layer and the capacitor circuit; before mounting the LSI chip, tall copper pillars are first made on the middle redistribution layer, the top plastic packaging layer covers the tall copper pillars, and the tall copper pillars are interconnected with the middle redistribution layer and the capacitor circuit.

[0026] Furthermore, the tall copper pillars covered by the bottom plastic packaging layer are interconnected with the bottom redistribution layer, and the bottom redistribution layer is bonded to the substrate through solder balls.

[0027] Furthermore, after the PMIC chip is mounted, a heat sink is mounted on the metal seed layer, and the bottom plastic layer covers the heat sink; after the LSI chip is mounted, a heat sink is mounted on the middle redistribution layer, and the top plastic layer wraps the heat sink; there is a heat sink in the substrate, and after the packaging on the substrate is completed, a heat sink cover is mounted, and the heat sink in the substrate is connected to the heat sink cover and the heat sinks in each plastic layer.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows: this patent adopts plastic-encapsulated through-hole and plastic-encapsulated embedded chip technology to embed the PMIC chip and LSI chip into two layers of plastic encapsulation respectively. The capacitor circuit and the middle redistribution layer are processed in the middle of the two layers of plastic encapsulation by PECVD\CVD\RIE technology. The top and bottom of the two layers of plastic encapsulation are processed with redistribution layers. The top is connected to the SOC and HBM chips, and the bottom is connected to the substrate. A heat sink is buried in the middle of the two layers of plastic encapsulation. The heat sink and the heat dissipation channel of the substrate are connected to conduct heat, forming a high-density 3D stacked fan-out packaging structure. The PMIC chip is vertically connected to the capacitor and the processor, shortening the connection path, reducing resistance and connection loss, solving the voltage, current, power and heat dissipation problems of high-performance processors, thereby improving the performance of high-performance processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 This is a schematic diagram of the production process of PMIC chip packaging;

[0030] Figure 2 This is a schematic diagram of the process of manufacturing the capacitor circuit to the top plastic package through-hole embedded chip layer;

[0031] Figure 3 It is a schematic diagram of the manufacturing process from the top redistribution layer to the heterogeneous chip package;

[0032] Figure 4 This is a schematic diagram of the production process of the bottom redistribution layer;

[0033] Figure 5 It is a schematic diagram of the process of attaching the wafer to the substrate and attaching the heat dissipation cover;

[0034] Figure 6The present invention is a structural schematic diagram of an embodiment of a high-density stacked packaging structure and a packaging method for an integrated capacitor and a PMIC chip.

[0035] Figure numerals: substrate-1; second solder ball-11; double-layer plastic-encapsulated through-hole interposer-2; bottom plastic-encapsulated through-hole embedded chip layer-21; PMIC chip-211; first metal bump-2111; bottom plastic-encapsulated layer-212; middle redistribution layer-22; capacitor circuit-221; top plastic-encapsulated through-hole embedded chip layer-23; LSI chip-231; top plastic-encapsulated layer-232; TSV through-hole-201; bottom redistribution layer-3; first solder ball-31; top redistribution layer-4; heterogeneous chip-5; SOC chip-51; HBM chip-52; second metal bump-501; upper plastic-encapsulated layer-502; heat dissipation cover-6; top cover-61; cofferdam-62; tall copper pillar-7; heat sink-8; component-9; temporary carrier-100; metal seed layer-101. DETAILED DESCRIPTION

[0036] The present invention will be further described below in conjunction with specific embodiments.

[0037] An embodiment of the present invention provides a high-density stacked packaging structure integrating a capacitor and a PMIC chip and a packaging method thereof.

[0038] like Figure 6 As shown, a high-density stacked package structure integrating capacitors and PMIC chips includes: a substrate 1, a heterogeneous chip 5, and a double-layer plastic-encapsulated through-hole interposer 2. The double-layer plastic-encapsulated through-hole interposer 2 is bonded to the substrate 1, and the heterogeneous chip 5 is bonded to the double-layer plastic-encapsulated through-hole interposer 2. The heterogeneous chip 5 includes an HBM chip 52 (HBM, High Bandwidth Memory chip) and a SOC chip 51 (SOC, System on Chip).

[0039] The double-layer plastic-encapsulated through-hole interposer 2 includes, from bottom to top, a bottom plastic-encapsulated through-hole embedded chip layer 21, a middle redistribution layer 22, and a top plastic-encapsulated through-hole embedded chip layer 23. The bottom plastic-encapsulated through-hole embedded chip layer 21 is used to encapsulate a PMIC chip 211 (Power Management IC), which has TSVs (Through Silicon Vias). A bottom plastic-encapsulated layer 212 surrounds PMIC chip 211. The top plastic-encapsulated through-hole embedded chip layer 23 is used to encapsulate an LSI chip 231 (Large Scale Integrated Circuit), which has TSVs. A top plastic-encapsulated layer 232 surrounds LSI chip 231. A capacitor circuit 221 is machined above the chip layer 21 embedded in the bottom plastic encapsulation through-holes, and when the intermediate redistribution layer 22 is fabricated, the capacitor circuit 221 is wrapped in the intermediate redistribution layer 22. In this embodiment, the LSI chip 231 is located directly above the PMIC chip 211. The LSI chip 231 is interconnected with the intermediate redistribution layer 22 and the heterogeneous chip 5 via the ends of the TSV through-holes 201. The LSI chip 231 is also interconnected with the capacitor circuit 221. The PMIC chip 211 is also interconnected with the substrate 1 and the intermediate redistribution layer 22 via the ends of the TSV through-holes 201. The PMIC chip 211 is also interconnected with the capacitor circuit 221. The PMIC chip 211 and the LSI chip 231 are respectively embedded in two layers of plastic encapsulation. The capacitor circuit 221 and the intermediate redistribution layer 22 are fabricated in the upper and lower plastic encapsulation layers. TSV through-hole technology is used to vertically interconnect the HBM chip 52 and the SOC chip 51 with the LSI chip 231, the capacitor circuit 221, the PMIC chip 211, and the substrate 1.

[0040] A top redistribution layer 4 and a bottom redistribution layer 3 can be respectively made on the top and bottom of the double-layer plastic-encapsulated through-hole interposer 2, the HBM chip 52 and the SOC chip 51 are soldered to the top redistribution layer 4, and the bottom redistribution layer 3 is bonded to the substrate 1 through the first solder ball 31. In this way, the LSI chip 231 is interconnected with the top redistribution layer 4 and the heterogeneous chip 5 in sequence through the TSV through-hole 201, and the PMIC chip 211 is interconnected with the bottom redistribution layer 3 and the substrate 1 in sequence through the TSV through-hole 201.

[0041] In order to simplify the packaging process and provide vertical interconnection packaging reliability and integration, high copper pillars 7 are pre-embedded in the bottom plastic-encapsulated through-hole embedded chip layer 21 and the top plastic-encapsulated through-hole embedded chip layer 23, and the upper and lower surfaces of the middle redistribution layer 22 are respectively interconnected with the high copper pillars 7 on both sides to realize vertical interconnection between the heterogeneous chip 5 and the substrate 1, as well as vertical interconnection between the heterogeneous chip 5, the capacitor circuit 221, and the substrate 1.

[0042] In order to solve the heat dissipation problem and meet the application environment requirements of high-performance processors, a heat dissipation cover 6 is mounted on the packaging structure, and heat sinks 8 are arranged in both the double-layer plastic-sealed through-hole interposer 2 and the substrate 1. In the case of a bottom redistribution layer 3, a heat sink 8 also needs to be mounted in the bottom redistribution layer 3. The cross-sectional view of the heat sink 8 in the substrate 1 is similar to a U-shape. One end of the heat sink 8 of the board is connected to the heat sink 8 of the double-layer plastic-sealed through-hole interposer 2, and the other end of the heat sink 8 of the substrate 1 is connected to the cofferdam 62 of the heat dissipation cover 6. The inner wall of the top cover 61 of the heat dissipation cover 6 is adhered to the HBM chip 52 and the SOC chip 51. Therefore, the heat sink 8 is buried in the two layers of plastic sealing, and the heat sink 8 is connected to the heat sink 8 in the substrate 1 to form a heat conduction channel. The heat can be transferred to the heat dissipation cover 6 to achieve efficient heat dissipation.

[0043] Combine Figures 1 to 5 The packaging method of the high-density stacked packaging structure of the integrated capacitor and PMIC chip in this embodiment is specifically described. The detailed steps of the method are as follows:

[0044] A temporary carrier 100 , a substrate 1 , a heterogeneous chip 5 , an LSI chip 231 and a PMIC chip 211 are provided. The temporary carrier 100 is made of glass. The heterogeneous chip 5 includes an HBM chip 52 and an SOC chip 51 . The LSI chip 231 and the PMIC chip 211 have TSV through-holes 201 .

[0045] Step S01: Figure 1 As shown in FIG1A , a metal seed layer 101 is processed on a temporary carrier 100 by a sputtering process.

[0046] Step S02: On the metal seed layer 101, a high copper pillar 7 is processed by photolithography / electroplating process, such as Figure 1 As shown in Figure 1B.

[0047] Step S03: Mount the PMIC chip 211 on the wafer through a mounting process, such as Figure 1 As shown in Figure 1C.

[0048] Step S04: The heat sink 8 is mounted on the wafer through a mounting process. The heat sink 8 is distributed around the PMIC chip 211 and the high copper pillar 7. Figure 1 As shown in Figure 1D.

[0049] Step S05: Through the wafer plastic packaging process, the high copper pillar 7 and the PMIC chip 211 are plastic packaged, as shown in FIG. Figure 1 As shown in Figure 1E.

[0050] Step S06: The high copper pillar 7 and the first metal bump 2111 of the PMIC chip 211 are exposed by grinding and CMP process, and the bottom plastic packaging layer 212 is processed. Figure 1 As shown in 1F.

[0051] Step S07: Process the capacitor circuit 221 through PECVD, CVDC, and RIE processes. The capacitor circuit 221 is interconnected with the first metal bump 2111 and the high copper pillar 7 of the PMIC chip 211. Figure 2 As shown in 1G.

[0052] Step S08: Processing RDL (redistribution layer) by photolithography and electroplating process to complete the processing of the middle redistribution layer 22. The capacitor circuit 221 is located in the middle redistribution layer 22. Figure 2 As shown in 1H.

[0053] Step S09: Processing high copper pillars 7 on the middle redistribution layer 22 by photolithography and electroplating processes, such as Figure 2 As shown in Figure 1I.

[0054] Step S10: mount the LSI chip 231 (silicon bridge interconnect chip) on the wafer through the TCB process, and then mount the heat sink 8 on the wafer through the mounting process, as shown in FIG. Figure 2 As shown in Figure 1J.

[0055] Step S11: Encapsulate the LSI chip 231 and the tall copper pillar 7 by a plastic encapsulation process. Figure 2 As shown in 1K.

[0056] Step S12: The high copper pillar 7 and the TSV through hole 201 of the LSI chip 231 are exposed by grinding and CMP process, and the processing of the top plastic layer 232 is completed. Figure 2 As shown in 1L.

[0057] Step S13: Process the RDL (redistribution layer) through photolithography and electroplating processes to complete the processing of the top redistribution layer 4, such as Figure 3 As shown in 1M.

[0058] Step S14: soldering the HBM chip 52 and the SOC chip 51 onto the top redistribution layer 4 by TCB process, as shown in FIG. Figure 3 As shown in 1N.

[0059] Step S15: The second metal bumps 501 for welding the HBM chip 52 and the SOC chip 51 are covered and protected by the bottom dispensing process. Figure 3 As shown in Figure 1O.

[0060] Step S16: The wafer above the top redistribution layer 4 is encapsulated and protected by a plastic encapsulation process to form an upper plastic encapsulation layer 502. Figure 3 As shown in 1P.

[0061] Step S17: Debonding the bottom temporary carrier 100 through a debonding process, and then removing the bottom metal seed layer 101 through an etching process, as shown in FIG. Figure 4 As shown in 1Q.

[0062] Step S18: The TSV through-hole 201 at the bottom of the PMIC chip 211 is exposed by grinding and CMP process. Figure 4 As shown in 1S.

[0063] Step S19: Figure 4 As shown in 1T and 1U, RDL is processed on the surface of the bottom plastic layer 212 in which the PMIC chip 211 is embedded through photolithography and electroplating processes. The first solder ball 31 is implanted on the surface of the RDL to complete the processing of the bottom redistribution layer 3, and the heat sink 8 is mounted through the mounting process.

[0064] Step S20: solder the chip obtained in the above steps onto the substrate 1 through a flip-chip process. Figure 5 As shown in 1V.

[0065] Step S21: solder the components 9 onto the substrate 1 through the surface mount process, and then protect the metal soldering points through the bottom dispensing process. Figure 5 As shown in 1W.

[0066] Step S22: Through the cover process, the heat dissipation cover 6 is mounted on the substrate 1. The top of the HBM chip 52 and the SOC chip 51 has an adhesive to adhere to the top cover 61 of the heat dissipation cover 6. The cofferdam 62 of the heat dissipation cover 6 is adhered to the substrate 1 with an adhesive. Figure 5 As shown in 1X.

[0067] Step S23: Place the second solder ball 11 and the component 9 on the back of the substrate 1 through the surface mounting process and the ball planting process. Figure 5 As shown in Figure 1Y.

[0068] In the specific steps of the above packaging method, whether to manufacture the bottom redistribution layer 3 and the top redistribution layer 4, as well as the specific design of the high copper pillars 7 and the heat sink 8 can be selectively considered according to the actual design of the packaging structure.

[0069] The present application adopts plastic-encapsulated through-hole and plastic-encapsulated embedded chip technology to embed the PMIC chip 211 and the LSI chip 231 into two layers of plastic-encapsulated layers respectively. The capacitor circuit 221 and the middle redistribution layer 22 are processed in the middle of the two layers of plastic-encapsulated layers by PECVD\CVD\RIE technology, forming a double-layer plastic-encapsulated through-hole interposer 2 with a top layer of plastic-encapsulated through-hole embedded chip layer 23, a middle redistribution layer 22 and a bottom layer of plastic-encapsulated through-hole embedded chip layer 21; and redistribution layers are processed on the top and bottom of the two layers of plastic-encapsulated layers, the top is connected to the SOC and HBM chips, and the bottom is connected to the substrate 1; and the two layers of plastic-encapsulated layers High copper pillars 7 and heat sinks 8 are embedded in the middle to achieve a high-density 3D stacked fan-out packaging structure, so that the HBM chip 52 / SOC chip 51 is vertically interconnected with the LSI chip 231, the capacitor circuit 221, and the PMIC chip 211, shortening the connection path, reducing resistance and connection loss, and solving the voltage and current shortage and power shortage problems of high-performance processors. The heat sink 8 in this double-layer plastic-sealed through-hole interposer 2 is connected to the heat dissipation channel of the substrate 1 to conduct heat to the heat dissipation cover 6, achieving effective heat dissipation, meeting the application environment requirements of high-performance processors, and greatly improving product performance.

[0070] The above are only some embodiments of the present invention. It should be pointed out that for ordinary technicians in this field, other variations and improvements can be made without departing from the creative concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A high-density stacked packaging structure integrating capacitors and PMIC chips, characterized in that: include: substrate; Heterogeneous chips, including HBM chips and SOC chips; A double-layer plastic-sealed through-hole interposer, wherein the double-layer plastic-sealed through-hole interposer is bonded to the substrate, and the heterogeneous chip is bonded to the double-layer plastic-sealed through-hole interposer; The double-layer plastic-sealed through-hole interposer includes a bottom plastic-sealed through-hole embedded chip layer, a middle redistribution layer, and a top plastic-sealed through-hole embedded chip layer, which are arranged in sequence from bottom to top. A PMIC chip is provided in the bottom plastic-sealed through-hole embedded chip layer, an LSI chip is provided in the top plastic-sealed through-hole embedded chip layer, a capacitor circuit is provided inside the middle redistribution layer, the PMIC chip and the LSI chip both have TSV through-holes, the LSI chip is interconnected with the middle redistribution layer and the heterogeneous chip through the two ends of the TSV through-holes, the LSI chip is interconnected with the capacitor circuit, the PMIC chip is interconnected with the substrate and the middle redistribution layer through the two ends of the TSV through-holes, and the PMIC chip is interconnected with the capacitor circuit; The heat dissipation cover has a top cover and cofferdams on all sides. The top cover is mounted on the heterogeneous chip, and the cofferdams are mounted on the substrate. Heat sinks are arranged in the double-layer plastic-sealed through-hole interposer and the substrate. One end of the heat sink of the substrate is connected to the heat sink of the double-layer plastic-sealed through-hole interposer, and the other end of the heat sink of the substrate is connected to the cofferdam of the heat dissipation cover.

2. The packaging structure according to claim 1, wherein: A top redistribution layer is provided on the top of the double-layer plastic-sealed through-hole interposer, and the LSI chip is interconnected with the top redistribution layer and the heterogeneous chip in sequence through TSV through-holes. A bottom redistribution layer is provided on the bottom of the double-layer plastic-sealed through-hole interposer, and the bottom redistribution layer is bonded to the substrate through a first solder ball. The PMIC chip is interconnected with the bottom redistribution layer and the substrate in sequence through TSV through-holes.

3. The packaging structure according to claim 2, wherein: The bottom layer of chip embedded in plastic-sealed through-holes and the top layer of chip embedded in plastic-sealed through-holes are both provided with high copper pillars. Both sides of the middle redistribution layer are interconnected with the high copper pillars to realize vertical interconnection between the heterogeneous chip and the substrate. The heterogeneous chip is vertically interconnected with the capacitor circuit through the high copper pillars.

4. A packaging method for a high-density stacked packaging structure integrating a capacitor and a PMIC chip, characterized in that: The method comprises: Providing a temporary carrier, a substrate, a heterogeneous chip, an LSI chip, and a PMIC chip, wherein the heterogeneous chip includes an HBM chip and a SOC chip; sputtering a metal seed layer onto a temporary carrier; Fabricate the bottom plastic-encapsulated through-hole embedded chip layer: mount the PMIC chip on the metal seed layer, mount a heat sink on the metal seed layer, and plastic-encapsulate the PMIC chip and heat sink to form a bottom plastic-encapsulated layer; Fabricate the middle redistribution layer: Process a capacitor circuit above the bottom plastic layer. The capacitor circuit is interconnected with the PMIC chip. A middle redistribution layer is formed above the bottom plastic layer. The middle redistribution layer covers the capacitor circuit. Fabricate a top plastic-encapsulated through-hole embedded chip layer: mount an LSI chip on the middle redistribution layer, interconnect the LSI chip with the capacitor circuit, mount a heat sink on the middle redistribution layer, and plastic-encapsulate the LSI chip and the heat sink to form a top plastic layer, exposing the TSV through-holes of the LSI chip; The HBM chip and the SOC chip are mounted on the top plastic layer and then encapsulated to form an upper plastic layer. The HBM chip and the SOC chip are vertically interconnected with the LSI chip, the capacitor circuit, and the PMIC chip. Remove the temporary carrier and metal seed layer to expose the TSV through-holes of the PMIC chip, forming a double-layer plastic-encapsulated through-hole interposer with the heterogeneous chip mounted; Mounting a double-layer plastic-encapsulated through-hole interposer on a substrate having a heat sink inside the substrate; After the packaging on the substrate is completed, the heat dissipation cover is mounted, and the heat sink in the substrate is connected to the heat dissipation cover and the heat sinks in each plastic sealing layer.

5. The packaging method according to claim 4, wherein: A top redistribution layer is fabricated above the chip layer embedded in the top plastic-encapsulated through-holes, and the LSI chip is interconnected with the top redistribution layer and the heterogeneous chip in sequence through TSV through-holes; a bottom redistribution layer is fabricated at the bottom of the chip layer embedded in the bottom plastic-encapsulated through-holes, and the PMIC chip is interconnected with the bottom redistribution layer and the substrate in sequence through TSV through-holes.

6. The packaging method according to claim 5, characterized in that: Before mounting the PMIC chip, tall copper pillars are first made on the metal seed layer, and the bottom plastic packaging layer covers the tall copper pillars. The tall copper pillars are interconnected with the middle redistribution layer and the capacitor lines. Before mounting the LSI chip, tall copper pillars are first made on the middle redistribution layer, and the top plastic packaging layer covers the tall copper pillars. The tall copper pillars are interconnected with the middle redistribution layer and the capacitor lines.

7. The packaging method according to claim 6, wherein: The high copper pillars covered by the bottom plastic packaging layer are interconnected with the bottom redistribution layer, and the bottom redistribution layer is bonded to the substrate through solder balls.

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