Axial lead packaging structure

Abstract

The invention discloses an axial lead packaging structure for a semiconductor device. The structure includes a metal oxide varistor component, a voltage suppression component coupled to the metal oxide varistor component and including a semiconductor chip and one or more conductive bumps coupled to the semiconductor chip, a lead frame coupled to the metal oxide varistor component and another lead frame coupled to the voltage suppression component.

Description

Technical Field

[0001] The present disclosure generally relates to the field of power semiconductor discrete devices, and in particular, to axial lead packages for use with various semiconductor device components, including but not limited to metal oxide varistors, thyristors (e.g., SIDACTor protected thyristors), and other devices. Background Art

[0002] Discrete semiconductors are devices designated to perform basic electronic functions and are indivisible into separate elements that are functional in themselves. Power semiconductors are used as switches or rectifiers in power electronic devices. Diodes, transistors, thyristors, and rectifiers are examples of discrete power semiconductors. Discrete power semiconductors are present in a variety of different environments, from very low power systems to very high power systems.

[0003] Packaging integrated circuits is typically the final stage of the semiconductor device manufacturing process. During packaging, the semiconductor die, which represents the core of the semiconductor device, is encapsulated in a housing that protects the die from physical damage and corrosion. For example, the semiconductor die is typically mounted on a copper substrate using solder alloy reflow, conductive epoxy, etc. The mounted semiconductor die is then typically encapsulated in plastic or epoxy. However, existing packaging technologies do not provide sufficient flexibility to create various lead connections and thus result in devices consuming a large area of the printed circuit board. Summary of the Invention

[0004] In some embodiments, the current subject matter relates to an axial lead package structure. The structure can include a metal oxide varistor component; a voltage suppression component coupled to the metal oxide varistor component, the voltage suppression component including a semiconductor chip and one or more conductive bumps coupled to the semiconductor chip; a lead frame coupled to the metal oxide varistor component; and another lead frame coupled to the voltage suppression component.

[0005] In some embodiments, the current subject matter may include one or more of the following optional features. In some embodiments, one or more conductive bumps may include a first conductive bump and a second conductive bump, and a semiconductor chip is positioned between the first conductive bump and the second conductive bump and is coupled to the first conductive bump and the second conductive bump. One side of the first conductive bump may be coupled to a metal oxide varistor component and the other side of the first conductive bump may be coupled to the semiconductor chip. A lead frame may be coupled to a linker terminal, and another lead frame may be coupled to another linker terminal. One side of the second conductive bump may be coupled to the semiconductor chip and the other side of the second conductive bump may be coupled to another linker terminal. Another lead frame may be coupled to a voltage suppression component using another linker terminal. The lead frame may be coupled to the metal oxide varistor component using a linker terminal.

[0006] In some embodiments, the semiconductor chip may include a semiconductor chip working area. One or more conductive bumps may be configured to be coupled to the semiconductor chip working area.

[0007] In some embodiments, one or more conductive bumps may include at least one of the following: copper bumps, metal bumps, silver bumps, copper alloy bumps, metal alloy bumps, silver alloy bumps, and / or any combination thereof.

[0008] In some embodiments, the structure may include a housing. The housing may be configured to encapsulate at least one of the metal oxide varistor component and the voltage suppression component. The housing may be configured to at least partially encapsulate at least one of the lead frame and another lead frame. The housing may be made of at least one of the following: epoxy compounds, plastics, and any combination thereof.

[0009] In some embodiments, the lead frame may include a lead frame terminal end and another lead frame includes another lead frame terminal end. The lead frame terminal end and another lead frame terminal end may be configured to be coupled to at least one of the following: a substrate, a printed circuit board, and any combination thereof.

[0010] In some embodiments, the voltage suppression component may include at least one of the following: a SIDACTor device, a thyristor, and any combination thereof.

[0011] In some embodiments, the present subject matter relates to a method for fabricating an axial lead package structure for a semiconductor device. The method may include providing a metal oxide varistor component; providing a voltage suppression component including a semiconductor chip and one or more conductive bumps coupled to the semiconductor chip; coupling the voltage suppression component to the metal oxide varistor component; coupling a lead frame to the metal oxide varistor component; and coupling another lead frame to the voltage suppression component.

[0012] Details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate certain aspects of the subject matter disclosed herein and, together with the description, help explain some of the principles associated with the disclosed embodiments. In the drawings,

[0014] Figures 1a - 1b an exemplary axial lead package structure in accordance with some embodiments of the present subject matter is shown;

[0015] Figures 2a - 2b the structure shown in the absence of a protective housing in accordance with some embodiments of the present subject matter is shown; Figures 1a - 1b is shown;

[0016] Figures 3a - 3c an example of a MOV component in accordance with some embodiments of the present subject matter is shown;

[0017] Figures 4a - 4b an example of a voltage suppression component in accordance with some embodiments of the present subject matter is shown;

[0018] Figures 5a - 5b an example of an exemplary bump in accordance with some embodiments of the present subject matter is shown;

[0019] Figures 6a - 6b an example of a semiconductor chip in accordance with some embodiments of the present subject matter is shown;

[0020] Figure 7 an exemplary process in accordance with some embodiments of the present subject matter is shown.

[0021] The drawings are not necessarily to scale. The drawings are merely illustrative and are not intended to depict specific parameters of the disclosure. The drawings are intended to depict exemplary embodiments of the subject matter and are therefore not to be considered as limiting the scope. In the drawings, like numerals represent like elements.

[0022] In addition, for clarity, some components in some of the figures may be omitted and / or not drawn to scale. Cross-sectional views may be in the form of "slices" or "near-sighted" cross-sectional views, and for clarity, some background lines that would otherwise be visible in a "true" cross-sectional view are omitted. In addition, for clarity, some reference numerals may be omitted in some of the drawings. Detailed Description

[0023] Various methods in accordance with the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of systems and methods are shown. Devices, systems, components, etc. may be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the current subject matter to those skilled in the art.

[0024] To address these and potential other deficiencies of currently available solutions, one or more embodiments of the current subject matter relate to methods, systems, articles of manufacture, etc., which, among other possible advantages, may provide axial lead packages for use with various semiconductor device components, various semiconductor devices including but not limited to metal oxide varistors, thyristors (such as SIDACTor protection thyristors), and other devices.

[0025] A voltage transient is defined as a short-duration surge of electrical energy and is the result of a sudden release of previously stored and / or otherwise induced energy (such as, for example, in a highly inductive load, lightning, etc.). Voltage transients can be classified as predictable or repeatable transients and random transients. In an electrical or electronic circuit, such energy can be released in a predictable manner via a controlled switching action or randomly induced into the circuit from an external source. Repeatable transients are often caused by the operation of motors, generators, and / or the switching of reactive circuit components. On the other hand, random transients are typically caused by electrostatic discharge (ESD) and lightning, which generally occur unpredictably.

[0026] ESD is characterized by very fast rise times and very high peak voltages and currents, which can be the result of an imbalance of positive and negative charges between objects. ESD generated by daily activities can exceed the vulnerability thresholds of standard semiconductor technologies. In the case of lightning, even though the direct strike is destructive, the voltage transients caused by lightning are not the result of the direct strike. When a lightning strike occurs, the event generates a magnetic field, which in turn induces a relatively large voltage transient in nearby cables. For example, cloud-to-cloud strikes can affect not only overhead cables but also buried cables. Even a strike 1 mile (1.6 km) away can generate 70 volts of voltage in a cable. In cloud-to-ground strikes, the voltage transient effects are significantly greater.

[0027] In some embodiments, to protect sensitive electronic components from surge currents, various surge protection devices (SPDs) can be used. An SPD can include a hybrid combination of a metal oxide varistor (MOV) unit and a SIDACTor protection thyristor. SIDACTor devices (such as those that can be obtained from Littelfuse, Inc., Chicago, Illinois, USA) can be designed to suppress overvoltage transients in various electronic devices (e.g., telecommunications, data communication, etc. devices) and can be capable of shunting currents of up to 5000 A to ground within nanoseconds of reaching their breakdown voltage.

[0028] Due to their hybrid nature, such SPD devices can be capable of providing protection for surge voltages greater than 6000 V and currents exceeding 3000 A. Due to their high energy handling density, these devices consume a single area of a printed circuit board (PCB), as opposed to some existing devices that typically require more space and thus involve additional costs. Some SPDs can be used in automotive, aerospace, and other applications and environments. For example, an SPD can provide power management and subsystem protection from an automotive passenger safety circuit and protect such circuits from high-energy transient pulses.

[0029] SIDACTor devices can be used for protection against peak current pulses. A SIDACTor device can be a solid-state crowbar device, which can be designed to protect equipment located in harsh environments from overvoltage transient currents within nanoseconds. In particular, a SIDACTor device can be a PNPN device, which can be similar to a thyristor device but without a gate. When the peak off-state voltage is exceeded, the SIDACTor device may clamp the transient voltage at the switching voltage (V S)Within the rated value. Once the current flowing through the SIDACTor device exceeds its switching current, the device can short-circuit (crowbar) and simulate a short-circuit condition. When the current flowing through the SIDACTor device is less than the holding current (I H ), the SIDACTor device can reset and return to its high-off-state impedance. The SIDACTor device provides fast response time, stable electrical characteristics, long-term reliability, and low capacitance. In addition, since the SIDACTor device is a crowbar device, it cannot be damaged by voltage. The SIDACtor device can be used as the main overvoltage protector in telecommunications and / or data communication circuits.

[0030] MOV devices can be used to protect circuits that typically experience high surge currents and provide energy handling capabilities to absorb transient overvoltages. MOV devices can also be clamping devices with two leads for assembly in a typical PCB. MOV devices can be two-lead, through-hole components that can be formed in the form of a disc. These devices can be similar or equivalent to back-to-back PN junctions, where the MOV device shunts transient current by reducing its resistance when voltage is applied. MOV devices can be used as clamping devices to provide transient protection in secondary AC line applications.

[0031] In some embodiments, the current subject matter relates to an axial lead package structure for protecting a device (e.g., an SPD device), which may include an MOV component, a SIDACTor component (and / or any other voltage suppression component), and copper bumps that can be positioned between the MOV component and the SIDACTor component to allow for faster heat dissipation between the two components. In addition, the axial lead package structure can implement an axial bond between the SIDACTor component and the MOV component. This can allow for a robust structure to cover a larger MOV component and a smaller SIDACTor component, where the SIDACTor component is positioned within the boundary of the MOV component. One of the benefits of the axial lead package structure of the current subject matter is that it can be configured to increase the available PCB space by allowing additional SPD devices to be positioned on the PCB. In addition, the design of this axial lead package can be configured to prevent the occurrence of parasitic capacitance and inductance for the PCB circuit that may be caused by multiple SPD devices.

[0032] Figures 1a - 1b An example of an axial lead package structure 100 according to some embodiments of the current subject matter is shown. Figures 1a - 1b is a perspective view of the structure 100 showing two sides of the structure 100, where Figure 1a shows the side having the MOV component (package) and Figure 1b shows the opposite side.

[0033] Structure 100 may include a metal oxide varistor (MOV) component 102, one or more leads 104(a, b), and a voltage suppression component (e.g., SIDACTor) 106. The MOV component 102 and the voltage suppression component 106 may be encapsulated in a protective housing 103. Additionally, at least a portion of the leads 104(a, b) may likewise be respectively encapsulated in protective housings 105(a, b). The protective housing may be made of any desired material. The protective housing 103 and the housings 105(a, b) may be separate housings. Alternatively or additionally, the housings 103 and 105 may form an integral housing. The housings 103, 105 may be used to protect the internal components of the structure 100, such as the MOV component 102, the voltage suppression component 106, and at least a portion of the leads 104 coupled to the respective MOV component 102 and voltage suppression component 106.

[0034] In addition, the housing 103 may be molded around the MOV component 102 (which may have a barbell shape, as Figures 1a - 1b shown, and / or any other shape) and the voltage suppression component 106. The housing 105 may likewise be molded around portions of the respective leads 104, with other portions of the leads 104 being exposed and not covered by the housing 105. The housing 103 and / or 105 may have any desired thickness, density, and / or any other structural features designed to protect the components 102 and 106.

[0035] As Figures 1a - 1b shown, the leads 104 may be configured to project substantially vertically away from the respective connection points to the MOV component 102 and / or the voltage suppression component 106. The leads 104 may also be bent and / or curved such that the exposed portions of the leads 104 may be used to couple the structure 100 to a printed circuit board (PCB) ( Figures 1a - 1b not shown in the figure). The leads 104 may be made of a conductive material, such as for example but not limited to copper, silver, metal, copper alloy, silver alloy, metal alloy, etc., and / or any combination thereof.

[0036] Figures 2a - 2b Figure shows the structure 100 without the protective housings 103, 105 according to some embodiments of the present subject matter Figures 1a - 1b as shown. Figures 2a - 2b is a perspective view of the structure 100 showing two sides of the structure 100, where Figure 2a the side having the MOV component is shown and Figure 2b the opposite side thereof is shown.

[0037] As Figures 2a - 2bAs shown, the structure 100 may include a MOV component 102, leads 104(a, b), and a voltage suppression component 106. The leads 104 may be coupled to components 102, 106 using linker terminals 210(a, b). In particular, lead 104a may be coupled to linker terminal 210a, where linker terminal 210a may be coupled to the MOV component 102 using solder 216. Lead 104b may be coupled to linker terminal 210b, where linker terminal 210b may be coupled to the voltage suppression component 106 using solder 208. The linker terminals 210 may be made of a conductive material such as, for example but not limited to, copper, silver, metal, copper alloy, silver alloy, metal alloy, etc., and / or any combination thereof.

[0038] Each of the leads 104(a, b) may be configured to include a respective lead protection region 212(a, b). In particular, lead 104a may include a lead protection region 212a. The lead protection region 212a may include a first portion 218a that extends substantially vertically away from the linker terminal 210a, a second portion 220a that curves away from the first portion 218a, and a third portion 222a that is configured to extend substantially vertically away from the first portion 218a. Similarly, the lead protection region 212b may include a first portion 218b that extends substantially vertically away from the linker terminal 210b, a second portion 220b that curves away from the first portion 218b, and a third portion 222b that is configured to extend substantially vertically away from the first portion 218b. The protection regions 212 may be configured to provide sufficient space to the structure 100 during operation.

[0039] Figures 3a - 3b An example of the MOV component 102 according to some embodiments of the current subject matter is shown. The MOV component 102 may be any type of known metal oxide varistor. Each side of the MOV component 102 may include an intermediate metal linker 302(a, b) and a respective outer ring 304(a, b). In particular, the outer ring 304a may be disposed around the perimeter of the intermediate metal linker 302a. The intermediate metal linker 302a may be coupled to the linker terminal 210a, as Figures 2a - 2b shown. The outer ring 304b may be disposed around the perimeter of the intermediate metal linker 302b. The intermediate metal linker 302b may be coupled to the component 106, as Figures 2a - 2b shown.

[0040] Figure 3c Another example of the MOV component 306 according to some embodiments of the current subject matter is shown. Only one side of the MOV component 306 is shown for ease of discussion. The opposite side of the MOV component 306 may be similar to Figure 3cOne of those shown in []. The MOV component 306 may include an intermediate metal linker 312 and an outer ring 314 disposed around the intermediate metal linker 312.

[0041] Referring back Figures 2a - 2b and referring Figures 4a - 4b , the voltage suppression component 106 may include a first bump 202, a second bump 206, and a chip 204. The first bump 202 may be coupled to the chip 206 using solder ( Figures 2a - 2b not shown in []). The chip 206 may be coupled to the second bump 204 using solder ( Figures 2a - 2b not shown in []). The first bump 202 may also be coupled to the MOV component 102 using solder 402 (as Figure 4b shown). The second bump 204 may be coupled to the linker terminal 210b using solder 208 (as Figure 2a and Figure 4a shown). The bumps 202 and 204 may be conductive bumps. As a non-limiting example, the bumps 202, 204 may be copper, silver, metal, copper alloy, silver alloy, metal alloy, and / or any other metallic, composite bump.

[0042] Figures 5a - 5b Examples of bumps 502 and 504 according to some embodiments of the present subject matter are shown. The bump 502 may be similar to the bumps 202, 204 shown in FIGS. 2 and Figures 4a - 4b . The bump 504 shown as Figure 5b may have a different shape (e.g., circular) from the bump 502. As can be appreciated, the bumps may have any desired shape, e.g., square, circular, oval, etc. Each of the bumps 502, 504 may have its own shape, thickness, and / or be made of a material that may be different for the other bump. Alternatively or additionally, each of the bumps 502, 504 may be the same as the other bumps. The bumps 502, 504 may be made of a conductive material such as, for example but not limited to, copper, silver, metal, copper alloy, silver alloy, metal alloy, etc., and / or any combination thereof.

[0043] Figures 6a - 6b Examples of chips 602, 604 that may be part of the voltage suppression component 106 according to some embodiments of the present subject matter are shown. The chip 602 may be similar to the chip 206 shown in Figure 2a and Figures 4a - 4b . The chips 602, 604 may be any type of semiconductor device, e.g., SIDACTor chips, thyristors, and / or any other type of chip that may be used to protect electronic components from transient voltages, overvoltages, etc.

[0044] As Figure 6aAs shown, the chip 602 may include a chip top portion 601, a chip middle portion 603, and a chip bottom portion 605. The chip top portion 601 (and the chip bottom portion 605) may include a chip working area 607 and a chip support area 609. The chip middle portion 603 may be disposed between the chip top portion 601 and the chip bottom portion 603. The chip support area 609 may be disposed near the chip working area 607 and / or may be coupled to the chip working area 607. The chip working area 607 may be enclosed by a chip protection area 609 and may be used to locate and / or couple various electronic components associated with the chip 602 (e.g., the bumps 202 and 206 may be coupled to the chip 602 using solder). The chip protection area 609 may be further enclosed by a chip protection ring ( Figure 6a not shown in

[0045] Although not shown in Figure 6a it, the chip bottom portion of the chip 602 may be constructed similarly to its top portion. For example, the chip bottom portion may similarly include a chip bottom working area and a chip bottom protection area. The chip bottom working area may be enclosed by a chip bottom protection ring and may be used to locate and / or couple various electronic components associated with the chip 602.

[0046] The chip 602 may be used in various electronic applications, such as, for example, in multi-point data transfer devices, systems, etc., where the chip 602 may be configured as, for example, a SIDACTor chip, a thyristor, and / or any other type of chip. The chip 602 may be used to prevent voltage transients that may be harmful to the operation of various electronic components.

[0047] Figure 6b An example chip 604 is shown. The chip 604 may be similar to the chip 602. However, it may include a smaller working area 611 and a larger protection area 613. Additionally, the working area 611 may be disposed in a portion of the chip 604, while the remaining area of the chip 604 may be consumed by the protection area 613.

[0048] In some embodiments, as discussed above and Figures 1a - 6bThe axial lead package structure 100 shown in [Figure] can be used to provide high power while having an overall small size. For example, the package structure can be used in a printed circuit board (PCB) to protect various electronic components from ESD, electrical fast transient (EFT), lightning, and / or any other transients. The package structure of the current subject can allow surface mounting of electronic components and optimization of the space on the PCB (where such components can be mounted on the PCB). It can also be further characterized by a small profile, improved clamping ability, and other enhanced features.

[0049] Figure 7 An exemplary process 700 for fabricating and / or manufacturing a lead package structure for a semiconductor device according to some embodiments of the current subject is shown. The process 700 can be used to fabricate and / or assemble the structure 100 described and discussed above in connection with Figures 1a - 6b the structure shown. The process 700 can be used to fabricate / assemble any type of axial lead structure.

[0050] At 702, a metal oxide varistor component (e.g., the MOV component 102 as shown in Figures 2a - 2b [Figure]) can be provided. The MOV component can be any type of known metal oxide varistor. Each side of the MOV component can include an intermediate metal linker and a corresponding outer ring.

[0051] At 704, a voltage suppression component can be provided. The voltage suppression component (e.g., Figures 2a - 2b the component 106 as shown in [Figure]) can include a semiconductor chip (e.g., chip 206) and one or more conductive bumps (e.g., bumps 202, 204) coupled to the semiconductor chip. The conductive bumps can include a first conductive bump and a second conductive bump. The semiconductor chip can be positioned between the first conductive bump and the second conductive bump and be coupled to the first conductive bump and the second conductive bump. Additionally, one side of the first conductive bump can be coupled to the metal oxide varistor component, and the other side of the first conductive bump can be coupled to the semiconductor chip.

[0052] The semiconductor chip can include a semiconductor chip working area. The conductive bumps can be configured to be coupled to the semiconductor chip working area. Additionally, the conductive bumps can include at least one of the following: copper bumps, metal bumps, silver bumps, copper alloy bumps, metal alloy bumps, silver alloy bumps, and / or any combination thereof.

[0053] At 706, a voltage suppression component can be coupled to a metal oxide varistor component (e.g., using solder). At 708 and 710, respectively, a lead frame can be coupled to the metal oxide varistor component, and another lead frame can be coupled to the voltage suppression component. For example, a lead frame can be coupled to a linker terminal, and another lead frame can be coupled to another linker terminal. One side of the second conductive bump can be coupled to the semiconductor chip and the other side of the second conductive bump can be coupled to another linker terminal. Such other lead frames can be coupled to the voltage suppression component using such other linker terminals. The lead frame can be coupled to the metal oxide varistor component using the linker terminal.

[0054] In some embodiments, a lead frame can include a lead frame terminal end, and another lead frame can include another lead frame terminal end. The lead frame terminal end and the other lead frame terminal end can be configured to be coupled to at least one of the following: a substrate, a printed circuit board, and any combination thereof.

[0055] In some embodiments, the structure can include a housing. The housing can be configured to encapsulate at least one of the metal oxide varistor component and the voltage suppression component. The housing can be configured to at least partially encapsulate at least one of the lead frame and the other lead frame. The housing can be made of at least one of the following: epoxy compounds, plastics, and any combination thereof.

[0056] In some embodiments, the voltage suppression component can include at least one of the following: a SIDACTor device, a thyristor, and any combination thereof.

[0057] The components and features of the devices described above can be implemented using any combination of discrete circuits, application-specific integrated circuits (ASICs), logic gates, and / or single-chip architectures. Additionally, the features of the devices can be implemented using a microcontroller, a programmable logic array, and / or a microprocessor or any combination of the foregoing, where appropriate. It should be noted that hardware, firmware, and / or software elements can be collectively or individually referred to herein as "logic" or "circuitry".

[0058] It will be appreciated that the exemplary devices shown in the block diagrams described above can represent a functional descriptive example of many potential embodiments. Thus, the partitioning, omission, or inclusion of the block functions depicted in the figures does not imply that the hardware components, circuitry, software, and / or elements for implementing these functions will necessarily be partitioned, omitted, or included in an embodiment.

[0059] Some embodiments may be described using the recitations "one embodiment" or "an embodiment" along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" (or its derivatives) in various places in the specification are not necessarily all referring to the same embodiment. Moreover, unless otherwise noted, the features described above are considered to be able to be used in any combination together. Thus, any feature discussed separately can be employed in combination with one another, unless it is noted that the features are incompatible with each other.

[0060] It is emphasized that the abstract of the disclosure is provided to enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Further, in the foregoing detailed description, it can be seen that for the purposes of simplifying the disclosure, various features are grouped together in a single embodiment. The method of the disclosure should not be construed as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as reflected in the following claims, the inventive subject matter lies in less than all of the features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, where each claim stands on its own as a separate embodiment. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein". Moreover, the terms "first", "second", "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects. The use of the terms "comprising", "including", or "having" and their variants herein is intended to cover the items listed thereafter and their equivalents as well as additional items. Thus, the terms "comprising", "including", or "having" and their variants are open-ended expressions and may be used interchangeably herein.

[0061] Examples of the disclosed architectures have been described above. Of course, it is not possible to describe every conceivable combination of components and / or methods, but one of ordinary skill in the art will recognize that many further combinations and permutations are possible. Thus, the novel architectures are intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.

[0062] The foregoing description of the example embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the disclosure. It is intended that the scope of the disclosure not be limited by this detailed description, but rather by the appended claims. Future filed applications claiming the priority of this application may claim the disclosed subject matter in a different manner and may generally include any subset of one or more of the limitations as disclosed herein or otherwise evidenced.

[0063] All directional references (e.g., proximal, distal, above, below, upward, downward, left, right, lateral, longitudinal, front, back, top, bottom, over, under, vertical, horizontal, radial, axial, clockwise, and counterclockwise) are for identification purposes only to assist the reader in understanding the disclosure. The directional references do not impose limitations, particularly as to the position, orientation, or use of the disclosure. Unless otherwise stated, connection references (e.g., attached, coupled, connected, and joined) should be construed broadly and may include intermediate members between elements and relative movement between elements. Thus, a connection reference does not necessarily infer that two elements are directly connected and in a fixed relationship to each other.

[0064] Furthermore, identification references (e.g., primary, secondary, first, second, third, fourth, etc.) are not intended to imply importance or priority but rather to distinguish one feature from another. The drawings are for illustrative purposes only, and the dimensions, positions, orders, and relative dimensions reflected in the drawings may vary.

[0065] The disclosure is not limited in scope by the specific embodiments described herein. Indeed, various other embodiments and modifications of the disclosure will be apparent to those of ordinary skill in the art from the foregoing description and the accompanying drawings. Accordingly, such other embodiments and modifications are intended to fall within the scope of the disclosure. In addition, the disclosure has been described herein in the context of a particular embodiment for a particular purpose in a particular environment. Those of ordinary skill in the art will recognize that the usefulness is not limited thereto and that the disclosure may be beneficially implemented for any number of purposes in any number of environments. Accordingly, the claims set forth below are to be interpreted in view of the full breadth and spirit of the disclosure as described herein.

Claims

1. An apparatus, comprising: Metal oxide varistor component; A voltage suppression component coupled to the metal oxide varistor component, the voltage suppression component including a semiconductor chip and one or more conductive bumps coupled to the semiconductor chip; A lead frame coupled to the metal oxide varistor component; And Another lead frame coupled to the voltage suppression component.

2. The apparatus according to claim 1, wherein, The one or more conductive bumps include a first conductive bump and a second conductive bump, and the semiconductor chip is positioned between the first conductive bump and the second conductive bump and coupled to the first conductive bump and the second conductive bump.

3. The apparatus according to claim 2, wherein, One side of the first conductive bump is coupled to the metal oxide varistor component and the other side of the first conductive bump is coupled to the semiconductor chip.

4. The apparatus according to claim 2, wherein, The lead frame is coupled to a linker terminal, and the other lead frame is coupled to another linker terminal.

5. The apparatus according to claim 4, wherein, One side of the second conductive bump is coupled to the semiconductor chip and the other side of the second conductive bump is coupled to the other linker terminal, wherein the other lead frame is coupled to the voltage suppression component using the other linker terminal.

6. The apparatus according to claim 4, wherein, The lead frame is coupled to the metal oxide varistor component using the linker terminal.

7. The apparatus according to claim 1, wherein, The semiconductor chip includes a semiconductor chip working area.

8. The apparatus according to claim 7, wherein, The one or more conductive bumps are configured to be coupled to the semiconductor chip working area.

9. The apparatus according to claim 1, wherein, The one or more conductive bumps include at least one of the following: copper bump, metal bump, silver bump, copper alloy bump, metal alloy bump, silver alloy bump, and / or any combination thereof.

10. The apparatus according to claim 1, further comprising a housing.

11. The apparatus according to claim 10, wherein, The housing is configured to encapsulate at least one of the metal oxide varistor component and the voltage suppression component.

12. The apparatus according to claim 11, wherein, The housing is configured to at least partially encapsulate at least one of the lead frame and the other lead frame.

13. The apparatus according to claim 10, wherein, The housing is made of at least one of the following: epoxy compound, plastic, and any combination thereof.

14. The apparatus according to claim 1, wherein, The lead frame includes a lead frame terminal end and the other lead frame includes another lead frame terminal end.

15. The apparatus according to claim 14, wherein, The lead frame terminal end and the other lead frame terminal end are configured to be coupled to at least one of the following: a substrate, a printed circuit board, and any combination thereof.

16. The apparatus according to claim 1, wherein, The voltage suppression component includes at least one of the following: a SIDACTor device, a thyristor, and any combination thereof.

17. An axial lead package structure for a semiconductor device, comprising: Housing; Metal oxide varistor component; A voltage suppression component coupled to the metal oxide varistor component, the voltage suppression component including a semiconductor chip and one or more conductive bumps coupled to the semiconductor chip; A lead frame coupled to the metal oxide varistor component; And Another lead frame coupled to the voltage suppression component; Wherein the housing is configured to encapsulate at least one of the metal oxide varistor component and the voltage suppression component, and at least partially encapsulate the lead frame and the other lead frame.

18. A method, comprising: Provide a metal oxide varistor component; Providing a voltage suppression component, the voltage suppression component including a semiconductor chip and one or more conductive bumps coupled to the semiconductor chip; Coupling the voltage suppression component to the metal oxide varistor component; Coupling a lead frame to the metal oxide varistor component; And Coupling another lead frame to the voltage suppression component.

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