Package substrate and manufacturing method thereof

Abstract

A package substrate and a method of fabricating the same are provided, including bonding an insulating layer on a core layer, forming a through hole, forming a wiring layer on the insulating layer, forming a conductive via electrically connected to the wiring layer in the through hole, and then forming a circuit structure on the insulating layer, thereby facilitating bonding of the wiring layer and the core layer by means of the configuration of the insulating layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging technology, and more particularly to a packaging substrate capable of improving reliability and a manufacturing method thereof. Background Art

[0002] With the evolution of semiconductor packaging technology, different packaging forms have been developed for semiconductor devices. The semiconductor device mainly disposes a chip on a packaging substrate, electrically connects the chip to the packaging substrate, and then coats the chip with a packaging colloid.

[0003] Figures 1A to 1E It is a cross-sectional schematic view of the manufacturing method of the existing packaging substrate 1.

[0004] As Figure 1A shown, a substrate 1a is provided, which includes a core layer 10 and copper foils 11 bonded to the upper and lower sides of the core layer 10.

[0005] As Figure 1B shown, a plurality of through holes 100, 101 are formed in the substrate 1a, and a part of the material of the copper foil 11 protrudes onto the wall surface of the through hole 100 to form an overhang 110.

[0006] As Figure 1C shown, a cleaning operation is performed, and the overhang 110 is removed by a desmear method.

[0007] As Figure 1D shown, a patterning process is performed on the upper and lower sides of the core layer 10 using the copper foil 11 to form a wiring layer 12 respectively, and at least one conductive via 13 electrically connecting the plurality of wiring layers 12 is formed in each of the through holes 100, 101.

[0008] As Figure 1E shown, a circuit structure 14 is formed on the upper and lower sides of the core layer 10 respectively, and a solder mask layer 15 is formed on each of the circuit structures 14. The circuit structure 14 includes at least one dielectric layer 140, a circuit layer 141 formed on the dielectric layer 140, and a plurality of conductive posts 142 formed in the dielectric layer 140 and electrically connecting the circuit layer 141 and the wiring layer 12. A plurality of openings 150 are formed in each of the solder mask layers 15 to expose a part of the surface of the circuit layer 141 to the plurality of openings 150, so that a surface treatment layer 16 can be formed on the exposed surface of the circuit layer 141 as required.

[0009] However, in the existing method for manufacturing the encapsulation substrate 1, when using the copper foil 11 to fabricate the wiring layer 12, not only is it difficult to reduce the material cost due to the high cost of the metal material, but also when forming the funnel-shaped through-hole 100, hangers 110 are likely to appear, which will affect the reliability of fabricating the conductive via 13. Therefore, it often takes time to remove the hangers 110, resulting in an increase in the process time and making it difficult to reduce the manufacturing cost.

[0010] Furthermore, the bonding strength between the existing copper foil 11 and the core layer 10 is poor, resulting in poor adhesion of the wiring layer 12. Therefore, it is not conducive to fabricating circuits with fine line / space (L / S) specifications, making it difficult for the existing encapsulation substrate 1 to meet the requirements of finer L / S.

[0011] Therefore, how to avoid various defects of the prior art has actually become an urgent issue to be solved currently. Summary of the Invention

[0012] In view of the above-mentioned various defects of the prior art, the present invention provides an encapsulation substrate, including: a core layer having opposite sides; two first insulating layers respectively bonded to the opposite sides of the core layer; two wiring layers respectively formed on each of the first insulating layers; at least one conductive via penetrating the core layer and each of the first insulating layers to electrically connect each of the wiring layers; and two circuit structures respectively formed on each of the first insulating layers.

[0013] The present invention also provides a method for manufacturing an encapsulation substrate, including: providing a first substrate including a core layer, two first insulating layers bonded to opposite sides of the core layer, and two first release layers bonded to each of the first insulating layers; forming at least one through-hole penetrating the first substrate; removing the first release layer; respectively forming a wiring layer on each of the first insulating layers, and forming a conductive via in the through-hole to electrically connect each of the wiring layers; and forming a circuit structure on each of the first insulating layers.

[0014] In the foregoing encapsulation substrate and its manufacturing method, the core layer is a dielectric material.

[0015] In the foregoing encapsulation substrate and its manufacturing method, the first insulating layer is a primer.

[0016] In the foregoing encapsulation substrate and its manufacturing method, the circuit structure includes a second substrate, and the second substrate has at least one dielectric layer formed on the first insulating layer and a second insulating layer formed on the dielectric layer, so that the circuit structure further includes a circuit layer formed on the second insulating layer and a plurality of conductive posts penetrating the dielectric layer and the second insulating layer and electrically connecting the circuit layer and the wiring layer. For example, the second insulating layer is a primer.

[0017] As described above, in the packaging substrate and its manufacturing method of the present invention, mainly by using the first insulating layer to replace the existing copper foil, not only can the material cost be saved, but also when the through hole is formed, there will be no hanging objects in the through hole, which is beneficial to improving the reliability of the packaging substrate. Further, since there are no hanging objects in the through hole and there is no need to spend time removing the hanging objects, compared with the prior art, the manufacturing method of the present invention is beneficial to reducing the process time, and thus reducing the manufacturing cost of the packaging substrate.

[0018] Furthermore, due to the configuration of the first insulating layer in the packaging substrate of the present invention, it is beneficial to bond the wiring layer and the core layer, so that the wiring layer has better adhesion, and thus it is beneficial to manufacture circuits with fine line / small pitch (L / S) specifications. Therefore, compared with the prior art, the packaging substrate of the present invention can meet the requirements of finer L / S. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1A to 1E It is a schematic cross-sectional view of the manufacturing method of the existing packaging substrate.

[0020] Figures 2A to 2H It is a schematic cross-sectional view of the manufacturing method of the packaging substrate of the present invention.

[0021] The reference numerals are as follows:

[0022] 1, 2 Packaging substrate

[0023] 1a Base material

[0024] 10, 20 Core layer

[0025] 100, 101, 200, 201 Through hole

[0026] 11 Copper foil

[0027] 110 Hanging object

[0028] 12, 22 Wiring layer

[0029] 13, 23 Conductive via

[0030] 14, 24 Circuit structure

[0031] 140, 240 Dielectric layer

[0032] 141, 241 Circuit layer

[0033] 142, 242 Conductive pillar

[0034] 15, 25 Solder mask

[0035] 150, 250 Opening

[0036] 16, 26 Surface treatment layer

[0037] 2a First base material

[0038] 2b Second substrate

[0039] 21a First insulating layer

[0040] 21b Second insulating layer

[0041] 29a First release layer

[0042] 29b Second release layer

[0043] 290 Blind hole Detailed implementation manners

[0044] The following describes the implementation manners of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0045] It should be noted that the structures, ratios, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the implementation conditions of the present invention. Therefore, they do not have technical essence. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present invention. At the same time, the terms such as "upper", "first", "second", "one", etc. cited in this specification are only for the convenience of clear narration and are not used to limit the implementation scope of the present invention. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope in which the present invention can be implemented.

[0046] Figures 2A to 2H It is a schematic cross-sectional view of the manufacturing method of the encapsulation substrate 2 of the present invention.

[0047] As Figure 2A shown, a first substrate 2a is provided, which includes a core layer 20, two first insulating layers 21a bonded to opposite sides of the core layer 20, and two first release layers 29a bonded to each of the first insulating layers 21a.

[0048] In this embodiment, the core layer 20 may include bis-maleimide / triazine

[0049] (Bismaleimide triazine, abbreviated as BT), prepreg (abbreviated as PP), ABF film (Ajinomotobuild-up film), poly(p-phenylene benzoxazole) (abbreviated as PBO), polyimide (abbreviated as PI), or other dielectric materials, and the material of the first insulating layer 21a is primer. The material of the primer described in the present invention may include a resin or a mixture of a resin and a compound having a carbon-carbon double bond. For example, the material of the primer includes a mixture of a hydrocarbon resin and a compound having more than 3 carbon-carbon double bonds, wherein the hydrocarbon resin includes polybutadiene, polyphenylene ether, or a mixture thereof, and the compound having more than 3 carbon-carbon double bonds includes methylvinyl cyclosiloxane, tetramethyltetravinylcyclotetrasiloxane, pentamethylpentavinylcyclopentasiloxane, octavinylocta silasesquioxane, or a mixture thereof, but is not limited thereto.

[0050] The release layer described in the present invention, for example, the material of the first release layer 29a or the second release layer 29b described later may be a polyester film coated with a silicone resin on the surface, such as a PET film.

[0051] As Figure 2B shown, a plurality of through holes 200, 201 penetrating the first substrate 2a are formed by laser or drilling.

[0052] In this embodiment, the shapes of the plurality of through holes 200, 201 may be the same or different. For example, the through hole 200 may be funnel-shaped or X-shaped, or the through hole 201 is circular and straight.

[0053] As Figure 2C shown, the first release layer 29a is removed.

[0054] As Figure 2D shown, a wiring layer 22 is respectively formed on the first insulating layers 21a on opposite sides of the core layer 20, and at least one conductive via 23 electrically connecting the plurality of wiring layers 22 is formed in each of the through holes 200, 201.

[0055] In this embodiment, the wiring layer 22 and the conductive via 23 may be formed by electroplating a metal (such as copper) or other methods.

[0056] Furthermore, the conductive via 23 is a solid metal column. It should be understood that in other embodiments, the conductive via 23 can also be a hollow copper column, and the hollow part can be filled with plugging materials such as insulating materials or conductive materials (not shown in the figure), without particular limitation.

[0057] Therefore, the manufacturing method of the present invention uses a primer as the first insulating layer 21a to facilitate the bonding of the wiring layer 22 (copper material) and the core layer 20 (prepreg). Therefore, compared with the prior art, the wiring layer 22 of the present invention has better adhesion.

[0058] As Figure 2E shown, a second substrate 2b is respectively formed on the first insulating layer 21a on the upper and lower sides of the core layer 20 to cover the wiring layer 22 with the second substrate 2b. The second substrate 2b includes a dielectric layer 240 formed on the first insulating layer 21a, a second insulating layer 21b formed on the dielectric layer 240, and a second release layer 29b bonded to the second insulating layer 21b.

[0059] In this embodiment, the dielectric layer 240 can include bismaleimide triazine (abbreviated as BT), prepreg (abbreviated as PP), ABF film (Ajinomotobuild-up film), polybenzoxazole (abbreviated as PBO), polyimide (abbreviated as PI), or other dielectric materials, and the material of the second insulating layer 21b is a primer. It should be understood that the dielectric layer 240 and the core layer 20 can be made of the same material (such as PP) or different materials.

[0060] Furthermore, the second substrate 2b can be laminated on the upper and lower sides of the core layer 20 by a lamination method.

[0061]

[0062] Figure 2F As shown, at least one blind via 290 is formed on each of the second substrates 2b by drilling, etching, laser, exposure and development, or other patterning methods, so that a part of the surface of each wiring layer 22 is exposed in each blind via 290.

[0063] In this embodiment, the second substrate 2b uses a primer (the second insulating layer 21b) and a release film (the second release layer 29b) to replace the existing copper foil. Therefore, when each blind via 290 is ablated by a laser method, no hanging objects will appear in each blind via 290. Further, because no hanging objects will appear in each blind via 290, there is no need to spend time removing the hanging objects, which is beneficial to reducing the process time.

[0064] As Figure 2GAs shown, the second release layer 29b is removed.

[0065] As Figure 2H shown, a circuit layer 241 is respectively formed on each of the second insulating layers 21b, and a plurality of conductive posts 242 electrically connecting the circuit layer 241 and the wiring layer 22 are formed in each of the blind vias 290, so as to respectively form a circuit structure 24 on opposite sides of the core layer 20, and then a solder mask layer 25 is respectively formed on each of the circuit structures 24.

[0066] In this embodiment, a plurality of openings 250 can be formed on each of the solder mask layers 25, so that a partial surface of the circuit layer 241 is exposed through the plurality of openings 250. Therefore, a surface treatment layer 26 can be formed on the exposed surface of the circuit layer 241 as required. For example, the surface treatment layer 26 can be made of nickel / gold. It should be understood that the number of layers of the circuit layer 241 can be designed as required and is not particularly limited.

[0067] Therefore, in the manufacturing method of the present invention, mainly by using a primer (the first insulating layer 21a) and a release film (the first release layer 29a) to replace the existing copper foil 11 for the first base material 2a, not only can the material cost be saved, but also when each of the perforations 100, 101 is ablated by a laser method, no hanging objects (especially the funnel-shaped perforation 100) will appear in each of the perforations 100, 101. Further, since no hanging objects will appear in each of the perforations 100, 101 and there is no need to spend time removing the hanging objects, compared with the prior art, the manufacturing method of the present invention is beneficial to reducing the process time, and thus reducing the manufacturing cost of the packaging substrate 2.

[0068] Furthermore, when manufacturing a multi-layer circuit structure, the second base material 2b is selected to use a primer (the second insulating layer 21b) and a release film (the second release layer 29b) to replace the existing copper foil, so as to effectively save the material cost, especially when manufacturing more layers, more cost can be saved.

[0069] In addition, the manufacturing method of the present invention uses a primer as the second insulating layer 21b to facilitate the bonding of the circuit layer 241 (copper material) and the dielectric layer 240 (prepreg). Therefore, compared with the prior art, the circuit layer 241 of the present invention has better adhesion.

[0070] In addition, since the adhesion between the wiring layer 22 and the circuit layer 241 of the present invention is excellent, it is beneficial to manufacture circuits with a fine line / fine pitch (L / S) specification. Therefore, compared with the prior art, the wiring layer 22 and the circuit layer 241 of the present invention can meet the requirements of a finer L / S.

[0071] The present invention also provides a packaging substrate 2, including: a core layer 20 having opposite sides, two first insulating layers 21a, two wiring layers 22, at least one conductive via 23, and two circuit structures 24.

[0072] The two first insulating layers 21a are respectively bonded to opposite sides of the core layer 20.

[0073] The two wiring layers 22 are respectively formed on each of the first insulating layers 21a.

[0074] The at least one conductive via 23 penetrates through the core layer 20 and each of the first insulating layers 21a to electrically connect each of the wiring layers 22.

[0075] The two circuit structures 24 are respectively formed on each of the first insulating layers 21a.

[0076] In one embodiment, the core layer 20 is a dielectric material.

[0077] In one embodiment, the first insulating layer 21a is a primer.

[0078] In one embodiment, the circuit structure 24 includes at least one dielectric layer 240 formed on the first insulating layer 21a, a second insulating layer 21b formed on the dielectric layer 240, a circuit layer 241 formed on the second insulating layer 21b, and a plurality of conductive posts 242 that penetrate through the dielectric layer 240 and the second insulating layer 21b and electrically connect the circuit layer 241 and the wiring layer 22. For example, the second insulating layer 21b is a primer.

[0079] In summary, for the packaging substrate 2 and its manufacturing method of the present invention, by using insulating materials (the first insulating layer 21a and the second insulating layer 21b) to replace the existing copper foil 11 in the base materials (the first base material 2a and the second base material 2b), not only can the material cost be saved, but also when holes (perforations 200, 201 or blind holes 290) are formed, there will be no hanging objects in the holes, which is beneficial to improving the reliability of the packaging substrate 2. Further, because there are no hanging objects in the holes and there is no need to spend time removing the hanging objects, the manufacturing method of the present invention is beneficial to reducing the process time, and thus reducing the manufacturing cost of the packaging substrate 2.

[0080] Furthermore, for the packaging substrate 2 of the present invention, by the configuration of the insulating materials (the first insulating layer 21a and the second insulating layer 21b), it is beneficial to bond the metal materials (the wiring layer 22 and the circuit layer 241) and the dielectric materials (the core layer 20 and the dielectric layer 240), so that the metal materials have better adhesion, and thus it is beneficial to manufacture circuits with a fine line / small pitch (L / S) specification. Therefore, the packaging substrate 2 of the present invention can meet the requirements of a finer L / S.

[0081] The above embodiments are used to illustratively explain the principles and effects of the present invention, rather than to limit the present invention. Those skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the patent protection of the present invention should be as listed in the claims.

Claims

1. A packaging substrate, characterized in that: include: a core layer having two opposing sides; Two first insulating layers are respectively bonded to opposite sides of the core layer; Two wiring layers are formed on the first insulating layers respectively; At least one conductive through hole penetrating the core layer and each of the first insulating layers to electrically connect each of the wiring layers; as well as Two circuit structures are formed on each of the first insulating layers.

2. The packaging substrate according to claim 1, wherein: The core layer is a dielectric material.

3. The packaging substrate according to claim 1, wherein: The first insulating layer is a primer.

4. The packaging substrate according to claim 1, wherein: The circuit structure includes at least one dielectric layer formed on the first insulating layer, a second insulating layer formed on the dielectric layer, a circuit layer formed on the second insulating layer, and a plurality of conductive posts penetrating the dielectric layer and the second insulating layer and electrically connecting the circuit layer and the wiring layer.

5. The packaging substrate according to claim 4, characterized in that The second insulating layer is a primer.

6. A method for manufacturing a packaging substrate, characterized in that: include: Providing a first substrate including a core layer, two first insulating layers bonded to opposite sides of the core layer, and two first release layers bonded to each of the first insulating layers; forming at least one through-hole penetrating the first substrate; removing the first release layer; Forming wiring layers on each of the first insulating layers, and forming conductive through holes in the through holes that are electrically connected to each of the wiring layers; as well as A circuit structure is formed on each of the first insulating layers.

7. The method for manufacturing a packaging substrate according to claim 6, wherein: The core layer is a dielectric material.

8. The method for manufacturing a packaging substrate according to claim 6, wherein: The first insulating layer is a primer.

9. The method for manufacturing a packaging substrate according to claim 6, wherein: The circuit structure includes a second substrate, and the second substrate has at least one dielectric layer formed on the first insulating layer and a second insulating layer formed on the dielectric layer, so that the circuit structure also includes a circuit layer formed on the second insulating layer and a plurality of conductive columns that penetrate the dielectric layer and the second insulating layer and electrically connect the circuit layer and the wiring layer.

10. The method for manufacturing a packaging substrate according to claim 9, wherein: The second insulating layer is a primer.

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