Semiconductor chip, method of manufacturing the same, and semiconductor package including the same

Abstract

The invention discloses a semiconductor chip, a method of manufacturing the semiconductor chip, and a semiconductor package including the semiconductor chip. The semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface; the interconnection structure is arranged on the second surface of the semiconductor substrate; a plurality of conductive patterns separated from the semiconductor substrate and each connected to an interconnect structure between the plurality of conductive patterns and the semiconductor substrate; a compensation pattern separated from the plurality of conductive patterns on the interconnection structure in a horizontal direction, and further away from a second surface of the semiconductor substrate than the plurality of conductive patterns away from the second surface of the semiconductor substrate; and an insulating spacer disposed between the plurality of conductive patterns and the compensation pattern.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2023-0186149, filed with the Korean Intellectual Property Office on December 19, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a semiconductor chip, a method of manufacturing a semiconductor chip, and a semiconductor package including the semiconductor chip. Background Art

[0003] According to the rapid development of the electronics industry and user demands, electronic devices have become smaller and lighter. Therefore, high integration is required for semiconductor chips used in electronic devices, and the design rules for components of semiconductor chips have been further reduced. Structures for improving the reliability of thin semiconductor chips and semiconductor packages including thin semiconductor chips have been proposed. Summary of the Invention

[0004] The inventive concept provides a semiconductor chip with improved reliability.

[0005] The inventive concept provides a method of manufacturing a semiconductor chip with improved reliability.

[0006] The inventive concept provides a semiconductor package including a semiconductor chip with improved reliability.

[0007] According to an aspect of the inventive concept, there is provided a semiconductor chip including: a semiconductor substrate having a first surface and a second surface above and opposite the first surface; an interconnect structure above the second surface of the semiconductor substrate; a plurality of conductive patterns spaced apart from the semiconductor substrate, the interconnect structure being between the plurality of conductive patterns and the semiconductor substrate, the plurality of conductive patterns being connected to the interconnect structure; a compensation pattern above the interconnect structure such that the compensation pattern is spaced apart from the plurality of conductive patterns in a horizontal direction and such that a distance from the compensation pattern to the second surface of the semiconductor substrate is greater than a distance from the plurality of conductive patterns to the second surface of the semiconductor substrate; and insulating spacers between the plurality of conductive patterns and the compensation pattern.

[0008] According to an aspect of the inventive concept, there is provided a semiconductor chip including: a semiconductor substrate; an interconnect structure on an upper surface of the semiconductor substrate, the interconnect structure including a plurality of interconnect lines, a plurality of interconnect vias, and an interconnect insulating layer surrounding the plurality of interconnect lines and the plurality of interconnect vias; a plurality of conductive patterns above the interconnect structure, the plurality of conductive patterns being spaced apart from each other in a horizontal direction and having a thickness greater than a thickness of the plurality of interconnect lines in a vertical direction; a compensation pattern above the interconnect structure, the compensation pattern being spaced apart from the plurality of conductive patterns in the horizontal direction; an insulating spacer between the compensation pattern and the plurality of conductive patterns and between the interconnect structure and the compensation pattern; a front-side dielectric layer covering the plurality of conductive patterns, the compensation pattern, and the insulating spacer; and a plurality of front-side bonding pads passing through the front-side dielectric layer and the insulating spacer and respectively contacting the plurality of conductive patterns.

[0009] According to an aspect of the inventive concept, there is provided a semiconductor package including: a first semiconductor chip; and a second semiconductor chip bonded to the first semiconductor chip, wherein the first semiconductor chip includes: a first semiconductor substrate including a first surface and a second surface opposite to each other, a plurality of first back-side bonding pads on the first surface of the first semiconductor substrate, and a first back-side dielectric layer surrounding sidewalls of each of the plurality of first back-side bonding pads on the first surface of the first semiconductor substrate, and wherein the second semiconductor chip includes: a second semiconductor substrate including a first surface facing away from the semiconductor substrate and a second surface facing the first surface of the first semiconductor substrate, an interconnect structure on the second surface of the second semiconductor substrate, a front-side interconnect layer spaced apart from the second semiconductor substrate, the interconnect structure being between the front-side interconnect layer and the second semiconductor substrate, a second front-side dielectric layer between the front-side interconnect layer and the first back-side dielectric layer of the first semiconductor chip, the second front-side dielectric layer of the second semiconductor chip being bonded to the first back-side dielectric layer of the first semiconductor chip, and a plurality of second front-side bonding pads passing through the second front-side dielectric layer such that the plurality of second front-side bonding pads are bonded to the plurality of first back-side bonding pads, wherein the front-side interconnect layer includes: a plurality of conductive patterns spaced apart from each other in a horizontal direction and each including a first surface contacting the interconnect structure and a second surface opposite to the first surface, a compensation pattern spaced apart from the plurality of conductive patterns in the horizontal direction and including a first surface facing the interconnect structure and a second surface opposite to the first surface, the second surface contacting the second front-side dielectric layer, the compensation pattern being, and an insulating spacer between the plurality of conductive patterns and the compensation pattern and contacting the second surface of each of the plurality of conductive patterns and the first surface of the compensation pattern, and wherein the plurality of second front-side bonding pads pass through the insulating spacer and contact the second surface of each of the plurality of conductive patterns.

[0010] According to an aspect of the inventive concept, there is provided a method of manufacturing a semiconductor chip, the method comprising: forming a plurality of conductive patterns on an interconnect structure such that the plurality of conductive patterns are separated from each other in a horizontal direction, the interconnect structure being formed on a semiconductor substrate; forming a concavo-convex structure including conformal insulating spacers covering the plurality of conductive patterns and the interconnect structure; forming a compensation material layer covering the concavo-convex structure such that the compensation material layer covers the plurality of conductive patterns and the insulating spacers; forming a compensation pattern by planarizing the compensation material layer such that the insulating spacers are exposed; forming a front dielectric layer covering the insulating spacers and the compensation pattern; forming a plurality of first openings that pass through the front dielectric layer and the insulating spacers to expose the plurality of conductive patterns; and forming a plurality of front-side bonding pads respectively filling the plurality of first openings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a cross-sectional view showing a semiconductor chip according to an embodiment;

[0013] Figure 2 is Figure 1 an enlarged view of region EXA1 in

[0014] Figure 3 is Figure 2 an enlarged view of region EXA2 in

[0015] Figure 4A , Figure 4B and Figure 4C are plan views showing a partial configuration of a semiconductor chip according to an exemplary embodiment;

[0016] Figure 5A is a cross-sectional view showing a partial region of a semiconductor chip according to some other embodiments;

[0017] Figure 5B is Figure 5A an enlarged view of region EXB1 in

[0018] Figure 6 is a cross-sectional view showing a partial region of a semiconductor chip according to some other embodiments;

[0019] Figure 7 is a cross-sectional view showing a partial region of a semiconductor chip according to some other embodiments;

[0020] Figure 8A is a cross-sectional view showing a partial region of a semiconductor chip according to some other embodiments;

[0021] Figure 8Bis a plan view showing a partial configuration of a semiconductor chip according to some other embodiments;

[0022] Figures 9A to 9F is a cross-sectional view shown according to a process sequence for explaining a method of manufacturing a semiconductor chip according to an exemplary embodiment;

[0023] Figures 10A to 10C is a cross-sectional view shown according to a process sequence for explaining a method of manufacturing a semiconductor chip according to some other embodiments;

[0024] Figure 11 is a cross-sectional view showing a method of manufacturing a semiconductor chip according to some other embodiments;

[0025] Figures 12A to 12E is a cross-sectional view shown according to a process sequence for explaining a method of manufacturing a semiconductor chip according to some other embodiments;

[0026] Figure 13 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment;

[0027] Figure 14 is Figure 11 an enlarged view of region EXC1 in; and

[0028] Figure 15 is a cross-sectional view showing a semiconductor package according to an exemplary embodiment. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and their repeated description is omitted.

[0030] Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings, in which, for clarity and ease of explanation, the dimensions of components in the drawings may be exaggerated. In addition, when the terms "about" or "substantially" are used in this specification in connection with numerical and / or geometric terms, it is intended that the associated numerical and / or geometric terms include manufacturing tolerances (e.g., ±10%) around the stated numerical value. Further, whether the numerical and / or geometric terms are modified by "about" or "substantially", it will be understood that these values should be interpreted as including manufacturing operation or operational tolerances (e.g., ±10%) around the stated numerical and / or geometric.

[0031] Figure 1 is a cross-sectional view showing a semiconductor chip 100 according to an embodiment. Figure 2 is Figure 1 an enlarged view of region EXA1 in. Figure 3 is Figure 2 an enlarged view of region EXA2 in. Figure 4A 、Figure 4B and Figure 4C is a plan view showing a partial configuration of a semiconductor chip 100 according to an exemplary embodiment.

[0032] Referring to Figures 1 to 4C , the semiconductor chip 100 may include a semiconductor substrate 102, an interconnect structure 152, a front-side interconnect layer 160, a front-side dielectric layer 182 (e.g., a front-side insulating layer), and a plurality of front-side bonding pads (or bonding pads) 184. According to an exemplary embodiment, the front-side interconnect layer 160 may include a plurality of conductive patterns 162, insulating spacers 164, and compensation patterns 174.

[0033] The semiconductor substrate 102 may include a first surface 102B and a second surface 102F that face each other. The first surface 102B of the semiconductor substrate 102 may be an inactive surface of the semiconductor substrate 102, and the second surface 102F of the semiconductor substrate 102 may be an active surface of the semiconductor substrate 102. Thus, the first surface 102B of the semiconductor substrate 102 may also be referred to as the back-side surface of the semiconductor substrate 102, and the second surface 102F of the semiconductor substrate 102 may also be referred to as the front-side surface of the semiconductor substrate 102.

[0034] Hereinafter, the direction parallel to the first surface 102B of the semiconductor substrate 102 is defined as the horizontal direction (X direction and / or Y direction), and the direction perpendicular to the first surface 102B of the semiconductor substrate 102 is defined as the vertical direction (Z direction). In addition, the horizontal width represents the length in the horizontal direction (X direction and / or Y direction), the vertical height represents the length in the vertical direction (Z direction), and the vertical level represents the distance from the first surface 102B of the semiconductor substrate 102 in the Z direction or -Z direction. However, such spatial relative terms are intended to encompass different orientations of the device during use or operation, in addition to the orientation depicted in the figures. More specifically, spatial relative terms including "horizontal", "vertical", "above", "below", etc. will be understood to encompass different orientations of the device during use or operation, such that the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein should be interpreted accordingly.

[0035] For example, unless otherwise specified in this specification, the upper surface represents the surface facing upward in the figure, and the lower surface represents the surface facing downward in the figure. For example, in Figures 1 to 3In [the figure], the first surface 102B of the semiconductor substrate 102 is set to face downward, and the second surface 102F of the semiconductor substrate 102 is set to face upward. In this case, the first surface 102B (e.g., the inactive surface) of the semiconductor substrate 102 may be referred to as the lower surface of the semiconductor substrate 102. The second surface 102F (e.g., the active surface) of the semiconductor substrate 102 may be referred to as the upper surface of the semiconductor substrate 102. On the contrary, in the semiconductor package 1000 described below with reference to Figures 11 to 13 the semiconductor substrates 202 and 302 of the plurality of semiconductor chips 200 and 300 may each have a downward-facing arrangement with an active surface facing downward. In this case, the active surface may be referred to as the lower surface of each of the semiconductor substrates 202 and 302.

[0036] The semiconductor substrate 102 may be formed of a semiconductor wafer. The semiconductor substrate 102 may include, for example, semiconductor elements (such as germanium (Ge) and / or silicon (Si)) and / or compound semiconductors (such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP)). The semiconductor substrate 102 may include conductive regions (e.g., wells doped with impurities and / or structures doped with impurities). In addition, the semiconductor substrate 102 may have various semiconductor devices and device isolation structures (such as a shallow trench isolation (STI) structure) formed on the second surface 102F.

[0037] The various semiconductor devices (not shown) may include memory devices, logic devices, and / or their components. The memory devices may include, for example, dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, electrically erasable programmable read-only memory (EEPROM) devices, phase change random access memory (PRAM) devices, magnetic random access memory (MRAM) devices, and / or resistive random access memory (RRAM) devices, etc. The logic devices may include, for example, AND gates, NAND gates, OR gates, NOR gates, exclusive OR (XOR) gates, exclusive NOR (XNOR) gates, inverters (INV), adders (ADD), delayers (DLY), filters (FIL), multiplexers (MXT / MXIT), OR / AND / inverters (OAI), AND / OR (AO), AND / OR / inverters (AOI), D flip-flops, reset flip-flops, master-slave flip-flops, latches, counters, and / or buffer devices, etc. In addition, the logic devices may include central processing units (CPUs), microprocessor units (MPUs), graphics processing units (GPUs), and / or application processors (APs), etc.

[0038] In some embodiments, the second surface 102F may be covered by the interlayer insulating layer 104. For example, the interlayer insulating layer 104 may surround a plurality of semiconductor devices (not shown) formed on the second surface 102F of the semiconductor substrate 102, and may insulate the plurality of semiconductor devices (not shown) from each other and / or protect the plurality of semiconductor devices (not shown). The interlayer insulating layer 104 may include an electrically insulating material. For example, in some embodiments, the interlayer insulating layer 104 may include a silicon oxide layer, a silicon nitride layer, and / or a combination thereof, but is not limited thereto. In the present specification, a layer including a plurality of semiconductor devices (not shown) and the interlayer insulating layer 104 surrounding the plurality of semiconductor devices may be referred to as a semiconductor device layer.

[0039] According to some example embodiments, the interconnect structure 152 and the front-side interconnect layer 160 may be sequentially disposed on the interlayer insulating layer 104. The interconnect structure 152 may be disposed on the second surface 102F of the semiconductor substrate 102. For example, the interconnect structure 152 may be disposed on the second surface 102F of the semiconductor substrate 102 and spaced apart from the semiconductor substrate 102, with the interlayer insulating layer 104 between the interconnect structure 152 and the semiconductor substrate 102. Although not shown in the drawings, a plurality of semiconductor devices (not shown) may be connected to the interconnect structure 152 through contacts (not shown) passing through the interlayer insulating layer 104.

[0040] According to some example embodiments, the interconnect structure 152 may include a first interconnect layer 122 and a second interconnect layer 142 sequentially stacked on the second surface 102F of the semiconductor substrate 102.

[0041] In some embodiments, the first interconnect layer 122 may include a plurality of conductive structures, the plurality of conductive structures including a plurality of first interconnect lines 124, a plurality of first interconnect vias 126, and a first interconnect insulating layer 128. The plurality of first interconnect lines 124 and the plurality of first interconnect vias 126 may be surrounded by the first interconnect insulating layer 128. The plurality of first interconnect lines 124 may include first interconnect lines 124 spaced apart from each other in the vertical direction (Z direction) within the first interconnect insulating layer 128, and may each extend in the horizontal direction (X direction and / or Y direction). For example, the plurality of first interconnect lines 124 may be arranged at different vertical levels to form a multi-layer interconnect structure. The plurality of first interconnect vias 126 may extend between the plurality of first interconnect lines 124 arranged at different vertical levels and electrically connect the plurality of first interconnect lines located at different vertical levels.

[0042] In some embodiments, the second interconnect layer 142 may include second interconnect lines 144, a plurality of second interconnect vias 146, and a second interconnect insulating layer 148 surrounding the second interconnect lines 144 and the plurality of second interconnect vias 146. In some embodiments, the second interconnect lines 144 may extend in a horizontal direction (at least one of the X direction and / or the Y direction). In some embodiments, the second interconnect lines 144 may not only have a line shape but may also include a dot-shaped pad structure. The plurality of second interconnect vias 146 may extend in a vertical direction (Z direction) within the second interconnect insulating layer 148. Some of the plurality of second interconnect vias 146 may connect multiple first interconnect lines 124 to the second interconnect lines 144, and some of the plurality of second interconnect vias 146 may connect a plurality of conductive patterns 162 to the second interconnect lines 144.

[0043] In Figure 2 FIG. 5, the semiconductor chip 100 is shown as including five layers of first interconnect lines 124 disposed at different vertical levels, but the example is not limited thereto. For example, the semiconductor chip 100 may include 1 to 4 layers, and / or 6 or more layers of first interconnect lines 124. In Figure 2 FIG. 7, the semiconductor chip 100 is shown as including one second interconnect line 144, but is not limited thereto. For example, the semiconductor chip 100 may include a plurality of second interconnect lines 144 separated from each other in a vertical direction (Z direction) within the second interconnect insulating layer 148. In these cases, the plurality of second interconnect vias 146 may connect the plurality of second interconnect lines 144 to each other within the second interconnect insulating layer 148, connect the lowermost second interconnect line 144 to the uppermost first interconnect line 124, and connect the uppermost second interconnect line 144 to the plurality of conductive patterns 162.

[0044] In some embodiments, the plurality of first interconnect lines 124, the plurality of first interconnect vias 126, the second interconnect lines 144, and the plurality of second interconnect vias 146 may each include a metal conductive material (such as a metal (e.g., copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof, etc.)).

[0045] In some embodiments, the plurality of first interconnect lines 124 and the plurality of first interconnect vias 126 in the first interconnect layer 122 may include different materials from the second interconnect lines 144 and the plurality of second interconnect vias 146 in the second interconnect layer 142. In some other embodiments, the plurality of first interconnect lines 124 and the plurality of first interconnect vias 126 in the first interconnect layer 122 may include the same materials as the second interconnect lines 144 and the plurality of second interconnect vias 146 in the second interconnect layer 142.

[0046] In some embodiments, the second interconnecting lines 144 of the second interconnect layer 142 may have a vertical thickness greater than that of the first interconnecting lines 124 of the first interconnect layer 122, and the second interconnect vias 146 of the second interconnect layer 142 may have a horizontal width greater than that of the first interconnect vias 126 of the first interconnect layer 122.

[0047] In some embodiments, the first interconnect insulating layer 128 and the second interconnect insulating layer 148 may each include an electrically insulating oxide layer (such as tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), plasma enhanced TEOS (PE-TEOS), or high density plasma chemical vapor deposition (HDP-CVD) layer), a carbon-containing oxide layer (such as a SiOC or SiCOH layer), a silicon nitride layer, a carbon-containing nitride layer, and / or a combination thereof, etc.

[0048] According to some example embodiments, the front-side interconnect layer 160 may be disposed on the upper surface 142u of the second interconnect layer 142, and the front-side dielectric layer 182 may be disposed on the front-side interconnect layer 160. For example, the front-side interconnect layer 160 may be spaced apart from the semiconductor substrate 102, and the interconnect structure 152 is between the front-side interconnect layer 160 and the semiconductor substrate 102. In some embodiments, the upper surface 142u of the second interconnect layer 142 may be parallel to the second surface 102F of the semiconductor substrate 102. For example, the upper surface 142u of the second interconnect layer 142 may extend flatly (and / or substantially flatly) in the horizontal direction (X direction and / or Y direction).

[0049] According to some example embodiments, a plurality of conductive patterns 162 may be arranged to be separated from each other on the upper surface 142u of the second interconnect layer 142. Each of the plurality of conductive patterns 162 may have a first surface 162a facing the semiconductor substrate 102 and a second surface 162b facing away from the semiconductor substrate 102. The plurality of conductive patterns 162 may be in contact with the upper surface 142u of the second interconnect layer 142. For example, the first surface 162a of each of the plurality of conductive patterns 162 may be in contact with some of the plurality of second interconnect vias 146 exposed at the upper surface 142u of the second interconnect layer 142, and the plurality of conductive patterns 162 may be electrically connected to the interconnecting lines 124 and 144 and the interconnect vias 126 and 146 in the interconnect structure 152. The first surface 162a of each of the plurality of conductive patterns 162 may include a portion in contact with the second interconnect insulating layer 148. In Figures 1 to 3 this case, the first surface 162a may be referred to as the lower surface of each of the plurality of conductive patterns 162, and the second surface 162b may be referred to as the upper surface of each of the plurality of conductive patterns 162.

[0050] According to some example embodiments, the insulating spacer 164 may cover the upper surface 142u of the plurality of conductive patterns 162 and the second interconnect layer 142. In some embodiments, the insulating spacer 164 may contact a portion of the second surface 162b of each of the plurality of conductive patterns 162, the sidewalls 162s of each of the plurality of conductive patterns 162, and the upper surface 142u of the second interconnect layer 142. In some embodiments, the insulating spacer 164 may include a portion disposed between the front-side dielectric layer 182 and the plurality of conductive patterns 162. For example, the second surface 162b of each of the plurality of conductive patterns 162 may include a portion facing the front-side dielectric layer 182 and another portion not vertically stacked with the insulating spacer 164, and the insulating spacer 164 is between the portion of the second surface 162b of each of the plurality of conductive patterns 162 facing the front-side dielectric layer 182 and the front-side dielectric layer 182.

[0051] According to some example embodiments, the compensation pattern 174 may be disposed on the insulating spacer 164 and spaced apart from the plurality of conductive patterns 162 in a horizontal direction (X direction and / or Y direction). The insulating spacer 164 may be disposed between the plurality of conductive patterns 162 and the compensation pattern 174.

[0052] The compensation pattern 174 may have a first surface 174a facing the semiconductor substrate 102 and a second surface 174b facing away from the semiconductor substrate 102. According to some example embodiments, at least one of the first surface 174a and the sidewalls 174s of the compensation pattern 174 may contact the insulating spacer 164. The compensation pattern 174 may face the upper surface 142u of the second interconnect layer 142, and the insulating spacer 164 is between the compensation pattern 174 and the upper surface 142u of the second interconnect layer 142. For example, the insulating spacer 164 may include a portion disposed between the compensation pattern 174 and the interconnect structure 152.

[0053] According to some example embodiments, the plurality of conductive patterns 162 may be disposed closer to the semiconductor substrate 102 than the compensation pattern 174 is to the semiconductor substrate 102. In some embodiments, the first surface 174a of the compensation pattern 174 may be higher than the first surface 162a of each of the plurality of conductive patterns 162 and may be at a lower vertical level than the second surface 162b of each of the plurality of conductive patterns 162. For example, the distance between the first surface 162a of each of the plurality of conductive patterns 162 and the second surface 102F of the semiconductor substrate 102 may be less than the distance between the first surface 174a of the compensation pattern 174 and the second surface 102F of the semiconductor substrate 102.

[0054] According to some example embodiments, the front-side dielectric layer 182 may be disposed on the front-side interconnect layer 160. The second surface 174b of the compensation pattern 174 and the uppermost surface 164um of the insulating spacer 164 may be covered by the front-side dielectric layer 182. For example, the uppermost surface 164um of the insulating spacer 164 may be the upper surface of the portion of the insulating spacer 164 that does not vertically overlap with the compensation pattern 174. For example, the uppermost surface 164um of the insulating spacer 164 may be the upper surface of the portion of the insulating spacer 164 that is farthest from the second surface 102F of the semiconductor substrate 102.

[0055] In some embodiments, the second surface 174b of the compensation pattern 174 may be at a higher vertical level than the second surface 162b of each of the plurality of conductive patterns 162. For example, the distance between the second surface 162b of each of the plurality of conductive patterns 162 and the second surface 102F of the semiconductor substrate 102 may be less than the distance between the second surface 174b of the compensation pattern 174 and the second surface 102F of the semiconductor substrate 102.

[0056] According to an example embodiment, the sidewall 174s of the compensation pattern 174 may face the sidewall 162s of each of the plurality of conductive patterns 162, and the insulating spacer 164 is between the sidewall 174s of the compensation pattern 174 and the sidewall 162s of each of the plurality of conductive patterns 162. According to an example embodiment, the sidewall 162s of each of the plurality of conductive patterns 162 may be spaced apart from the sidewall 174s of the compensation pattern 174 by a first separation distance da1 in a horizontal direction (X direction and / or Y direction). In some embodiments, a first conductive pattern 162 and a second conductive pattern 162 selected from among the plurality of conductive patterns 162 and separated from each other may each be spaced apart from the compensation pattern 174 by the first separation distance da1, and the compensation pattern 174 is between the first conductive pattern 162 and the second conductive pattern 162 selected from among the plurality of conductive patterns 162 and separated from each other. In some embodiments, the portions of the sidewalls 162s of the plurality of conductive patterns 162 (the portions facing the compensation pattern 174) may all have the same first separation distance da1.

[0057] According to some example embodiments, the first surface 174a of the compensation pattern 174 may be spaced apart from the interconnect structure 152 by a second separation distance da2 in a vertical direction (Z direction), and the insulating spacer 164 is between the first surface 174a of the compensation pattern 174 and the interconnect structure 152. In some embodiments, the second separation distance da2 may be substantially equal to (and / or substantially similar to) the first separation distance da1.

[0058] In some embodiments, the distance in the vertical direction (Z - direction) between the second surface 162b of each of the plurality of conductive patterns 162 and the front - side dielectric layer 182 may be substantially equal to (and / or substantially similar to) the second separation distance da2. In some other embodiments, the distance in the vertical direction (Z - direction) between the second surface 162b of each of the plurality of conductive patterns 162 and the front - side dielectric layer 182 may be different from the second separation distance da2. For example, the distance in the vertical direction (Z - direction) between the second surface 162b of each of the plurality of conductive patterns 162 and the front - side dielectric layer 182 may be less than the distance in the vertical direction (Z - direction) between the first surface 174a of the compensation pattern 174 and the interconnect structure 152.

[0059] Referring to Figures 1 to 3 , the vertical cross - sections of the plurality of conductive patterns 162 and the compensation pattern 174 are each shown as having a rectangular shape, but the exemplary embodiments of the inventive concept are not limited thereto. For example, in some embodiments, the horizontal width of each of the plurality of conductive patterns 162 may increase toward the second surface 102F of the semiconductor substrate 102, such that the vertical cross - section of each of the plurality of conductive patterns 162 may have a trapezoidal shape. For example, the sidewall 162s of each of the plurality of conductive patterns 162 may have an inclination with respect to the second surface 102F of the semiconductor substrate 102 and the vertical direction (Z - direction). In this case, the sidewall 174s of the compensation pattern 174 may have an inclination with respect to the second surface 102F of the semiconductor substrate 102 and the vertical direction (Z - direction) to correspond to the sidewall 162s of each of the plurality of conductive patterns 162. For example, the horizontal width of the portion of the compensation pattern 174 disposed between two adjacent conductive patterns 162 may decrease toward the second surface 102F of the semiconductor substrate 102.

[0060] Figure 4A ,, Figure 4B and Figure 4C shows the planar arrangement relationship between the plurality of conductive patterns 162, the compensation pattern 174, and the insulating spacers 164 in the front - side interconnect layer 160. According to some exemplary embodiments, the compensation pattern 174 may have a plurality of holes HP that accommodate the plurality of conductive patterns 162. The inner wall / inner boundary of each of the plurality of holes HP is formed by the sidewall 174s of the compensation pattern 174. At least one conductive pattern 162 may be disposed in each of the plurality of holes HP. In a plan view, the compensation pattern 174 may be arranged to surround the plurality of conductive patterns 162. According to some exemplary embodiments, the compensation pattern 174 may fill the regions in the front - side interconnect layer 160 where the plurality of conductive patterns 162 are not provided, and thus, the deviation of the pattern density according to the regions of the front - side interconnect layer 160 may be reduced.

[0061] Referring to Figure 4A, among the plurality of conductive patterns 162, a first group of the conductive patterns 162 may be individually disposed in each of the plurality of holes HP. The first group of conductive patterns 162 may be arranged to be separated from each other in a horizontal direction (X direction and / or Y direction), and may each be surrounded by an insulating spacer 164, with a compensation pattern 174 between the first group of conductive patterns 162. For example, the compensation pattern 174 may be disposed between every two of the first group of conductive patterns 162. In some embodiments, in a plan view, each of the first group of conductive patterns 162 may be separated from an inner boundary of a corresponding one of the plurality of holes HP by a first separation distance da1. For example, in a plan view, each of the conductive patterns 162 in the first group may have an independent island shape. In some embodiments, a first pattern pitch dpw1, which is a distance between two conductive patterns 162 selected from the first group of conductive patterns 162 and arranged adjacent to each other, may be greater than twice the first separation distance da1. For example, the first pattern pitch dpw1 may be a horizontal distance between two adjacent conductive patterns 162, with the compensation pattern 174 between the two adjacent conductive patterns 162 arranged adjacent to each other.

[0062] Referring to Figure 4B , a second group of the conductive patterns 162 among the plurality of conductive patterns 162 may be disposed in a single hole HP. Compared with the first group of conductive patterns 162 described with reference to Figure 4A , the second group of conductive patterns 162 may be arranged to be relatively dense with respect to each other. In some embodiments, two adjacent conductive patterns 162 among the second group of conductive patterns 162 may have a second pattern pitch dpw2 that is less than the first pattern pitch dpw1. For example, the second pattern pitch dpw2 may be less than twice the first separation distance da1. For example, the second pattern pitch dpw2 may be a horizontal distance between two adjacent conductive patterns 162, with an insulating spacer 164 between the two adjacent conductive patterns 162 arranged adjacent to each other.

[0063] In some embodiments, the compensation pattern 174 may not be disposed between two adjacent conductive patterns 162 among the second set of conductive patterns 162, and the two conductive patterns 162 may be separated from each other with an insulating spacer 164 therebetween. A first conductive pattern 162 selected from among the second set of conductive patterns 162 may be disposed on the central side of the second set of conductive patterns 162 and may be surrounded by other adjacent conductive patterns 162. In these cases, the distance between the sidewall 162s of the first conductive pattern 162 and the sidewall 174s of the compensation pattern 174 may be greater than a first separation distance da1. In some embodiments, the distance between the first conductive pattern 162 disposed on the central side of the second set of conductive patterns 162 and at least one of the other first conductive patterns 162 of the second set of conductive patterns 162 may be less than twice the first separation distance da1. In some embodiments, the sidewall 162s of each of the outer conductive patterns 162 among the second set of densely arranged conductive patterns 162 may include a portion facing the sidewall 174s of the compensation pattern 174. In these cases, the sidewall 162s of each of the outer conductive patterns 162 may be separated from the compensation pattern 174 by the first separation distance da1. Thus, in at least some of these cases, the second pattern pitch dpw2 may be less than twice the first separation distance da1 and greater than or equal to the first separation distance da1 (e.g., da1 ≤ dpw2 < (2 × da1)).

[0064] Referring Figure 4C , the plurality of conductive patterns 162 may include a plurality of groups separated from each other in a horizontal direction (X direction and / or Y direction). In some embodiments, the plurality of groups may each be disposed in a corresponding one of a plurality of holes HP, and the plurality of groups may be separated from each other with a compensation pattern 174 therebetween. In some embodiments, the conductive patterns 162 of some of the plurality of groups may be arranged in rows in one horizontal direction. In some embodiments, the conductive patterns 162 of some other of the plurality of groups may be arranged in a zigzag pattern in one horizontal direction. Within each hole HP, the conductive patterns 162 constituting each group may be separated from each other by a second pattern pitch dpw2. Each of the plurality of groups is disposed in one hole HP, but is separated from Figure 4Bis different from the conductive pattern 162. The conductive patterns 162 forming each group may all have sidewalls 162s facing the compensation pattern 174. In some embodiments, a third group of conductive patterns 162 and a fourth group of conductive patterns 162 selected from among the multiple groups may be separated from each other, and the compensation pattern 174 is between the third group of conductive patterns 162 and the fourth group of conductive patterns 162 selected from among the multiple groups. A first conductive pattern 162 selected from the third group of conductive patterns 162 and adjacent to the fourth group of conductive patterns 162 may be separated from a second conductive pattern 162 selected from the fourth group of conductive patterns 162 and adjacent to the third group of conductive patterns 162 by a first pattern interval dwp1, and the compensation pattern 174 is between the first conductive pattern 162 selected from the third group of conductive patterns 162 and adjacent to the fourth group of conductive patterns 162 and the second conductive pattern 162 selected from the fourth group of conductive patterns 162 and adjacent to the third group of conductive patterns 162. For example, in a plan view, the compensation pattern 174 may surround the first group of conductive patterns 162, the second group of conductive patterns 162, the third group of conductive patterns 162, or the fourth group of conductive patterns 162.

[0065] In Figures 4A to 4C , the multiple conductive patterns 162 are shown as having a rectangular pad shape with different widths in a first horizontal direction (X direction) and a second horizontal direction (Y direction), but are not limited thereto. For example, the multiple conductive patterns 162 may each have a planar geometric shape (such as a square, a rhombus, and / or a circle, etc.). In addition, different from the description in Figures 4A to 4C , the multiple conductive patterns 162 may each have a line shape extending in a horizontal direction (X direction and / or Y direction). Figures 4A to 4C shows the planar arrangement relationship among the multiple conductive patterns 162, the insulating spacers 164, and the compensation pattern 174 according to an exemplary embodiment, but the exemplary embodiments of the inventive concept are not limited thereto, and the planar arrangement relationship may be modified and changed in various ways by those of ordinary skill in the art within the technical spirit and scope of the inventive concept.

[0066] In some embodiments, the multiple conductive patterns 162 and the compensation pattern 174 may each include a metal (such as Cu, Al, W, Ti, Ta, In, Mo, Mn, Co, Sn, Ni, Mg, Re, Be, Ga, or Ru, or an alloy thereof).

[0067] In some embodiments, the multiple conductive patterns 162 and the compensation pattern 174 may include the same material. In some other embodiments, the multiple conductive patterns 162 and the compensation pattern 174 may include different materials. In some embodiments, the multiple conductive patterns 162 may include the same material as the second interconnect lines 144 of the second interconnect layer 142 and the multiple second interconnect vias 146.

[0068] In some embodiments, the insulating spacer 164 may include an oxide layer (such as a TEOS, PSG, BPSG, USG, PE-TEOS, or HDP-CVD layer), a carbon-containing oxide layer (such as a SiOC or SiCOH layer), a silicon nitride layer, a carbon-containing nitride layer, and / or a combination thereof, etc.

[0069] The interconnect structure 152 and the front-side interconnect layer 160 may form a back-end-of-line (BEOL) structure disposed on the second surface 102F of the semiconductor substrate 102. In some embodiments, the thickness of the interconnect lines constituting the BEOL structure may increase as the distance from the second surface 102F of the semiconductor substrate 102 increases. In some embodiments, the thickness of the plurality of conductive patterns 162 in the vertical direction (Z direction) may be greater than the thickness of the plurality of first interconnect lines 124 and the second interconnect lines 144 in the vertical direction (Z direction). In some other embodiments, the vertical thickness of the plurality of conductive patterns 162 may be substantially equal to the vertical thickness of the second interconnect lines 144 and may be greater than the vertical thickness of the plurality of first interconnect lines 124.

[0070] The semiconductor chip 100 according to an exemplary embodiment may include a compensation pattern 174 disposed between the plurality of conductive patterns 162, and thus may cause a uniform pattern density in each region within the front-side interconnect layer 160. Accordingly, surface deformation of the front surface 100F of the semiconductor chip 100 that may occur when the plurality of conductive patterns 162 are only concentrated in some regions in a plan view may be reduced. The compensation pattern 174 according to some embodiments may include a material having a relatively high thermal conductivity (such as a metal), and thus, the heat dissipation characteristics of the semiconductor chip 100 may also be improved.

[0071] According to some exemplary embodiments, the plurality of front-side bonding pads 184 may pass through the front-side dielectric layer 182 and the insulating spacer 164 and may each contact at least some of the plurality of conductive patterns 162. The plurality of front-side bonding pads 184 may be arranged to be separated from each other in the horizontal direction (X direction and / or Y direction) and may be exposed on the front surface 100F of the semiconductor chip 100. The plurality of front-side bonding pads 184 may be connected to the interconnect structure 152 through the plurality of conductive patterns 162.

[0072] In some embodiments, each of the plurality of front-side bonding pads 184 may be in contact with a second surface 162b of a corresponding one of the plurality of conductive patterns 162. In some embodiments, a sidewall of each of the plurality of front-side bonding pads 184 may include a portion in contact with the front-side dielectric layer 182 and a portion in contact with the insulating spacer 164. The insulating spacer 164 may cover a portion of the second surface 162b of each of the plurality of conductive patterns 162 that is not in contact with the plurality of front-side bonding pads 184. In some embodiments, a sidewall of each of the plurality of front-side bonding pads 184 may include a portion facing the compensation pattern 174, and the insulating spacer 164 is between the portion of the sidewall of each of the plurality of front-side bonding pads 184 facing the compensation pattern 174 and the compensation pattern 174.

[0073] In some embodiments, the plurality of front-side bonding pads 184 may include a metal conductive material (such as chromium (Cr), tungsten (W), titanium (Ti), copper (Cu), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), and / or a combination thereof, etc.). In some embodiments, the metal conductive material of the plurality of front-side bonding pads 184 may be selected based on bonding compatibility with, for example, solder or a direct bonding member.

[0074] In some embodiments, the front-side dielectric layer 182 may include an electrically insulating material (such as at least one of SiO, SiN, SiCN, SiCO, and / or a polymer-based insulator material, etc.). For example, the polymer-based insulator material may be and / or include BCB, PI, PBO, silicone, and / or epoxy resin. In some embodiments, the front-side dielectric layer 182 may have a multi-layer structure including a plurality of insulating material layers stacked in the vertical direction (Z direction).

[0075] Referring to Figure 1 , the semiconductor chip 100 may include a passivation layer 192 and a back-side dielectric layer 194 (e.g., a back-side insulating layer) sequentially stacked on a first surface 102B of the semiconductor substrate 102. The semiconductor chip 100 includes a plurality of through electrodes 106 passing through the semiconductor substrate 102 and the passivation layer 192 in the vertical direction (Z direction), and a plurality of back-side bonding pads 196 respectively in contact with the plurality of through electrodes 106 on a lower surface of the passivation layer 192 and surrounded by the back-side dielectric layer 194. For example, a sidewall of each of the plurality of back-side bonding pads 196 may be surrounded by the back-side dielectric layer 194.

[0076] In some embodiments, the plurality of vias 106 may each have a columnar shape extending through the semiconductor substrate 102, the interlayer dielectric layer 104, and the passivation layer 192. In some embodiments, one end of each of the plurality of vias 106 in the vertical direction (Z direction) may pass through the interlayer dielectric layer 104 and contact and connect to the lowermost first interconnect line 124 among the plurality of first interconnect lines 124. The other ends of the plurality of vias 106 in the vertical direction (Z direction) may respectively contact and connect to the plurality of backside bonding pads 196. The plurality of vias 106 may form a circuit path between the plurality of backside bonding pads 196 and at least some of various semiconductor devices (not shown) formed on the second surface 102F of the semiconductor substrate 102. The circuit path may be configured such that, for example, the various semiconductor devices (not shown) can communicate with and / or receive power from an external device (not shown) connected to the plurality of backside bonding pads 196.

[0077] Although not shown in the drawings, each of the plurality of vias 106 may include a conductive plug extending in the vertical direction (Z direction) and a conductive barrier layer provided on the outer surface of the conductive plug. In some embodiments, the conductive plug may include a metallic conductive material (such as, Cu, Ni, Au, Ag, W, Ti, Ta, In, Mo, Mn, Co, Sn, Mg, Re, Be, Ga, Ru, and / or a combination thereof, etc.). In some embodiments, the conductive barrier layer may include Ti, titanium nitride (TiN), Ta, tantalum nitride (TaN), W, tungsten nitride (WN), Ru, Co, and / or a combination thereof, etc. In some embodiments, the semiconductor chip 100 may include a via insulating layer disposed between the plurality of vias 106 and the semiconductor substrate 102, between the plurality of vias 106 and the interlayer dielectric layer 104, and between the plurality of vias 106 and the passivation layer 192. In some embodiments, the via insulating layer may include an ozone / tetraethyl orthosilicate (O3 / TEOS)-based high aspect ratio process (HARP) oxide, but is not limited thereto.

[0078] In some embodiments, the passivation layer 192 and the backside dielectric layer 194 may each include an oxide and / or a nitride. In some embodiments, the passivation layer 192 may include at least one of SiO, SiN, SiCN, SiCO, and a polymer material. For example, the polymer material may be and / or include benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), silicone, and / or epoxy resin. For example, the passivation layer 192 and the backside dielectric layer 194 may each have a multi-layer structure including a plurality of insulating material layers stacked in the vertical direction (Z direction).

[0079] In some embodiments, the plurality of backside bonding pads 196 may include a metal conductive material (such as Cr, W, Ti, Cu, Ni, Al, Pd, Au, and / or combinations thereof, etc.). In some embodiments, the metal conductive material of the plurality of backside bonding pads 196 may be selected based on bonding compatibility with, for example, solder or a direct bonding member.

[0080] According to an exemplary embodiment, the semiconductor chip 100 includes a front-side interconnect layer 160 disposed on the second surface 102F of the semiconductor substrate 102 closest to the front surface 100F of the semiconductor chip 100. In a plan view, regions in the front-side interconnect layer 160 where the plurality of conductive patterns 162 are not provided are filled with compensation patterns 174, and the compensation patterns 174 may be separated from the plurality of conductive patterns 162 by insulating spacers 164. The first surface 162a of each of the plurality of conductive patterns 162 is in contact with the upper surface of the interconnect structure 152 (e.g., the upper surface 142u of the second interconnect layer 142), but the compensation patterns 174 are separated from the interconnect structure 152, and the insulating spacers 164 are between the compensation patterns 174 and the interconnect structure 152. The compensation patterns 174 and the insulating spacers 164 may be formed to conformally cover the upper surface 142u of the second interconnect layer 142 and the plurality of conductive patterns 162 after the plurality of conductive patterns 162 are formed. Thus, the first separation distance da1 between the compensation patterns 174 and the plurality of conductive patterns 162 can be adjusted with low process difficulty.

[0081] Figure 5A is a cross-sectional view showing a partial region of the semiconductor chip 100a according to some other embodiments. Specifically, Figure 5A shows the region corresponding to Figure 1 the region EXA1 in. Figure 5B is Figure 5A an enlarged view of the region EXB1 in. In Figure 5A and Figure 5B , the same reference numerals as in Figures 1 to 4C indicate the same components, and their repeated descriptions are omitted here.

[0082] Referring to Figure 5A and Figure 5B , the insulating spacer 164 may include a first spacer layer 164a and a second spacer layer 164b sequentially stacked on the upper surface of the interconnect structure 152 (e.g., the upper surface 142u of the second interconnect layer 142).

[0083] According to some example embodiments, the first spacer layer 164a may cover and contact the upper surface 142u of the second interconnect layer 142, the sidewalls 162s of each of the plurality of conductive patterns 162, and a portion of the second surface 162b of each of the plurality of conductive patterns 162. According to some example embodiments, the second spacer layer 164b may cover and contact the first surface 174a and the sidewalls 174s of the compensation pattern 174 on the first spacer layer 164a, but may not cover the second surface 162b of each of the plurality of conductive patterns 162. For example, according to some example embodiments, the second spacer layer 164b may not be vertically stacked with the second surface 162b of each of the plurality of conductive patterns 162.

[0084] In some embodiments, the second spacer layer 164b may be spaced apart from the plurality of conductive patterns 162 in a horizontal direction (X direction and / or Y direction). In some embodiments, the second surface 162b of each of the plurality of conductive patterns 162 may be spaced apart from the front-side dielectric layer 182, and the first spacer layer 164a is between the second surface 162b of each of the plurality of conductive patterns 162 and the front-side dielectric layer 182. In some embodiments, the first spacer layer 164a and the second spacer layer 164b may be disposed between the sidewalls 162s of each of the plurality of conductive patterns 162 and the sidewalls 174s of the compensation pattern 174. In some embodiments, the first separation distance da1 may be the sum of the thickness of the first spacer layer 164a and the thickness of the second spacer layer 164b.

[0085] In some embodiments, the first spacer layer 164a and the second spacer layer 164b may be disposed between the compensation pattern 174 and the interconnect structure 152. For example, the second separation distance da2 may be the sum of the thickness of the first spacer layer 164a and the thickness of the second spacer layer 164b. In some embodiments, the distance in the vertical direction (Z direction) between the second surface 162b of each of the plurality of conductive patterns 162 and the front-side dielectric layer 182 may be less than the second separation distance da2. In some embodiments, the distance in the vertical direction (Z direction) between the second surface 162b of each of the plurality of conductive patterns 162 and the front-side dielectric layer 182 may be substantially equal to the thickness of the first spacer layer 164a.

[0086] In some embodiments, the uppermost surface of the first spacer layer 164a and the uppermost surface of the second spacer layer 164b may each contact the front-side dielectric layer 182 and may constitute the uppermost surface 164um of the insulating spacer 164. In some embodiments, the uppermost surface of the first spacer layer 164a may be coplanar with the uppermost surface of the second spacer layer 164b.

[0087] In some embodiments, the sidewalls of each of the plurality of front-side bonding pads 184 may be in contact with the first spacer layer 164a and the front-side dielectric layer 182, but may not be in contact with the second spacer layer 164b.

[0088] In Figure 5A and Figure 5B the thickness of the first spacer layer 164a is shown to be less than the thickness of the second spacer layer 164b, but the exemplary embodiments are not limited thereto. In some embodiments, the thickness of the first spacer layer 164a may be equal to or greater than the thickness of the second spacer layer 164b. In Figure 5A and Figure 5B the insulating spacer 164 is shown to include two spacer layers 164a and 164b, but the exemplary embodiments of the inventive concept are not limited thereto. For example, the insulating spacer 164 may include three or more spacer layers.

[0089] Figure 6 is a cross-sectional view showing a partial region of the semiconductor chip 100b according to some other embodiments. Specifically, Figure 6 shows a region corresponding to the region EXA1 in Figure 1 . In Figure 6 the same reference numerals as in Figures 1 to 4C as well as Figure 5A and Figure 5B indicate the same components, and their repeated descriptions are omitted herein.

[0090] Referring to Figure 6 , the insulating spacer 164 of the semiconductor chip 100b may cover the sidewalls 162s of each of the plurality of conductive patterns 162, but does not cover the second surfaces 162b of each of the plurality of conductive patterns 162. According to some exemplary embodiments, the plurality of front-side bonding pads 184 may pass through the front-side dielectric layer 182 and be in contact with the plurality of conductive patterns 162. In some embodiments, the sidewalls of each of the plurality of front-side bonding pads 184 may be surrounded by the front-side dielectric layer 182. In some embodiments, a portion of the second surface 162b of each of the plurality of conductive patterns 162 (the portion not in contact with the plurality of front-side bonding pads 184) may be in contact with the front-side dielectric layer 182.

[0091] In some embodiments, the second surface 162b of each of the plurality of conductive patterns 162 and the second surface 174b of the compensation pattern 174 may be at the same vertical level (and / or substantially similar vertical levels). In some embodiments, the second surface 162b of each of the plurality of conductive patterns 162, the second surface 174b of the compensation pattern 174, and the uppermost surface 164um of the insulating spacer 164 may be coplanar. In some embodiments, the thickness of each of the plurality of conductive patterns 162 in the vertical direction (Z direction) may be greater than the thickness of the compensation pattern 174 in the vertical direction (Z direction). In some embodiments, the sidewalls 174s of the compensation pattern 174 may face the plurality of conductive patterns 162, but may not face the plurality of front-side bonding pads 184.

[0092] Figure 7 is a cross-sectional view showing a partial region of the semiconductor chip 100c according to some other embodiments. Specifically, Figure 7 shows the region corresponding to the region EXA1 in Figure 1 . In Figure 7 , the same reference numerals as in Figures 1 to 4C , Figure 5A and Figure 5B as well as Figure 6 indicate the same components, and their repeated descriptions are omitted here.

[0093] Referring to Figure 7 , the semiconductor chip 100c may include a plurality of first front-side dummy pads 186 (or, at least one first front-side dummy pad 186) that pass through the front-side dielectric layer 182 and contact the compensation pattern 174. For example, the plurality of first front-side dummy pads 186 may contact the second surface 174b of the compensation pattern 174. In some embodiments, the plurality of first front-side dummy pads 186 may be exposed at the front surface 100F of the semiconductor chip 100c, and the upper surfaces of the plurality of first front-side dummy pads 186 may be exposed at the front surface 100F of the semiconductor chip 100c. The upper surfaces of the plurality of first front-side dummy pads 186 may be coplanar with the upper surfaces of the front-side bonding pads 184. In some embodiments, the plurality of first front-side dummy pads 186 may be separated from the plurality of front-side bonding pads 184, with the front-side dielectric layer 182 between the plurality of first front-side dummy pads 186 and the plurality of front-side bonding pads 184.

[0094] The plurality of first front-side dummy pads 186 may be disposed on the compensation pattern 174, and the compensation pattern 174 is not vertically stacked with the plurality of front-side bonding pads 184 and reduces the pattern density deviation in each region within the front-side dielectric layer 182. Although only one first front-side dummy pad 186 is shown in Figure 7 , the plurality of first front-side dummy pads 186 may be arranged to be separated from each other on the compensation pattern 174 extending in the horizontal direction (X direction and / or Y direction).

[0095] Figure 8A is a cross-sectional view showing a partial region of a semiconductor chip 100d according to some other embodiments. Specifically, Figure 8A shows a region corresponding to the region EXA1 in Figure 1 . Figure 8B is a plan view showing a partial configuration of a semiconductor chip 100d according to some other embodiments. In Figure 8A and Figure 8B , the same reference numerals as those in Figures 1 to 7 indicate the same components, and their repeated descriptions are omitted here.

[0096] Referring to Figure 8A and Figure 8B , the semiconductor chip 100d may include a plurality of dummy patterns 163 and a plurality of second front-side dummy pads 187. According to an exemplary embodiment, the plurality of dummy patterns 163 and the plurality of second front-side dummy pads 187 may have substantially the same structure as the plurality of conductive patterns 162 and the plurality of front-side bonding pads 184 described with reference to Figures 1 to 7 . However, the plurality of dummy patterns 163 may not be in contact with the plurality of second interconnect vias 146 and / or the second interconnect lines 144 in the second interconnect layer 142. For example, the plurality of dummy patterns 163 may not be connected to the conductive structures 124, 126, 144, and 146 that constitute the interconnect structure 152. In the plan view, the plurality of dummy patterns 163 and the plurality of second front-side dummy pads 187 may not be electrically connected to the conductive structures 124, 126, 144, and 146, and may improve the topological characteristics of the front surface 100F of the semiconductor chip 100 by filling the region where the plurality of conductive patterns 162 are not provided.

[0097] For example, a plurality of dummy patterns 163 may be in contact with the upper surface 142u of the second interconnect layer 142, and may be separated from each other and from the plurality of conductive patterns 162. The plurality of dummy patterns 163 may be separated from the compensation pattern 174, with an insulating spacer 164 therebetween. The insulating spacer 164 may include a portion disposed between the plurality of dummy patterns 163 and the front-side dielectric layer 182. For example, the upper surface of each of the plurality of dummy patterns 163 may be spaced apart from the front-side dielectric layer 182, with the insulating spacer 164 therebetween. A plurality of second front-side dummy pads 187 may individually contact the plurality of dummy patterns 163 by passing through the front-side dielectric layer 182 and the insulating spacer 164. The sidewall of each of the plurality of second front-side dummy pads 187 may include a portion facing the front-side dielectric layer 182 and a portion facing the compensation pattern 174. In some embodiments, the insulating spacer 164 may include a portion in contact with the sidewall 163s of each of the plurality of dummy patterns 163 and a portion in contact with the sidewall of each of the plurality of second front-side dummy pads 187.

[0098] Referring Figure 8B , in a plan view, the plurality of dummy patterns 163 may be surrounded by the insulating spacer 164 and may be surrounded by the compensation pattern 174, with the insulating spacer 164 therebetween. As Figure 8B shown, a first group of dummy patterns 163 selected from among the plurality of dummy patterns 163 may each be disposed within one via hole HP and have an independent island shape. For example, each of the first group of dummy patterns 163 may be separated from the compensation pattern 174 by a first separation distance da1.

[0099] In some embodiments, a second group of dummy patterns 163 selected from among the plurality of dummy patterns 163 may be disposed within one via hole HP and adjacent to each other. For example, two dummy patterns 163 selected from the second group of dummy patterns 163 may be arranged to be separated from each other, with the insulating spacer 164 therebetween. A third pattern pitch dpw3, which is the distance between two dummy patterns 163 selected from the second group of dummy patterns 163 and arranged adjacent to each other, may be less than twice the first separation distance da1. Thus, in at least some of these cases, the third pattern pitch dpw3 may be less than twice the first separation distance da1 and greater than or equal to the first separation distance da1 (e.g., da1 ≤ dpw3 < (2 × da1)).

[0100] In some embodiments, a third set of dummy patterns 163 selected from among the plurality of dummy patterns 163 may be disposed within a via HP and adjacent to some of the conductive patterns 162. For example, each of the third set of dummy patterns 163 may be separated from an adjacent conductive pattern 162 or another dummy pattern 163, with an insulating spacer 164 therebetween. For example, a fourth pattern pitch dpw4, which is the distance between a selected one of the third set of dummy patterns 163 and an adjacent conductive pattern 162, may be less than twice the first separation distance da1. Thus, in at least some of these cases, the fourth pattern pitch dpw4 may be less than twice the first separation distance da1 and greater than or equal to the first separation distance da1 (e.g., da1 ≤ dpw4 < (2 × da1)).

[0101] In some embodiments, some of the plurality of dummy patterns 163 may be separated from other dummy patterns or conductive patterns 162 among the plurality of dummy patterns 163, with a compensation pattern 174 therebetween. For example, a first dummy pattern 163 selected from among the plurality of dummy patterns 163 and disposed within a first via HP among the plurality of vias HP may be separated from another dummy pattern 163 or a conductive pattern 162 by a fifth pattern pitch dpw5, the other dummy pattern 163 or conductive pattern 162 being disposed within a second via HP selected from among the plurality of vias HP and disposed adjacent to the first via HP. For example, the fifth pattern pitch dpw5 may be greater than twice the first separation distance da1. In some embodiments, the first dummy pattern 163 may be disposed between a first conductive pattern 162 and a second conductive pattern 162 disposed within different vias HP. The compensation pattern 174 may include portions disposed between the first conductive pattern 162 and the first dummy pattern 163 and between the second conductive pattern 162 and the first dummy pattern 163, and may be separated from each of the first dummy pattern 163, the first conductive pattern 162, and the second conductive pattern 162, with an insulating spacer 164 therebetween. In one example, the insulating spacer 164 may separate the compensation pattern 174, the first dummy pattern 163, the first conductive pattern 162, and the second conductive pattern 162 from each other.

[0102] Figure 8BShows the planar arrangement relationship among a plurality of conductive patterns 162, a plurality of dummy patterns 163, insulating spacers 164, and a compensation pattern 174 according to an exemplary embodiment. However, the exemplary embodiments of the inventive concept are not limited thereto, and the planar arrangement relationship can be modified and changed in various ways by those of ordinary skill in the art within the technical spirit and scope of the inventive concept.

[0103] Hereinafter, a method of manufacturing a semiconductor chip according to an embodiment will be described using specific examples.

[0104] Figures 9A to 9F Is a cross-sectional view shown according to the process sequence for explaining a method of manufacturing a semiconductor chip 100 according to some exemplary embodiments. Specifically, Figures 9A to 9F Is related to Figure 1 A cross-sectional view of the corresponding part of the area EXA1 in, which is shown according to the process sequence. Referring to Figures 9A to 9F Will describe the manufacturing Figures 1 to 4C An exemplary method of the semiconductor chip 100 shown in. In Figures 9A to 9F In, the same reference numerals as in Figures 1 to 4C Indicate the same components, and their repeated descriptions are omitted here.

[0105] Referring to Figure 9A After forming a plurality of semiconductor devices on the second surface 102F of the semiconductor substrate 102, an interlayer insulating layer 104 may be formed, and a plurality of vias 106 passing through the interlayer insulating layer 104 and a part of the semiconductor substrate 102 may be formed. For example, the plurality of vias 106 may pass through the interlayer insulating layer 104, extend into the semiconductor substrate 102, and be partially buried in the semiconductor substrate 102.

[0106] Thereafter, an interconnect structure 152 may be formed on the second surface 102F of the semiconductor substrate 102. For example, a first interconnect layer 122 and a second interconnect layer 142 may be sequentially formed on the interlayer insulating layer 104 and the plurality of vias 106.

[0107] In some embodiments, the first interconnect layer 122 may be formed by an inlay process (or a damascene process) using an electroplating method, and the second interconnect layer 142 may be formed by a photolithography process (photo process) for depositing a metal material by physical vapor deposition (PVD) and then patterning the deposited material. In some other embodiments, both the first interconnect layer 122 and the second interconnect layer 142 may be formed using an inlay process.

[0108] Thereafter, a compensation material layer covering the upper surface 142u of the second interconnection layer 142 may be formed, and then a pattern mask (not shown) may be formed on the compensation material layer to expose partial regions of the compensation material layer. Partial regions of the compensation material layer may be removed by using the pattern mask (not shown) as an etching mask to form a plurality of conductive patterns 162 on the upper surface 142u of the second interconnection layer 142. Thereafter, the pattern mask (not shown) may be removed by an ashing process or the like. In some embodiments, some of the plurality of conductive patterns 162 may be in contact with some of the plurality of second interconnection vias 146 exposed through the upper surface 142u of the second interconnection layer 142.

[0109] Referring to Figure 9B , an insulating spacer 164 may be formed to conformally cover Figure 9A the resulting surface. In some embodiments, the insulating spacer 164 may conformally cover the second surface 162b of each of the plurality of conductive patterns 162, the sidewalls 162s of each of the plurality of conductive patterns 162, and a portion of the upper surface 142u of the second interconnection layer 142 that is not vertically stacked with the plurality of conductive patterns 162. In some embodiments, the thickness of the insulating spacer 164 may be substantially equal to the first separation distance da1 (see Figure 3 ).

[0110] In some embodiments, the vertical level of the first portion of the insulating spacer 164 that is vertically stacked with the plurality of conductive patterns 162 may be higher than the vertical level of the second portion of the insulating spacer 164 that is in contact with the upper surface 142u of the second interconnection layer 142. For example, compared with the upper surface of the first portion that is closer to the second surface 102F of the semiconductor substrate 102, the upper surface of the second portion may be arranged to be closer to the second surface 102F of the semiconductor substrate 102, and the plurality of conductive patterns 162 and the insulating spacer 164 may form a concavo-convex structure including a plurality of convex portions CC1 and concave portions CC2.

[0111] Referring to Figure 9C , under Figure 9B the result, a compensation material layer 172 covering the upper surface of the concavo-convex structure may be formed. In some embodiments, the compensation material layer 172 may be formed to have a sufficient thickness to fill the concave portions CC2 of the concavo-convex structure. For example, the upper surface of the portion of the compensation material layer 172 disposed in a region not vertically stacked with the plurality of conductive patterns 162 may be disposed at a vertical level higher than the vertical level of the upper surfaces of the plurality of convex portions CC1 of the concavo-convex structure.

[0112] In some embodiments, when two adjacent conductive patterns 162 among the plurality of conductive patterns 162 are separated from each other by a second pattern interval dpw2 (see Figure 4B ), the two adjacent conductive patterns 162 may constitute a convex portion CC1. For example, in Figures 4A to 4CAmong them, the plurality of holes HP may each be a region forming one convex portion selected from the plurality of convex portions CC1, and according to the process described below, the compensation pattern 174 may be formed by a compensation material layer 172 filling the recess CC2 defined between the plurality of convex portions CC1 (see Figure 9C ).

[0113] Refer to Figure 9D , as a result of Figure 9C , the compensation pattern 174 may be formed by planarizing the compensation material layer 172 so as to expose the insulating spacer 164. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process, an etch-back process, and / or a combination thereof, etc.

[0114] In some embodiments, the insulating spacer 164 may be used as a stop during the grinding process for removing the compensation material layer 172 and planarizing the compensation material layer 172. The grinding process may be performed such that the uppermost surface 164um of the insulating spacer 164 is exposed, and the second surface 174b of the compensation pattern 174 and the uppermost surface 164um of the insulating spacer 164 may be located at the same vertical level. In some embodiments, the plurality of conductive patterns 162 may be surrounded by the insulating spacer 164 and not be exposed.

[0115] In some embodiments, the compensation pattern 174 may be spaced apart from the plurality of conductive patterns 162 (the insulating spacer 164 is between the compensation pattern 174 and the plurality of conductive patterns 162), and may fill the recess CC2 of the uneven structure ( Figure 9B ) to reduce the pattern density deviation of each region within the front-side interconnect layer 160.

[0116] In some other embodiments, as a result of Figure 9C , the compensation material layer 172 and the insulating spacer 164 may be planarized so as to expose the plurality of conductive patterns 162. In this case, the portion of the insulating spacer 164 covering the second surface 162b of each of the plurality of conductive patterns 162 may be removed, and the second surface 162b of each of the plurality of conductive patterns 162 and the second surface 174b of the compensation pattern 174 may be in the same plane. Thereafter, the semiconductor chip 100b described with reference to Figure 9E and Figure 9F may be manufactured by performing the same process as the process described with reference to Figure 6 .

[0117] Refer to together Figure 9E and Figure 9F , as a result of Figure 9DUnder the result, a front dielectric layer 182 covering the front interconnect layer 160 can be formed. For example, the front dielectric layer 182 can be in contact with the uppermost surface 164um of the insulating spacer 164 and the second surface 174b of the compensation pattern 174.

[0118] Thereafter, a plurality of first openings op1 can be formed to at least partially expose the second surface 162b of each of the plurality of conductive patterns 162. In some embodiments, the plurality of first openings op1 can be formed by forming a pattern mask on the front dielectric layer 182 and then removing a portion of the front dielectric layer 182 and a portion of the insulating spacer 164 via an etching process.

[0119] Referring together Figure 9F and Figures 1 to 4C In Figure 9F Under the result, a plurality of front side bonding pads 184 individually filling the plurality of first openings op1 can be formed. In some embodiments, a metal seed layer covering the inner walls and bottom surfaces of the plurality of first openings op1 can be formed, and then a metal core layer can be formed from the metal seed layer by an electroplating process to form the plurality of front side bonding pads 184.

[0120] Thereafter, a portion of the semiconductor substrate 102 can be removed to expose the plurality of through electrodes 106 and form a first surface 102B of the semiconductor substrate 102. In some embodiments, the ends of the plurality of through electrodes 106 on the first surface 102B can penetrate through the semiconductor substrate 102 and protrude from the first surface 102B of the semiconductor substrate 102. Thereafter, a passivation layer 192 can be formed to cover the first surface 102B of the semiconductor substrate 102 and the exposed portions of the plurality of through electrodes 106, and then a polishing process can be performed to form the plurality of through electrodes 106. For example, the passivation layer 192 and the lower surfaces of the plurality of through electrodes 106 can be in the same plane. Thereafter, a backside dielectric layer 194 can be formed to cover the lower surface of the passivation layer 192 and the lower surfaces of the plurality of through electrodes 106, and then a plurality of backside bonding pads 196 respectively connected to the plurality of through electrodes 106 can be formed through the backside dielectric layer 194.

[0121] A method of manufacturing a semiconductor chip 100 according to an exemplary embodiment may include: forming a concave-convex structure including a plurality of conductive patterns 162 and insulating spacers 164, and then forming a compensation pattern 174 filling the recess CC2 of the concave-convex structure. Since the compensation pattern 174 is separated from the plurality of conductive patterns 162 by a first separation distance da1 which is the thickness of the insulating spacer 164 and is self-aligned, the topological characteristics of the front surface 100F of the semiconductor chip 100 can be improved by separating the plurality of conductive patterns 162 and the compensation pattern 174 with low process difficulty.

[0122] Figures 10A to 10Cis a cross-sectional view showing a method of manufacturing a semiconductor chip 100a according to some other embodiments. Specifically, Figures 10A to 10C is a cross-sectional view of a portion corresponding to Figure 5A and is shown according to the process sequence. Referring to Figures 10A to 10C , an example method of manufacturing the Figure 5A and Figure 5B shown in the semiconductor chip 100a will be described. In Figures 10A to 10C , the same reference numerals as in Figures 1 to 9F indicate the same components, and their repeated descriptions are omitted here.

[0123] An interconnect structure 152 including a first interconnect layer 122 and a second interconnect layer 142 can be formed on the second surface 102F of the semiconductor substrate 102 in the same manner as described with reference to Figure 9A , and a process of forming a plurality of conductive patterns 162 on the upper surface 142u of the second interconnect layer 142 can be performed.

[0124] Referring to Figure 10A , an insulating spacer 164 can be formed by sequentially forming a first spacer layer 164a and a second spacer layer 164b that conformally cover the Figure 9A result (e.g., a plurality of conductive patterns 162 and the interconnect structure 152). For example, the first spacer layer 164a can conformally cover the second surface 162b of each of the plurality of conductive patterns 162, the sidewalls 162s of each of the plurality of conductive patterns 162, and a portion of the upper surface 142u of the second interconnect layer 142 that is not vertically stacked with the plurality of conductive patterns 162. The second spacer layer 164b can be disposed on the first spacer layer 164a, and the first spacer layer 164a can be covered by the second spacer layer 164b. The second spacer layer 164b can be separated from the plurality of conductive patterns 162 and the interconnect structure 152, and the first spacer layer 164a is between the second spacer layer 164b and the plurality of conductive patterns 162 and the interconnect structure 152. In some embodiments, the plurality of conductive patterns 162, the first spacer layer 164a, and the second spacer layer 164b can form a concavo-convex structure including a convex portion CC1 and a concave portion CC2.

[0125] Referring to Figure 10B , in Figure 10A result, a compensation material layer 172 covering the upper surface of the concavo-convex structure can be formed. The compensation material layer 172 can fill the concave portion CC2 of the concavo-convex structure, and can be separated from the plurality of conductive patterns 162 and the interconnect structure 152, and the first spacer layer 164a and the second spacer layer 164b are between the compensation material layer 172 and the plurality of conductive patterns 162 and the interconnect structure 152.

[0126] Referring to Figure 10C , by makingFigure 10B The result (e.g., the compensation material layer 172 and the second spacer layer 164b) is planarized to form a compensation pattern 174, such that the first spacer layer 164a is exposed. In the planarization process, a portion of the compensation material layer 172 and a portion of the second spacer layer 164b may be removed. For example, the first spacer layer 164a may be used as a stop layer in the planarization process. In Figure 10C this case, the second spacer layer 164b vertically stacked with the plurality of conductive patterns 162 may be removed, and the second surface 162b of each of the plurality of conductive patterns 162 may be covered by the first spacer layer 164a. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process, an etch-back process, and / or a combination thereof, etc.

[0127] In some embodiments, the first spacer layer 164a may thus be spaced apart from the compensation pattern 174, and the second spacer layer 164b is between the first spacer layer 164a and the compensation pattern 174. The uppermost surface 164um of the insulating spacer 164 may be constituted by the uppermost surface of the first spacer layer 164a and the uppermost surface of the second spacer layer 164b.

[0128] Thereafter, as a result of Figure 10C this, as described with reference to Figure 9E and Figure 9F above, a front-side dielectric layer 182 covering the upper surfaces of each of the first spacer layer 164a, the second spacer layer 164b, and the compensation pattern 174 may be formed, and then a plurality of first openings op1 may be formed. Thereafter, a semiconductor chip 100a described with reference to Figure 5A and Figure 5B may be formed by forming a plurality of front-side bonding pads 184 filling the plurality of first openings op1.

[0129] Figure 11 FIG. [X] is a cross-sectional view showing a method of manufacturing a semiconductor chip 100c according to some other embodiments. Specifically, Figure 11 FIG. [X] is a cross-sectional view of a portion corresponding to Figure 7 FIG. [X]. With reference to Figure 11 FIG. [X], an exemplary method of manufacturing the semiconductor chip 100c shown in Figure 7 FIG. [X] will be described. In Figure 11 FIG. [X], the same reference numerals as in Figures 1 to 10C FIG. [X] denote the same components, and their repeated descriptions are omitted herein.

[0130] The [semiconductor chip 100c] may be manufactured by using the method with reference to Figures 9A to 9EThe described method forms an interconnect structure 152 on a second surface 102F of a semiconductor substrate 102. A front-side interconnect layer 160 including a plurality of conductive patterns 162, compensation patterns 174, and insulating spacers 164 can be formed on the interconnect structure 152, and then a front-side dielectric layer 182 can be formed on the front-side interconnect layer 160.

[0131] Referring Figure 11 , as a result of Figure 9E , a plurality of first openings op1 exposing at least a portion of a second surface 162b of each of the plurality of conductive patterns 162 and a plurality of second openings op2 exposing at least a portion of a second surface 174b of the compensation pattern 174 can be formed. For example, the plurality of first openings op1 and the plurality of second openings op2 can be formed together in the same process.

[0132] Thereafter, a plurality of front-side bonding pads 184 filling the plurality of first openings op1 and a plurality of first front-side dummy pads 186 filling the plurality of second openings op2 can be formed. Thus, a semiconductor chip 100c as described in Figure 7 can be formed. In some embodiments, the plurality of front-side bonding pads 184 and the plurality of first front-side dummy pads 186 can be formed together in the same process. For example, after forming a metal seed layer covering inner walls and bottom surfaces of each of the plurality of first openings op1 and the plurality of second openings op2 and an upper surface of the front-side dielectric layer 182, a metal core layer can be formed from the metal seed layer by electroplating. Thereafter, a polishing process can be performed such that the front-side dielectric layer 182 is exposed to form the plurality of front-side bonding pads 184 and the plurality of first front-side dummy pads 186.

[0133] Figures 12A to 12E is a cross-sectional view shown according to a process sequence for explaining a method of manufacturing a semiconductor chip 100d according to some other embodiments. Specifically, Figures 12A to 12E is a cross-sectional view of a corresponding portion, which is shown according to the process sequence. Referring Figure 8A , an example method of manufacturing the semiconductor chip 100d shown in Figures 12A to 12E and Figure 8A and Figure 8B will be described. In Figures 12A to 12E , the same reference numerals as in Figures 1 to 11 indicate the same components, and their repeated descriptions are omitted here.

[0134] Referring Figure 12A , an interconnect structure 152 including a first interconnect layer 122 and a second interconnect layer 142 can be formed on a second surface 102F of a semiconductor substrate 102 in the same manner as described in Figure 9A . Then, a plurality of conductive patterns 162 and a plurality of dummy patterns 163 can be formed on the interconnect structure 152.

[0135] In some embodiments, a plurality of conductive patterns 162 may be formed to contact a plurality of second interconnect vias 146 and connect to a second interconnect line 144, but a plurality of dummy patterns 163 may be formed not to contact the plurality of second interconnect vias 146. For example, the plurality of dummy patterns 163 may contact a second interconnect insulating layer 148 and are not connected to the second interconnect line 144.

[0136] In some embodiments, the plurality of dummy patterns 163 may be formed by the same process as the plurality of conductive patterns 162, and the plurality of conductive patterns 162 and the plurality of dummy patterns 163 may include the same material. In some embodiments, the upper surface of each of the plurality of dummy patterns 163 may be at the same vertical level as the second surface 162b of each of the plurality of conductive patterns 162.

[0137] Referring to Figure 12B , in Figure 12A As a result, an insulating spacer 164 may be formed to cover a portion of the upper surface 142u of the second interconnect layer 142 that covers the plurality of conductive patterns 162, the plurality of dummy patterns 163 and that is not vertically stacked with the plurality of conductive patterns 162 and the plurality of dummy patterns 163. For example, the insulating spacer 164 may cover the upper surface and sidewalls of each of the plurality of dummy patterns 163.

[0138] In some embodiments, the portion of the insulating spacer 164 that covers the plurality of conductive patterns 162 and the plurality of dummy patterns 163 may be disposed at a higher vertical height than the portion of the insulating spacer 164 that does not cover the plurality of conductive patterns 162 and the plurality of dummy patterns 163. The plurality of conductive patterns 162, the plurality of dummy patterns 163, and the insulating spacer 164 may form a concavo-convex structure including a convex portion CC1 and a concave portion CC2.

[0139] Referring together to Figure 12C and Figure 12D , in Figure 12B As a result, a compensation material layer 172 may be formed to cover the concavo-convex structure. For example, the compensation material layer 172 may fill the concave portion CC2 of the concavo-convex structure. Thereafter, the compensation material layer 172 may be planarized such that the insulating spacer 164 is exposed to form a compensation pattern 174. The second surface 174b of the compensation pattern 174 and the uppermost surface 164um of the insulating spacer 164 may be in the same plane. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process, an etch-back process, and / or a combination thereof, etc.

[0140] Referring to Figure 12E , in Figure 12DAs a result, after forming the front dielectric layer 182 covering the second surface 174b of the exposed "compensation pattern 174 and the uppermost surface 164um of the insulating spacer 164", a portion of the front dielectric layer 182 and a portion of the insulating spacer 164 may be removed to form a plurality of first openings op1 respectively exposing the plurality of conductive patterns 162 and a plurality of third openings op3 respectively exposing the plurality of dummy patterns 163. In some embodiments, the plurality of first openings op1 and the plurality of third openings op3 may be formed together by the same process. Thereafter, a plurality of front bonding pads 184 filling the first openings op1 and a plurality of second front dummy pads 187 filling the third openings op3 may be formed.

[0141] Figure 13 is a cross-sectional view showing a semiconductor package 1000 according to an exemplary embodiment. Figure 14 is Figure 11 an enlarged view of the region marked "EXC1" in

[0142] Referring to Figure 13 and Figure 14 , the semiconductor package 1000 may include a first semiconductor chip 200 and a plurality of second semiconductor chips 300. The plurality of second semiconductor chips 300 may be stacked on the first semiconductor chip 200 in a vertical direction (Z direction). In Figure 13 , the semiconductor package 1000 is shown as including four second semiconductor chips 300, but the number of the second semiconductor chips 300 is not limited thereto. For example, the semiconductor package 1000 may include two or more second semiconductor chips 300. In the exemplary embodiment, the semiconductor package 1000 may include a multiple of 4 second semiconductor chips 300. In the present specification, the semiconductor package 1000 may be referred to as a sub-semiconductor package.

[0143] According to the exemplary embodiment, the first semiconductor chip 200 may be electrically connected to the lowermost second semiconductor chip 300 among the plurality of second semiconductor chips 300, exchange signals, and provide power and ground. Among the plurality of second semiconductor chips 300, two adjacent second semiconductor chips 300 may be electrically connected to each other, exchange signals, and provide or receive power and ground.

[0144] According to an exemplary embodiment, the first semiconductor chip 200 may include a first semiconductor substrate 202 having an active surface 202F and an inactive surface 202B opposite to each other, a first interconnect structure 252 formed on the active surface 202F of the first semiconductor substrate 202 and including a plurality of interconnect lines and a plurality of interconnect vias, a plurality of first through electrodes 206 connected to some of the plurality of interconnect lines of the first interconnect structure 252 and passing through the first semiconductor substrate 202, a plurality of first backside bonding pads 296 connected to the plurality of first through electrodes 206 on the inactive surface 202B of the first semiconductor substrate 202, and a first backside dielectric layer 294 surrounding the sidewalls of each of the plurality of first backside bonding pads 296. Although not shown in Figure 13 , the first semiconductor chip 200 may include a first passivation layer (not shown) surrounding the upper sidewalls of the plurality of through electrodes 106 on the inactive surface 202B of the first semiconductor substrate 202, and a first interlayer insulating layer (not shown) for protecting a plurality of semiconductor devices between the active surface 202F of the first semiconductor substrate 202 and the first interconnect structure 252.

[0145] The active surface 202F of the first semiconductor substrate 202 may be the front side surface of the first semiconductor substrate 202, and the inactive surface 202B of the first semiconductor substrate 202 may be the back side surface of the first semiconductor substrate 202. In Figure 13 , the active surface 202F of the first semiconductor substrate 202 may have a downward-facing arrangement, and the active surface 202F of the first semiconductor substrate 202 may be referred to as the lower surface of the first semiconductor substrate 202.

[0146] According to some example embodiments, the first semiconductor chip 200 may include a first front-side interconnect layer 260 and a first front-side dielectric layer 282 that are sequentially stacked on a lower surface of the first interconnect structure 252. The first front-side interconnect layer 260 may be separated from the first semiconductor substrate 202, and the first interconnect structure 252 is between the first front-side interconnect layer 260 and the first semiconductor substrate 202. According to an example embodiment, the first front-side interconnect layer 260 may include a plurality of first conductive patterns 262, a first compensation pattern 274, and a first insulating spacer 264 disposed between the plurality of first conductive patterns 262 and the first compensation pattern 274. The plurality of first conductive patterns 262 may be disposed closer to the active surface 202F of the first semiconductor substrate 202 than the first compensation pattern 274 that is closer to the active surface 202F of the first semiconductor substrate 202. The first insulating spacer 264 may include a portion disposed between the first compensation pattern 274 and the first interconnect structure 252, a portion disposed between the plurality of first conductive patterns 262 and the first front-side dielectric layer 282, and a portion disposed between the plurality of first conductive patterns 262 and the first compensation pattern 274. The first front-side dielectric layer 282 may contact a lower surface of the first compensation pattern 274 and may be separated from the plurality of first conductive patterns 262, and the first insulating spacer 264 is between the first front-side dielectric layer 282 and the plurality of first conductive patterns 262. According to an example embodiment, the first semiconductor chip 200 may include a plurality of first front-side bonding pads 284 that pass through the first front-side dielectric layer 282 and the first insulating spacer 264 and respectively contact the plurality of first conductive patterns 262. In some embodiments, each first front-side bonding pad 284 may include a first portion surrounded by the first front-side dielectric layer 282 and the first insulating spacer 264, and a second portion disposed on a lower surface of the first front-side dielectric layer 282. A sidewall of the first portion may face the first compensation pattern 274, and the first insulating spacer 264 is between the sidewall of the first portion and the first compensation pattern 274. According to an example embodiment, the semiconductor package 1000 may include a plurality of connection bumps 286 respectively attached to the plurality of first front-side bonding pads 284 of the first semiconductor chip 200.

[0147] The first semiconductor substrate 202 is substantially the same or similar to Figure 1 and Figure 2 the semiconductor substrate 102 shown in, and the plurality of first vias 206 are substantially the same or similar to Figure 1 and Figure 2 the plurality of vias 106 shown in, and the first interconnect structure 252 is substantially the same or similar to Figures 1 to 3 the interconnect structure 152 shown in, and the plurality of first back-side bonding pads 296 are substantially the same or similar to Figure 1 the plurality of back-side bonding pads 196 shown in, and the first back-side dielectric layer 294 is substantially the same or similar to Figure 1The dorsal dielectric layer 194 shown in [reference] is substantially the same or similar, and the first passivation layer (not shown) is Figure 1 substantially the same or similar to the passivation layer 192 shown in [reference], and thus its detailed description is omitted. The plurality of first conductive patterns 262, the first insulating spacers 264, and the first compensation patterns 274 are respectively Figures 1 to 4C substantially the same or similar to the plurality of conductive patterns 162, the insulating spacers 164, and the compensation patterns 174 shown in [reference]. The first front-side dielectric layer 282 is Figures 1 to 3 substantially the same or similar to the front-side dielectric layer 182 shown in [reference], and the plurality of first front-side bonding pads 284 are Figures 1 to 3 substantially the same or similar to the plurality of front-side bonding pads 184 shown in [reference], and thus their detailed descriptions are omitted. However, the exemplary embodiments are not limited thereto. For example, the first front-side interconnect layer 260 may additionally be Figures 1 to 8B substantially the same or similar to the front-side interconnect layer 160 of [reference].

[0148] According to an exemplary embodiment, the second semiconductor chip 300 may include a second semiconductor substrate 302 having active surfaces 302F and inactive surfaces 302B facing each other, a second interconnect structure 352 formed on the active surface 302F of the second semiconductor substrate 302 and including a plurality of interconnect lines and a plurality of interconnect vias, a plurality of second through electrodes 306 connected to some of the plurality of interconnect lines of the second interconnect structure 352 and passing through the second semiconductor substrate 302, a second passivation layer 392 formed on the inactive surface 302B of the second semiconductor substrate 302, a plurality of second dorsal bonding pads 396 connected to the plurality of second through electrodes 306 on the second passivation layer 392, and a second dorsal dielectric layer 394 surrounding the sidewalls of each of the plurality of second dorsal bonding pads 396. According to an exemplary embodiment, the second semiconductor chip 300 may include a second interlayer insulating layer 304 disposed between the second semiconductor substrate 302 and the second interconnect structure 352 to protect semiconductor devices formed on the active surface 302F of the second semiconductor substrate 302.

[0149] The active surface 302F of the second semiconductor substrate 302 may be the front-side surface of the second semiconductor substrate 302, and the inactive surface 302B of the second semiconductor substrate 302 may be the dorsal surface of the second semiconductor substrate 302. In Figure 13 and Figure 14 , the active surface 302F of the second semiconductor substrate 302 may have a downward-facing arrangement, and the active surface 302F of the second semiconductor substrate 302 may be referred to as the lower surface of the second semiconductor substrate 302.

[0150] According to an example embodiment, the second semiconductor chip 300 may include a second front-side interconnect layer 360 and a second front-side dielectric layer 382 that are sequentially stacked on a lower surface of the second interconnect structure 352. The second front-side interconnect layer 360 may be separated from the second semiconductor substrate 302, and the second interconnect structure 352 is between the second front-side interconnect layer 360 and the second semiconductor substrate 302. According to an example embodiment, the second front-side interconnect layer 360 may include a plurality of second conductive patterns 362, a second compensation pattern 374, and second insulating spacers 364 disposed between the plurality of second conductive patterns 362 and the second compensation pattern 374. The plurality of second conductive patterns 362 may be disposed closer to the effective surface 302F of the second semiconductor substrate 302 than the second compensation pattern 374 that is closer to the effective surface 302F of the second semiconductor substrate 302. The second insulating spacers 364 may include a portion disposed between the second compensation pattern 374 and the second interconnect structure 352, a portion disposed between the plurality of second conductive patterns 362 and the second front-side dielectric layer 382, and a portion disposed between the plurality of second conductive patterns 362 and the second compensation pattern 374. The second front-side dielectric layer 382 may be in contact with a lower surface of the second compensation pattern 374 and may be separated from the plurality of second conductive patterns 362, and the second insulating spacers 364 are between the second front-side dielectric layer 382 and the plurality of second conductive patterns 362. According to an example embodiment, the second semiconductor chip 300 may include a plurality of second front-side bonding pads 384 that pass through the second front-side dielectric layer 382 and the second insulating spacers 364 and respectively contact the plurality of second conductive patterns 362. In some embodiments, each second front-side bonding pad 384 may be surrounded by the second front-side dielectric layer 382 and the second insulating spacers 364. A sidewall of each of the plurality of second front-side bonding pads 384 may include a portion facing the second compensation pattern 374, and the second insulating spacers 364 are between the portion of the sidewall of each of the plurality of second front-side bonding pads 384 facing the second compensation pattern 374 and the second compensation pattern 374.

[0151] The second semiconductor substrate 302 is substantially the same as or similar to Figure 1 and Figure 2 the semiconductor substrate 102 shown in, and the plurality of second through electrodes 306 are substantially the same as or similar to Figure 1 and Figure 2 the plurality of through electrodes 106 shown in, the second interconnect structure 352 is substantially the same as or similar to Figures 1 to 3 the interconnect structure 152 shown in, the plurality of second back-side bonding pads 396 are substantially the same as or similar to Figure 1 the plurality of back-side bonding pads 196 shown in, the second back-side dielectric layer 394 is substantially the same as or similar to Figure 1 the back-side dielectric layer 194 shown in, and the second passivation layer 392 is substantially the same as or similar to Figure 1The passivation layer 192 shown therein is substantially the same or similar, and thus its detailed description is omitted. A plurality of second conductive patterns 362, second insulating spacers 364, and second compensation patterns 374 are respectively Figures 1 to 4C substantially the same or similar to the plurality of conductive patterns 162, insulating spacers 164, and compensation patterns 174 shown therein. The second front-side dielectric layer 382 is Figures 1 to 3 substantially the same or similar to the front-side dielectric layer 182 shown therein, and the plurality of second front-side bonding pads 384 are Figures 1 to 3 substantially the same or similar to the plurality of front-side bonding pads 184 shown therein, and thus their detailed descriptions are omitted. However, the exemplary embodiments are not limited thereto. For example, the second front-side interconnect layer 360 may additionally be Figures 1 to 8B substantially the same or similar to the front-side interconnect layer 160 of

[0152] In some embodiments, the uppermost second semiconductor chip 300 among the plurality of second semiconductor chips 300 may not include the plurality of second through electrodes 306, the second passivation layer 392, the second back-side dielectric layer 394, and the plurality of second back-side bonding pads 396. In some embodiments, the vertical height of the uppermost second semiconductor chip 300 among the plurality of second semiconductor chips 300 may be greater than the vertical height of each of the remaining second semiconductor chips 300. The vertical heights of the remaining second semiconductor chips 300 may be substantially the same.

[0153] In some embodiments, the semiconductor package 1000 including the first semiconductor chip 200 and the plurality of second semiconductor chips 300 may be referred to as a high-bandwidth memory (HBM) DRAM semiconductor chip. For example, the first semiconductor chip 200 may be a buffer chip including a serial-parallel conversion circuit and controlling the plurality of second semiconductor chips 300, and the plurality of second semiconductor chips 300 may be core chips including DRAM memory cells. In the exemplary embodiment, the first semiconductor chip 200 may be referred to as the main chip, and each of the plurality of second semiconductor chips 300 may be referred to as a slave chip.

[0154] In some other embodiments, at least one of the first semiconductor chip 200 and the plurality of second semiconductor chips 300 may be a memory semiconductor chip. At least one of the first semiconductor chip 200 and the plurality of second semiconductor chips 300 may be a logic chip. Examples of the logic chip may include a CPU chip, a GPU chip, and / or an AP chip.

[0155] As Figure 14As shown, two second semiconductor chips 300 adjacent to each other in the vertical direction (Z direction) can be joined using a direct bonding method (e.g., a hybrid direct bonding method). A plurality of second backside bonding pads 396 of the lower second semiconductor chip 300 among the two adjacent second semiconductor chips 300 can be aligned and bonded to a plurality of second frontside bonding pads 384 of the upper second semiconductor chip 300 among the two adjacent second semiconductor chips 300 in the vertical direction (e.g., the Z direction). In addition, the second backside dielectric layer 394 of the lower second semiconductor chip 300 can be bonded to the second frontside dielectric layer 382 of the upper second semiconductor chip 300. The surfaces of the second backside dielectric layer 394 of the lower second semiconductor chip 300 and the second frontside dielectric layer 382 of the upper second semiconductor chip 300 can each have a bonding force suitable for bonding through plasma treatment and / or wet treatment. For example, the bonding between the two adjacent second semiconductor chips 300 can be achieved by bringing the bonding surface of the lower second semiconductor chip 300 into contact with the bonding surface of the upper second semiconductor chip 300 and then applying heat to connect the plurality of second backside bonding pads 396 and the second backside dielectric layer 394 of the lower second semiconductor chip 300 to the plurality of second frontside bonding pads 384 and the second frontside dielectric layer 382 of the upper second semiconductor chip 300, respectively.

[0156] In some embodiments, a direct bonding method that is substantially the same as or similar to the bonding method between two second semiconductor chips 300 adjacent to each other in the vertical direction (Z direction) can be used to bond the first semiconductor chip 200 and the lowermost second semiconductor chip 300 among the second semiconductor chips 300. For example, a plurality of first backside bonding pads 296 of the first semiconductor chip 200 and a plurality of second frontside bonding pads 384 of the lowermost second semiconductor chip 300 can be aligned and bonded to each other in the vertical direction (e.g., the Z direction). For example, the upper surface of the first backside dielectric layer 294 of the first semiconductor chip 200 can be in contact with the lower surface of the second frontside dielectric layer 382 of the second semiconductor chip 300.

[0157] According to some example embodiments, the semiconductor package 1000 may further include a molding layer 810 disposed on the first semiconductor chip 200 and covering the side surfaces of the plurality of second semiconductor chips 300. The molding layer 810 can cover a part of the upper surface of the first semiconductor chip 200 that is not covered by the plurality of second semiconductor chips 300. In the example embodiment, the molding layer 810 may not cover the upper surface of the uppermost second semiconductor chip 300. In other example embodiments, the molding layer 810 may be formed to further cover the upper surface of the uppermost second semiconductor chip 300. The molding layer 810 may include, for example, an epoxy molding compound (EMC).

[0158] In a semiconductor package according to a comparative example, when two semiconductor chips that do not include a compensation pattern according to an exemplary embodiment are bonded by a direct bonding method, the topology of the bonding interface between the two semiconductor chips deteriorates due to the residual stress of the plurality of conductive patterns in the front-side interconnect layer, thereby reducing the bonding reliability between the two semiconductor chips.

[0159] According to some exemplary embodiments, the compensation pattern 374 may fill the blank areas between the plurality of conductive patterns 362 in the front-side interconnect layer 360 to balance the pattern density of the front-side interconnect layer 360. Therefore, when bonding two or more semiconductor chips by direct bonding, surface deformation of the bonding interface can be reduced, voids or peeling of the insulating layer occurring at the bonding surface can be suppressed, and the bonding reliability between the two bonded semiconductor chips can be improved.

[0160] Figure 15 is a cross-sectional view showing a semiconductor package 2000 according to an exemplary embodiment.

[0161] Referring to Figure 15 , the semiconductor package 2000 may include an interposer 500, a main board 600 on which the interposer 500 is mounted, at least one sub-semiconductor package 1000 attached to the interposer 500 and including a first semiconductor chip 200 and a plurality of second semiconductor chips 300, and a third semiconductor chip 400. In Figure 14 , at least one sub-semiconductor package 1000 may correspond to the semiconductor package 1000 described with reference to Figure 13 and Figure 14 . In the present specification, the semiconductor package 2000 may also be referred to as a system.

[0162] According to some exemplary embodiments, at least one sub-semiconductor package 1000 may be attached to the interposer 500 through a plurality of first connection bumps 286. The plurality of first connection bumps 286 may be attached to a plurality of first front-side bonding pads 284 and are electrically connected to the plurality of first conductive patterns 262 of the first semiconductor chip 200 described with reference to Figure 13 and the multiple interconnect lines and a plurality of interconnect vias of the first interconnect structure 252 of the first semiconductor chip 200. The plurality of first connection bumps 286 may provide at least one of signals, power, or ground to the sub-semiconductor package 1000.

[0163] In Figure 15 , the semiconductor package 2000 is shown as including two sub-semiconductor packages 1000, but the inventive concept is not limited thereto. For example, the semiconductor package 2000 may include one sub-semiconductor package 1000 or may include three or more sub-semiconductor packages 1000.

[0164] The third semiconductor chip 400 may include a third semiconductor substrate 410 and a plurality of connection pads 420. The third semiconductor substrate 410 has an active surface on which semiconductor devices are formed. In an exemplary embodiment, each of the plurality of connection pads 420 may include at least one of aluminum, copper, and nickel. The third semiconductor chip 400 may be attached to the interposer 500 through a plurality of second connection bumps 460. The plurality of second connection bumps 460 may be attached to the plurality of connection pads 420. The third semiconductor chip 400 may be a logic chip. For example, the third semiconductor chip 400 may be a CPU chip, a GPU chip, and / or an AP chip.

[0165] The third semiconductor substrate 410 may be substantially similar to Figure 13 the first semiconductor substrate 202 and / or the second semiconductor substrate 302 shown in, and the second connection bumps 460 are substantially similar to the first connection bumps 286, and thus, the detailed description is omitted.

[0166] According to some exemplary embodiments, the interposer 500 may include a base layer 510, a plurality of first upper pads 522 and a plurality of first lower pads 524 respectively disposed on the upper surface and the lower surface of the base layer 510, and a plurality of first interconnect paths 530 that electrically connect the first upper pads 522 to the first lower pads 524 through the base layer 510. The base layer 510 may include, for example, a semiconductor, glass, ceramic, or plastic. For example, the base layer 510 may include silicon. The plurality of first interconnect paths 530 may include an interconnect layer connected to the plurality of first upper pads 522 and / or the plurality of first lower pads 524 on the upper surface and / or the lower surface of the base layer 510, and / or internal vias disposed inside the base layer 510 to electrically connect the plurality of first upper pads 522 to the plurality of first lower pads 524. The plurality of first connection bumps 286 that electrically connect the sub-semiconductor package 1000 to the interposer 500 or the plurality of second connection bumps 460 that electrically connect the third semiconductor chip 400 to the interposer 500 may be electrically connected to the plurality of first upper pads 522.

[0167] The first underfill layer 820 may be disposed between the sub-semiconductor package 1000 and the interposer 500, and the second underfill layer 480 may be disposed between the third semiconductor chip 400 and the interposer 500. The first underfill layer 820 may surround the first connection bumps 286, and the second underfill layer 480 may surround the second connection bumps 460.

[0168] The semiconductor package 2000 may further include a package molding layer 900 surrounding the side surfaces of the sub-semiconductor package 1000 and the third semiconductor chip 400 on the interposer 500. The package molding layer 900 may include, for example, EMC. In an exemplary embodiment, the package molding layer 900 may cover the upper surfaces of the sub-semiconductor package 1000 and the third semiconductor chip 400. In other exemplary embodiments, the package molding layer 900 may not cover the upper surfaces of the sub-semiconductor package 1000 and the third semiconductor chip 400. For example, a heat dissipation member may be attached to the sub-semiconductor package 1000 and the third semiconductor chip 400, and a thermal interface material (TIM) layer may be between the heat dissipation member and the sub-semiconductor package 1000 and the third semiconductor chip 400.

[0169] A plurality of board connection terminals 540 may be attached to the plurality of first under pads 524. The plurality of board connection terminals 540 may electrically connect the interposer 500 to the main board 600.

[0170] The main board 600 may include a base layer 610, a plurality of second upper pads 622 and a plurality of second under pads 624 respectively disposed on the upper surface and the lower surface of the base layer 610, and a plurality of second interconnect paths 630 electrically connecting the plurality of second upper pads 622 to the plurality of second under pads 624 through the base layer 610.

[0171] In some exemplary embodiments, the main board 600 may be a printed circuit board. For example, the main board 600 may be a multi-layer printed circuit board. The base layer 610 may include at least one material selected from phenol resin, epoxy resin, and polyimide.

[0172] A solder mask layer (not shown) exposing the plurality of second upper pads 622 and the plurality of second under pads 624 may be formed on each of the upper surface and the lower surface of the base layer 610. The plurality of board connection terminals 540 may be connected to the plurality of second upper pads 622, and a plurality of external connection terminals 640 may be connected to the plurality of second under pads 624. The plurality of board connection terminals 540 may electrically connect the plurality of first under pads 524 to the plurality of second upper pads 622. The plurality of external connection terminals 640 connected to the plurality of second under pads 624 may electrically connect and physically connect the semiconductor package 2000 to an external device.

[0173] In an exemplary embodiment, the semiconductor package 2000 may not include the main board 600, and the plurality of board connection terminals 540 of the interposer 500 may be used as external connection terminals.

[0174] Although the inventive concept has been specifically shown and described with reference to embodiments of the inventive concept, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor chip, comprising: A semiconductor substrate having a first surface and a second surface above and opposite to the first surface; an interconnect structure over the second surface of the semiconductor substrate; a plurality of conductive patterns spaced apart from the semiconductor substrate, an interconnect structure between the plurality of conductive patterns and the semiconductor substrate, the plurality of conductive patterns connected to the interconnect structure; a compensation pattern over the interconnect structure such that the compensation pattern is spaced apart from the plurality of conductive patterns in a horizontal direction and such that a distance from the compensation pattern to the second surface of the semiconductor substrate is greater than a distance from the plurality of conductive patterns to the second surface of the semiconductor substrate; as well as An insulating spacer is between the plurality of conductive patterns and the compensation pattern.

2. The semiconductor chip according to claim 1, wherein: The insulating spacer also includes a portion between the compensation pattern and the interconnection structure.

3. The semiconductor chip according to claim 1, further comprising: a front-side dielectric layer covering the plurality of conductive patterns, the compensation patterns and the insulating spacers; as well as A plurality of front side bonding pads pass through the front side dielectric layer and respectively contact the plurality of conductive patterns.

4. The semiconductor chip according to claim 3, wherein: The plurality of conductive patterns each include a first surface facing the semiconductor substrate and a second surface away from the semiconductor substrate, and the compensation pattern includes a first surface facing the semiconductor substrate and a second surface away from the semiconductor substrate. The second surface of each of the plurality of conductive patterns is spaced apart from the front dielectric layer, a portion of the insulating spacer is between the second surface of each of the plurality of conductive patterns and the front dielectric layer, and the first surface of the compensation pattern contacts another portion of the insulating spacer.

5. The semiconductor chip according to claim 3, wherein: The sidewall of the compensation pattern includes a portion facing the plurality of front side bonding pads, and an insulating spacer is between the portion of the sidewall of the compensation pattern facing the plurality of front side bonding pads and the plurality of front side bonding pads.

6. The semiconductor chip according to claim 1, wherein: The plurality of conductive patterns each include a first surface facing the semiconductor substrate and a second surface away from the semiconductor substrate, and the compensation pattern includes a first surface facing the semiconductor substrate and a second surface away from the semiconductor substrate. Wherein, the second surface of each of the plurality of conductive patterns and the second surface of the compensation pattern are on the same plane.

7. The semiconductor chip according to claim 1, wherein: The plurality of conductive patterns each include a first surface facing the semiconductor substrate and a second surface away from the semiconductor substrate, and the compensation pattern includes a first surface facing the semiconductor substrate and a second surface away from the semiconductor substrate. Wherein, the insulating spacer comprises: a first spacer layer over the interconnect structure, the first spacer layer covering the second surface of each of the plurality of conductive patterns and a sidewall of each of the plurality of conductive patterns; and A second spacer layer is on the first spacer layer, and the second spacer layer covers the first surface and the sidewalls of the compensation pattern.

8. The semiconductor chip according to claim 7, further comprising: a front-side dielectric layer covering the plurality of conductive patterns, the compensation patterns and the insulating spacers; as well as a plurality of front side bonding pads, passing through the front side dielectric layer and respectively contacting the second surfaces of the plurality of conductive patterns, wherein the second surface of each of the plurality of conductive patterns is spaced apart from the front-side dielectric layer, the first spacer layer is between the second surface of each of the plurality of conductive patterns and the front-side dielectric layer, and the sidewall of each of the plurality of conductive patterns is spaced apart from the sidewall of the compensation pattern, the first spacer layer and the second spacer layer are between the sidewall of each of the plurality of conductive patterns and the sidewall of the compensation pattern.

9. The semiconductor chip according to claim 1, further comprising: a front-side dielectric layer covering the plurality of conductive patterns, the compensation patterns and the insulating spacers; a plurality of front side bonding pads, passing through the front side dielectric layer and contacting the plurality of conductive patterns respectively; as well as At least one first front dummy pad passes through the front dielectric layer and contacts the compensation pattern.

10. The semiconductor chip according to claim 1, further comprising: a dummy pattern on the interconnect structure and between a first conductive pattern among the plurality of conductive patterns and a second conductive pattern among the plurality of conductive patterns, The compensation pattern includes a first portion between the first conductive pattern and the dummy pattern and a second portion between the second conductive pattern and the dummy pattern, and the insulating spacer separates the compensation pattern, the first conductive pattern, the second conductive pattern and the dummy pattern from each other.

11. A semiconductor chip, comprising: Semiconductor substrate; An interconnect structure, on an upper surface of the semiconductor substrate, the interconnect structure comprising a plurality of interconnect lines, a plurality of interconnect vias, and an interconnect insulation layer surrounding the plurality of interconnect lines and the plurality of interconnect vias; a plurality of conductive patterns above the interconnect structure, the plurality of conductive patterns being spaced apart from each other in a horizontal direction and having a thickness in a vertical direction greater than a thickness of the plurality of interconnect lines; a compensation pattern, above the interconnect structure, the compensation pattern being spaced apart from the plurality of conductive patterns in a horizontal direction; an insulating spacer between the compensation pattern and the plurality of conductive patterns and between the interconnect structure and the compensation pattern; a front-side dielectric layer covering the plurality of conductive patterns, the compensation patterns and the insulating spacers; as well as A plurality of front side bonding pads pass through the front side dielectric layer and the insulating spacer and contact the plurality of conductive patterns respectively.

12. The semiconductor chip according to claim 11, wherein: A lower surface of the compensation pattern is at a lower vertical level than an upper surface of each of the plurality of conductive patterns.

13. The semiconductor chip according to claim 11, wherein: In a plan view, the compensation pattern surrounds the plurality of conductive patterns.

14. The semiconductor chip according to claim 11, wherein: The plurality of conductive patterns include a first conductive pattern and a second conductive pattern adjacent to each other, the compensation pattern being between the first conductive pattern and the second conductive pattern, In the plan view, a first distance between the first conductive pattern and the compensation pattern is equal to a second distance between the second conductive pattern and the compensation pattern.

15. The semiconductor chip according to claim 11, wherein: In plan view, the compensation pattern has a plurality of holes, The plurality of conductive patterns are respectively within the plurality of holes, so that each of the plurality of conductive patterns has an independent island shape.

16. The semiconductor chip according to claim 11, wherein: In a plan view, the compensation pattern has holes for accommodating the plurality of conductive patterns, Wherein, the plurality of conductive patterns include: a first conductive pattern; and a first group of conductive patterns surrounding the first conductive pattern in a plan view so that at least a portion of the first group of conductive patterns has a sidewall facing the compensation pattern, The outer conductive patterns in the first group of conductive patterns are each spaced apart from the compensation pattern by a first separation distance, and a distance between the first conductive pattern and at least one conductive pattern in the first group of conductive patterns is less than twice the first separation distance.

17. The semiconductor chip according to claim 11, further comprising: a dummy pattern, above the interconnect structure, the dummy pattern being between a first conductive pattern among the plurality of conductive patterns and a second conductive pattern among the plurality of conductive patterns, In which, in a plan view, a first conductive pattern, a second conductive pattern and a dummy pattern are arranged in a hole in a compensation pattern, the first conductive pattern, the second conductive pattern and the dummy pattern are each separated from the compensation pattern by a first separation distance, and a first distance between the first conductive pattern and the dummy pattern and a second distance between the second conductive pattern and the dummy pattern are each less than twice the first separation distance.

18. A semiconductor package, comprising: a first semiconductor chip; as well as a second semiconductor chip bonded to the first semiconductor chip, Wherein, the first semiconductor chip comprises: The first semiconductor substrate includes a first surface and a second surface opposite to each other, a plurality of first backside bonding pads on the first surface of the first semiconductor substrate, and a first backside dielectric layer surrounding a sidewall of each of the plurality of first backside bonding pads on the first surface of the first semiconductor substrate, Wherein, the second semiconductor chip comprises: a second semiconductor substrate including a first surface facing away from the first semiconductor substrate and a second surface facing the first surface of the first semiconductor substrate, An interconnect structure is provided on the second surface of the second semiconductor substrate. a front-side interconnection layer, spaced apart from the second semiconductor substrate, and an interconnection structure between the front-side interconnection layer and the second semiconductor substrate, a second front-side dielectric layer between the front-side interconnect layer and the first back-side dielectric layer of the first semiconductor chip such that the second front-side dielectric layer of the second semiconductor chip is bonded to the first back-side dielectric layer of the first semiconductor chip, and a plurality of second front side bonding pads, passing through the second front side dielectric layer so that the plurality of second front side bonding pads are bonded to the plurality of first back side bonding pads, Among them, the front-side interconnection layer includes: a plurality of conductive patterns spaced apart from each other in a horizontal direction and each including a first surface contacting the interconnect structure and a second surface opposite to the first surface, a compensation pattern spaced apart from the plurality of conductive patterns in a horizontal direction and comprising a first surface facing the interconnect structure and a second surface opposite to the first surface, the second surface of the compensation pattern contacting the second front-side dielectric layer, and an insulating spacer between the plurality of conductive patterns and the compensation pattern and in contact with the second surface of each of the plurality of conductive patterns and the first surface of the compensation pattern, The plurality of second front side bonding pads pass through the insulating spacer and contact the second surface of each of the plurality of conductive patterns.

19. The semiconductor package according to claim 18, wherein: The sidewall of the compensation pattern includes a portion facing the plurality of second front side bonding pads, and an insulating spacer is between the portion of the sidewall of the compensation pattern facing the plurality of second front side bonding pads and the plurality of second front side bonding pads.

20. The semiconductor package according to claim 18, wherein Insulating spacers include: a first spacer layer over the interconnect structure and covering the second surface and sidewalls of each of the plurality of conductive patterns; and a second spacer layer spaced apart from the plurality of conductive patterns and covering the first surface and the sidewall of the compensation pattern, the first spacer layer being between the second spacer layer and the plurality of conductive patterns, wherein the second surface of each of the plurality of conductive patterns is spaced apart from the second front side dielectric layer, the first spacer layer is between the second surface of each of the plurality of conductive patterns and the second front side dielectric layer, and the side wall of each of the plurality of conductive patterns is spaced apart from the side wall of the compensation pattern, the first spacer layer and the second spacer layer are between the side wall of each of the plurality of conductive patterns and the side wall of the compensation pattern.

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