Frequency folding output current-limiting protection circuit

Abstract

The invention relates to the field of current-limiting protection circuits, in particular to a frequency folding output current-limiting protection circuit which comprises a starting module, a comparison module, a logic trigger module, a switching time control module, an output module and a current comparator. The difference value between the output signal of the current comparator and the oscillating voltage is amplified by the comparison module and then is output to the logic trigger module; the logic trigger module folds the switching frequency by exponential times of 2, reduces energy transmission in unit time, limits average current, reduces switching loss, performs low-frequency operation, reduces high-frequency switching noise, and reduces interference to a sensitive circuit. And during continuous overload or short circuit, the current limiting intensity can be dynamically adjusted by frequency folding, frequent turn-off is avoided, and the device is suitable for a long-time current limiting scene, such as a battery charging scene.

Description

Technical Field

[0001] The present invention relates to the field of current-limiting protection circuits, and particularly to a frequency-folded output current-limiting protection circuit. Background Art

[0002] A current-limiting protection circuit is a circuit used to limit the magnitude of current in a circuit. Its core purpose is to limit the current within a safe range when the circuit experiences abnormalities (such as load short-circuit, power supply voltage being too high, component failures, etc.) that cause the current to increase sharply, prevent the components in the circuit from being damaged due to overcurrent, and ensure the stability and reliability of the entire circuit system. Current-limiting protection circuits are widely used in many electronic fields. In power supply systems, whether it is a switching power supply or a linear power supply, the current-limiting protection circuit plays a crucial role. It can effectively prevent the power supply from outputting overcurrent, avoid the power supply itself from being damaged due to overcurrent, and at the same time protect the load devices connected to the power supply output from being impacted by excessive current.

[0003] The core working mechanism of the current-limiting protection circuit revolves around current monitoring and dynamic regulation. It first uses a specific sampling component (such as a sampling resistor) to monitor the current in the circuit in real time and converts the current signal into a voltage signal proportional to it. Subsequently, this voltage signal is compared with a pre-set current-limiting threshold voltage. Once the monitored voltage signal exceeds the threshold, indicating that the circuit current has exceeded the safe range, the circuit will trigger the current-limiting protection action.

[0004] However, the frequent turn-off and restart of traditional current-limiting protection will lead to an increase in switching losses. Especially during light overload, the efficiency drops significantly. For power devices (such as MOSFETs, inductors), the cumulative thermal stress may shorten their service life. It has poor adaptability to periodic overloads and may cause system instability due to repeated triggering of protection. Summary of the Invention

[0005] The purpose of the present invention is to provide a frequency-folded output current-limiting protection circuit, aiming to improve the problems that the frequent turn-off and restart of traditional current-limiting protection will lead to an increase in switching losses, especially during light overload, the efficiency drops significantly. For power devices (such as MOSFETs, inductors), the cumulative thermal stress may shorten their service life. It has poor adaptability to periodic overloads and may cause system instability due to repeated triggering of protection.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions: A frequency-folded output current-limiting protection circuit, comprising a startup module, a comparison module, a logic trigger module, a switching time control module, an output module, and a current comparator; Both the external drive voltage BST and the oscillation voltage SW are input to the startup module and the comparison module; the regulator oscillation frequency signal current ramp is input to the non-inverting input terminal of the current comparator, the output feedback signal is input to the external error amplifier, the output terminal of the external error amplifier outputs the feedback signal feedback to the inverting input terminal of the current comparator, and the output terminal of the current comparator and the output terminal of the startup module are electrically connected to the comparison module. The logic trigger module includes x consecutive flip-flops, the output terminals and input terminals of the consecutive flip-flops are electrically connected in sequence, the output terminal of the comparison module is electrically connected to the input terminal of the first consecutive flip-flop, the first output terminal of the last consecutive flip-flop is electrically connected to the output module and outputs a logic feedback signal to the comparison module, the second output terminal of the last consecutive flip-flop is electrically connected to the switching time control module, and the control terminal of the switching time control module is electrically connected to the comparison module. The external power supply VIN is input to the output module, and the output module outputs the oscillation voltage SW.

[0007] Further, the startup module includes MOS transistor P0, MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor P4, MOS transistor P5, MOS transistor P6 and resistor R0. The external drive voltage BST is input to the source electrodes of MOS transistor P0, MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor P4, MOS transistor P5 and MOS transistor P6. The gate and drain of MOS transistor P0, the gates of MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor P4, MOS transistor P5, MOS transistor P6 and one end of resistor R0 are electrically connected, and the other end of resistor R0 is electrically connected to the oscillation voltage SW. The drains of MOS transistor P1, MOS transistor P2, the substrate, the drains of MOS transistor P3, MOS transistor P4, MOS transistor P5 and MOS transistor P6, and the substrate are all electrically connected to the comparison module.

[0008] Further, the comparison module includes MOS transistor P7, MOS transistor P8, MOS transistor P9, MOS transistor P10, MOS transistor P11, MOS transistor P12, MOS transistor N0, MOS transistor N1, MOS transistor N2, MOS transistor N3, MOS transistor N4, MOS transistor N5, MOS transistor N6, MOS transistor N7, MOS transistor N8, MOS transistor N9, MOS transistor N10 and resistors R1, R2. The drain of MOS transistor P1 is electrically connected to the gate of MOS transistor P7 and the drain of MOS transistor N0. The drain of MOS transistor P2 is electrically connected to the sources of MOS transistors P9 and P10, and the substrate of MOS transistor P2 is electrically connected to the substrates of MOS transistors P7, P8, P9, and P10; The drain of MOS transistor P3 is electrically connected to the sources of MOS transistors P7 and P8. The drain of MOS transistor P7 is electrically connected to the gate of MOS transistor P9 and one end of resistor R1. The drain of MOS transistor P9 is electrically connected to the drain, gate of MOS transistor N1, and the gate of MOS transistor N2. The drain of MOS transistor N2 is electrically connected to the drain of MOS transistor P10, the source of MOS transistor N3, the drain of MOS transistor N4, and the gate of MOS transistor N7. The drain of MOS transistor P8 is electrically connected to the gate of MOS transistor P10 and one end of resistor R2. The output terminal of the current comparator is electrically connected to the gate of MOS transistor P8; The drain of MOS transistor P4 is electrically connected to the drain of MOS transistor N3. The drain of MOS transistor P5 is electrically connected to the gate of MOS transistor N3, the drain of MOS transistor N5, the drain, gate of MOS transistor N6, the drain of MOS transistor P11, and the gate of MOS transistor N9. The source of MOS transistor N6 is electrically connected to the gate and drain of MOS transistor N7. The source of MOS transistor N7 is electrically connected to the drain of MOS transistor N8; The logic feedback signal is input to the gates of MOS transistor N0, MOS transistor P11, and MOS transistor N8. The external drive voltage BST is input to the source of MOS transistor P11; The drain of MOS transistor P6 is electrically connected to the source of MOS transistor P12. The substrate of MOS transistor P6 is electrically connected to the substrate of MOS transistor P12. The drain of MOS transistor P12 is electrically connected to the drains of MOS transistor N9 and MOS transistor N10, and serves as the output terminal and is electrically connected to the input terminal of the first consecutive flip-flop; The control terminal of the switching time control module is electrically connected to the gates of MOS transistor N4, MOS transistor P12, and MOS transistor N10; The sources of MOS transistor N0, MOS transistor N1, MOS transistor N2, the substrate of MOS transistor N3, the substrate, source of MOS transistor N4, the source of MOS transistor N5, the substrate of MOS transistor N6, the substrate of MOS transistor N7, the source of MOS transistor N8, the source of MOS transistor N9, the source of MOS transistor N10, and the other ends of resistor R1 and resistor R2 are electrically connected to the oscillation voltage SW.

[0009] Further, the output module includes power transistor N11, The external power supply VIN is electrically connected to the drain of the power transistor N11. The first output terminal of the continuous flip-flop at the end is electrically connected to the gate of the power transistor N11. The source of the power transistor N11 outputs the oscillation voltage SW.

[0010] Furthermore, the output module further includes an inductor L1, a capacitor C1, and a diode D1. The source of the power transistor N11 is electrically connected to one end of the inductor L1 and the cathode of the diode D1. The other end of the inductor L1 is electrically connected to one end of the capacitor C1 and serves as the output terminal to output Vout. The other end of the capacitor C1 and the anode of the diode D1 are both grounded.

[0011] Furthermore, the logic trigger module includes a counter, a frequency divider, a MOS transistor P21, a MOS transistor N21, a capacitor C21, a resistor R21, a NOT gate x201, a NOT gate x202, a NOT gate x203, a NOT gate x206, a NOT gate x211, a NOT gate x215, a NOR gate y204, a NOR gate y205, a NOR gate y207, a NOR gate y208, a NOR gate y212, a NOR gate y213, a NOR gate y214, and a NAND gate z216. The external drive voltage BST is input to the source of the MOS transistor P21. The output terminal of the comparison module is electrically connected to the anode of the NOT gate z201. The cathode of the NOT gate x201 is electrically connected to the anode of the NOT gate z202. The cathode of the NOT gate x202 is electrically connected to the gates of the MOS transistor P21 and the MOS transistor N21. The drain of the MOS transistor P21 is electrically connected to one end of the resistor R21. The other end of the resistor R21 is electrically connected to the drain of the MOS transistor N21, one end of the capacitor C21, and the anode of the NOT gate x203. The source of the MOS transistor N21 and the other end of the capacitor C21 are both electrically connected to the oscillation voltage SW. The cathode of the NOT gate x203 is electrically connected to the first input terminal of the NOR gate y204 and the second input terminal of the NOR gate y207. The external control signal is electrically connected to the second input terminal of the NOR gate y205 and the first input terminal of the NOR gate y207. The output terminal of the NOR gate y205 is electrically connected to the second input terminal of the NOR gate y204. The output terminal of the NOR gate y204 is electrically connected to the first input terminal of the NOR gate y205 and the anode of the NOT gate x206. The cathode of the NOT gate x206 is electrically connected to the first input terminal of the counter. The output terminal of the NOR gate y207 is electrically connected to the first input terminal of the NOR gate y208. The first output terminal of the switching time control module is electrically connected to the second input terminal of the NOR gate y208. The output terminal of the NOR gate y208 is electrically connected to the second input terminal of the counter and the anode of the NOT gate x211. The negative electrode of the NOT gate x211 is electrically connected to the first input terminal of the NOR gate y212. The output terminal of the counter is electrically connected to the input terminal of the frequency divider. The output terminal of the frequency divider is electrically connected to the second input terminal of the NOR gate y212, the second input terminal of the NOR gate y214, and the positive electrode of the NOT gate x215. The output terminal of the NOR gate y212 is electrically connected to the first input terminal of the NOR gate y213. The output terminal of the NOR gate y213 is electrically connected to the first input terminal of the NOR gate y214 and the first input terminal of the NAND gate z216. The output terminal of the NOR gate y214 is electrically connected to the second input terminal of the NOR gate y213. The negative electrode of the NOT gate x215 is electrically connected to the second input terminal of the NAND gate z216. The output terminal of the NAND gate z216 serves as the output terminal of the logic trigger module and is electrically connected to the switch time control module, the comparison module, and the output module.

[0012] Further, the switch time control module includes an MOS transistor P31, an MOS transistor N31, a resistor R31, a capacitor C31, and a NOT gate x301. The external drive voltage BST is input to the source electrode of the MOS transistor P31. The output terminal of the logic trigger module is electrically connected to the gate electrode of the MOS transistor P31 and the gate electrode of the MOS transistor N31. The drain electrode of the MOS transistor P31 is electrically connected to one end of the resistor R31. The other end of the resistor R31 is electrically connected to the drain electrode of the MOS transistor N31, one end of the capacitor C31, and the positive electrode of the NOT gate x301. The negative electrode of the NOT gate x301 serves as the output terminal and is electrically connected to the comparison module and the logic trigger module. The source electrode of the MOS transistor N31 and the other end of the capacitor C31 are both electrically connected to the oscillation voltage SW.

[0013] After adopting the above technical solution, compared with the background technology, the present invention has the following advantages: The oscillation voltage SW serves as the virtual ground of the current limiting protection circuit. The drive voltage BST is the boost voltage for the oscillation voltage SW to be the virtual ground. The drive voltage BST controls the operation of the start module to turn on the overall circuit. When the output current of the output module exceeds the current limit within the minimum detection time, the difference between the output signal of the current comparator and the oscillation voltage is amplified by the comparison module and then output to the logic trigger module. The logic trigger module folds the switching frequency by an exponential multiple of 2, reduces the energy transmission per unit time, limits the average current while reducing the switching loss. It operates at a low frequency, reduces high-frequency switching noise, and reduces interference to sensitive circuits. And in the case of continuous overload or short circuit, the frequency folding can dynamically adjust the current limiting intensity, avoid frequent shutdowns, and is suitable for scenarios that require long-term current limiting, such as the battery charging scenario. Description of the Drawings

[0014] Figure 1This is the circuit diagram of the frequency folding output current limiting protection circuit of the present invention; Figure 2 This is the circuit diagram of the logic trigger module and the switch time control module of the frequency folding output current limiting protection circuit of the present invention; Figure 3 This is the circuit diagram of the output module of the frequency folding output current limiting protection circuit of the present invention; Figure 4 This is the output waveform diagram of the frequency folding output current limiting protection circuit of the present invention; Figure 5 This is the simulation waveform diagram of the frequency folding output current limiting protection circuit of the present invention at the critical frequency.

[0015] Explanation of reference numerals: 1. Startup module; 2. Comparison module; 3. Logic trigger module; 4. Switch time control module; 5. Output module; 6. Current comparator; 7. Inverter. Detailed implementation manners

[0016] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0017] In addition, it should be noted that: the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are all based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the devices or elements of the present invention must have a specific orientation, so it cannot be understood as a limitation to the present invention.

[0018] When an element is referred to as being "fixed to" or "disposed on" or "provided on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0019] Unless otherwise clearly defined and limited, the terms "installation", "connection", and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the invention can be understood according to specific situations. Embodiment

[0020] Please refer toFigures 1-5 As shown in the figure, this embodiment provides a frequency folding output current limiting protection circuit, including a startup module 1, a comparison module 2, a logic trigger module 3, a switching time control module 4, an output module 5, and a current comparator 6. The external drive voltage BST and the oscillation voltage SW are both input to the startup module 1 and the comparison module 2; the regulator oscillation frequency signal currentramp is input to the non-inverting input terminal of the current comparator 6, the output feedback signal is input to an external error amplifier, and the output terminal of the external error amplifier outputs the feedback signal feedback to the inverting input terminal of the current comparator 6. The output terminal of the current comparator 6 and the output terminal of the startup module 1 are electrically connected to the comparison module 2. The logic trigger module 3 includes x consecutive flip-flops, and the output terminals and input terminals of the consecutive flip-flops are electrically connected in sequence. The output terminal of the comparison module 2 is electrically connected to the input terminal of the first consecutive flip-flop. The first output terminal of the last consecutive flip-flop is electrically connected to the output module 5 and outputs a logic feedback signal to the comparison module 2; the second output terminal of the last consecutive flip-flop is electrically connected to the switching time control module 4. The control terminal of the switching time control module 4 is electrically connected to the comparison module 2. The external power supply VIN is input to the output module 5, and the output module 5 outputs the oscillation voltage SW. In this embodiment, x is an integer greater than 0.

[0021] The oscillation voltage SW serves as the virtual ground of the current limiting protection circuit, and the drive voltage BST is the boost voltage for the oscillation voltage SW to be the virtual ground. The drive voltage BST controls the operation of the startup module 1 to turn on the entire circuit. When the output current of the output module 5 exceeds the current limit within the minimum detection time, the difference between the signal output by the current comparator 6 and the oscillation voltage is amplified by the comparison module 2 and then output to the logic trigger module 3; the logic trigger module 3 folds the switching frequency by an exponential multiple of 2, reduces the energy transmission per unit time, limits the average current while reducing the switching loss. It operates at a low frequency, reduces high-frequency switching noise, and reduces interference to sensitive circuits. And in the case of continuous overload or short circuit, the frequency folding can dynamically adjust the current limiting intensity, avoid frequent shutdowns, and is suitable for scenarios that require long-term current limiting, such as the battery charging scenario.

[0022] Please refer to Figure 1 As shown in the figure, specifically, the startup module 1 includes MOS transistor P0, MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor P4, MOS transistor P5, MOS transistor P6, and resistor R0.

[0023] ​The external drive voltage BST is input to the source electrodes of MOS transistors P0, P1, P2, P3, P4, P5, and P6. The gate and drain electrodes of MOS transistor P0 are electrically connected to the gate electrodes of MOS transistors P1, P2, P3, P4, P5, P6, and one end of resistor R0. The drain electrodes of MOS transistors P1, P2, the substrate, the drain electrodes of MOS transistors P3, P4, P5, P6, and the substrate are all electrically connected to comparison module 2. The other end of resistor R0 is electrically connected to the oscillation voltage SW. The external drive voltage BST drives MOS transistors P1 - P6 to conduct, enabling the activation of the overall circuit.

[0024] Comparison module 2 includes MOS transistors P7, P8, P9, P10, P11, P12, MOS transistors N0, N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, and resistors R1, R2.

[0025] The drain electrode of MOS transistor P1 is electrically connected to the gate electrode of MOS transistor P7 and the drain electrode of MOS transistor N0. The drain electrode of MOS transistor P2 is electrically connected to the source electrodes of MOS transistors P9 and P10, and the substrate of MOS transistor P2 is electrically connected to the substrates of MOS transistors P7, P8, P9, and P10.

[0026] The drain electrode of MOS transistor P3 is electrically connected to the source electrodes of MOS transistors P7 and P8. The drain electrode of MOS transistor P7 is electrically connected to the gate electrode of MOS transistor P9 and one end of resistor R1. The drain electrode of MOS transistor P9 is electrically connected to the drain, gate electrodes of MOS transistor N1 and the gate electrode of MOS transistor N2. The drain electrode of MOS transistor N2 is electrically connected to the drain electrode of MOS transistor P10, the source electrode of MOS transistor N3, the drain electrode of MOS transistor N4, and the gate electrode of MOS transistor N7. The drain electrode of MOS transistor P8 is electrically connected to the gate electrode of MOS transistor P10 and one end of resistor R2. The output terminal of current comparator 6 is electrically connected to the gate electrode of MOS transistor P8.

[0027] The drain of MOS transistor P4 is electrically connected to the drain of MOS transistor N3; the drain of MOS transistor P5 is electrically connected to the gate of MOS transistor N3, the drain of MOS transistor N5, the drain and gate of MOS transistor N6, the drain of MOS transistor P11, and the gate of MOS transistor N9; the source of MOS transistor N6 is electrically connected to the gate and drain of MOS transistor N7, and the source of MOS transistor N7 is electrically connected to the drain of MOS transistor N8.

[0028] The logic feedback signal is input to the gates of MOS transistor N0, MOS transistor P11, and MOS transistor N8; the external drive voltage BST is input to the source of MOS transistor P11.

[0029] The drain of MOS transistor P6 is electrically connected to the source of MOS transistor P12, the substrate of MOS transistor P6 is electrically connected to the substrate of MOS transistor P12, and the drain of MOS transistor P12 is electrically connected to the drains of MOS transistor N9 and MOS transistor N10, and serves as the output terminal and is electrically connected to the input terminal of the first consecutive flip-flop.

[0030] The control terminal of the switching time control module 4 is electrically connected to the gates of MOS transistor N4, MOS transistor P12, and MOS transistor N10.

[0031] The sources of MOS transistor N0, MOS transistor N1, MOS transistor N2, the substrate of MOS transistor N3, the substrates and sources of MOS transistor N4, the source of MOS transistor N5, the substrate of MOS transistor N6, the substrate of MOS transistor N7, the source of MOS transistor N8, the source of MOS transistor N9, the source of MOS transistor N10, and the other ends of resistor R1 and resistor R2 are electrically connected to the oscillation voltage SW.

[0032] Please refer to Figure 2 As shown, specifically, the logic trigger module 3 includes a counter, a frequency divider, MOS transistor P21, MOS transistor N21, capacitor C21, resistor R21, NOT gate x201, NOT gate x202, NOT gate x203, NOT gate x206, NOT gate x211, NOT gate x215, NOR gate y204, NOR gate y205, NOR gate y207, NOR gate y208, NOR gate y212, NOR gate y213, NOR gate y214, NAND gate z216, and inverter 7.

[0033] The external drive voltage BST is input to the source of MOS transistor P21; The output terminal of the comparison module is electrically connected to the positive pole of the NOT gate z201. The negative pole of the NOT gate x201 is electrically connected to the positive pole of the NOT gate z202. The negative pole of the NOT gate x202 is electrically connected to the gates of the MOS transistor P21 and the MOS transistor N21. The drain of the MOS transistor P21 is electrically connected to one end of the resistor R21. The other end of the resistor R21 is electrically connected to the drain of the MOS transistor N21, one end of the capacitor C21, and the positive pole of the NOT gate x203. The source of the MOS transistor N21 and the other end of the capacitor C21 are both electrically connected to the oscillating voltage SW. The negative pole of the NOT gate x203 is electrically connected to the first input terminal of the NOR gate y204 and the second input terminal of the NOR gate y207. The external control signal is electrically connected to the second input terminal of the NOR gate y205 and the first input terminal of the NOR gate y207. The output terminal of the NOR gate y205 is electrically connected to the second input terminal of the NOR gate y204. The output terminal of the NOR gate y204 is electrically connected to the first input terminal of the NOR gate y205 and the positive pole of the NOT gate x206. The negative pole of the NOT gate x206 is electrically connected to the first input terminal of the counter. The output terminal of the NOR gate y207 is electrically connected to the first input terminal of the NOR gate y208. The first output terminal of the switching time control module is electrically connected to the second input terminal of the NOR gate y208. The output terminal of the NOR gate y208 is electrically connected to the second input terminal of the counter and the positive pole of the NOT gate x211. The negative pole of the NOT gate x211 is electrically connected to the first input terminal of the NOR gate y212. The output terminal of the counter is electrically connected to the input terminal of the frequency divider. The output terminal of the frequency divider is electrically connected to the second input terminal of the NOR gate y212, the second input terminal of the NOR gate y214, and the positive pole of the NOT gate x215. The output terminal of the NOR gate y212 is electrically connected to the first input terminal of the NOR gate y213. The output terminal of the NOR gate y213 is electrically connected to the first input terminal of the NOR gate y214 and the first input terminal of the NAND gate z216. The output terminal of the NOR gate y214 is electrically connected to the second input terminal of the NOR gate y213. The negative pole of the NOT gate x215 is electrically connected to the second input terminal of the NAND gate z216. The output terminal of the NAND gate z216 serves as the output terminal of the logic trigger module and is electrically connected to the switching time control module, the comparison module, and the output module. That is, the output terminal of the NAND gate z216 is electrically connected to the gate of the MOS transistor N0, the input terminal of the inverter 7, the switching time control module, and the output module. The output terminal of the inverter 7 is electrically connected to the gates of the MOS transistor P11 and the MOS transistor N8.

[0034] The external control signal has the same potential as the oscillation voltage SW when the oscillation voltage SW starts up normally. When the output current continuously exceeds the limit, that is, the input level of the logic trigger module remains unchanged continuously, the output level of the comparator is counted by the counter according to the current limiting trigger times, and the frequency divider divides the frequency according to the count value in the counter. By setting the number N of consecutive flip-flops in the frequency divider, the switching frequency can be set to be divided by 2^N (N = 0, 1, 2..7).

[0035] The switching time control module 4 includes an MOS transistor P31, an MOS transistor N31, a resistor R31, a capacitor C31, and a NOT gate x301; The external drive voltage BST is input to the source electrode of the MOS transistor P31; The output terminal of the logic trigger module is electrically connected to the gate electrodes of the MOS transistor P31 and the MOS transistor N31, that is, the output terminal of the NAND gate z216 is electrically connected to the gate electrodes of the MOS transistor P31 and the MOS transistor N31; the drain electrode of the MOS transistor P31 is electrically connected to one end of the resistor R31, and the other end of the resistor R31 is electrically connected to the drain electrode of the MOS transistor N31, one end of the capacitor C31, and the positive electrode of the NOT gate x301. The negative electrode of the NOT gate x301 is used as the output terminal and is electrically connected to the comparison module and the logic trigger module; that is, the negative electrode of the NOT gate x301 is electrically connected to the second input terminal of the NOR gate y208, the gate electrode of the MOS transistor N4, the gate electrode of the MOS transistor N10, and the gate electrode of the MOS transistor P12.

[0036] The source electrode of the MOS transistor N31 and the other end of the capacitor C31 are both electrically connected to the oscillation voltage SW. By controlling the charging delay of the resistor R31 and the capacitor C31, the states of P12, N4, and N10 are kept unchanged for a period of time, so that the power transistor N11 is ensured to be turned on within this minimum time period.

[0037] Specifically, the output module 5 includes a power transistor N11. The external power supply VIN is electrically connected to the drain electrode of the power transistor N11, and the first output terminal of the last consecutive flip-flop is electrically connected to the gate electrode of the power transistor N11, that is, the output terminal of the NAND gate z216 is electrically connected to the gate electrode of the power transistor N11; the source electrode of the power transistor N11 outputs the oscillation voltage SW. Further, please refer to Figure 3 As shown, the output module 5 further includes an inductor L1, a capacitor C1, and a diode D1. The source electrode of the power transistor N11 is electrically connected to one end of the inductor L1 and the negative electrode of the diode D1. The other end of the inductor L1 is electrically connected to one end of the capacitor C1 and is used as the output terminal to output Vout. The other end of the capacitor C1 and the positive electrode of the diode D1 are both grounded.

[0038] The current ramp of the voltage regulator oscillation frequency signal is related to the internal oscillation frequency of the voltage regulator. The feedback signal is the signal output by the output module and fed back through error amplification (Error amp). The gate voltage control signal of MOS transistor N0 is the same as that of power transistor N11. When power transistor N11 is turned on, MOS transistor N0 is also turned on. The input end of the comparison module receives the oscillation voltage SW, that is, the gate of MOS transistor P7 receives the oscillation voltage SW; the gate of MOS transistor P8 receives the result of the current comparator.

[0039] When the current of power transistor N11 exceeds the current limit within the minimum detection time, the comparison result between the output of the current comparator and the oscillation voltage SW will become low level to turn off MOS transistor N5. The gate of MOS transistor N9 is connected to a high potential to turn on, and the output of the comparator is low level. The input signals of MOS transistor P11 and MOS transistor N8 are reversed with the output of the logic trigger module, and the gate potential of MOS transistor N9 is maintained during current limiting. MOS transistors P12, N4, and N10 control the minimum turn-on time of power transistor N11. The output of the logic trigger module is used as the gate input after the capacitor charging delay of the switching time control module to control the states of MOS transistors P12, N4, and N10 to remain unchanged for a period of time, so that power transistor N11 is guaranteed to be turned on during this minimum time.

[0040] To prevent current divergence, the increase in inductor current ΔI rise during the conduction period of power transistor N11 should be equal to the decrease in inductor current ΔI fall during the off period. That is: ΔI rise =ΔI fall .

[0041] Among them, D = T ON / T SW is the ratio of the conduction time to the total period; among them, T ON is the turn-on time of power transistor N11, and T SW is the turn-on period of power transistor N11; VIN - VOUT is the voltage difference between the input and output.

[0042] IOUT·R DSON is the conduction resistance loss of the MOS transistor, where R DSON is the conduction resistance of the MOS transistor; IOUT·DCR is the DC resistance loss of inductor L1. The sum of the two gives the power path voltage drop, where DCR is the DC resistance of the inductor.

[0043] VF is the voltage drop of diode D1, and VOUT+VF is the reverse voltage driving current drop. L is the inductance value; F SW is the switching frequency.

[0044] If unbalanced, the net current increases in each cycle, leading to out-of-control current and triggering overcurrent protection. By forcing them to be equal, the system can operate stably.

[0045] Please refer to Figure 4 as shown, attached Figure 4 is the output waveform simulation diagram. From the attached Figure 4 it can be seen that at the minimum on-time Ton_min of each cycle, when the detected output current IOUT exceeds I LIM where I LIM is the limit current; then the switching frequency is folded, the frequency decreases, the switching period TSW increases, the duty cycle within each cycle decreases, and the power transistor N11 turns off, resulting in a decrease in the inductive energy storage and limiting the current growth. When overcurrent or short circuit is detected, the frequency-folded output current-limiting protection circuit reduces the switching frequency step by step, such as from 100 kHz to 50 kHz, 25 kHz, etc. to reduce the energy transmitted in each cycle, thereby limiting the average current. The specific manifestation of frequency-folded current limiting protection lies in the decrease in switching frequency and the reduction in energy transmission. Although the frequency folding causes the single-cycle time to become longer, the overall protection action time t still satisfies the inverse-time characteristic, that is, t∝1 / I 2 , where I is; the reasons are as follows: Assume that the frequency folding times n and the current satisfy: The total action time t is the sum of the times of each cycle: + If the frequency decreases exponentially by 2, that is, ƒ k =ƒ0 / 2 k-1 , then: When n∝I 2 the total time t∝2 n / ƒ0. By adjusting ƒ0 and the trigger logic, t∝1 / I 2 can be achieved. When the current limiting is triggered once, 2 0 pulses are skipped. When the current limiting is triggered again, 2 1 pulses are skipped. By analogy, when the current limiting is triggered n times, 2 n pulses will be skipped.

[0046] Please refer to the attached Figure 5 attachment Figure 5 is the simulation waveform diagram of the frequency-folded output current-limiting protection circuit at the critical frequency. FromFigure 5 It can be known that the external drive voltage BST and the oscillation voltage SW have a frequency of 538 kHz when the current limiting is not triggered. After the current limiting is triggered once, the frequency is folded once and reduced to 268 kHz. However, at the limit frequency, the frequency cannot be continuously folded by an exponential multiple of 2. When the frequency of the oscillation voltage SW is set to a critical high point, the output voltage is short-circuited and the current limiting protection is triggered. The switching frequency can only be folded once. If the switching frequency is too high, the current limiting protection circuit cannot effectively limit the current, that is, the response speed of the protection circuit cannot match the extremely short switching period, which will cause the current to exceed the preset safety value.

[0047] Assume that the output voltage is short-circuited, then VOUT = 0 and the current is limited to I LIM and IOUT = I LIM , D / F SW =T ON_MIN , (1 - D) / F SW 1 / F SW , where T ON_MIN is the minimum turn-on time of the power transistor N11; at this time, the duty cycle D becomes very small and approaches the corresponding duty cycle of T ON_MIN . Therefore, according to the above formula, the maximum switching frequency to ensure current limiting is: As mentioned above, the above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A frequency folding output current limiting protection circuit, characterized in that: It includes a start-up module, a comparison module, a logic trigger module, a switch time control module, an output module and a current comparator; The external driving voltage BST and the oscillation voltage SW are both input to the startup module and the comparison module; The voltage regulator oscillation frequency signal current ramp is input to the non-inverting input terminal of the current comparator, and the output feedback signal is input to the external error amplifier. The output terminal of the external error amplifier outputs the feedback signal feedback to the inverting input terminal of the current comparator. The output terminal of the current comparator and the output terminal of the startup module are electrically connected to the comparison module. The logic trigger module includes x continuous triggers, the output end and the input end of the continuous trigger are electrically connected in sequence, the output end of the comparison module is electrically connected to the input end of the first continuous trigger, the first output end of the continuous trigger at the end is electrically connected to the output module, and outputs a logic feedback signal to the comparison module, the second output end of the continuous trigger at the end is electrically connected to the switch time control module, and the control end of the switch time control module is electrically connected to the comparison module, The external power source VIN is input to the output module, and the output module outputs the oscillation voltage SW.

2. The frequency folding output current limiting protection circuit according to claim 1, characterized in that: The startup module includes MOS transistor P0, MOS transistor P1, MOS transistor P2, MOS transistor P3, MOS transistor P4, MOS transistor P5, MOS transistor P6 and resistor R0; The external driving voltage BST is input to the source of the MOS transistor P0, the source of the MOS transistor P1, the source of the MOS transistor P2, the source of the MOS transistor P3, the source of the MOS transistor P4, the source of the MOS transistor P5 and the source of the MOS transistor P6; The gate and drain of the MOS transistor P0 are electrically connected to the gates of the MOS transistors P1, P2, P3, P4, P5, P6 and one end of the resistor R0, and the other end of the resistor R0 is electrically connected to the oscillation voltage SW; The drain of the MOS transistor P1, the drain of the MOS transistor P2, the substrate, the drain of the MOS transistor P3, the drain of the MOS transistor P4, the drain of the MOS transistor P5 and the drain of the MOS transistor P6, and the substrate are all electrically connected to the comparison module.

3. The frequency folding output current limiting protection circuit according to claim 2, characterized in that: The comparison module includes MOS transistor P7, MOS transistor P8, MOS transistor P9, MOS transistor P10, MOS transistor P11, MOS transistor P12, MOS transistor N0, MOS transistor N1, MOS transistor N2, MOS transistor N3, MOS transistor N4, MOS transistor N5, MOS transistor N6, MOS transistor N7, MOS transistor N8, MOS transistor N9, MOS transistor N10 and resistors R1 and R2; The drain of the MOS transistor P1 is electrically connected to the gate of the MOS transistor P7 and the drain of the MOS transistor N0; The drain of the MOS transistor P2 is electrically connected to the source of the MOS transistor P9 and the source of the MOS transistor P10, and the substrate of the MOS transistor P2 is electrically connected to the substrate of the MOS transistor P7, the substrate of the MOS transistor P8, the substrate of the MOS transistor P9 and the substrate of the MOS transistor P10; The drain of the MOS transistor P3 is electrically connected to the source of the MOS transistor P7 and the source of the MOS transistor P8, the drain of the MOS transistor P7 is electrically connected to the gate of the MOS transistor P9 and one end of the resistor R1, the drain of the MOS transistor P9 is electrically connected to the drain and gate of the MOS transistor N1 and the gate of the MOS transistor N2, the drain of the MOS transistor N2 is electrically connected to the drain of the MOS transistor P10, the source of the MOS transistor N3, the drain of the MOS transistor N4 and the gate of the MOS transistor N7; the drain of the MOS transistor P8 is electrically connected to the gate of the MOS transistor P10 and one end of the resistor R2, and the output end of the current comparator is electrically connected to the gate of the MOS transistor P8; The drain of the MOS transistor P4 is electrically connected to the drain of the MOS transistor N3; the drain of the MOS transistor P5 is electrically connected to the gate of the MOS transistor N3, the drain of the MOS transistor N5, the drain and gate of the MOS transistor N6, the drain of the MOS transistor P11 and the gate of the MOS transistor N9; the source of the MOS transistor N6 is electrically connected to the gate and drain of the MOS transistor N7, and the source of the MOS transistor N7 is electrically connected to the drain of the MOS transistor N8; The logic feedback signal is input to the gate of the MOS transistor N0, the gate of the MOS transistor P11 and the gate of the MOS transistor N8; the external driving voltage BST is input to the source of the MOS transistor P11; The drain of the MOS transistor P6 is electrically connected to the source of the MOS transistor P12, the substrate of the MOS transistor P6 is electrically connected to the substrate of the MOS transistor P12, the drain of the MOS transistor P12 is electrically connected to the drain of the MOS transistor N9 and the drain of the MOS transistor N10, and is electrically connected to the input of the first continuous trigger as an output terminal; The control end of the switch time control module is electrically connected to the gate of the MOS transistor N4, the gate of the MOS transistor P12 and the gate of the MOS transistor N10; The source of the MOS transistor N0, the source of the MOS transistor N1, the source of the MOS transistor N2, the substrate of the MOS transistor N3, the substrate and the source of the MOS transistor N4, the source of the MOS transistor N5, the substrate of the MOS transistor N6, the substrate of the MOS transistor N7, the source of the MOS transistor N8, the source of the MOS transistor N9, the source of the MOS transistor N10 and the other end of the resistor R1 and the other end of the resistor R2 are electrically connected to the oscillation voltage SW.

4. The frequency folding output current limiting protection circuit according to claim 1, characterized in that: The output module includes a power tube N11, The external power source VIN is electrically connected to the drain of the power tube N11 , the first output terminal of the continuous trigger at the end is electrically connected to the gate of the power tube N11 , and the source of the power tube N11 outputs the oscillation voltage SW.

5. The frequency folding output current limiting protection circuit according to claim 4, characterized in that: The output module also includes an inductor L1, a capacitor C1 and a diode D1. The source of the power tube N11 is electrically connected to one end of the inductor L1 and the cathode of the diode D1, and the other end of the inductor L1 is electrically connected to one end of the capacitor C1 and serves as an output end to output Vout; The other end of the capacitor C1 and the anode of the diode D1 are both grounded.

6. The frequency folding output current limiting protection circuit according to claim 1, characterized in that: The logic trigger module includes a counter, a frequency divider, a MOS tube P21, a MOS tube N21, a capacitor C21, a resistor R21, a NOT gate x201, a NOT gate x202, a NOT gate x203, a NOT gate x206, a NOT gate x211, a NOT gate x215, a NOR gate y204, a NOR gate y205, a NOR gate y207, a NOR gate y208, a NOR gate y212, a NOR gate y213, a NOR gate y214 and a NAND gate z216; The external driving voltage BST is input to the source of the MOS tube P21; The output end of the comparison module is electrically connected to the positive electrode of the NOT gate z201, the negative electrode of the NOT gate x201 is electrically connected to the positive electrode of the NOT gate z202, and the negative electrode of the NOT gate x202 is electrically connected to the gate of the MOS transistor P21 and the gate of the MOS transistor N21; the drain of the MOS transistor P21 is electrically connected to one end of the resistor R21, and the other end of the resistor R21 is electrically connected to the drain of the MOS transistor N21, one end of the capacitor C21 and the positive electrode of the NOT gate x203; the source of the MOS transistor N21 and the other end of the capacitor C21 are both electrically connected to the oscillation voltage SW; The negative pole of the NOT gate x203 is electrically connected to the first input terminal of the NOR gate y204 and the second input terminal of the NOR gate y207, the external control signal is electrically connected to the second input terminal of the NOR gate y205 and the first input terminal of the NOR gate y207, the output terminal of the NOR gate y205 is electrically connected to the second input terminal of the NOR gate y204, the output terminal of the NOR gate y204 is electrically connected to the first input terminal of the NOR gate y205 and the positive pole of the NOT gate x206, the negative pole of the NOT gate x206 is electrically connected to the first input terminal of the counter, the output terminal of the NOR gate y207 is electrically connected to the first input terminal of the NOR gate y208, the first output terminal of the switch time control module is electrically connected to the second input terminal of the NOR gate y208, and the output terminal of the NOR gate y208 is electrically connected to the second input terminal of the counter and the positive pole of the NOR gate x211; The negative pole of the NOT gate x211 is electrically connected to the first input terminal of the NOR gate y212, the output terminal of the counter is electrically connected to the input terminal of the frequency divider, the output terminal of the frequency divider is electrically connected to the second input terminal of the NOR gate y212, the second input terminal of the NOR gate y214 and the positive pole of the NOT gate x215; the output terminal of the NOR gate y212 is electrically connected to the first input terminal of the NOR gate y213, the output terminal of the NOR gate y213 is electrically connected to the first input terminal of the NOR gate y214 and the first input terminal of the NAND gate z216, the output terminal of the NOR gate y214 is electrically connected to the second input terminal of the NOR gate y213, the negative pole of the NOT gate x215 is electrically connected to the second input terminal of the NAND gate z216, and the output terminal of the NAND gate z216 is electrically connected to the switch time control module, the comparison module and the output module as the output terminal of the logic trigger module.

7. The frequency folding output current limiting protection circuit according to claim 1, characterized in that: The switch time control module includes a MOS tube P31, a MOS tube N31, a resistor R31, a capacitor C31, and a NOT gate x301; The external driving voltage BST is input to the source of the MOS tube P31; The output end of the logic trigger module is electrically connected to the gate of the MOS transistor P31 and the gate of the MOS transistor N31, the drain of the MOS transistor P31 is electrically connected to one end of the resistor R31, the other end of the resistor R31 is electrically connected to the drain of the MOS transistor N31, one end of the capacitor C31 and the positive electrode of the NOT gate x301, and the negative electrode of the NOT gate x301 is electrically connected to the comparison module and the logic trigger module as the output end; The source of the MOS transistor N31 and the other end of the capacitor C31 are both electrically connected to the oscillation voltage SW.

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