A mixed-mode modulation method for BOOST converters

Abstract

The present invention discloses a hybrid mode modulation method for a BOOST converter, belonging to the technical field of BOOST converter modulation circuits. The method is applied to a BOOST converter. When the hybrid mode modulation circuit begins operation and the output voltage reaches a stable 12V, the method determines whether the value of the output signal MODESEL is equal to 0 or 1, thereby entering PWM mode or Burst mode. The hybrid mode modulation method for a BOOST converter according to the present invention operates in PWM mode under heavy load and in burst mode under light load. The switching between the two modes is very smooth, and no hysteresis comparator for real-time detection of the VCOMP voltage is required. The heavy load and light load operating modes share a common loop. The switching between the light load and heavy load modes is determined by the level of the output signal MODESEL of the PWM / Burst mode select module. The output ripple is low under different output voltages, and the efficiency is high under light load.

Description

Technical Field

[0001] The present invention belongs to the technical field of BOOST converter modulation circuits, and in particular relates to a mixed-mode modulation method used in a BOOST converter. Background Art

[0002] In traditional burst mode, the error amplifier (EA) output, VCOMP, is monitored in real time and compared with the threshold voltage of a hysteresis comparator. When VCOMP exceeds the upper threshold of the hysteresis comparator, a sleep signal is issued, shutting down the power transistors, oscillator, inductor current sampling circuit, comparator, and other modules to reduce static power consumption and improve efficiency under light loads. However, this control mode is highly dependent on the performance of the hysteresis comparator, resulting in power consumption and high output ripple. Furthermore, when the output range of the boost converter is wide, the duty cycle variation range is also large. This, in turn, increases the range of both the slope compensation current and the sampled inductor current. This makes it difficult to set the appropriate upper and lower threshold voltages for the hysteresis comparator, requiring auxiliary circuit optimization.

[0003] This design discloses a new hybrid mode modulation method to optimize these problems. Summary of the Invention

[0004] The present invention aims to provide a hybrid-mode modulation method for a BOOST converter, which operates in PWM mode under heavy load and in burst mode under light load. The method allows smooth switching between the two modes, eliminating the need for a hysteresis comparator for real-time VCOMP voltage detection. The heavy-load and light-load operating modes share a common loop, and the transition between light-load and heavy-load modes is determined by the level of the output signal MODESEL of the PWM / Burstmode select module. The method provides low output ripple at different output voltages and high efficiency under light load, thereby resolving the problems raised in the aforementioned background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a hybrid-mode modulation method for a BOOST converter, applied to the BOOST converter. According to this method, when the hybrid-mode modulation circuit begins operation, after the output voltage reaches a stable 12V, the output signal MODESEL of the PWM / Burst mode select module will output a high-level logic 1, and the BOOST converter will enter Burst mode, indicating that the circuit is in light load. Conversely, when the output voltage falls below the stable voltage value of 12V, the output signal MODESEL of the PWM / Burst mode select module will output a low-level logic 0, and the BOOST converter will enter PWM mode, indicating that the circuit is in heavy load.

[0006] Preferably, the hybrid mode modulation circuit includes an input VIN, an inductor L, a diode Diode, a capacitor C, a load Rload, Rf1, Rf2, an output VOUT, a PWM / Burst mode select module, a comparator and an EA (error amplifier);

[0007] Among them, the input VIN is connected to one end of the inductor L, and the other end of the inductor L is connected to the switch SW; the switch SW is connected to the anode of the diode Diode and the drain of the transistor NLD12; the source of the transistor NLD12 is grounded; the cathode of the diode Diode is connected to the capacitor C, the load Rload and one end of the load Rf1; the cathode of the diode Diode is the output VOUT; the other end of the capacitor C and the load Rload is grounded; the other end of the load Rf1 is connected to the load Rf2 and the negative end of the EA, and the other end of the load Rf2 is grounded; the positive end of the EA is connected to the reference voltage VREF, the output end of the EA is VCOMP, and is connected to the negative end of the comparator; the positive end of the comparator is connected to VSUM;

[0008] When VSUM is in the active state of PWM mode and burst mode, VSUM = (idc + iramp + iL * K) * Ri. In the sleep state of burst mode, VSUM = idc * Ri. Here, K is the proportional coefficient of the sampled inductor current, Ri is the current-to-voltage resistor, idc is the DC current, iL is the sampled inductor current, and iramp is the ramp compensation current.

[0009] At the same time, the output end of the Comparator is PWM_COMP_Z, and PWM_COMP_Z serves as the input of the PWM / Burstmode select module; the IMIN end of the Comparator is also an input, the SLEEPE end is the indication signal output of the sleep mode, and the IMIN_VTH end is the threshold control signal of the current Comparator; when the IMIN_VTH end is high, the ith end is set to the high current threshold; the output end NCHON of the PWM / Burst mode select module is connected to the Driver drive circuit, and the output of the Driver drive circuit controls the opening and closing of the gate of the transistor NLD12.

[0010] Preferably, when the hybrid mode modulation circuit is in the PWM mode state, the rising edge of the clock signal CLKB arrives, the output terminal NCHON of the PWM / Burst mode select module is high, the gate of the transistor NLD12 is high, the sampling inductor current iL begins to gradually rise, VSUM=(idc+iramp+iL*K)*Ri, VSUM gradually rises; the IMIN_VTH terminal continues to be low, and the IMIN terminal of the comparator also jumps to high; when the peak value of VSUM touches VCOMP, the input PWM_COMP_Z of the PWM / Burst mode select module changes from low to high, and PWM also changes from low to high; at this time, the sampling inductor current iL gradually decreases, VSUM also gradually decreases, the input PWM_COMP_Z of the PWM / Burst mode select module changes from high to low, and PWM also changes from high to low; PWM / Burst mode The output terminal NCHON of the select module turns from high to low, the gate of the transistor NLD12 is low, the diode Diode starts to conduct, and the energy of the inductor L is transferred to the output VOUT, and the output VOUT rises; and the next cycle repeats.

[0011] Preferably, when the hybrid mode modulation circuit is in the sleep state of the Burst mode, the voltage of the output VOUT is provided by the capacitor C. When the output VOUT gradually decreases, VCOMP gradually increases. When it touches VSUM, the input PWM_COMP_Z of the PWM / Burst mode select module changes from high to low, and VSUM in the sleep state = idc*Ri; at this time, PWM also changes from high to low, the flag bit MODESEL changes from high to low, and the SLEEPE terminal changes from high to low, exiting the sleep state and entering the active state. At this time, VSUM = (idc+iramp+iL*K) *Ri;

[0012] When the next rising edge of the clock signal CLKB arrives, the output terminal NCHON of the PWM / Burst Mode Select module transitions from low to high. After remaining active for five cycles, the IMIN_VTH terminal transitions from high to low. During these five cycles, the threshold current of the current comparator is set to 1A. The sampled inductor current iL gradually increases, and the voltage of the switch SW gradually increases. When the sampled inductor current iL exceeds the threshold current of 1A, the output terminal IMIN of the current comparator transitions from low to high. After nine rising edges of the clock signal CLKB, the module enters the sleep state again. At this time, the sampled inductor current iL decreases, and VSUM = idc*Ri.

[0013] Preferably, the current comparator includes PMOS transistors P1-P3, NMOS transistors N1-N4, IMIN_VT, INV1, INV2 and IMIN;

[0014] Among them, the substrates of PMOS transistors P1 to P3 are all connected to the power supply VDD, and the substrates of NMOS transistors N1 to N4 are all grounded; MIN_VTH is connected to the input of INV1, INV1 is connected to the gate of NMOS transistor N1, the source of NMOS transistor N1 is connected to one end of resistor R1 and ground, and the drain of NMOS transistor N1 is connected to the other end of resistor R1 and the source of NMOS transistor N2; the gate and drain of NMOS transistor N2 are connected to the gate of NMOS transistor N3 and the drain of PMOS transistor P1; the sources of PMOS transistors P1 to P3 are connected to the power supply VDD, and the gates are connected to the bias voltage VBIAS; the drain of PMOS transistor P2 is connected to the drain of NMOS transistor N3 and the gate of NMOS transistor N4; the drain of PMOS transistor P3 is connected to the drain of NMOS transistor N4 and serves as the input of INV2, and the output of INV2 is IMIN; in Burst In the active phase of mode, IMIN_VTH is high, and the resistor R1 effectively generates an inductor current threshold point corresponding to 1A; the voltage of the switch SW is the voltage drop of the sampled inductor current iL on the transistor NLD12.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The hybrid mode modulation method for a BOOST converter according to the present invention operates in a PWM mode under heavy load and in a burst mode under light load. The switching between the two modes is very smooth and does not require a hysteresis comparator for real-time detection of the VCOMP voltage. The heavy load and light load operating modes share a common loop. The switching between the light load and heavy load modes is determined by the level of the output signal MODESEL of the PWM / Burst mode select module. The output ripple is low under different output voltages and the efficiency is high under light load. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is the logic diagram for switching the working mode of the BOOST converter.

[0018] Figure 2 This is the overall circuit diagram of the hybrid modulation used for the BOOST converter.

[0019] Figure 3 This is the PWM mode waveform.

[0020] Figure 4 This is the Burst mode waveform.

[0021] Figure 5 This is the PWM / Burst mode select module circuit.

[0022] Figure 6 This is the circuit diagram of the Current comparator.

[0023] Figure 7 This is the Logic_dff logic circuit diagram. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0025] In traditional burst mode, the error amplifier (EA) output, VCOMP, is monitored in real time and compared with the threshold voltage of a hysteresis comparator. When VCOMP exceeds the upper threshold of the hysteresis comparator, a sleep signal is issued, shutting down the power transistors, oscillator, inductor current sampling circuit, comparator, and other modules to reduce static power consumption and improve efficiency under light loads. However, this control mode is highly dependent on the performance of the hysteresis comparator, resulting in power consumption and high output ripple. Furthermore, when the output range of the boost converter is wide, the duty cycle variation range is also large. This, in turn, increases the range of both the slope compensation current and the sampled inductor current. This makes it difficult to set the appropriate upper and lower threshold voltages for the hysteresis comparator, requiring auxiliary circuit optimization.

[0026] To address the problems of the above-mentioned prior art, this embodiment provides a hybrid-mode modulation method for a BOOST converter. The method operates in PWM mode under heavy load and in burst mode under light load. The switching between the two modes is very smooth, and no hysteresis comparator for real-time detection of the VCOMP voltage is required. The heavy-load and light-load operating modes share a common loop. The transition between the light-load and heavy-load modes is determined by the level of the output signal MODESEL of the PWM / Burst mode select module. The output ripple is low at different output voltages, and the efficiency is high under light load.

[0027] like Figure 1 As shown, the circuit begins operating with soft start. When the output voltage reaches a stable 12V, the MODESEL output signal is equal to 1 to determine whether it enters PWM mode (pulse width modulation) or Burst mode. When MODESEL outputs a low-level logic 0, it indicates a heavy load and enters PWM mode. When MODESEL outputs a high-level logic 1, it indicates a light load and enters Burst mode.

[0028] Figure 2This is the overall circuit diagram of the hybrid modulation mode for the boost converter of the present invention. VIN is the input connected to inductor L. The other side of inductor L is connected to switch SW. Switch SW is connected to the anode of the diode and the drain of transistor NLD12 (12V LDMOS). The source of NLD12 is grounded. The cathode of the diode is connected to capacitor C, Rload, and Rf1, and this end is VOUT. The other ends of capacitor C and Rload are grounded. The other end of Rf1 is connected to Rf2 and the negative end of EA (error amplifier). The other end of Rf2 is grounded. The positive end of EA is connected to the VREF reference voltage. EA output is VCOMP, which is connected to the negative terminal of the comparator. The positive terminal of the comparator is connected to VSUM. In PWM mode and the active state of the burst, VSUM is (idc+iramp+iL*K) *Ri; in the sleep state of the burst, it is idc*Ri. Among them, K is the proportional coefficient of the sampled inductor current, Ri is the resistance of the current-to-voltage conversion, idc is the DC current, iL is the sampled inductor current, and iramp is the ramp compensation current.

[0029] The comparator output, PWM_COMP_Z, serves as an input to the PWM / Burst mode select module. IMIN is also an input. SLEEPE is the sleep mode indicator output. IMIN_VTH is the threshold control signal for the current comparator. When high, IMIN sets the high current threshold (1A in this design). The PWM / Burst select output, NCHON, is connected to the driver circuit. The driver output controls the gate opening and closing of NLD12.

[0030] Figure 3 The following figure shows the PWM mode waveform. When the clock signal CLKB rises, NCHON goes high, the gate of NLD12 goes high, and the inductor current begins to gradually increase. VSUM = (idc + iramp + iL * K) * Ri, and VSUM gradually rises. IMIN_VTH remains low in this mode, and IMIN also jumps high. When the peak of VSUM reaches VCOMP, PWM_COMP_Z transitions from low to high, and PWM also transitions from low to high. At this point, the inductor current gradually decreases, VSUM also gradually decreases, PWM_COMP_Z transitions from high to low, and PWM also transitions from high to low. NCHON transitions from high to low, the gate of NLD12 goes low, and the diode begins to conduct. Energy from the inductor is transferred to the output VOUT, causing VOUT to rise. This cycle repeats.

[0031] Figure 4This is a burst mode waveform. In the sleep state, the VOUT voltage is provided by the output capacitor. As VOUT gradually decreases, VCOMP gradually increases. When it reaches VSUM, PWM_COMP_Z transitions from high to low. Note that in the sleep state, VSUM = idc * Ri. At this time, PWM also transitions from high to low, MODESEL transitions from high to low, and SLEEPE transitions from high to low, exiting the sleep state and entering the active state. At this point, VSUM = (idc + iramp + iL * K) * Ri. When the next CLKB rising edge arrives, NCHON transitions from low to high. IMIN_VTH remains active for five cycles before transitioning from high to low. During these five cycles, the threshold current of the current comparator module is set to 1A (the threshold current can be set according to the application). At this time, the sampled inductor current iL gradually increases, and the switch SW voltage gradually increases. When the sampled inductor current iL exceeds the 1A threshold, the current comparator output IMIN transitions from low to high. After 9 CLKB cycles, the system enters the sleep state again. At this time, the sampled inductor current iL decreases, and VSUM = idc*Ri.

[0032] Figure 5 This is the circuit diagram of the PWM / Burst mode select module. The circuit is divided into five functional modules:

[0033] Figure 5 In (a), PWM_COMP_Z is connected to inverter INV1, the output of INV1 is connected to the input of NOR gate NOR3, IMIN is connected to inverter INV2, INV2 is connected to the input of NOR gate NOR1, and NCHON is connected to the blank time (leading edge cancellation circuit) and the input of INV4. Blank time is connected to the input of INV3, the output of INV3 is connected to the input of NOR1, and the outputs of NOR1 and INV4 are connected to the inputs of NOR2. The output of NOR2 is connected to the input of NOR3. The output of NOR3 is PWM. The PWM output is controlled by PWM_COMP_Z, IMIN, and NCHON.

[0034] In Figure 5 (b), the CLK clock is connected to the input of inverter INV1, and the output of INV1 is connected to the input of INV2. The output of INV2 is connected to the CLK terminal of DFF1 to DFF8. The PWM is connected to the D terminal of DFF1. The Q output of DFF1 is Q1, which is connected to the D terminal of DFF2. This continues until Q8.

[0035] Figure 5(c) PWM, Q1 and Q2 are connected to the inputs of AND gate 1, Q3 through Q5, and Q6 through Q8 are connected to the inputs of AND gates AND2 and AND3, respectively. The outputs of AND gates AND1 through AND3 are connected to the input of AND gate 4. The output of AND gate 3 is IMIN_VTH, and the output of AND gate 4 is MODESEL. Figure 5 (b) and Figure 5 (c) shows a fully functional circuit. During PWM operation, when all Q1-Q8 are 1, MODESEL outputs a high-level logic 1. If any one is 0, MODESEL outputs a low-level logic 0. When the first 0 appears in PWM, MODESEL is a low-level logic 0, and the circuit enters the active state from the sleep state. IMIN_VTH remains high for five clock cycles, and the threshold current of the current comparator module is set to 1A.

[0036] Figure 5 (d) CLKB and SLEEP are connected to the inputs of NOR gate NOR1. The output of NOR1 is connected to the input of NOR3. SLEEPE and PWM are connected to the inputs of NOR gate NOR2. The output of NOR2 is connected to the input of INV1. The output of INV1 is connected to the input of NOR4. The output of NOR3 is connected to the input of NOR4. The output of NOR4 is connected to the input of NOR3 and is NCHON. NCHON is controlled by CLKB, PWM, and SLEEP.

[0037] Figure 5 The (e) CLK clock signal is connected to INV1, generating the output CLKB. CKB is connected to the CLK terminal of logic_diff, and MODESEL is connected to D, resulting in the output SLEEPE. When the output signal MODESEL is a low-level logic 0, SLEEPE is set to 0; when the output signal MODESEL is a high-level logic 1, SLEEPE is set to 1 when the next clock CLK arrives.

[0038] Figure 6The following is the circuit diagram of the current comparator. In the figure, P1-P3 are PMOS transistors, all connected to the power supply VDD. N1-N4 are NMOS transistors, all connected to the ground. IMIN_VTH is connected to the input of INV1, which is connected to the gate of N1. The source of N1 is connected to one end of R1 and ground, and the drain is connected to the other end of R1, the source of N2, the gate and drain of N2, the gate of N3, and the drain of P1. The sources of P1-P3 are connected to the power supply VDD, and the gates are connected to the bias voltage VBIAS. The drain of P2 is connected to the drain of N3 and the gate of N4. The drain of P3 is connected to the drain of N4 and serves as the input of INV2, whose output is IMIN. During the active phase of the burst mode, IMIN_VTH is high, and R1 effectively generates an inductor current threshold corresponding to 1A. The voltage on switch SW is the voltage drop across NLD12 caused by the inductor current.

[0039] Figure 7 It is a Logic_dff logic circuit. The circuit can be implemented in different structures. The present invention provides an implementation circuit.

[0040] P1~P10 are PMOS tubes, and the substrates of PMOS tubes P1~P10 are all connected to the power supply VDD. N1~N10 are NMOS tubes, and the substrates of NMOS tubes N1~N10 are all grounded; CLK is connected to INV1 to generate CN, and CN is connected to INV2 to generate CP; CN is connected to the gates of N2, P5, N10, and P10, and CP is connected to the gates of P2, N6, and P7; D is connected to the gates of P1, N1, P3, N3, N9, and N9; the source of N1 is grounded, the drain is connected to the source of N2, the source of N2 is connected to the gate of P2, INV3 input, P5 drain, and N5 source; the source of P2 is connected to the drain of P1. The drain of P3 is connected to the drain of P4, and the source of P5 is connected; the source of N5 is connected to the drain of N4, and the source of N4 is connected to the drain of N3; the source of N3 is grounded; the gate of P4 is connected to the gate of N4, the output of INV1, the source of N6, and the source of P10; the drains of P10 and N6 are connected to the gates of P8 and N8, the drain of P7, and the drain of N10; the drain of P6 is connected to the gate of P7, the source of N10 is connected to the drain of N9, and the source of N9 is grounded. The gates of P6 and N9 are connected to the drains of P8, P9, and N8, the input stage of INV4; the source of N8 is connected to the drain of N7; the source of N7 is grounded; the output of INV4 is Q.

[0041] The hybrid-mode modulation method for a BOOST converter operates in PWM mode under heavy load and in burst mode under light load. The switching between the two modes is very smooth, eliminating the need for a hysteresis comparator to monitor the VCOMP voltage in real time. The heavy-load and light-load operating modes share a common loop, and the transition between light-load and heavy-load modes is determined by the level of the PWM / Burst mode select module's output signal, MODESEL. This method achieves low output ripple at various output voltages and high efficiency under light load. This hybrid-mode modulation method has been demonstrated in a 3.3V to 5-12V BOOST converter with a 400mA load.

[0042] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0043] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A mixed-mode modulation method for a BOOST converter, applied to a BOOST converter, characterized in that: In this method, when the hybrid mode modulation circuit starts working, when the output voltage reaches a stable 12V, the output signal MODESEL of the PWM / Burst mode select module will output a high-level logic 1, and the BOOST converter will enter the burst mode, indicating that the circuit is in light load. Conversely, when the output voltage is lower than the stable voltage value of 12V, the output signal MODESEL of the PWM / Burst mode select module will output a low-level logic 0, and the BOOST converter will enter the PWM mode, indicating that the circuit is in heavy load. The hybrid mode modulation circuit includes an input VIN, an inductor L, a diode Diode, a capacitor C, a load Rload, Rf1, Rf2, an output VOUT, a PWM / Burst mode select module, a comparator and an EA; Among them, the input VIN is connected to one end of the inductor L, and the other end of the inductor L is connected to the switch SW; the switch SW is connected to the anode of the diode Diode and the drain of the transistor NLD12; the source of the transistor NLD12 is grounded; the cathode of the diode Diode is connected to the capacitor C, the load Rload and one end of the load Rf1; the cathode of the diode Diode is the output VOUT; the other end of the capacitor C and the load Rload is grounded; the other end of the load Rf1 is connected to the load Rf2 and the negative end of the EA, and the other end of the load Rf2 is grounded; the positive end of the EA is connected to the reference voltage VREF, the output end of the EA is VCOMP, and is connected to the negative end of the comparator; the positive end of the comparator is connected to VSUM; When VSUM is in the active state of PWM mode and burst mode, VSUM = (idc + iramp + iL * K) * Ri. In the sleep state of burst mode, VSUM = idc * Ri. Here, K is the proportional coefficient of the sampled inductor current, Ri is the current-to-voltage resistor, idc is the DC current, iL is the sampled inductor current, and iramp is the ramp compensation current. At the same time, the output of the comparator is PWM_COMP_Z, and PWM_COMP_Z serves as the input of the PWM / Burstmode select module. The IMIN terminal of the comparator is also an input, the SLEEPE terminal is the sleep mode indication signal output, and the IMIN_VTH terminal is the threshold control signal of the current comparator. When the IMIN_VTH terminal is high, the ith terminal is set to the high current threshold. The output terminal NCHON of the PWM / Burst mode select module is connected to the Driver drive circuit. The output of the Driver drive circuit controls the opening and closing of the gate of transistor NLD12. When the hybrid-mode modulation circuit is in PWM mode, the rising edge of the clock signal CLKB arrives, the output terminal NCHON of the PWM / Burstmode select module goes high, the gate of transistor NLD12 goes high, and the sampled inductor current iL begins to gradually increase. VSUM = (idc + iramp + iL * K) * Ri, VSUM gradually increases. The IMIN_VTH terminal remains low, and the IMIN terminal of the comparator also jumps high. When the peak of VSUM reaches VCOMP, the input PWM_COMP_Z of the PWM / Burstmode select module transitions from low to high, and PWM also transitions from low to high. At this time, the sampled inductor current iL gradually decreases, VSUM also gradually decreases, the input PWM_COMP_Z of the PWM / Burstmode select module transitions from high to low, and PWM also transitions from high to low. The output terminal NCHON of the PWM / Burstmode select module transitions from high to low, the gate of transistor NLD12 goes low, and diode Diode begins to conduct. The energy in the inductor L is transferred to the output VOUT, causing the output VOUT to rise. This cycle repeats. When the hybrid-mode modulation circuit is in the sleep state of Burst mode, the output VOUT voltage is provided by capacitor C. When the output VOUT gradually decreases, VCOMP gradually increases. When it touches VSUM, the input PWM_COMP_Z of the PWM / Burst mode select module turns from high to low. VSUM in the sleep state = idc*Ri. At this time, PWM also turns from high to low, the flag bit MODESEL turns from high to low, and the SLEEPE terminal turns from high to low, exiting the sleep state and entering the active state. At this time, VSUM = (idc+iramp+iL*K)*Ri. When the next rising edge of the clock signal CLKB arrives, the output terminal NCHON of the PWM / Burst Mode Select module transitions from low to high. After remaining active for five cycles, the IMIN_VTH terminal transitions from high to low. During these five cycles, the threshold current of the current comparator is set to 1A. The sampled inductor current iL gradually increases, and the voltage across the switch SW gradually increases. When the sampled inductor current iL exceeds the threshold current of 1A, the output of the current comparator IMIN transitions from low to high. After nine rising edges of the clock signal CLKB, the module enters the sleep state again. At this time, the sampled inductor current iL decreases, and VSUM = idc*Ri.

2. The hybrid mode modulation method for BOOST converter according to claim 1, characterized in that: The current comparator includes PMOS tubes P1-P3, NMOS tubes N1-N4, IMIN_VT, INV1, INV2 and IMIN; Among them, the substrates of PMOS transistors P1 to P3 are all connected to the power supply VDD, and the substrates of NMOS transistors N1 to N4 are all grounded; MIN_VTH is connected to the input of INV1, INV1 is connected to the gate of NMOS transistor N1, the source of NMOS transistor N1 is connected to one end of resistor R1 and ground, and the drain of NMOS transistor N1 is connected to the other end of resistor R1 and the source of NMOS transistor N2; the gate and drain of NMOS transistor N2 are connected to the gate of NMOS transistor N3 and the drain of PMOS transistor P1; the sources of PMOS transistors P1 to P3 are connected to the power supply VDD, and the gates are connected to the bias voltage VBIAS; the drain of PMOS transistor P2 is connected to the drain of NMOS transistor N3 and the gate of NMOS transistor N4; the drain of PMOS transistor P3 is connected to the drain of NMOS transistor N4 and serves as the input of INV2, and the output of INV2 is IMIN; in the burst In the active phase of mode, IMIN_VTH is high, and the resistor R1 effectively generates an inductor current threshold point corresponding to 1A; the voltage of the switch SW is the voltage drop of the sampled inductor current iL on the transistor NLD12.

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