System and method for power switch control of an electric vehicle inverter

Abstract

The invention relates to a system and method for power switch control of an electric vehicle inverter. A system includes an inverter configured to convert DC power from a battery to AC power to drive a motor, where the inverter includes: a power switch including a gate terminal; and a gate driver configured to receive a pulse controlling an operation of the power switch, generate a first signal to the gate terminal based on the received pulse, the controller is configured to receive a pulse to increase a gate voltage level of the power switch from an off-state gate voltage level to a first on-state gate voltage level at a first rate within a first period of time, and to generate a second signal to the gate terminal based on the received pulse, the gate voltage level of the power switch is increased to a second on-state gate voltage level at a second rate less than the first rate for a second time period after the first time period.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to systems and methods for one or more controllers for power switches, and more particularly, to systems and methods for controlling gate drivers of power switches of inverters for electric vehicles. Background Art

[0002] For example, an inverter such as an inverter for driving a motor in an electric vehicle is responsible for converting high-voltage direct current (HVDC) into alternating current (AC) to drive the motor. In an inverter, switching losses of power device switches may result in low inverter efficiency.

[0003] The present disclosure aims to overcome the above one or more challenges. Summary of the Invention

[0004] In some aspects, the techniques described herein relate to a system including: an inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter includes: a power switch including a gate terminal; and a gate driver configured to: receive a pulse controlling an operation of the power switch, generate a first signal based on the received pulse to the gate terminal to increase a gate voltage level of the power switch from an off-state gate voltage level to a first on-state gate voltage level at a first rate within a first time period, and generate a second signal based on the received pulse to the gate terminal to increase the gate voltage level of the power switch to a second on-state gate voltage level at a second rate less than the first rate within a second time period after the first time period.

[0005] In some aspects, the techniques described herein relate to a system, wherein the first rate is configured to cause the power switch to transition from the off-state gate voltage level to the first on-state gate voltage level in less than 1 μs.

[0006] In some aspects, the techniques described herein relate to a system, wherein the second time period is after stabilization of a ringing phase at the gate terminal of the power switch, and the ringing phase is caused by the generated first signal.

[0007] In some aspects, the techniques described herein relate to a system, wherein the second rate is configured to cause the power switch to increase to the second on-state gate voltage level with reduced oscillation, the reduced oscillation being relative to the oscillation of the gate voltage level of the power switch within the first time period.

[0008] In some aspects, the techniques described herein relate to a system, wherein the gate driver is further configured to generate a third signal to the gate terminal based on the received pulse to reduce the gate voltage level of the power switch from the first on-state gate voltage level to a third on-state gate voltage level lower than the first on-state gate voltage level during a third time period after the first time period and before the second time period.

[0009] In some aspects, the techniques described herein relate to a system, wherein the second signal is configured to increase the gate voltage level of the power switch from the third on-state gate voltage level to the second on-state gate voltage level.

[0010] In some aspects, the techniques described herein relate to a system, wherein the third signal is configured to reduce the power switch to the third on-state gate voltage level to avoid an overshoot of the gate voltage level of the power switch that is higher than the maximum rated gate voltage level of the power switch.

[0011] In some aspects, the techniques described herein relate to a system, wherein the gate driver is further configured to generate a fourth signal to the gate terminal based on the received pulse to reduce the gate voltage level of the power switch from the second on-state gate voltage level to the off-state gate voltage level during a fourth time period after the second time period.

[0012] In some aspects, the techniques described herein relate to a system, the system further comprising: the battery configured to supply the DC power to the inverter; and the motor configured to receive the AC power for driving the motor from the inverter.

[0013] In some aspects, the techniques described herein relate to a system, the system further comprising: an electric vehicle including the battery, the inverter, and the motor.

[0014] In some aspects, the techniques described herein relate to a system including: a power switch driver configured to receive a pulse for controlling the operation of a power switch, generate a first signal to the power switch based on the received pulse to increase the gate voltage level of the power switch from an off-state gate voltage level to a first on-state gate voltage level at a first rate during a first time period, and generate a second signal to the power switch based on the received pulse to increase the gate voltage level of the power switch to a second on-state gate voltage level at a second rate less than the first rate during a second time period after the first time period.

[0015] In some aspects, the techniques described herein relate to a system, wherein: the first rate is at least 22 V / 1 μs, and the second rate is approximately 3 V / 8 μs.

[0016] In certain aspects, the techniques described herein relate to a system, wherein the power switch driver is an external waveform controller for a gate driver.

[0017] In some aspects, the techniques described herein relate to a system, wherein the power switch driver includes one or more power supplies to generate one or more of the first signal and the second signal.

[0018] In some aspects, the techniques described herein relate to a system, wherein the power switch driver includes one or more switches to generate one or more of the first signal and the second signal.

[0019] In certain aspects, the techniques described herein relate to a system, wherein the power switch driver includes one or more diodes to control the flow of current from an external power supply.

[0020] In some aspects, the techniques described herein relate to a system, wherein the power switch driver includes one or more resistors to control the first rate and the second rate.

[0021] In some aspects, the techniques described herein relate to a system that includes: a gate driver configured to receive a pulse that controls the operation of a power switch and generate a gate signal based on the pulse; and a waveform controller configured to: receive the gate signal from the gate driver, generate a first signal for the power switch based on the received gate signal to increase the gate voltage level of the power switch from an off-state gate voltage level to a first on-state gate voltage level at a first rate during a first time period, and generate a second signal for the power switch based on the received gate signal to increase the gate voltage level of the power switch to a second on-state gate voltage level at a second rate less than the first rate during a second time period after the first time period.

[0022] In certain aspects, the techniques described herein relate to a system, wherein the waveform controller includes one or more electrical hardware components that control a time delay between an initial rise of the gate voltage level of the power switch to the first on-state gate voltage level and a subsequent rise of the gate voltage level of the power switch to the second on-state gate voltage level.

[0023] In some aspects, the techniques described herein relate to a system, wherein the waveform controller includes one or more electrical hardware components that control the second rate.

[0024] In certain aspects, the techniques described herein relate to a method that includes the following operations performed by one or more controllers: receiving a pulse that controls the operation of a power switch, the power switch including a gate terminal; generating, based on the received pulse, a first signal to the gate terminal to increase the gate voltage level of the power switch from an off-state gate voltage level to a first on-state gate voltage level at a first rate during a first time period; and generating, based on the received pulse, a second signal to the gate terminal to increase the gate voltage level of the power switch to a second on-state gate voltage level at a second rate that is less than the first rate during a second time period after the first time period.

[0025] In some aspects, the techniques described herein relate to a method, wherein the first rate is configured to cause the power switch to transition from the off-state gate voltage level to the first on-state gate voltage level in less than 1 μs.

[0026] In some aspects, the techniques described herein relate to a method, wherein the second time period is after stabilization of a ringing phase at the gate terminal of the power switch, and the ringing phase is caused by the generated first signal.

[0027] In certain aspects, the techniques described herein relate to a method, wherein the second rate is configured to cause the power switch to increase to the second on-state gate voltage level with reduced oscillation, the reduced oscillation being relative to the oscillation of the gate voltage level of the power switch during the first time period.

[0028] In certain aspects, the techniques described herein relate to a method, wherein the operation further includes: generating, based on the received pulse, a third signal to the gate terminal to reduce the gate voltage level of the power switch from the first on-state gate voltage level to a third on-state gate voltage level that is lower than the first on-state gate voltage level during a third time period after the first time period and before the second time period.

[0029] In some aspects, the techniques described herein relate to a method, wherein the second signal is configured to increase the gate voltage level of the power switch from the third on-state gate voltage level to the second on-state gate voltage level.

[0030] In some aspects, the techniques described herein relate to a method in which the third signal is configured to reduce the power switch to the third on-state gate voltage level to avoid an overshoot of the gate voltage level of the power switch that is higher than the maximum rated gate voltage level of the power switch.

[0031] In some aspects, the techniques described herein relate to a method, and the operation further includes: generating a fourth signal based on the received pulse to the gate terminal to reduce the gate voltage level of the power switch from the second on-state gate voltage level to the off-state gate voltage level within a fourth time period after the second time period.

[0032] In some aspects, the techniques described herein relate to a method, and the method further includes: receiving DC power from a battery; converting the DC power to AC power using the operation of the power switch; and supplying the AC power to a motor.

[0033] In some aspects, the techniques described herein relate to a method, in which: the one or more controllers, the power switch, the battery, and the motor are provided as a system in an electric vehicle.

[0034] In some aspects, the techniques described herein relate to a method, and the method includes the following operations performed by one or more controllers: receiving a pulse for controlling the operation of a power switch; generating a first signal based on the received pulse to increase the gate voltage level of the power switch from the off-state gate voltage level to a first on-state gate voltage level at a first rate within a first time period; and generating a second signal based on the received pulse to increase the gate voltage level of the power switch to a second on-state gate voltage level at a second rate less than the first rate within a second time period after the first time period.

[0035] In some aspects, the techniques described herein relate to a method, in which the first rate is configured to cause the power switch to transition from the off-state gate voltage level to the first on-state gate voltage level in less than 1 μs, and the second rate is configured to cause the power switch to increase to the second on-state gate voltage level with reduced oscillation, where the reduced oscillation is with respect to the oscillation of the gate voltage level of the power switch within the first time period.

[0036] In some aspects, the techniques described herein relate to a method, in which the second time period is after a stable ringing phase of the power switch, and the ringing phase is caused by the generated first signal.

[0037] In some aspects, the techniques described herein relate to a method, wherein the operation further comprises: generating a third signal to the power switch based on the received pulse to reduce the gate voltage level of the power switch from the first on-state gate voltage level to a third on-state gate voltage level lower than the first on-state gate voltage level during a third time period after the first time period and before the second time period.

[0038] In some aspects, the techniques described herein relate to a method, wherein the second signal is configured to increase the gate voltage level of the power switch from the third on-state gate voltage level to the second on-state gate voltage level.

[0039] In some aspects, the techniques described herein relate to a method, wherein the third signal is configured to lower the power switch to the third on-state gate voltage level to avoid an overshoot of the gate voltage level of the power switch that is higher than the maximum rated gate voltage level of the power switch.

[0040] In some aspects, the techniques described herein relate to a method, wherein the operation further comprises: generating a fourth signal to the power switch based on the received pulse to reduce the gate voltage level of the power switch from the second on-state gate voltage level to the off-state gate voltage level during a fourth time period after the second time period.

[0041] In some aspects, the techniques described herein relate to a method that includes performing the following operations by one or more controllers: receiving a pulse that controls the operation of a power switch; generating a gate signal based on the pulse; generating a first signal to the power switch based on the received gate signal to increase the gate voltage level of the power switch from the off-state gate voltage level to a first on-state gate voltage level at a first rate during a first time period; and generating a second signal to the power switch based on the received gate signal to increase the gate voltage level of the power switch to a second on-state gate voltage level at a second rate less than the first rate during a second time period after the first time period.

[0042] In some aspects, the techniques described herein relate to a method, wherein: the first rate is configured to cause the power switch to transition from the off-state gate voltage level to the first on-state gate voltage level in less than 1 μs, and the second rate is configured to cause the power switch to increase to the second on-state gate voltage level with a reduced oscillation, the reduced oscillation being relative to the oscillation of the gate voltage level of the power switch during the first time period.

[0043] In some aspects, the techniques described herein relate to a method, wherein the operation further includes: generating a third signal for the power switch based on the received pulse to reduce the gate voltage level of the power switch from the first conduction state gate voltage level to a third conduction state gate voltage level lower than the first conduction state gate voltage level during a third time period after the first time period and before the second time period.

[0044] Other objects and advantages of the disclosed embodiments will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the disclosed embodiments. The objects and advantages of the disclosed embodiments will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.

[0045] It should be understood that the foregoing general description and the following detailed description are merely exemplary and explanatory and do not limit the disclosed embodiments claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various exemplary embodiments and together with the description serve to explain the principles of the disclosed embodiments.

[0047] Figure 1 An exemplary system infrastructure of a vehicle including a combined inverter and converter is depicted in accordance with one or more embodiments.

[0048] Figure 2 A power schematic of a three-phase inverter module in a connection system is depicted in accordance with one or more embodiments.

[0049] Figure 3 An implementation of a computer system capable of executing the techniques presented herein is depicted in accordance with one or more embodiments.

[0050] Figure 4 A power switch control system is depicted in accordance with one or more embodiments.

[0051] Figure 5 An output signal of a power switch control system is depicted in accordance with one or more embodiments.

[0052] Figure 6 An electrical schematic of power switch control in a system is depicted in accordance with one or more embodiments.

[0053] Figure 7 Selected signals of a power switch control system are depicted in accordance with one or more embodiments.

[0054] Figure 8Depicts an electrical schematic diagram of a power switch control system according to one or more embodiments.

[0055] Figure 9 Depicts selected signals of a power switch control system according to one or more embodiments. Detailed embodiments

[0056] The foregoing general description and the following detailed description are merely exemplary and explanatory and do not limit the claimed features. As used herein, the terms "comprising," "including," "having," or other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. In the present disclosure, unless otherwise specified, relative terms (such as "about," "substantially," and "approximately") are used to indicate that the stated value may vary by ±10%. In the present disclosure, unless otherwise specified, any numerical value may include a variation of ±10% of the stated value.

[0057] The terms used hereinafter may be interpreted in the broadest reasonable manner, even if it is used in conjunction with the detailed description of certain specific examples of the present disclosure. In fact, certain terms may even be emphasized hereinafter; however, any term intended to be interpreted in any restrictive manner will be clearly and specifically defined in this detailed description section. For example, in the context of the present disclosure, a switching device may be described as a switch or a device, but may refer to any device used to control the power flow in a circuit. For example, a switch may be a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), an insulated-gate bipolar transistor (IGBT), or a relay, or any combination thereof, but is not limited thereto.

[0058] Various embodiments of the present disclosure generally relate to systems and methods for one or more controllers for power switches, and more particularly, to systems and methods for controlling a gate driver of a power switch of an inverter of an electric vehicle.

[0059] An inverter, such as an inverter for driving a motor in an electric vehicle, is responsible for converting high-voltage direct current (HVDC) into alternating current (AC) to drive the motor. A three-phase inverter may include a bridge having six power device switches (e.g., power transistors, such as IGBTs or MOSFETs), which are controlled by pulse-width modulation (PWM) signals generated by a controller. The inverter may include three phase-switching groups (e.g., six power switches) to control the phase voltage, upper and lower gate drivers to control the switches, and a PWM controller to control the gate drivers. The PWM controller may generate signals to define the expected state of the system. The gate drivers may send amplified signals from the PWM controller to the phase switches. The phase switches may drive the phase voltage.

[0060] In a traction inverter, the power module may be an important part of the entire system, and the efficiency of the system may be proportional to the losses occurring in the power module. Addressing the switching losses and conduction losses of the power module may be necessary for an efficient, economical, and robust inverter design. One or more embodiments may reduce the switching losses and conduction losses.

[0061] In some solutions, the gate of the MOSFET is turned on by a fixed gate voltage. Therefore, the gate pull current is only limited by the gate resistance. The fixed gate voltage does not allow the on-state resistance of the MOSFET to be reduced. Some solutions address this limitation by using a current-controlled gate driver to control the gate pull current of the MOSFET. Some solutions use the gate voltage margin to reach the maximum limit (Vgs max) based on the oscillation and dynamic behavior. Some solutions use a variable gate resistor to change the gate pull current.

[0062] The power switch can be controlled by the gate-source voltage (Vgs). For example, a negative Vgs can turn the power switch into an off or open state, while a positive Vgs can turn the power switch into an on or closed state. The positive Vgs or on Vgs is limited to a value lower than the maximum positive Vgs of the power switch to keep the dynamic voltage within the safety margin of the power switch, thus avoiding failures of the power switch. Similarly, the negative Vgs or off Vgs is limited to a value higher than the maximum negative Vgs of the power switch. For example, a power switch with a maximum rating of -8V to 19V may have an off Vgs of -4V and an on Vgs of 15V.

[0063] The switching losses in the power switch depend on the switching speed of the power switch, such as the losses in the turn-on transition of the power switch. Turning on the power switch faster will reduce this turn-on loss.

[0064] One or more embodiments may include a system that turns on a power switch using an initial Vgs having a first value, reduces the Vgs from the first value to a second value during a ringing phase, and increases the Vgs from the second value to a third value after the ringing phase. For example, for a power switch having a maximum range from -8V to 19V, the first value of Vgs may be 18V, the second value may be 15V, and the third value may be 18V. The initial Vgs can rapidly transition the power switch from an off state to an on state at a first rate, which, if unmitigated, may introduce excessive oscillation or ringing in the power switch. For example, if the initial Vgs of 18V is maintained during the ringing phase, the power switch may exceed the maximum current rating of the switch, which may damage the power switch.

[0065] Accordingly, one or more embodiments may reduce the initial Vgs (e.g., 18V) to a second value (e.g., 15V) during the ringing phase of the power switch after initial turn-on. Reducing the initial Vgs to the second value can avoid exceeding the rated gate voltage of the power switch during the ringing phase. The voltage level at the gate driver output may be higher than the MOSFET gate voltage capability. Thus, the gate voltage may be reduced due to static gate voltage limitations to avoid exceeding the limit during ringing. However, the reduced Vgs also increases the on-state resistance of the power switch, which may increase the junction temperature of the power switch and / or increase the conduction losses of the power switch.

[0066] Accordingly, one or more embodiments may slowly increase the Vgs to a third value (e.g., 18V) that is higher than the second value (e.g., 15V) at a second rate that is less than the first rate. Slowly increasing to the third value can limit the dynamics of the entire inverter / converter system. The increased Vgs can reduce the on-state resistance of the power switch, thereby reducing (or avoiding an increase in) the junction temperature of the power switch and / or reducing the conduction losses of the power switch.

[0067] The first value may be less than, equal to, or greater than the maximum Vgs of the power switch. The second value may be less than the first value. The third value may be greater than the second value and may be less than, equal to, or greater than the first value.

[0068] One or more embodiments may utilize a first high Vgs to reduce the switching losses of a power switch. One or more embodiments may utilize a second lower Vgs to avoid exceeding the rated gate voltage during the ringing phase of the power switch. The voltage level at the gate driver output may be higher than the MOSFET gate voltage capability. Thus, the gate voltage may be reduced due to the static gate voltage limit to avoid exceeding the limit during ringing. One or more embodiments may utilize a third high Vgs to reduce the conduction losses of the power switch. One or more embodiments may utilize a ramp Vgs to limit the dynamics during the transition from the second lower Vgs to the third high Vgs, such as additional ringing of the power switch.

[0069] During the initial turn-on phase, one or more embodiments may apply a high gate voltage. The gate voltage may then be reduced to avoid exceeding the rated gate voltage. The voltage level at the gate driver output may be higher than the MOSFET gate voltage capability. Thus, the gate voltage may be reduced due to the static gate voltage limit to avoid exceeding the limit during ringing. After the ringing phase caused by the high gate voltage in the initial turn-on phase, one or more embodiments may increase the gate voltage to reduce the on-state resistance (Rds-on) of the power switch. One or more embodiments may increase the gate voltage slowly to avoid further ringing in the circuit. Due to the increase in the gate voltage, the conduction losses in the power switch will be reduced. This reduced conduction loss may lower the junction temperature of the power switch and thus may reduce the thermal requirements of the substrate. One or more embodiments may provide a gate signal pattern that increases the gate voltage after ringing (after the initial turn-on of the power switch). For example, one or more embodiments may provide a power level signal pattern for one or more SiMOSFETs, SiC MOSFETs, IGBTs, or GaN devices. The power level may refer to the output signal from the gate driver. For example, the power level may be the gate voltage level.

[0070] One or more embodiments may apply a higher gate voltage to charge the gate faster. One or more embodiments may reduce the gate voltage to avoid exceeding the rated gate voltage. The voltage level at the gate driver output may be higher than the MOSFET gate voltage capability. Thus, the gate voltage may be reduced due to the static gate voltage limit to avoid exceeding the limit during ringing. One or more embodiments may increase the gate voltage to a higher voltage to reduce the on-state resistance when the ringing subsides.

[0071] One or more embodiments can provide a power switch with fast turn-on without increasing ringing. One or more embodiments can provide reduced on-state resistance, reduced conduction loss, and reduced junction temperature. Due to the reduced junction temperature, one or more embodiments can provide a reduced substrate size as well as a reduction in the cost and overall size of the power module.

[0072] Figure 1 An exemplary system infrastructure of a vehicle including a combined inverter and converter according to one or more embodiments is depicted. In the context of the present disclosure, the combined inverter and converter may be referred to as an inverter. As Figure 1 shown, an electric vehicle 100 may include an inverter 110, a motor 190, and a battery 195. The inverter 110 may include components for receiving power from an external source and outputting power to charge the battery 195 of the electric vehicle 100. For example, the inverter 110 may convert DC power from the battery 195 in the electric vehicle 100 into AC power to drive the motor 190 of the electric vehicle 100, but the embodiments are not limited thereto. The inverter 110 may be bidirectional and may convert DC power into AC power or convert AC power into DC power, for example, during regenerative braking. The inverter 110 may be a three-phase inverter, a single-phase inverter, or a multi-phase inverter.

[0073] Figure 2 A power schematic of a three-phase inverter module according to one or more embodiments is depicted. As Figure 1 and Figure 2 shown, the inverter 110 may be connected to the battery or power supply 195 and the motor or load 190. The inverter 110 may include a first three-phase switch group 210 and a second three-phase switch group 220. The first phase U may be associated with ΦA including switches Q1 and Q4, the second phase V may be associated with ΦB including switches Q3 and Q6, and the third phase W may be associated with ΦC including switches Q5 and Q2, as Figure 2 shown. The first three-phase switch group 210 may include a first-phase switch Q1, a second-phase switch Q3, and a third-phase switch Q5. For example, the second three-phase switch group 220 may include a first-phase switch Q4, a second-phase switch Q6, and a third-phase switch Q2. The switches Q1 to Q6 may be metal-oxide-semiconductor field-effect transistors (MOSFETs), but are not limited thereto.

[0074] The first three-phase switch group 210 and the second three-phase switch group 220 may be controlled by PWM signals generated by the inverter controller 300 (e.g., as Figure 5 、 Figure 7 and Figure 9driven as shown to convert DC power delivered via the input terminal set 285 at the capacitor 230 into three-phase AC power output to the motor 190 at the output terminals U, V, and W via the output terminal set 295. Additionally, although Figure 1 and Figure 2 illustrate a three-phase inverter, the present disclosure is not limited thereto and may include single-phase or multi-phase inverters.

[0075] Figure 3 depicts an exemplary system infrastructure of an Figure 2 inverter controller 300 according to one or more embodiments. The inverter controller 300 may include one or more controllers.

[0076] The inverter controller 300 may include a set of instructions that may be executed to cause the inverter controller 300 to perform any one or more of the methods or computer-based functions disclosed herein. The inverter controller 300 may operate as a stand-alone device or may be connected to other computer systems or peripheral devices (e.g., using a network).

[0077] In a networked deployment, the inverter controller 300 may operate as a server, or as a client in a server-client user network environment, or as a peer computer system in a peer-to-peer (or distributed) network environment. The inverter controller 300 may also be implemented as or incorporated into various devices, such as an inverter 110 in an electric vehicle 100, a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile device, a palm computer, a laptop computer, a desktop computer, a communication device, a wireless phone, a landline phone, a control system, a camera, a scanner, a fax machine, a printer, a pager, a personal trust device, a network device, a network router, a switch, or a bridge, or any other machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. In a particular implementation, the inverter controller 300 may be implemented using an electronic device that provides voice, video, or data communication. Additionally, although the inverter controller 300 is illustrated as a single system, the term "system" should also be understood to include any collection of systems or subsystems that individually or jointly execute a set of or multiple sets of instructions to implement one or more computer functions.

[0078] As Figure 3As shown, the inverter controller 300 may include a processor 302, such as a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor 302 may be a component in various systems. For example, the processor 302 may be part of a standard inverter. The processor 302 may be one or more general-purpose processors, digital signal processors, application-specific integrated circuits, field-programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other devices now known or later developed for analyzing and processing data. The processor 302 may implement software programs, such as manually generated (i.e., programmed) code.

[0079] The inverter controller 300 may include a memory 304, which may communicate via a bus 308. The memory 304 may be a main memory, a static memory, or a dynamic memory. The memory 304 may include, but is not limited to, computer-readable storage media, such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, magnetic tapes or disks, optical media, etc. In one implementation, the memory 304 includes a cache or random access memory for the processor 302. In an alternative implementation, the memory 304 is separate from the processor 302, such as a cache memory of the processor, a system memory, or other memories. The memory 304 may be an external storage device or a database for storing data. Examples include hard disks, compact discs ("CDs"), digital video discs ("DVDs"), memory cards, memory sticks, floppy disks, universal serial bus ("USB") memory devices, or any other device that operationally stores data. The memory 304 is operable to store instructions executable by the processor 302. The functions, actions, or tasks shown in the figure or described herein may be performed by the processor 302 executing instructions stored in the memory 304. The functions, actions, or tasks are independent of a particular type of instruction set, storage medium, processor, or processing strategy and may be performed by software, hardware, integrated circuits, firmware, microcode, etc., alone or in combination. Similarly, the processing strategy may include multiprocessing, multitasking, parallel processing, etc.

[0080] As shown in the figure, the inverter controller 300 may further include a display 310, such as a liquid crystal display (LCD), an organic light-emitting diode (OLED), a flat panel display, a solid-state display, a cathode ray tube (CRT), a projector, a printer, or other display devices now known or later developed for outputting determined information. The display 310 may act as an interface for a user to view the operation of the processor 302, or specifically as an interface to the software stored in the memory 304 or the drive unit 306.

[0081] Additionally or alternatively, the inverter controller 300 may include an input device 312 configured to allow a user to interact with any component of the inverter controller 300. The input device 312 may be a numeric keypad, a keyboard, or a cursor control device (such as a mouse, a joystick, a touch screen display, a remote control, or any other device that interacts operationally with the inverter controller 300).

[0082] The inverter controller 300 may also or alternatively include a drive unit 306 implemented as a disk or an optical disk drive. The drive unit 306 may include a computer-readable medium 322 in which one or more sets of instructions 324 (such as software) may be embedded. Additionally, the instructions 324 may embody one or more of the methods or logics described herein. During execution by the inverter controller 300, the instructions 324 may exist, in whole or in part, within the memory 304 and / or within the processor 302. The memory 304 and the processor 302 may also include computer-readable media as described above.

[0083] In some systems, the computer-readable medium 322 includes the instructions 324 or receives and executes the instructions 324 in response to a propagated signal such that a device connected to the network 370 can transmit voice, video, audio, images, or any other data over the network 370. Additionally, the instructions 324 may be sent or received via the communication port or interface 320 over the network 370 and / or sent or received using the bus 308. The communication port or interface 320 may be part of the processor 302 or a separate component. The communication port or interface 320 may be created in software or be a physical connection in hardware. The communication port or interface 320 may be configured to connect to the network 370, an external medium, the display 310, or any other component of the inverter controller 300 or a combination thereof. The connection to the network 370 may be a physical connection, such as a wired Ethernet connection, or may be established wirelessly, as described below. Similarly, additional connections to other components of the inverter controller 300 may be physical or established wirelessly. The network 370 may alternatively be directly connected to the bus 308.

[0084] Although the computer-readable medium 322 is shown as a single medium, the term "computer-readable medium" may include a single medium or multiple media, such as a centralized or distributed database, and / or an associated cache and server storing one or more sets of instructions. The term "computer-readable medium" may also include any medium that can store, encode, or carry a set of instructions for execution by a processor or that causes a computer system to perform any one or more of the methods or operations disclosed herein. The computer-readable medium 322 may be non-transitory and may be tangible.

[0085] The computer-readable medium 322 may include solid-state memory such as a memory card or other encapsulation that houses one or more non-volatile read-only memories. The computer-readable medium 322 may be random access memory or other volatile rewritable memory. Additionally or alternatively, the computer-readable medium 322 may include magneto-optical or optical media such as a disk or tape or other storage device to capture a carrier signal such as a signal transmitted through a transmission medium. Digital file attachments of e-mails or other self-contained information archives or sets of archives may be considered distribution media (i.e., tangible storage media). Accordingly, the present disclosure is considered to include any one or more of a computer-readable medium or distribution medium and other equivalents and subsequent media in which data or instructions may be stored.

[0086] In alternative implementations, dedicated hardware implementations such as application specific integrated circuits, programmable logic arrays, and other hardware devices may be constructed to implement one or more of the methods described herein. Applications of devices and systems that may include various implementations may broadly include a variety of electronic and computer systems. One or more of the implementations described herein may be implemented using two or more specific interconnected hardware modules or devices having associated control and data signals that may be transferred between and through the modules, or as part of an application specific integrated circuit. Accordingly, the present system encompasses software, firmware, and hardware implementations.

[0087] The inverter controller 300 may be connected to a network 370. The network 370 may define one or more networks, including wired or wireless networks. The wireless network may be a cellular telephone network, 802.11, 802.16, 802.20, or WiMAX network. Additionally, such networks may include a public network (e.g., the Internet), a private network (e.g., an intranet), or a combination thereof, and may utilize a variety of existing or later developed networking protocols, including but not limited to TCP / IP-based networking protocols. The network 370 may include a wide area network (WAN) such as the Internet, a local area network (LAN), a campus network, a metropolitan area network, a direct connection (e.g., through a universal serial bus (USB) port), or any other network that permits data communication. The network 370 may be configured to couple one computing device to another computing device such that data can be transferred between the devices. The network 370 can generally employ any form of machine-readable medium to transfer information from one device to another. The network 370 may include a communication method by which information travels between computing devices. The network 370 may be divided into sub-networks. The sub-networks may allow access to all other components connected thereto, or the sub-networks may restrict access between components. The network 370 may be considered a public or private network connection and may include, for example, a virtual private network or encryption or other security mechanisms employed over the public Internet.

[0088] In accordance with various implementations of the present disclosure, the methods described herein may be implemented by software programs executable by a computer system. Additionally, in exemplary, non-limiting implementations, the implementations may include distributed processing, component or object distributed processing, and parallel processing. Alternatively, a virtual computer system processing may be constructed to implement one or more of the methods or functions described herein.

[0089] Although this specification describes components and functions that may be implemented with reference to specific standards and protocols in a particular implementation, the present disclosure is not limited to such standards and protocols. For example, standards for Internet and other packet-switched network transmissions (e.g., TCP / IP, UDP / IP, HTML, HTTP) represent examples of the prior art. Such standards are periodically replaced by faster or more efficient equivalent standards having substantially the same functionality. Accordingly, alternative standards and protocols having the same or similar functionality as those disclosed herein are considered to be their equivalent standards and protocols.

[0090] It should be understood that in one implementation, the operations of the methods discussed are performed by a suitable processor (or processors) of a processing (i.e., computer) system that executes instructions (computer-readable code) stored in a storage unit. It should also be understood that the present disclosure is not limited to any particular implementation or programming technique, and the present disclosure may be implemented using any suitable technique for implementing the functions described herein. The present disclosure is not limited to any particular programming language or operating system.

[0091] Figure 4 A power switch control system according to one or more implementations is depicted. As Figure 4 shown, the gate driver system 400 may include a gate driver 450 and a power switch 420. The gate driver 450 may receive a pulse width modulation signal as the PWM signal 405 from an external source (e.g., the inverter controller 300). The gate driver 450 provides an output signal to the gate of the power switch 420 through a gate resistor 415 based on the PWM signal 405 (e.g., see Figure 5The output signal in (501). The gate driver 450 can convert the input voltage 410 into an output signal using one or more of the logic unit 455, the first switch 460, or the second switch 465. The logic unit 455 can be one or more of hardware-based logic or software-based logic. The logic unit 455 can receive the PWM signal 405 and control the operation of one or more of the first switch 460 or the second switch 465 to generate an output signal as one or more of the input voltage 410 or the converted voltage of the input voltage 410. The gate driver system 400 can include an external waveform controller for the gate driver or an internal waveform controller in the gate driver. The input voltage 410 can be any voltage limit according to the power switch rating and is not limited to 19V. The power switch limit voltage can be divided into two or more voltages and can be controlled later to set a specific conduction loss or RDSon of the MOSFET.

[0092] Figure 5 Depicts the output signal of a power switch control system according to one or more embodiments. As shown in the plot 500, the output signal 501 can be an output signal to the gate of a power switch, for example, an output signal generated to the gate of the power switch 420. The output signal 501 can be a signal at the gate of the power switch. For example, this signal can be different from the output signal from the gate driver to the gate. The output signal 501 can include a first off-state power level 505, a first on-state power level 510, a second on-state power level 515, and a turn-off signal 520 to a second off-state power level 525. The power level can refer to the output signal from the gate driver. For example, the power level can be the gate voltage level. The output signal 501 may include various signal artifacts, such as signal spikes in the first off-state power level 505. The output signal 501 can be periodic such that the second off-state power level 525 corresponds to the first off-state power level 505 with a time delay. For example, the output signal 501 can have a period of approximately 25 μs. For example, the output signal 501 can include a first off-state power level 505 of approximately -4V, a first on-state power level 510 of approximately 15V, a second on-state power level 515 of approximately 18V, and a turn-off signal 520 from a power level of approximately 18V to a second off-state power level 525 of approximately -4V.

[0093] As Figure 5As shown, the output signal 501 can increase from the first off-state power level 505 to the first on-state power level 510 at a first rate, thereby quickly transitioning from the first off-state power level 505 to the first on-state power level 510. The output signal 501 can increase from the first on-state power level 510 to the second on-state power level 515 at a second rate, thereby increasing to the second on-state power level 515 with a reduced oscillation relative to the oscillation of the power level of the power switch from the first off-state power level 505 to the first on-state power level 510.

[0094] Figure 6 Depicts an electrical schematic of power switch control in a system according to one or more embodiments. As Figure 6 shown, the system 600 can include a power supply 610, a high-side gate supply 621, a high-side gate connection 631, a high-side drain connection 641, a high-side source connection 643, a high-side power switch 651, a low-side gate supply 622, a low-side gate connection 632, a low-side source connection 642, a low-side power switch 652, and a load 660.

[0095] The high-side gate supply 621 can include a voltage source V0, a characteristic resistor R12, and a characteristic inductor L3. The high-side power switch 651 can include parallel switches V1, V2, V3, V4, V9, and V10. The low-side gate supply 622 can include a voltage source V4, a characteristic resistor R5, and a characteristic inductor L4. The low-side power switch 652 can include parallel switches V5, V6, V7, V8, V11, and V12.

[0096] Figure 7 Depicts a selected signal 700 of a power switch control system according to one or more embodiments. As shown in the plot 701, the load current (e.g., Figure 6 at L16 in) can follow a substantially square-wave pulse from approximately 0 A to approximately 600 A based on the corresponding conduction pulses from the power switch (e.g., power switch 420, high-side power switch 651, or low-side power switch 652). As shown in the plot 702, the power switch resistance (e.g., the on-state resistance Rds-on of the high-side power switch 651) can follow a substantially inverse square-wave pulse from approximately 1.35 Ω to approximately 0 Ω based on the corresponding conduction pulses from the power switch. As shown in the plot 703, the power switch gate-source voltage (e.g., the gate-source voltage of the high-side power switch 651) can substantially follow the output signal waveform.

[0097] As shown in the plot graph 703, one or more embodiments may increase the power level of a power switch from an off-state power level to a first on-state power level at a first rate during a first time period (from approximately 8.9 μs to approximately 9.1 μs). For example, the power switch may increase from an off-state power level of approximately -4V to a first on-state power level of approximately 18V in less than approximately 1 μs (i.e., at a rate of at least 22V / 1 μs).

[0098] One or more embodiments may increase the power level of the power switch to a second on-state power level at a second rate during a second time period from approximately 10 μs to approximately 18 μs. For example, the power switch may increase from approximately 15V to a second on-state power level of approximately 18V during the second time period from approximately 10 μs to approximately 18 μs (i.e., at a rate of 3V / 8 μs). As Figure 7 shown, the second time period is after the ringing phase of the power switch has stabilized, where the ringing phase is caused by increasing from the off-state power level to the first on-state power level at the first rate during the first time period.

[0099] One or more embodiments may decrease the power level of the power switch from the first on-state power level (e.g., approximately 18V) to a third on-state power level (e.g., approximately 15V) below the first on-state power level during a third time period (e.g., from approximately 9.1 μs to approximately 10 μs) after the first time period (e.g., from approximately 8.9 μs to approximately 9.1 μs) and before the second time period (e.g., from approximately 10 μs to approximately 18 μs).

[0100] Figure 8 Depicts an electrical schematic of a power switch control system according to one or more embodiments. The gate driver system 800 may include various electrical hardware components. The gate driver system 800 may include an R5 delay resistor 805, an R12 ramp resistor 812, an R14 delay resistor 814, a C1 delay capacitor 821, a V3 power supply 833, an R8 resistor 808, a V2 power supply 832, a U2 comparator 842, a V1 power supply 831, an R9 resistor 809, an R6 resistor 806, an R3 resistor 803, an R4 resistor 804, a Q1 switch 851, a Q2 switch 852, an R12 ramp resistor 812, an R15 resistor 815, a D2 diode 862, and an R7 resistor 807. The gate driver system 800 may be used as a waveform controller to adjust the PWM signal. The D2 diode 862 may control the flow of current from an external power supply to the gate driver system 800. The gate driver system 800 may be an external waveform controller for a gate driver or may be integrated into the gate driver.

[0101] The R5 delay resistor 805, the R14 delay resistor 814, and the C1 delay capacitor 821 can control the time delay between the initial rise of the conduction signal (e.g., the first conduction state power level 510) and the subsequent rise of the conduction signal (e.g., the second conduction state power level 515). For example, increasing the resistance value of the R5 delay resistor 805 can increase the time delay of the subsequent rise (e.g., the second conduction state power level 515). The resistance value of the R12 ramp resistor 812 can control the waveform shape of the subsequent ramp of the conduction signal (e.g., the second conduction state power level 515). For example, increasing the resistance value of the R12 ramp resistor 812 can flatten the waveform of the subsequent ramp of the conduction signal (e.g., the second conduction state power level 515).

[0102] Figure 9 A selected signal 900 of a power switch control system according to one or more embodiments is depicted. As shown in the plot 901, the gate-source voltage of the switch controls the drain-source voltage and the drain-source current such that when the switch is turned on, the drain-source voltage decreases and the drain-source current increases. As shown in the plots 902 and 903, the gate-source voltage may increase rapidly, which may result in a ringing phase. Subsequently, the gate-source voltage can be decreased to avoid exceeding the rated gate voltage during the ringing phase. The voltage level at the gate driver output may be higher than the MOSFET gate voltage capability. Therefore, due to the static gate voltage limit, the gate voltage can be decreased to avoid exceeding the limit during ringing. Subsequently, the gate-source voltage can be increased without generating excessive ringing.

[0103] One or more embodiments can utilize a first high Vgs to reduce the switching losses of the power switch. One or more embodiments can utilize a second lower Vgs to avoid exceeding the rated gate voltage during the ringing phase of the power switch. The voltage level at the gate driver output may be higher than the MOSFET gate voltage capability. Therefore, the gate voltage can be decreased due to the static gate voltage limit to avoid exceeding the limit during ringing. One or more embodiments can utilize a third high Vgs to reduce the conduction losses of the power switch. One or more embodiments can utilize a ramp Vgs to limit the dynamics, such as additional ringing of the power switch, during the transition from the second lower Vgs to the third high Vgs.

[0104] One or more embodiments can provide a power switch with fast turn-on without increasing ringing. One or more embodiments can provide a reduced on-state resistance, reduced conduction losses, and a reduced junction temperature. Due to the reduced junction temperature, one or more embodiments can provide a reduced substrate size as well as a reduction in the cost and overall size of the power module.

[0105] For those skilled in the art, other embodiments of the present disclosure will become apparent by considering the specification and practice of the invention disclosed herein. The specification and examples are only to be considered exemplary, and the true scope and spirit of the invention are indicated by the appended claims.

Claims

1. A system, comprising: An inverter configured to convert DC power from a battery into AC power to drive a motor, wherein the inverter comprises: a power switch comprising a gate terminal; and A gate driver, the gate driver being configured to: receiving a pulse to control the operation of the power switch, generating a first signal to the gate terminal based on the received pulse to increase a gate voltage level of the power switch from an off-state gate voltage level to a first on-state gate voltage level at a first rate over a first time period, and A second signal is generated to the gate terminal based on the received pulse to increase a gate voltage level of the power switch to a second on-state gate voltage level at a second rate less than the first rate within a second time period after the first time period.

2. The system according to claim 1, wherein: The first rate is configured to cause the power switch to transition from the off-state gate voltage level to the first on-state gate voltage level in less than 1 μs.

3. The system according to claim 1, wherein: The second time period is after stabilization of a ringing phase at the gate terminal of the power switch, wherein the ringing phase is caused by the generated first signal.

4. The system according to claim 1, wherein: The second rate is configured to cause the power switch to increase to the second on-state gate voltage level with reduced oscillation relative to oscillations of the gate voltage level of the power switch during the first time period.

5. The system according to claim 1, wherein: The gate driver is further configured to: A third signal is generated to the gate terminal based on the received pulse to reduce the gate voltage level of the power switch from the first on-state gate voltage level to a third on-state gate voltage level lower than the first on-state gate voltage level within a third time period after the first time period and before the second time period.

6. The system according to claim 5, wherein: The second signal is configured to increase a gate voltage level of the power switch from the third on-state gate voltage level to the second on-state gate voltage level.

7. The system according to claim 5, wherein: The third signal is configured to cause the power switch to decrease to the third on-state gate voltage level to avoid an overshoot of the gate voltage level of the power switch above a maximum rated gate voltage level of the power switch.

8. The system according to claim 1, wherein: The gate driver is further configured to: A fourth signal is generated to the gate terminal based on the received pulse to reduce a gate voltage level of the power switch from the second on-state gate voltage level to the off-state gate voltage level within a fourth time period after the second time period.

9. The system according to claim 1, further comprising: the battery, the battery being configured to supply the DC power to the inverter; as well as The motor is configured to receive the AC power for driving the motor from the inverter.

10. The system according to claim 9, further comprising: An electric vehicle includes the battery, the inverter, and the motor.

11. A system, comprising: A power switch driver, the power switch driver being configured to: receiving pulses for controlling the operation of the power switch, generating a first signal to the power switch based on the received pulse to increase a gate voltage level of the power switch from an off-state gate voltage level to a first on-state gate voltage level at a first rate over a first time period, and A second signal is generated to the power switch based on the received pulse to increase a gate voltage level of the power switch to a second on-state gate voltage level at a second rate less than the first rate within a second time period after the first time period.

12. The system of claim 11, wherein: The first rate is at least 22V / 1μs, and The second rate is approximately 3V / 8μs.

13. The system according to claim 11, wherein: The power switch driver is an external waveform controller for the gate driver.

14. The system according to claim 11, wherein: The power switch driver includes one or more power supplies to generate one or more of the first signal and the second signal.

15. The system according to claim 11, wherein: The power switch driver includes one or more switches to generate one or more of the first signal and the second signal.

16. The system according to claim 11, wherein: The power switch driver includes one or more diodes to control the flow of current from an external power source.

17. The system of claim 11, wherein: The power switch driver includes one or more resistors to control the first rate and the second rate.

18. A system, comprising: a gate driver configured to receive pulses that control operation of the power switch and to generate a gate signal based on the pulses; as well as A waveform controller, the waveform controller being configured to: receiving the gate signal from the gate driver, generating a first signal to the power switch based on the received gate signal to increase a gate voltage level of the power switch from an off-state gate voltage level to a first on-state gate voltage level at a first rate over a first time period, and A second signal is generated to the power switch based on the received gate signal to increase a gate voltage level of the power switch to a second on-state gate voltage level at a second rate less than the first rate within a second time period after the first time period.

19. The system of claim 18, wherein: The waveform controller includes one or more electrical hardware components, which control the time delay between an initial rise and a subsequent rise, wherein the gate voltage level of the power switch rises to the first on-state gate voltage level, and the subsequent rise is when the gate voltage level of the power switch rises to the second on-state gate voltage level.

20. The system of claim 18, wherein: The waveform controller includes one or more electrical hardware components that control the second rate.

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