Gain boosting type floating anti-phase dynamic amplifier circuit

Abstract

The invention discloses a gain boosting type floating anti-phase dynamic amplifier circuit, and relates to the technical field of integrated circuits, the gain boosting type floating anti-phase dynamic amplifier circuit comprises a power supply, a main amplifier, a first auxiliary amplifier and a second auxiliary amplifier, and the main amplifier and the auxiliary amplifiers both adopt a cascode floating anti-phase dynamic amplifier structure; the main amplifier comprises a first power supply capacitor, a second power supply capacitor, a plurality of first common-source transistors and a plurality of first common-gate transistors; a plurality of drain electrodes of the plurality of first common-source transistors are respectively connected with the input ends of the first auxiliary amplifier and the second auxiliary amplifier, and a plurality of grid electrodes of the first common-gate transistors are respectively connected with the output ends of the first auxiliary amplifier and the second auxiliary amplifier; the first auxiliary amplifier and the second auxiliary amplifier each comprise a plurality of second common-gate transistors, and a plurality of gates of the second common-gate transistors are directly connected to the common-mode level. According to the amplifier circuit, the gain of the amplifier is improved on the premise that the speed and the stability are guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a gain-boosting floating inverter dynamic amplifier circuit. Background Art

[0002] An analog-to-digital converter (ADC) is used to convert analog signals in the real world into digital signals and plays a very important role in modern electronic information systems. Most ADCs (such as pipelined ADCs and Delta-Sigma ADCs, etc.) rely on amplifiers to complete functions such as internal signal amplification and integration. The performance of the amplifier, such as noise, gain, and power consumption, largely determines key indicators of the overall ADC, such as accuracy and power consumption. Therefore, improving the performance of the amplifier and reducing power consumption are crucial for the design of ADCs for systems such as sensor networks and biomedical devices.

[0003] As the process feature size of integrated circuits continues to shrink, the characteristic frequency of devices continues to increase, and the power supply voltage continues to decrease, thus significantly improving the power efficiency of ADCs. However, due to the limitation of thermal noise, the amplifier has gradually become the main power consumption source of ADCs. To reduce power consumption, a clock-controlled dynamic amplifier structure has been applied to the design of ADCs in recent years. The dynamic amplifier does not consume static current and only generates dynamic power consumption at specific clock phases, so the overall power consumption is greatly reduced. However, the gain of the traditional dynamic amplifier structure is very low and it can only operate in open loop, so it is greatly affected by PVT fluctuations. PVT includes Process, Voltage, and Temperature, and it is difficult to provide stable performance. In addition, the performance of the traditional dynamic amplifier, such as noise, offset, and speed, depends heavily on the input common-mode voltage, which severely limits the accuracy of the ADC when it is applied in the ADC.

[0004] In recent years, a floating inverter amplifier (FIA) has emerged. Its structure uses a floating energy storage capacitor to supply power to an amplifier, which can reduce power consumption while providing a certain gain to facilitate the construction of a closed-loop amplification structure in the system and improve the amplifier's ability to suppress PVT fluctuations. In addition, the FIA has a natural ability to suppress fluctuations in the input common mode, making it very suitable for application in low-power ADCs.

[0005] However, the gain of existing single-stage FIA is relatively low (usually below 60 dB), making it difficult to achieve precise closed-loop amplification or integration functions and unable to meet the design requirements of high-precision Delta-Sigma ADCs and pipelined ADCs. Although cascading two-stage or multi-stage FIAs can increase the gain, multi-stage circuits will generate multiple low-frequency poles, significantly affecting the circuit speed and potentially causing system instability. Therefore, the cascaded FIA scheme is difficult to apply in practical ADCs. Therefore, how to increase the gain of dynamic amplifiers such as FIA while ensuring the speed and stability of the amplifier has become a key issue in the design of high-efficiency and high-precision ADCs. Summary of the Invention

[0006] Based on the defects of the above existing technologies, the present invention provides a gain-boosting floating inverting dynamic amplifier circuit, which solves the problem that the existing cascaded FIA ADC design scheme can increase the gain, but the multi-stage circuit will generate multiple low-frequency poles, significantly affecting the circuit speed and potentially causing system instability.

[0007] The present invention adopts the following technical solutions: The present invention provides a gain-boosting floating inverting dynamic amplifier circuit, including a main amplifier, a first auxiliary amplifier, and a second auxiliary amplifier; The main amplifier includes a first power supply capacitor C RES31 , a second power supply capacitor C RES32 , a plurality of first common-source transistors, a plurality of first common-gate transistors, a first control switch, a second control switch, a third control switch, a fourth control switch, and a fifth control switch; the drains of the plurality of first common-source transistors are respectively connected to the input terminals of the first auxiliary amplifier and the second auxiliary amplifier, and the gates are used to receive input signals; the gates of the plurality of first common-gate transistors are respectively connected to the output terminals of the first auxiliary amplifier and the second auxiliary amplifier; the two ends of the first power supply capacitor C RES31 are connected to the power supply through the first control switch, the two ends of the first power supply capacitor and the two ends of the second power supply capacitor are connected through the second control switch, the two ends of the first power supply capacitor are connected to the sources of the plurality of first common-source transistors through the third control switch, and the two ends of the second power supply capacitor are connected to the sources of the plurality of first common-source transistors through the fourth control switch; Both the first auxiliary amplifier and the second auxiliary amplifier include a plurality of second common-gate transistors, and the gates of the plurality of second common-gate transistors are directly connected to the common-mode level.

[0008] Preferably, the plurality of first common-source transistors include a first transistor M n31 , a second transistor M n32 , a third transistor Mp31 and the fourth transistor M p32 , the first common-gate transistor includes a fifth transistor M cn31 , a sixth transistor M cn32 , a seventh transistor M cp31 and an eighth transistor M cp32 ; the first control switch includes a first switch s 301 and a second switch s 302 , the second control switch includes a third switch s 303 and a fourth switch s 304 , the third control switch includes a fifth switch s 305 and a sixth switch s 306 , the fourth control switch includes a seventh switch s 307 and an eighth switch s 308 , the fifth control switch includes a ninth switch s 309 and a tenth switch s 310 ; One end of the first switch s 301 is connected to the power supply, one end of the second switch s 302 is grounded, and the other ends of the first switch s 301 and the second switch s 302 are respectively connected to both ends of the first power supply capacitor C RES31 ; one ends of the third switch s 303 and the fourth switch s 304 are respectively connected to both ends of the first power supply capacitor C RES31 , and the other ends are respectively connected to both ends of the second power supply capacitor C RES32 ; the sources of the first transistor M n31 and the second transistor M n32 are connected to one ends of the sixth switch s 306 and the eighth switch s 308 , the sources of the third transistor M p31 and the fourth transistor M p32 are connected to one ends of the fifth switch s 305 and the seventh switch s 307 , the other ends of the fifth switch s 305 and the sixth switch s 306 are respectively connected to both ends of the first power supply capacitor C RES31 , and the other ends of the seventh switch s 307 and the eighth switch s 308 are respectively connected to both ends of the second power supply capacitor C RES32 ; the first transistor M n31and the third transistor M p31 have their gates interconnected and are used to input the input signal V in ; the gates of the second transistor M n32 and the fourth transistor M p32 are interconnected and are used to input the input signal V ip ; the drains of the first transistor M n31 and the second transistor M n32 are respectively connected to the input terminals of the first auxiliary amplifier, and the drains of the third transistor M p31 and the fourth transistor M p32 are respectively connected to the input terminals of the second auxiliary amplifier.

[0009] Preferably, the gates of the fifth transistor M cn31 and the sixth transistor M cn32 are respectively connected to the output terminal of the first auxiliary amplifier, and the sources are respectively connected to the drains of the first transistor M n31 and the second transistor M n32 ; the drains of the seventh transistor M cp31 and the eighth transistor M cp32 are respectively connected to the output terminals of the second auxiliary amplifier, and the sources are respectively connected to the drains of the third transistor M p31 and the fourth transistor M p32 ; the drains of the fifth transistor M cn31 and the seventh transistor M cp31 are both connected to one end of the ninth switch s 309 and are used to output the output signal V op ; the drains of the sixth transistor M cn32 and the eighth transistor M cp32 are both connected to one end of the tenth switch s 310 and are used to output the output signal V on , and the other ends of the ninth switch s 309 and the tenth switch s 310 are connected to the common-mode level.

[0010] Preferably, the first auxiliary amplifier and the second auxiliary amplifier further include a third power supply capacitor C RES4 , a plurality of second common-source transistors, a sixth control switch, a seventh control switch, an eighth control switch, a ninth control switch, and a tenth control switch; the structures of the first auxiliary amplifier and the second auxiliary amplifier both adopt a cascode floating inverting dynamic amplifier structure.

[0011] Preferably, the first control switch is controlled by the first control signal φ 11 , and the second control signal φ12 Control the second control switch via a third control signal φ 21 Control the third control switch via a fourth control signal φ 22 Control the fourth control switch.

[0012] Preferably, when the first control signal φ 11 is at a high level, the first control switch closes, and the power supply charges the first power supply capacitor C RES31 while the output node is reset to the common mode level; When the second control signal φ 12 is at a high level, the second control switch closes, and the first power supply capacitor C RES31 and the second power supply capacitor C RES32 are in parallel for charge sharing; When the third control signal φ 21 is at a high level, the third control switch closes, the input signal is input to the gain-boosting floating inverter dynamic amplifier, and the first power supply capacitor C RES31 powers the amplifier to obtain a first-order amplified output signal; When the fourth control signal φ 22 is at a high level, the fourth control switch closes, the input signal is input to the gain-boosting floating inverter dynamic amplifier, and the first power supply capacitor C RES31 and the second power supply capacitor C RES32 power the amplifier to obtain a second-order amplified output signal.

[0013] Compared with the prior art, the above at least one technical solution adopted by the present invention can achieve the following beneficial effects: The present invention provides a gain-boosting floating inverter dynamic amplifier circuit, which includes a main amplifier, a first auxiliary amplifier, and a second auxiliary amplifier. The main amplifier and the auxiliary amplifiers all adopt the floating inverter dynamic amplifier structure of the cascode type. Therefore, their pole frequencies will change synchronously with the working state of the circuit, ensuring the stability of the circuit. At the same time, the introduction of a common-mode feedback circuit is avoided, reducing the complexity of the circuit. Further, the main amplifier of the present invention includes a first power supply capacitor and a second power supply capacitor, and two energy storage capacitors are used to achieve reverse-related level conversion. Through the charge sharing between the power supply capacitors, the power supply voltage during signal amplification is reduced, avoiding current waste caused by excessive current at the moment of circuit conduction, thereby effectively improving the utilization efficiency of the current. The gate of the common-gate device of the main amplifier is connected to the output terminal of the auxiliary amplifier, improving the output swing of the overall amplifier. When applied in an ADC, the signal range and signal-to-noise ratio of the ADC can be improved. By introducing two auxiliary amplifiers to form a gain-boosting structure, the overall gain of the amplifier is significantly improved with a small circuit and power consumption overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0015] Figure 1 is the circuit structure diagram of the traditional FIA; Figure 2 is the timing diagram of the traditional FIA; Figure 3 is the circuit structure diagram of the traditional cascode FIA; Figure 4 is the timing diagram of the traditional cascode FIA; Figure 5 is the circuit structure diagram of the gain-boosting floating inverter dynamic amplifier of the present invention; Figure 6 is the timing diagram of the gain-boosting floating inverter dynamic amplifier of the present invention; Figure 7 is the structural schematic diagram of the auxiliary amplifier of the present invention; Figure 8 is the abstract structural schematic diagram of the auxiliary amplifier of the present invention; Figure 9 is the timing diagram of the auxiliary amplifier of the present invention; Figure 10 is the circuit structure diagram of the switched-capacitor integrator implemented based on the fully differential GBFIA of the present invention; Figure 11 Timing diagram of the switched-capacitor integrator implemented based on the fully differential GBFIA of the present invention; Figure 12 Schematic diagram of the fully differential GBFIA circuit of the present invention in the reset stage; Figure 13 Timing diagram of the fully differential GBFIA circuit of the present invention in the reset stage; Figure 14 Schematic diagram of the fully differential GBFIA circuit of the present invention in the conversion stage; Figure 15 Timing diagram of the fully differential GBFIA circuit of the present invention in the conversion stage; Figure 16 Schematic diagram of the fully differential GBFIA circuit of the present invention in the first-order amplification stage; Figure 17 Timing diagram of the fully differential GBFIA circuit of the present invention in the first-order amplification stage; Figure 18 Schematic diagram of the fully differential GBFIA circuit of the present invention in the second-order amplification stage; Figure 19 Timing diagram of the fully differential GBFIA circuit of the present invention in the second-order amplification stage; Figure 20 Comparison diagram of the passband gain simulation results between the traditional cascode FIA and the fully differential GBFIA of the present invention. Detailed implementation manner

[0016] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0017] To illustrate the principle and effect of the present invention, first, the structure and principle of the traditional FIA are described. Figure 1 And Figure 2 Are respectively the circuit structure and timing diagram of the traditional single-stage FIA. M n11 , M n112 , M p11 And M p12 Are transistors in the single-stage FIA. s 101 -s 110 Are control switches in the single-stage FIA. C RES1 Is a single floating energy storage capacitor, providing power for the amplifier. V in And V ipis the input signal, V on and V op are the output signals, V CM is the common-mode level, V DD is the power supply, and GND is the ground. The switch s 101 -s 110 is controlled by the control signals φ 1 and φ 2 to turn on and off. When the control signal φ 1 is at a high level, C RES1 stores the V DD voltage; φ During the period when 2 is at a high level, the FIA enters the amplification phase. As current passes through the amplifier, C RES1 the charge stored in C RES1 gradually depletes, eventually causing the amplifier to turn off, thus forming a self-attenuation mechanism. For the FIA circuit, power consumption is only consumed when charging the energy storage capacitor C RES1 , so the power consumption of the amplifier is significantly reduced. At the same time, since the energy storage capacitor C RES1 works like a floating power supply, the current flowing out of I top the top plate must be equal to the current flowing into the bottom plate, that is I bottom . Therefore, only differential current can flow in the amplifier circuit, ensuring that the FIA has a stable output common-mode voltage, avoiding the common-mode feedback circuit introduced in traditional amplifiers, and reducing the circuit complexity.

[0018] The gain of a single-stage FIA circuit is usually less than 30 dB, making it difficult to meet the requirements of the switched-capacitor integrator circuit for the amplifier gain. To increase the amplifier gain, a cascode-structured FIA can be used, as shown in Figure 3 and Figure 4 . In the figure, M n21 , M n22 , M p21 and M p22 are the common-source transistors of the cascode FIA, and M cn21 , M cn22 , M cp21 and M cp22 are the common-gate transistors of the cascode FIA, and s 201 -s 210 is the control switch of the cascode FIA, C RES2The floating energy storage capacitor supplies power to the cascode FIA, V in and V ip are input signals, V on and V op are output signals, V CM is the common-mode level (whose value is V DD / 2, i.e., half of the power supply voltage), V DD is the power supply for the overall circuit, and GND is the ground. The switches s 201 -s 210 are controlled to conduct and turn off by the control signals φ 1 and φ 2. Its DC gain expression is: (1); where, A v,FIA is the DC gain, g mn21,22 and g mp21,22 are the transconductances of the common-source transistors M n21 、M n22 、M p21 and M p22 respectively, g mcn21,22 and g mcp21,22 are the transconductances of the common-gate transistors M cn21 、M cn22 、M cp21 and M cp22 respectively, r on21,22 、 r op21,22 、 r onc21,22 and r opc21,22 are the output resistances of M n21 、M n22 、M p21 、M p22 、M cn21 、M cn22 、M cp21 and M cp22 respectively. To avoid generating additional bias voltages, the gates of the common-gate devices are connected to V CM = V DD / 2. M cn21 、M cn22 、M cp21 and M cp22is designed to be large enough to ensure its operation in the subthreshold region, thus ensuring that the drain voltages of the common-source devices M n21 、M n22 、M p21 and M p22 are high enough to prevent them from entering the linear region. The cascode FIA can achieve a gain of 50 dB to 60 dB, which is an improvement compared to the single-stage FIA, but still cannot meet the requirements in the switched-capacitor integrator circuit. And since the gate of the cascode device is V CM , this will significantly reduce the output swing of the amplifier.

[0019] To overcome the shortcomings of the prior art, the present invention provides a gain-boosted floating inverter amplifier (GBFIA) circuit, specifically a fully differential gain-boosted floating inverter amplifier circuit. It has the advantages of high gain, low power consumption, and high stability. When applied in high-precision pipelined and Delta-Sigma ADCs, it can significantly reduce the power consumption of the ADC while ensuring the accuracy of the ADC. This circuit introduces two auxiliary amplifiers into the main FIA to form a gain-boosted structure, thereby significantly increasing the total gain of the amplifier by increasing the output impedance of the FIA. Different from the traditional FIA, two energy storage capacitors are used in the structure of the main FIA of the present invention to achieve reverse-related level conversion, improving the current utilization efficiency. And the input of the main FIA does not need to be reset to the common-mode level, effectively avoiding the error introduced by the reset switch operation.

[0020] The auxiliary amplifier in the fully differential GBFIA of the present invention also adopts a cascode type FIA structure, which not only further reduces the power consumption but also avoids introducing a common-mode feedback circuit, reducing the circuit complexity. A significant feature of the fully differential GBFIA is that the pole frequencies of the auxiliary FIA and the main FIA change synchronously with the state of the circuit, ensuring the stability of the circuit. The control timing of the main FIA and the auxiliary FIA is generated based on the same clock through frequency division and logic circuits, simplifying the circuit design. In addition, the gate bias level of the cascode transistor of the main FIA is determined by the output of the auxiliary FIA, thereby further increasing the output swing of the fully differential GBFIA.

[0021] To achieve the required high gain (greater than 100 dB) and avoid introducing a traditional common-mode feedback circuit, while ensuring the stability of the circuit, both the main amplifier and the auxiliary amplifier in the present invention are cascode type FIAs. To avoid introducing an additional bias voltage, the gate of the cascode device of the auxiliary FIA is directly connected to the common-mode level V CM , where the common-mode level VCM About half of the power supply voltage V DD (i.e., V CM ≈ V DD / 2). The gates of the common-gate devices of the main FIA are connected to the output terminals of the auxiliary FIA, thereby further improving the output swing of the GBFIA.

[0022] In the present invention, the fully differential GBFIA is composed of a main amplifier and two auxiliary FIAs. The two auxiliary FIAs include a first auxiliary amplifier and a second auxiliary amplifier, and both the main amplifier and the auxiliary amplifiers adopt the FIA structure. The structure and typical control timing of the GBFIA are as Figure 5 and Figure 6 shown.

[0023] The main amplifier includes a first power supply capacitor C RES31 , a second power supply capacitor C RES32 , a plurality of first common-source transistors, a plurality of first common-gate transistors, a first control switch, a second control switch, a third control switch, a fourth control switch, and a fifth control switch.

[0024] In this embodiment, the plurality of first common-source transistors include a first transistor M n31 , a second transistor M n32 , a third transistor M p31 , and a fourth transistor M p32 . The first common-gate transistors include a fifth transistor M cn31 , a sixth transistor M cn32 , a seventh transistor M cp31 , and an eighth transistor M cp32 . The first control switch includes a first switch s 301 and a second switch s 302 . The second control switch includes a third switch s 303 and a fourth switch s 304 . The third control switch includes a fifth switch s 305 and a sixth switch s 306 . The fourth control switch includes a seventh switch s 307 and an eighth switch s 308 . The fifth control switch includes a ninth switch s 309 and a tenth switch s 310 .

[0025] The drains of the plurality of first common-source transistors are respectively connected to the input terminals of the first auxiliary amplifier and the second auxiliary amplifier, and the gates of the first common-gate transistors are respectively connected to the output terminals of the first auxiliary amplifier and the second auxiliary amplifier. The first power supply capacitorC RES31 Both ends and the power supply are connected through a first control switch. Both ends of the first power supply capacitor and both ends of the second power supply capacitor are connected through a second control switch. Both ends of the first power supply capacitor and multiple source electrodes of the first common-source transistor are connected through a third control switch. Both ends of the second power supply capacitor and multiple source electrodes of the first common-source transistor are connected through a fourth control switch.

[0026] The first switch s 301 has one end connected to the power supply. The second switch s 302 has one end grounded. The first switch s 301 and the second switch s 302 have their other ends respectively connected to both ends of the first power supply capacitor C RES31 . The third switch s 303 and the fourth switch s 304 have their one ends respectively connected to both ends of the first power supply capacitor C RES31 , and their other ends are respectively connected to both ends of the second power supply capacitor C RES32 . The source electrodes of the first transistor M n31 and the second transistor M n32 are connected to one end of the sixth switch s 306 and the eighth switch s 308 . The source electrodes of the third transistor M p31 and the fourth transistor M p32 are connected to one end of the fifth switch s 305 and the seventh switch s 307 . The other ends of the fifth switch s 305 and the sixth switch s 306 are respectively connected to both ends of the first power supply capacitor C RES31 . The other ends of the seventh switch s 307 and the eighth switch s 308 are respectively connected to both ends of the second power supply capacitor C RES32 . The gates of the first transistor M n31 and the third transistor M p31 are interconnected and used to input the input signal V in . The gates of the second transistor M n32 and the fourth transistor M p32 are interconnected and used to input the input signal V ip . The drains of the first transistor M n31 and the second transistor M n32 are respectively connected to the input ends of the first auxiliary amplifier. The drains of the third transistor M p31 and the fourth transistor M p32The drains are respectively connected to the input terminals of the second auxiliary amplifier.

[0027] The fifth transistor M cn31 and the sixth transistor M cn32 have their gates respectively connected to the output terminals of the first auxiliary amplifier, and their sources respectively connected to the drains of the first transistor M n31 and the second transistor M n32 . The seventh transistor M cp31 and the eighth transistor M cp32 have their drains respectively connected to the output terminals of the second auxiliary amplifier, and their sources respectively connected to the drains of the third transistor M p31 and the fourth transistor M p32 . The drains of the fifth transistor M cn31 and the seventh transistor M cp31 are both connected to one end of the ninth switch s 309 and are used to output the output signal V op . The drains of the sixth transistor M cn32 and the eighth transistor M cp32 are both connected to one end of the tenth switch s 310 and are used to output the output signal V on , and the other ends of the ninth switch s 309 and the tenth switch s 310 are connected to the common-mode level.

[0028] The first control switch is controlled by the first control signal φ 11 , the second control switch is controlled by the second control signal φ 12 , the fourth control switch is controlled by the third control signal φ 21 , and the fourth control switch is controlled by the fourth control signal φ 22 .

[0029] M n31 , M n32 and M p31 , M p32 are the common-source transistors of the main FIA in the fully differential GBFIA, M cn31 , M cn32 and M cp31 , M cp32 are the common-gate transistors of the main FIA in the fully differential GBFIA, s 301 -s 310 are the control switches of the main FIA in the fully differential GBFIA, C RES31 and C RES32The floating energy storage capacitor supplies power to the main FIA, V in and V ip are input signals, V on and V op are output signals, V DD is the power supply for the overall circuit, and GND is the ground. The drain electrodes of the common-source transistors M n31 , M n32 , M p31 and M p32 in the main FIA are connected to the input terminal of the auxiliary FIA, and the output terminal of the auxiliary FIA is connected to the gate electrodes of the common-gate transistors M cn31 , M cn32 , M cp31 and M cp32 in the main FIA. s 301 -s 310 is controlled by φ 11 , φ 12 , φ 21 , φ 22 to turn on and off. The working timing sequence of the main FIA includes a reset stage ( φ 11 is at a high level), a conversion stage ( φ 12 is at a high level), a first-order amplification stage ( φ 21 is at a high level) and a second-order amplification stage ( φ 22 is at a high level). A switched-capacitor integrator circuit is built using a fully differential GBFIA. In the reset stage ( φ 11 is at a high level), the main power supply capacitor C RES31 starts to charge, and at the same time the output node is reset to the common-mode level V CM . In the conversion stage ( φ 12 is at a high level), the main power supply capacitor C RES31 is connected in parallel with the auxiliary power supply capacitor C RES32 for charge sharing. In the first-order amplification stage, the main power supply capacitor C RES31 supplies power to the amplifier. By the end of this stage, the output node obtains a result of the FIA integration output powered only by the main power supply capacitor. In the second-order amplification stage, the main power supply capacitor C RES31 and the auxiliary power supply capacitor CRES32 They jointly supply power to the fully differential GBFIA, further enhancing the overall gain, thereby improving the accuracy of the integrator implemented using the GBFIA. The circuit timing ensures that while fully utilizing the operating current provided by the capacitor, the high gain of the amplifier is maintained.

[0030] The structure and timing of the auxiliary FIA are as Figures 7 - 9 shown. It includes a third power supply capacitor C RES4 , multiple second common-source transistors, a sixth control switch, a seventh control switch, an eighth control switch, a ninth control switch, and a tenth control switch.

[0031] The multiple second common-source transistors include a ninth transistor M n41 , a tenth transistor M n42 , an eleventh transistor M p41 , and a twelfth transistor M p42 . The second common-gate transistors include a thirteenth transistor M cn41 , a fourteenth transistor M cn42 , a fifteenth transistor M cp41 , and a sixteenth transistor M cp42 . The sixth control switch includes an eleventh switch s 401 and a twelfth switch s 402 . The seventh control switch includes a thirteenth switch s 403 and a fourteenth switch s 404 . The eighth control switch includes a fifteenth switch s 405 and a sixteenth switch s 406 . The ninth control switch includes a seventeenth switch s 407 and an eighteenth switch s 408 . The tenth control switch includes a nineteenth switch s 409 and a twentieth switch s 410 .

[0032] M n41 , M n42 , M p41 , and M p42 are the common-source transistors of the auxiliary FIA in the fully differential GBFIA. M cn41 , M cn42 , M cp41 , and M cp42 are the common-gate transistors of the auxiliary FIA in the fully differential GBFIA. s 401 - s 410 are the control switches of the auxiliary FIA in the fully differential GBFIA. C RES4 is the floating energy storage capacitor that supplies power to the auxiliary FIA. V in_au and V ip_au are the input signals. Von_au and V op_au are output signals, V DD is the power supply for the overall circuit, and GND is the ground. The switch s 401 -s 410 is controlled to conduct and turn off by the control signals φ 1 and φ 2. To simplify the circuit design, the operation of the auxiliary FIA is divided into a charging stage ( φ 1 is at a high level) and an amplification stage ( φ 2 is at a high level). In the charging stage, the energy storage capacitor C RES4 is charged to V DD , and the input and output nodes of the auxiliary FIA are reset to the common-mode level V CM . In the amplification stage, the capacitor C RES4 powers the auxiliary FIA, and the output node of the auxiliary FIA is connected to the gate of the common-gate device of the main FIA, which not only improves the output resistance of the overall fully differential GBFIA, increases the gain, but also further expands the output swing.

[0033] To better illustrate the benefits of the fully differential GBFIA of the present invention when applied, Figure 10 and Figure 11 respectively give the structure and timing diagram of a switched-capacitor integrator implemented based on the fully differential GBFIA, where the black part is the GBFIA and the gray part is the switched-capacitor circuit required to form the integrator. The operating timing of the gain-boosting floating inverter dynamic amplifier (GBFIA) circuit includes a reset phase ( φ 11 phase), a conversion phase ( φ 12 phase), a first-order amplification phase ( φ 21 phase) and a second-order amplification phase ( φ 22 phase). When the switched-capacitor integrator samples, the fully differential GBFIA operates in the reset phase and the conversion phase. In the reset phase, the power supply charges C RES31 , and in the conversion phase, the main supply capacitor C RES1 shares charge with the auxiliary supply capacitor C RES32 . When the switched-capacitor integrator integrates, the fully differential GBFIA operates in the first-order amplification phase and the second-order amplification phase. In the first-order amplification phase, the main supply capacitor C RES31 powers the amplifier, and in the second-order amplification phase, the main supply capacitor CRES31 and the auxiliary power supply capacitor C RES32 jointly supply power to the fully differential GBFIA. During the entire operation of the switched-capacitor integrator, power consumption occurs only when charging the energy storage capacitor C RES1 (i.e., the reset phase), thus significantly reducing the power consumption of the switched-capacitor integrator. At the same time, the high gain in the amplification stage of the fully differential GBFIA ensures the accuracy of the integration result of the switched-capacitor integrator.

[0034] Similar to the FIA, during its operation, the current in the fully differential GBFIA is not fixed but shows a trend of exponential decrease. When the amplifier circuit just enters the amplification stage ( φ 21 is at a high level, the first-order amplification stage), the current is large, but the current generated at this time cannot be fully utilized in the switched-capacitor integrator composed of the amplifier. To solve this problem, the main FIA of the present invention supplies power through the main power supply capacitor C RES31 and the auxiliary power supply capacitor C RES32 jointly, and the overall working timing of the circuit is as shown in Figures 12 - 19 . φ 11 , φ 12 , φ 21 , φ 22 are control signals that control the conduction and cutoff of switches s 31 -s 310 . Specifically, during the reset phase ( φ 11 is at a high level), after the power supply finishes charging C RES31 , during the conversion phase ( φ 12 is at a high level), the main power supply capacitor C RES1 and the auxiliary power supply capacitor C RES32 achieve charge sharing, thereby realizing reverse correlated level conversion and reducing the voltages of the two capacitors. This process helps to reduce the supply voltage of the amplifier during the first-order amplification stage ( φ 21 is at a high level), thus reducing the current in this stage and effectively improving the utilization efficiency of the current. When entering the second-order amplification stage ( φ 22 is at a high level), then C RES32 and C RES31In parallel, they achieve common power supply to ensure the performance of the overall circuit in the middle and late stages of the amplification stage.

[0035] The main effect of the GBFIA of the present invention is that through the gain-boosting structure formed by two auxiliary FIAs, the output impedance of the amplifier is increased, thereby enhancing the gain of the amplifier, and thus improving the accuracy of the entire integrator when applied in the integrator. It can be derived that Figure 5 The gain expression of the GBFIA in it is: (2); Among them, A v,GBFIA is the DC gain of the GBFIA, g mn31,32 , g mp31,32 are the transconductances of the common-source transistors M n31 , M n32 , M p31 and M p32 respectively, g mcn31,32 , g mcp31,32 are the transconductances of the common-gate transistors M cn31 , M cn32 , M cp31 and M cp32 respectively, r on31,32 , r op31,32 , r onc31,32 , r opc31,32 are the output resistances of M n31 , M n32 , M p31 , M p32 , M cn31 , M cn32 , M cp31 and M cp32 respectively, A v,FIA,au is Figure 7 the gain of the auxiliary FIA in A v,FIA,auThe expression is the same as that in Equation (1). It can be seen that the total gain of the GBFIA of the present invention is the product of the gain of the main FIA and the gain of the auxiliary FIA, which is greatly improved compared with the gain of the traditional FIA. To ensure the stability of the gain-boosting amplifier, it is necessary to ensure that the unity-gain bandwidth (Gain–BandWidth Product, GBW) of the auxiliary FIA is greater than the -3dB bandwidth of the main amplifier. During the operation of the FIA circuit, the voltage and current are constantly changing, so its poles will also change accordingly. To ensure that the circuit remains stable throughout the operating cycle, the poles of the auxiliary amplifier need to change synchronously. In the fully differential GBFIA of the present invention, since the auxiliary amplifier also adopts the cascode FIA structure and the energy storage capacitor of the auxiliary amplifier is smaller than that of the main amplifier, this can ensure that the circuit can meet the required pole magnitude relationship between the main FIA and the auxiliary FIA at any time, thus ensuring the stability of the entire GBFIA. In addition, the use of the FIA structure for the auxiliary amplifier can also avoid introducing a common-mode feedback circuit, thereby reducing the system complexity and further improving the overall performance of the circuit. Since the output node voltage of the auxiliary FIA will deviate from the common-mode voltage V CM (i.e., the NMOS terminal is lower than V CM , and the PMOS terminal is higher than V CM ), this further improves the output swing of the overall circuit, optimizes the signal transmission ability of the circuit, and improves its performance and stability.

[0036] To verify the effectiveness of the present invention, a cascode FIA and the fully differential GBFIA of the present invention were built based on the 180nm CMOS (Complementary Metal-Oxide-Semiconductor) process, and their gains were simulated and compared respectively. Both schemes are powered by a 1.8V power supply, and a unity-gain integrator is built for integration, and a small-signal simulation is performed on the output to obtain the gain of the amplifier. The results are as Figure 20 shown. It can be seen from the simulation results that the passband gain of the fully differential GBFIA of the present invention exceeds 100dB, while the DC gain of the traditional cascode FIA is only about 50dB. By analyzing the average operating current of the circuit, it is obtained that the average power consumption of the fully differential GBFIA is 7.56μW, while the power consumption of the cascode FIA is 2.43μW. The results show that compared with the FIA, the fully differential GBFIA of the present invention improves the gain by 50dB with a very low power consumption overhead. When the traditional continuous-time differential amplifier reaches the same gain and bandwidth as the fully differential GBFIA of the present invention, the power consumption is usually in the range of dozens to hundreds of μW. Therefore, the fully differential GBFIA of the present invention has an obvious low-power advantage.

[0037] In summary, the fully differential GBFIA proposed by the present invention not only significantly improves the FIA gain, but also maintains low power consumption and increases the output swing. Compared with the traditional differential amplifier circuit, the present invention does not need to introduce a common-mode feedback circuit, thus effectively reducing the system complexity and improving the circuit stability.

[0038] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0039] Obviously, those skilled in the art can make various changes and deformations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and deformations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and deformations.

Claims

1. A gain-boosting floating inverting dynamic amplifier circuit, characterized in that, It includes a main amplifier, a first auxiliary amplifier, and a second auxiliary amplifier; The main amplifier includes a first power supply capacitor ( C RES31 ), a second power supply capacitor ( C RES32 ), a plurality of first common-source transistors, a plurality of first common-gate transistors, a first control switch, a second control switch, a third control switch, a fourth control switch, and a fifth control switch; the drains of the plurality of first common-source transistors are respectively connected to the input ends of a first auxiliary amplifier and a second auxiliary amplifier, and the plurality of gates are used for receiving input signals; The gates of the plurality of first common-gate transistors are respectively connected to the output terminals of the first auxiliary amplifier and the second auxiliary amplifier; the two ends of the first power supply capacitor ( C RES31 ) and the power supply are connected through a first control switch, the two ends of the first power supply capacitor and the two ends of the second power supply capacitor are connected through a second control switch, the two ends of the first power supply capacitor and the sources of the plurality of first common-source transistors are connected through a third control switch, and the two ends of the second power supply capacitor and the sources of the plurality of first common-source transistors are connected through a fourth control switch; Both the first auxiliary amplifier and the second auxiliary amplifier include a plurality of second common-gate transistors, and a plurality of gates of the second common-gate transistors are directly connected to a common-mode level.

2. The gain-boosting floating inverting dynamic amplifier circuit according to claim 1, characterized in that, The multiple first common-source transistors include a first transistor (M n31 ), a second transistor (M n32 ), a third transistor (M p31 ), and a fourth transistor (M p32 ), the first common-gate transistor includes a fifth transistor (M cn31 ), a sixth transistor (M cn32 ), a seventh transistor (M cp31 ), and an eighth transistor (M cp32 ); the first control switch includes a first switch (s 301 ), and a second switch (s 302 ), the second control switch includes a third switch (s 303 ), and a fourth switch (s 304 ), the third control switch includes a fifth switch (s 305 ), and a sixth switch (s 306 ), the fourth control switch includes a seventh switch (s 307 ), and an eighth switch (s 308 ), the fifth control switch includes a ninth switch (s 309 ), and a tenth switch (s 310 ); One end of the first switch (s 301 ) is connected to a power supply, one end of the second switch (s 302 ) is grounded, and the other ends of the first switch (s 301 ) and the second switch (s 302 ) are respectively connected to both ends of the first power supply capacitor ( C RES31 ); One ends of the third switch (s 303 ) and the fourth switch (s 304 ) are respectively connected to both ends of the first power supply capacitor ( C RES31 ), and the other ends are respectively connected to both ends of the second power supply capacitor ( C RES32 ); The sources of the first transistor (M n31 ) and the second transistor (M n32 ) are connected to one ends of the sixth switch (s 306 ) and the eighth switch (s 308 ), the sources of the third transistor (M p31 ) and the fourth transistor (M p32 ) are connected to one ends of the fifth switch (s 305 ) and the seventh switch (s 307 ), the other ends of the fifth switch (s 305 ) and the sixth switch (s 306 ) are respectively connected to both ends of the first power supply capacitor ( C RES31 ), and the other ends of the seventh switch (s 307 ) and the eighth switch (s 308 ) are respectively connected to both ends of the second power supply capacitor ( C RES32 ); The gates of the first transistor (M n31 ) and the third transistor (M p31 ) are connected to each other and are used for inputting an input signal V in ; The gates of the second transistor (M n32 ) and the fourth transistor (M p32 ) are connected to each other and are used for inputting an input signal V ip ; The drains of the first transistor (M n31 ) and the second transistor (M n32 ) are respectively connected to the input ends of the first auxiliary amplifier, and the drains of the third transistor (M p31 ) and the fourth transistor (M p32 ) are respectively connected to the input ends of the second auxiliary amplifier.

3. The gain-boosting floating inverting dynamic amplifier circuit according to claim 2, characterized in that, The gates of the fifth transistor (M cn31 ) and the sixth transistor (M cn32 ) are respectively connected to the output terminal of the first auxiliary amplifier, and the sources are respectively connected to the drains of the first transistor (M n31 ) and the second transistor (M n32 ); the drains of the seventh transistor (M cp31 ) and the eighth transistor (M cp32 ) are respectively connected to the output terminal of the second auxiliary amplifier, and the sources are respectively connected to the drains of the third transistor (M p31 ) and the fourth transistor (M p32 ); the drains of the fifth transistor (M cn31 ) and the seventh transistor (M cp31 ) are both connected to one end of the ninth switch (s 309 ) and are used to output the output signal V op ; the drains of the sixth transistor (M cn32 ) and the eighth transistor (M cp32 ) are both connected to one end of the tenth switch (s 310 ) and are used to output the output signal V on , and the other ends of the ninth switch (s 309 ) and the tenth switch (s 310 ) are connected to the common-mode level.

4. The gain-boosting floating inverting dynamic amplifier circuit according to claim 1, characterized in that, The first auxiliary amplifier and the second auxiliary amplifier further include a third power supply capacitor ( C RES4 ), a plurality of second common-source transistors, a sixth control switch, a seventh control switch, an eighth control switch, a ninth control switch, and a tenth control switch; the structures of the first auxiliary amplifier and the second auxiliary amplifier both adopt a cascode floating inverter dynamic amplifier structure.

5. The gain-boosting floating inverting dynamic amplifier circuit according to claim 1, characterized in that, Control the first control switch through the first control signal ( φ 11 ), control the second control switch through the second control signal ( φ 12 ), control the third control switch through the third control signal ( φ 21 ), and control the fourth control switch through the fourth control signal ( φ 22 ).

6. The gain-boosting floating inverting dynamic amplifier circuit according to claim 5, characterized in that, When the first control signal ( φ 11 ) is at a high level, the first control switch closes, and the power supply charges the first power supply capacitor ( C RES31 ), and at the same time the output node is reset to the common mode level; When the second control signal ( φ 12 ) is at a high level, the second control switch closes, and the first power supply capacitor ( C RES31 ) and the second power supply capacitor ( C RES32 ) are in parallel for charge sharing; When the third control signal ( φ 21 ) is at a high level, the third control switch closes, and the input signal is input to the gain-boosting floating inverter dynamic amplifier. The first power supply capacitor ( C RES31 ) supplies power to the amplifier, and a first-order amplified output signal is obtained; When the fourth control signal ( φ 22 ) is at a high level, the fourth control switch closes, and the input signal is input to the gain-boosting floating inverter dynamic amplifier. The first power supply capacitor ( C RES31 ) and the second power supply capacitor ( C RES32 ) supply power to the amplifier, and a second-order amplified output signal is obtained.

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