Broadband inter-stage matching

Abstract

The invention relates to broadband inter-stage matching. Systems and devices for impedance matching are described. A system may include a first amplification stage configured to amplify an input signal to an intermediate signal; and a second amplification stage configured to amplify the intermediate signal into an output signal. The system may also include a matching network configured to match an output impedance of the first amplification stage with an input impedance of the second amplification stage. The configuration of the first amplification stage may define an impedance transformation ratio that minimizes an impedance mismatch between the output impedance of the first amplification stage and the input impedance of the second amplification stage. The configuration of the first amplification stage may specify at least one property of one or more transistors in the first amplification stage and at least one operating condition of the first amplification stage.

Description

Technical Field

[0001] The present disclosure generally relates to systems and devices for impedance matching. In particular, specific configurations are defined for the stage prior to the inter-stage matching network. Background Art

[0002] Multiple-input multiple-output (massive MIMO) is a wireless communication technology that can use multiple transmit and receive antennas to multiply the capacity of a radio link by exploiting multipath propagation. A MIMO system can simultaneously transmit and receive more than one data signal on the same radio channel by taking advantage of the differences in signal propagation between different antennas (e.g., due to multipath propagation). Another class of technology is massive MIMO, in which a base station is equipped with a very large number of antenna elements to further improve spectral and energy efficiency. In massive MIMO technology, the number of terminals may be much less than the number of base station antennas. Massive MIMO systems can use relatively simple beamforming strategies such as maximum ratio transmission, maximum ratio combining, or zero forcing. Summary of the Invention

[0003] In one embodiment, a system for impedance matching is generally described. The system can include a first amplification stage configured to amplify an input signal to an intermediate signal. The system can also include a second amplification stage configured to amplify the intermediate signal to an output signal. The system can also include a matching network configured to match the output impedance of the first amplification stage with the input impedance of the second amplification stage. The configuration of the first amplification stage can define an impedance transformation ratio that minimizes the impedance mismatch between the output impedance of the first amplification stage and the input impedance of the second amplification stage. The configuration of the first amplification stage can specify at least one attribute of one or more transistors in the first amplification stage and at least one operating condition of the first amplification stage.

[0004] In one embodiment, a system for impedance matching is generally described. The system can include a first amplification stage configured to amplify an input signal to an intermediate signal. The first amplification stage can include a first main amplifier and a first peaking amplifier. The system can also include a second amplification stage configured to amplify the intermediate signal to an output signal. The second amplification stage can include a second main amplifier and a second peaking amplifier. The system can also include a first matching network configured to match the output impedance of the first main amplifier with the input impedance of the second peaking amplifier. The system can also include a second matching network configured to match the output impedance of the first peaking amplifier with the input impedance of the second peaking amplifier. The configuration of the first amplification stage can define an impedance transformation ratio that minimizes the impedance mismatch between the first amplification stage and the second amplification stage. The configuration of the first amplification stage specifies at least one attribute of one or more transistors in the first amplification stage and at least one operating condition of the first amplification stage.

[0005] In one embodiment, a system for impedance matching is generally described. The system may include an antenna. The system may also include a first amplification stage configured to amplify an input signal to an intermediate signal. The system may further include a second amplification stage configured to amplify the intermediate signal to an output signal and provide the output signal to the antenna. The system may also include a matching network configured to match the output impedance of the first amplification stage with the input impedance of the second amplification stage. The configuration of the first amplification stage may define an impedance transformation ratio that minimizes the impedance mismatch between the output impedance of the first amplification stage and the input impedance of the second amplification stage. The configuration of the first amplification stage may specify at least one attribute of one or more transistors in the first amplification stage and at least one operating condition of the first amplification stage.

[0006] Other features as well as the structures and operations of various embodiments are described in detail below with reference to the accompanying drawings. In the drawings, like reference numerals indicate identical or functionally similar elements. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a diagram showing an example system in which broadband inter-stage matching can be implemented in one embodiment.

[0008] Figure 2 is a diagram showing another example system in which broadband inter-stage matching can be implemented in one embodiment.

[0009] Figure 3 is a diagram showing another example system in which broadband inter-stage matching can be implemented in one embodiment.

[0010] Figure 4 is a diagram showing additional details of an implementation of broadband inter-stage matching in one embodiment.

[0011] Figure 5 is a diagram showing an example implementation of broadband inter-stage matching in one embodiment.

[0012] Figure 6 is a diagram showing another example implementation of broadband inter-stage matching in one embodiment.

[0013] Figure 7 is a diagram showing another example implementation of broadband inter-stage matching in one embodiment.

[0014] Figure 8 is a diagram showing another example implementation of broadband inter-stage matching in one embodiment.

[0015] Figure 9 is a diagram showing another example implementation of broadband inter-stage matching in one embodiment.

[0016] Figure 10 FIG. is another exemplary embodiment showing broadband inter-stage matching in one embodiment.

[0017] Figure 11 FIG. is another exemplary embodiment showing broadband inter-stage matching in one embodiment.

[0018] Figure 12 FIG. is another exemplary embodiment showing broadband inter-stage matching in one embodiment.

[0019] Figure 13 FIG. is another exemplary embodiment showing broadband inter-stage matching in one embodiment.

[0020] Figure 14 FIG. is another exemplary embodiment showing broadband inter-stage matching in one embodiment.

[0021] Figure 15 FIG. is another exemplary embodiment showing broadband inter-stage matching in one embodiment.

[0022] Figure 16 FIG. is another exemplary embodiment showing broadband inter-stage matching in one embodiment. DETAILED DESCRIPTION

[0023] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of various embodiments of the present application. However, those of ordinary skill in the art will understand that the various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0024] Figure 1 FIG. is a diagram showing an exemplary system in which broadband inter-stage matching can be implemented. System 100 may be part of a transmission chain implemented by one or more semiconductor devices in a radio frequency (RF) transmitter. System 100 may at least include a first amplification stage 110 (referred to herein as "driver stage 110"), a second amplification stage (referred to herein as "output stage 120"), and a matching network 130. The driver stage 110 may include at least one amplifier 112, and the output stage 120 may include at least one amplifier 122. The matching network 130 may be an inter-stage matching network configured to create a matching impedance between the driver stage 110 and the output stage 120. The matching network 130 may include matching elements that may be reactive circuit components, such as capacitors and inductors. System 100 may be implemented using one or more semiconductor devices.

[0025] An input signal 102 can be provided to a driver stage 110. An amplifier 112 in the driver stage 110 can amplify the input signal 102 into an intermediate signal 103, and the intermediate signal 103 can be transmitted to an output stage 120 via a matching network 130. An amplifier 122 in the output stage 120 can further amplify the intermediate signal 103 to generate an output signal 104. In one embodiment, if the output stage 120 is an amplification stage located before a load (such as an antenna 106), the output signal 104 can be provided to the load. In one embodiment, the input signal 102, the intermediate signal 103, and the output signal 104 can be radio frequency (RF) signals, and the antenna 106 can transmit radio waves to transmit the output signal 104 to other devices.

[0026] In one aspect, the driver stage 110 can be a source having a source resistance R S , and the output stage 120 can be a load having a load resistance R L . The matching network 130 can change the load resistance R L to match the source resistance R S . If R S >R L , then a power matching factor of m = R S / R L >1 can be used to increase or enlarge R L to match R S . If R S <R L , then a power matching factor of m = R S / R L <1 can be used to reduce R L to match R S . As the power matching factor approaches the value 1 (e.g., the difference between R L and R S decreases), the quality factor ("Q factor") can decrease because the Q factor can be expressed as As the Q factor decreases, the bandwidth of the system 100 can be increased, and the insertion loss of the system 100 can be reduced.

[0027] In a massive MIMO system, the last stage of the transmission chain before the antenna can pose challenges in terms of gain, efficiency, and bandwidth. In one aspect, the MIMO density can determine the power capability of the last stage. The range of the typical average power level of each stage can be from 5 watts (W) to 10 W, respectively driven by signals with a peak-to-average ratio of 8.5 decibels (dB) to 9 dB. It is desirable to construct a MIMO system that can simultaneously cover high power, high efficiency, and large bandwidth while keeping the system cost low.

[0028] In one aspect, some large-scale MIMO systems use multiple cascaded gain blocks in a transmitter chain to achieve high array gain, and use conventional inter-stage network matching, which involves matching the higher impedance of an input device with the lower impedance of an output device. However, due to the large transformation ratio between stages, the inter-stage loss may be higher, which may lead to reduced efficiency between subsequent stages and affect the entire transmitter array. Moreover, the bandwidth can be narrower, and the number of matching elements can be higher. The increase in the number of matching elements may lead to an increase in occupied space (e.g., on-chip area), total cost, conduction loss, and component sensitivity, thus affecting product yield.

[0029] As will be described in more detail below, by implementing the driver stage 110 with the specific configuration 140, the system 100 can achieve higher transmitter chain array efficiency, bandwidth, a more compact smaller occupied space, and overall yield. In one embodiment, the configuration 140 can specify one or more specific operating conditions and settings of the driver stage 110. By way of example, the configuration 140 can specify one or more properties of one or more devices or transistors in the driver stage 110, and can specify one or more operating conditions of the driver stage 110. One or more properties can include, but are not limited to, the type, size, technology, material, and / or substrate of one or more devices (e.g., transistors) used to implement the driver stage 110 or other properties. The configuration 140 can also specify the type of devices in which amplification can be implemented in the amplification stages described herein, such as cascode devices, common-source devices, Darlington configurations, or other types of devices. Operating conditions can include, but are not limited to, the drain supply voltage (VDD) applied to the driver stage 110 or other operating conditions. In one embodiment, the operating conditions set in the configuration 140 can depend on one or more properties. In one embodiment, the topology of the matching network 130 can also be selected based on the configuration 140. The combination of the configuration 140 and the selected topology of the matching network 130 can optimize and enhance the performance of the transmitter chain using the system 100. Further, the configuration 140 of the driver stage 110 can make the power matching factor (e.g., depending on the ratio of R S / R L be closer to the value 1, thereby reducing the Q factor, making the impedance transformation ratio closer to 1, and increasing the bandwidth. The impedance transformation ratio based on the configuration 140 can minimize the impedance mismatch between the driver stage 110 and the output stage 120. Moreover, the configuration 140 of the driver stage 110 can allow the use of relatively simple components to implement the matching network 130 and maintain the size of the matching network 130 at a relatively compact size.

[0030] Figure 2 is a diagram showing another example system in which broadband inter-stage matching can be implemented in one embodiment.Figure 2 The description may refer to Figure 1 the components shown. In Figure 2 the embodiment shown, the transmission chain of system 100 in Figure 1 may include additional driver or amplification stages before driver stage 110 (e.g., input signal 102 may be provided by another driver or amplification stage in the transmission chain). Additional matching networks may be located between different driver stages to perform impedance matching. In Figure 2 the embodiment shown, another driver stage 202 may be before driver stage 110, matching network 201 may be before driver stage 202, and matching network 204 may be located between driver stages 202 and 110 to perform impedance matching. Further, in Figure 2 the embodiment shown, another output stage or load (such as antenna 106) may be after output stage 120 (and before antenna 106 in Figure 1 ), and matching network 206 may be located between output stage 120 and the next output stage or load to perform impedance matching. Driver stage 202, driver stage 110, and output stage 120 may be optimized based on various configurations (such as configuration 140). In Figure 2 the embodiment shown, configuration 140 may specify different attributes and / or operating conditions for different stages, such as supply voltages V_supply1, V_supply2, and V_supply3 for driver stage 202, driver stage 110, and output stage 120, respectively.

[0031] Figure 3 FIG. is a diagram showing another example system in which broadband inter-stage matching may be implemented in one embodiment. Figure 3 The description may refer to Figure 1 and Figure 2 the components shown. In Figure 3In the illustrated embodiment, the driver stage 110 and the output stage 120 of the system 100 may be implemented by a Doherty amplifier including a main path and a peak path. The driver stage 110 may include at least amplifier 312 and amplifier 314, where amplifier 312 may be the main amplifier in the main path, and amplifier 314 may be the peak amplifier in the peak path. The matching network 330 may be an inter-stage matching network configured to create a matching impedance between amplifier 312 in the driver stage 310 and amplifier 322 in the output stage 320. The output stage 120 may include at least amplifier 322 and amplifier 324, where amplifier 322 may be the main amplifier in the main path, and amplifier 324 may be the peak amplifier in the peak path. The matching network 332 may be an inter-stage matching network configured to create a matching impedance between amplifier 314 in the driver stage 310 and amplifier 324 in the output stage 320. The matching networks 330, 332 may include reactive circuit components such as capacitors and inductors. The description of the matching network 130 herein may also apply to the matching networks 330, 332.

[0032] The input signal 102 may be split (e.g., by a quadrature coupler) and distributed to amplifiers 312, 314 of the driver stage 310. Amplifier 312 may amplify the input signal 102 into an intermediate signal 303, and the intermediate signal 303 may be transmitted to amplifier 322 in the output stage 320 via the matching network 330. Amplifier 322 in the output stage 320 may further amplify the intermediate signal 303 to generate an output signal 307. Amplifier 314 may amplify the input signal 102 into an intermediate signal 305, and the intermediate signal 305 may be transmitted to amplifier 324 in the output stage 320 via the matching network 332. Amplifier 324 in the output stage 320 may further amplify the intermediate signal 305 to generate an output signal 309. In the Doherty amplifier architecture, the amplifier 322 in the main path and the amplifier circuit 324 in the peak path may be biased differently. Therefore, the signals 307, 309 may be out of phase by 90 degrees. The signals 307, 309 may be combined and in-phase using, for example, a quarter-wavelength transmission line. The combination of the signals 307, 309 may be output as the output signal 304. The output signal 304 may be provided to a load such as an antenna 306. In one embodiment, the input signal 302, the intermediate signals 303, 307, and the output signals 304, 307, 309 may be radio frequency (RF) signals, and the antenna 306 may transmit radio waves to transmit the output signal 304 to other devices.

[0033] In one embodiment, the configuration 140 may specify one or more of the size, technology, and / or substrate of the devices (e.g., transistors) used to implement the amplifiers 312, 314 in the driver stage 110 and the drain supply voltage applied to the amplifiers 312, 314 in the driver stage 110. The configuration 140 may specify the same or different sizes, technologies, substrates, and / or drain supply voltages for the amplifiers 312, 314.

[0034] Figure 4 is a diagram showing additional details of an implementation of broadband inter-stage matching in one embodiment. Figure 4 The description of may refer to Figures 1 to 3 the components shown. In Figure 4 the embodiment shown, the driver stage 110 may include one or more devices, such as device 402, which may implement Figure 1 the amplifier 112 in Figure 2 the amplifier 312 in Figure 2 and / or the amplifier 314 in Figure 1 The output stage 120 may include one or more devices, such as device 404, which may implement Figure 2 the amplifier 122 in Figure 2 the amplifier 322 in Figure 4 and / or the amplifier 324 in. In the example shown, to match the input impedance Zin of the output stage 120 with the output impedance of the driver stage 110, the configuration 140 may specify various settings and parameters in the driver stage 110 to make the output impedance of the driver stage 110 equivalent to the optimal impedance Zopt, where Zopt is substantially the same as Zin.

[0035] In one embodiment, to achieve Zopt at the output of the driver stage 110, the configuration 140 may specify the settings and parameters that make the resistance across device 402 equivalent to the optimal resistance Ropt, where Ropt is the resistance corresponding to Zopt (e.g., Ropt is the real part of Zopt). The optimal resistance Ropt can be expressed as:

[0036]

[0037] where VDD is the drain supply voltage operating device 402, Vknee is the knee voltage of device 402, and Imax is the maximum value of the drain current Id flowing into the drain of device 402. In one embodiment, to achieve Ropt, the configuration 140 may specify the value of VDD that makes the resistance across device 402 equal to Ropt.

[0038] In one embodiment, the value of VDD specified by configuration 140 may depend on the size and / or technology or material used to implement device 402. The size and / or technology of device 402 may define a range of values for VDD. In one embodiment, the technology of device 402 in driver stage 110 may have a lower breakdown voltage than the technology of device 404 in output stage 120. In another embodiment, the technologies of device 402 and device 404 in driver stage 110 may be the same, but device 402 may have a smaller size and thus may have a lower breakdown voltage than device 404. The lower breakdown voltage in driver stage 110 may reduce the on-resistance (RDSon) of device 402 and may also reduce losses. Based on the lower breakdown voltage in driver stage 110, configuration 140 may specify operating conditions for driver stage 110 that are lower than VDD of output stage 120, such as VDD.

[0039] In one aspect, the voltage standing wave ratio (VSWR) of system 100 may be a measure of the efficiency of signal transmission from driver stage 110 to output stage 120. The VSWR may vary with the impedance transformation ratio Zopt / Zin. In an ideal scenario, the VSWR is equal to 1, indicating that 100% of the energy is transmitted. Figure 4 The VSWR of the illustrated system 100 may be expressed as:

[0040]

[0041] where Γ match is the reflection coefficient and is expressed as:

[0042]

[0043] According to the relationship between Γ match , Zopt, and Zin in the above expression, as the difference between Zopt and Zin decreases, the value of Γ match may approach the value 1. Therefore, configuration 140 may specify the attributes of device 402 and the operating conditions of driver stage 110 to cause Γ match to converge to 1.

[0044] Figure 5 is a diagram showing an exemplary implementation of broadband inter-stage matching in one embodiment. Figure 5 The description of Figures 1 to 4 may refer to the components shown in Figure 5In the example shown, the initial operating condition 502 (or initial condition 502) of driver stage 110 may include the VDD value of VDD1. If driver stage 110 operates based on VDD1 and Rg in output stage 120 is 0.75 ohms, then Ropt may be approximately 57 ohms and the Q factor may be 8.66. By way of example, configuration 140 may specify a new value for VDD, such as VDD2. If driver stage 110 operates based on VDD2, Rg in output stage 120 remains 0.75 ohms, and matching network 130 remains unchanged, then Ropt may be approximately 2 ohms. The optimal impedance Zopt may become (2 - j0.2) ohms and the Q factor may be reduced to approximately 1.29. Thus, configuration 140 may specify new operating conditions, such as a new value for VDD in driver stage 110, to reduce the Q factor and improve the overall performance of system 100.

[0045] Figure 6 is a diagram showing another exemplary implementation of broadband inter-stage matching in one embodiment. Figure 6 The description of Figures 1 to 5 may refer to the components shown. In Figure 6 the example shown, device 402 may be implemented by technologies that can operate at a relatively low breakdown voltage, such as gallium nitride (GaN) devices, gallium arsenide (GaAs) devices, and silicon (Si) devices. Device 404 may be implemented by technologies that can operate at a relatively high breakdown voltage, such as GaN devices or silicon carbide (SiC) devices. In response to device 402 being a GaN device, GaAs device, or silicon device, configuration 140 may specify a VDD value for driver stage 110 that is lower than the VDD used to operate output stage 120. In Figure 6 the embodiment shown, output stage 120 may operate at a VDD of 50 volts (V), and configuration 140 may specify that driver stage 110 operates at a lower VDD (such as 5V). Thus, configuration 140 may specify the operating conditions of driver stage 110, such as the value of VDD, depending on the technology used to implement device 402 in driver stage 110 (e.g., GaN, GaAs, Si, or other technologies with a relatively low breakdown voltage). In an embodiment, the lower VDD in driver stage 110 may allow matching network 130 to use relatively simple components to match the reduced output impedance of driver stage 110, thereby reducing the complexity and size of matching network 130.

[0046] Figure 7 is a diagram showing another exemplary implementation of broadband inter-stage matching in one embodiment. Figure 7 The description of Figures 1 to 6 may refer to the components shown. In Figure 7In the example shown, device 402 can be one of a GaN device, a GaAs device, and a Si device, and device 404 can be one of a GaN device and a SiC device, and device 402 can be smaller than device 404. Since device 402 is smaller than device 404, device 402 can have a breakdown voltage lower than that of device 404, and the VDD used to operate device 402 will be lower than the VDD used to operate device 404. In response to device 402 being smaller than device 404, configuration 140 can specify a VDD value for driver stage 110 that is lower than the VDD used to operate output stage 120. In Figure 7 the illustrated embodiment, output stage 120 can operate at a VDD of 50 volts (V), and configuration 140 can specify that driver stage 110 operates at a lower VDD (such as 5V). Thus, configuration 140 can specify the operating conditions of driver stage 110, such as the value of VDD, depending on the size of device 402 in driver stage 110. In an embodiment, the lower VDD in driver stage 110 can allow matching network 130 to match the reduced output impedance of driver stage 110 using relatively simple components, thereby reducing the complexity and size of matching network 130.

[0047] Figure 8 FIG. is a diagram showing another exemplary implementation of broadband inter-stage matching in one embodiment. Figure 8 The description of can refer to Figures 1 to 7 the components shown. In Figure 8 the example shown, driver stage 110 and output stage 120 can implement a Doherty amplifier (similar to Figure 3 ). In one embodiment, in response to amplifier 312 being implemented by a GaN device, a GaAs device, or a silicon device, configuration 140 can specify a value of VDD for amplifier 312, such as VDD1A. VDD1A can be lower than the VDD (e.g., VDD2) used to operate amplifiers 322, 324 in output stage 120. In response to amplifier 314 being implemented by a GaN device or a silicon device, configuration 140 can specify a value of VDD for amplifier 314, such as VDD1B. VDD1B can be lower than the VDD (e.g., VDD2) used to operate amplifiers 322, 324 in output stage 120. In one embodiment, VDD1A can be equal to VDD1B. In another embodiment, VDD1A can be different from VDD1B.

[0048] In one embodiment, in response to amplifier 312 being implemented by a device smaller than the device implementing amplifier 322, configuration 140 may specify a VDD value, such as VDD1A, for amplifier 312 that is lower than VDD2 used to operate amplifier 322. In response to amplifier 314 being implemented by a device smaller than the device implementing amplifier 324, configuration 140 may specify a VDD value, such as VDD1B, for amplifier 314 that is lower than VDD2 used to operate amplifier 324. In one embodiment, VDD1A may be equivalent to VDD1B. In another embodiment, VDD1A may be different from VDD1B. Configuration 140 may specify different operating conditions for different amplifiers or drivers in the Doherty amplifier to perform optimal impedance matching without increasing the complexity of matching networks 330, 332.

[0049] Figure 9 FIG. [FIGURE NUMBER] is a diagram illustrating another exemplary implementation of broadband inter-stage matching in one embodiment. Figure 9 The description of [COMPONENT NAME] may refer to Figures 1 to 8 the components shown in Figure 9 the example shown in FIG. [FIGURE NUMBER]. In the example shown in FIG. [FIGURE NUMBER], configuration 140 may specify operating conditions, such as the output power from device 402 in driver stage 110, to control Zopt and control the VSWR of system 100 to be closer to 1. In Figure 9 the embodiment shown in FIG. [FIGURE NUMBER], reducing the output power from device 402 may increase the impedance value range of Zopt that can be used to match the output impedance of driver stage 110. By way of example, as the output power is reduced from 40.5 dBm to 40.25 dBm, and then to 40.0 dBm, the Zopt range that can be used to match the output impedance of driver stage 110 may increase. The increase in the available Zopt range may increase the number of different matching network topologies that can be used to implement matching network 130.

[0050] Figure 10 FIG. [FIGURE NUMBER] is a diagram illustrating another exemplary implementation of broadband inter-stage matching in one embodiment. Figure 10 The description of [COMPONENT NAME] may refer to Figures 1 to 9 the components shown in Figure 10 the example shown in FIG. [FIGURE NUMBER]. In the example shown in FIG. [FIGURE NUMBER], in addition to configuration 140 specifying various attributes and operating conditions for driver stage 110, the operating conditions of device 404 in output stage 120 may also be configured to control Zin and control the VSWR of system 100 to be closer to 1. In Figure 10In the illustrated embodiment, reducing the gain from device 404 can increase the impedance value range of Zin, and this impedance value range can be used to match the input impedance of output stage 120. By way of example, as the gain is reduced from 16 dB to 15.75 dB and then to 15.50 dB, the Zin range that can be used to match the input impedance of output stage 120 can increase. The increase in the available Zin range can increase the number of different matching network topologies that can be used to implement matching network 130.

[0051] Figure 11 FIG. is a diagram showing another exemplary implementation of broadband inter-stage matching in one embodiment. Figure 11 The description of can refer to Figures 1 to 10 the components shown. In Figure 11 the illustrated embodiment, the device manifolds in driver stage 110 and / or output stage 120 can be adjusted depending on configuration 140. In Figure 11 the illustrated embodiment, each of driver stage 110 and output stage 120 can include more than one amplifier, and output stage 120 can include more amplifiers than driver stage 110. By way of example, if configuration 140 specifies a reduced VDD, a smaller device size, and / or a technology using a lower VDD, then the number of amplifiers in driver stage 110 can be reduced to a number that can be smaller than the number of amplifiers in output stage 120. The reduction in the number of devices in driver stage 110 can reduce the number of components in matching network 130 that are used to match the output impedance of driver stage 110.

[0052] By manipulating the device manifolds in driver stage 110 and / or output stage 120 based on configuration 140, the impedance transformation ratio Zopt / Zin can be closer to 1 (e.g., reducing the difference between Zopt and Zin), and the reduced impedance transformation ratio can result in a lower Q factor. By way of example, if driver stage 110 is split into two amplifiers as Figure 11 shown, then the output impedance of each amplifier in driver stage 110 will be reduced to half of the total output impedance Zout of driver stage 110. Matching network 130 can use two relatively smaller and less complex sets of components having a Zopt that matches Zout / 2, rather than using larger or more complex components to match Zout. Moreover, implementing driver stage 110 using multiple amplifiers does not affect the VDD specified by configuration 140, and the same VDD can be applied to multiple amplifiers.

[0053] And moreover in Figure 11In the example shown, output stage 120 is split into eight amplifiers, which causes matching network 130 to include two sets of 1:4 matching networks (e.g., one input to four outputs). The input impedance of each amplifier in output stage 120 will be reduced to 1 / 8 of the total input impedance Zin of output stage 120. Matching network 130 can use two relatively small and less complex sets of components, whose impedance matches Zin / 8, rather than using larger or more complex components to match Zin.

[0054] Figure 12 is a diagram showing another exemplary implementation of broadband inter-stage matching in one embodiment. Figure 12 The description of can refer to Figures 1 to 11 the components shown. In Figure 12 the embodiment shown, driver stage 110 can be implemented by cascode device 1202. Cascode device 1202 can include two transistors or devices connected in a cascode arrangement. Exemplary techniques or materials for the cascode devices described herein can include GaN on SiC, GaN on Si, silicon-on-insulator (SOI), or other techniques and materials for forming different types of cascode devices. Configuration 140 can specify a relatively low VDD in response to driver stage 110 implemented using cascode device 1202. By way of example, the VDD specified by configuration 140 can be supplied to cascode device 1202, and each device in cascode device 1202 can be operated using VDD / 2. The reduced VDD for each device (such as VDD / 2) can reduce the effective resistance of each device in cascode device 1202. Since one of the two devices in cascode device 1202 is connected to matching network 130, matching network 130 can use relatively small components, whose Zopt can match VDD / 2.

[0055] In one embodiment, configuration 140 can specify a fixed and non-adjustable VDD. In response to configuration 140 specifying a fixed VDD, configuration 140 can also specify a device configuration that can make Zopt match the output impedance of driver stage 110, such that the impedance transformation ratio Zopt / Zin can be closer to 1 (e.g., reduce the difference between Zopt and Zin). By way of example, if configuration 140 specifies a fixed VDD of 10V, and a VDD value of 5V can make Zopt / Zin approximately 1, then configuration 140 can further specify using a device configuration that can split the fixed VDD in half, such as Figure 12 the cascode device 1202 in.

[0056] Figure 13 is a diagram showing another exemplary implementation of broadband inter-stage matching in one embodiment. Figure 13The description can refer to Figures 1 to 12 the components shown. In Figure 13 the embodiment shown, driver stage 110 can be implemented by a multi-transistor structure 1302 having a relatively low output impedance, such as a Darlington structure. As shown by multi-transistor structure 1302, a Darlington structure can be a circuit including two transistors or devices (e.g., bipolar transistors), where the emitter of one transistor is connected to the base of the other transistor such that the current amplified by the first transistor is further amplified by the second transistor. A Darlington structure can have a relatively high input impedance and a relatively low output impedance. Thus, using a Darlington structure to implement multi-transistor structure 1302 can allow matching network 130 to use relatively smaller components, whose Zopt can match the reduced output impedance of multi-transistor structure 302.

[0057] In one embodiment, configuration 140 can specify a fixed and non-adjustable VDD. In response to configuration 140 specifying a fixed VDD, configuration 140 can also specify a device configuration that can operate using a VDD lower than the fixed VDD, such that the impedance transformation ratio Zopt / Zin can be closer to 1 (e.g., reduce the difference between Zopt and Zin). By way of example, if configuration 140 specifies a fixed VDD of 10V, then configuration 140 can further specify a device configuration that can operate driver stage 110 using a VDD lower than 10V, such as Figure 13 the multi-transistor structure 1302 in

[0058] Figure 14 is a diagram showing another exemplary implementation of broadband inter-stage matching in one embodiment. Figure 14 The description can refer to Figures 1 to 13 the components shown. In Figure 14 the embodiment shown, devices 402, 404 can be interconnected with matching network 130 using wire bonds 1402, 1404 respectively. The wire geometries of wire bonds 1402, 1404 can affect the total inductance of driver stage 110 and output stage 120, and thus also affect Zopt and Zin. Configuration 140 can specify various wire geometries for wire bonds 1402, 1404, such as their thickness, diameter, number of wires, width, radius, total number of parallel wires. By configuration 140's specification of wire bond geometry, Zopt and Zin can be controlled such that the impedance transformation ratio Zopt / Zin can be closer to 1 (e.g., reduce the difference between Zopt and Zin). Specification of wire bond geometry can allow tuning of Zopt and / or Zin without changing matching network 130. Thus, a matching network 130 with relatively less complex components can be used, and the wire bond geometry can be adjusted based on the matching network used.

[0059] Figure 15 FIG. is another exemplary embodiment showing broadband inter-stage matching in one embodiment. Figure 15 The description of can refer to Figures 1 to 14 the components shown in Figure 15 In the embodiment shown in Figure 15 the matching network 130 in is a single-section matching network including various matching elements such as capacitors C1, C2, C3, C_DC and inductors (e.g., wiring or transmission lines) L1, L2, L3. In one embodiment, the matching network 130 can be selected based on the specifications in configuration 140. In one embodiment, the matching elements C1 and L1 can be reused as part of a first bias network on the input side of the matching network 130. By using the matching elements C1, L1 as part of the first bias network, the matching elements C1 and L2 can also be reused as part of a second bias network on the output side of the matching network 130, such that a separate second bias network does not need to be constructed. Thus, circuit board space can be conserved.

[0060] Figure 16 FIG. is another exemplary embodiment showing broadband inter-stage matching in one embodiment. Figure 16 The description of can refer to Figures 1 to 15 the components shown in Figure 16 In the embodiment shown in Figure 16 the matching network 130 in is a multi-section matching network including various matching elements such as capacitors C1, C2, C3, C4, C5, C6, C_DC and inductors (e.g., wiring or transmission lines) L1, L2, L3, L4. In one embodiment, if the bandwidth of system 100 is limited to a fixed value, then a multi-section matching network such as Figure 16 the embodiment shown in etc. can be used for impedance matching between the driver stage 110 and the output stage 120. Similar to Figure 15 the embodiment shown in, matching elements such as C1, L1 and C2, L2 can be reused as bias networks. Note that when compared with Figure 16 the multi-section matching network in Figure 15 the embodiment shown in etc., a single section (such as Figure 16 the multi-section matching network of can be used for embodiments where the bandwidth may be limited.

[0061] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It is also to be understood that when the terms "comprises" and / or "comprising" are used in this specification, they specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0062] All structural, material, acts, and equivalents of the components or steps of the following claims, plus functional elements (if any), are intended to include any structure, material, or act for performing the function in combination with other claimed elements for which protection is specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments having various modifications as are suited to the particular use contemplated.

Claims

1. A system comprising: a first amplifier stage configured to amplify an input signal into an intermediate signal; a second amplifier stage configured to amplify the intermediate signal into an output signal; as well as a matching network configured to match the output impedance of the first amplifier stage to the input impedance of the second amplifier stage, wherein: the configuration of the first amplifier stage defines an impedance transformation ratio that minimizes an impedance mismatch between the output impedance of the first amplifier stage and the input impedance of the second amplifier stage; and The configuration of the first amplification stage specifies at least one of the following: at least one property of one or more transistors in the first amplifier stage; and At least one operating condition of the first amplification stage.

2. The system of claim 1, wherein: The at least one attribute includes at least one of the following: a type of the one or more transistors in the first amplifier stage; the material of the one or more transistors in the first amplifier stage; as well as a size of the one or more transistors; and The at least one operating condition includes at least a supply voltage used to operate the first amplifier stage. 3 . The system of claim 2 , wherein the supply voltage depends on the material of the one or more transistors in the first amplification stage.

4. The system of claim 1, wherein the at least one operating condition of the first amplifier stage comprises a first supply voltage used to operate the first amplifier stage, and the first supply voltage is less than a second supply voltage used to operate the second amplifier stage.

5. The system of claim 1, wherein the at least one property comprises a size of the one or more transistors in the first amplifier stage, and the size of the one or more transistors in the first amplifier stage is smaller than a size of one or more transistors in the second amplifier stage.

6. The system of claim 1, wherein: The at least one property comprises a material of the one or more transistors in the first amplifier stage, and the material is one of gallium nitride GaN on silicon carbide SiC, GaN on silicon Si, gallium arsenide GaAs, silicon on insulator SOI, and silicon Si; and The second amplifier stage includes one or more transistors formed from one of GaN on SiC and GaN on Si.

7. The system of claim 1, wherein the first amplifier stage and the second amplifier stage are Doherty amplifiers.

8. The system of claim 1, wherein the one or more transistors in the first amplifier stage include at least one cascode device.

9. The system of claim 1, wherein the one or more transistors in the first amplifier stage include at least one Darlington structure.

10. The system of claim 1, wherein the configuration specifies the at least one property and the at least one operating condition so that the impedance transformation ratio approaches a value of 1.

11. A system comprising: a first amplifier stage configured to amplify the input signal into an intermediate signal, wherein the first amplifier stage comprises a first main amplifier and a first peak amplifier; a second amplifier stage configured to amplify the intermediate signal into an output signal, wherein the second amplifier stage comprises a second main amplifier and a second peak amplifier; a first matching network configured to match an output impedance of the first main amplifier to an input impedance of the second main amplifier; as well as a second matching network configured to match the output impedance of the first peaking amplifier to the input impedance of the second peaking amplifier, wherein: The configuration of the first amplifier stage defines an impedance transformation ratio that minimizes an impedance mismatch between the first amplifier stage and the second amplifier stage; and The configuration of the first amplification stage specifies at least one of the following: at least one property of one or more transistors in the first amplifier stage; and At least one operating condition of the first amplification stage.

12. The system of claim 11, wherein: The at least one attribute includes at least one of the following: a type of the one or more transistors in the first amplifier stage; the material of the one or more transistors in the first amplifier stage; as well as a size of the one or more transistors; and The at least one operating condition includes at least one of the supply voltages used to operate the first amplification stage.

13. The system of claim 12, wherein the supply voltage is dependent on the material of the one or more transistors in the first amplification stage.

14. The system of claim 11, wherein the at least one operating condition of the first amplification stage includes a first supply voltage used to operate the first main amplifier and the first peak amplifier, and the first supply voltage is less than a second supply voltage used to operate the second main amplifier and the second peak amplifier.

15. The system of claim 11, wherein the at least one property comprises a size of the one or more transistors in the first amplifier stage, and the size of the one or more transistors in the first amplifier stage is smaller than a size of one or more transistors in the second amplifier stage.

16. The system of claim 11, wherein: The at least one property comprises a material of the one or more transistors in the first amplifier stage, and the material is one of gallium nitride GaN on silicon carbide SiC, GaN on silicon Si, gallium arsenide GaAs, silicon on insulator SOI, and silicon Si; and The second amplifier stage includes one or more transistors formed from one of GaN on SiC and GaN on Si.

17. The system of claim 11, wherein the configuration specifies the at least one property and the at least one operating condition so that the impedance transformation ratio approaches a value of 1.

18. A system comprising: antenna; a first amplifier stage configured to amplify an input signal into an intermediate signal; The second amplifier stage is configured as: amplifying the intermediate signal into an output signal; as well as providing the output signal to the antenna; as well as a matching network configured to match the output impedance of the first amplifier stage to the input impedance of the second amplifier stage, wherein: The configuration of the first amplification stage and the second amplification stage defines an impedance transformation ratio that minimizes an impedance mismatch between the output impedance of the first amplification stage and the input impedance of the second amplification stage; and The configuration specifies at least one of the following: at least one property of one or more transistors in the first amplifier stage; and At least one operating condition of the first amplifier stage and the second amplifier stage.

19. The system of claim 18, wherein: The at least one attribute includes at least one of the following: a type of the one or more transistors in the first amplifier stage; The material of the one or more transistors in the first amplifier stage; and a size of the one or more transistors; The at least one operating condition includes at least one of the following: a supply voltage used to operate the first amplifier stage; output power from the first amplifier stage; and The gain of the second amplifier stage.

20. The system of claim 18, wherein the at least one operating condition of the first amplifier stage comprises a first supply voltage used to operate the first amplifier stage, and the first supply voltage is less than a second supply voltage used to operate the second amplifier stage.

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