Power-on reset circuit and integral reset circuit

Abstract

The invention discloses a power-on reset circuit and an integral reset circuit, and relates to the field of reset circuits, and the power-on reset circuit is provided with an analog voltage input end and a digital voltage input end; the analog voltage input end of the power-on reset circuit is connected with analog voltage; the digital voltage input end of the power-on reset circuit is connected with digital voltage; when the analog voltage rises to a first preset voltage value, the digital voltage reaches a second preset voltage value, and the digital voltage is smaller than a third preset voltage value, the output end of the upper reset circuit outputs power-on reset voltage to carry out power-on reset on the digital circuit. The power-on reset operation is triggered when both the analog circuit and the digital circuit reach the working voltage for normal working, so that the digital circuit stably enters the working state, and the stability of the working state of the low-power-consumption electronic equipment is guaranteed.

Description

Technical Field

[0001] This application relates to the field of reset circuits, and in particular to a power-on reset circuit and an overall reset circuit. Background Art

[0002] In many low-power electronic devices that include analog circuits and digital circuits, there are two power supplies: an analog power supply and a digital power supply. In the related art, the power-on reset circuit only focuses on the power-on of the analog power supply and ignores the digital power supply. It may occur that the analog power supply meets the operating voltage for the normal operation of the analog circuit, but the digital power supply has not yet reached the operating voltage for the normal operation of the digital circuit, which may cause the voltage to be unstable when the digital circuit enters the operating state, thereby resulting in an unstable operating state of the low-power electronic device. Summary of the Invention

[0003] The purpose of this application is to provide a power-on reset circuit and an overall reset circuit, which can trigger the power-on reset operation when both the analog circuit and the digital circuit reach the operating voltage for normal operation, enable the digital circuit to stably enter the operating state, and ensure the stability of the operating state of the low-power electronic device.

[0004] To achieve the above purpose, this application provides the following solutions:

[0005] In the first aspect, this application provides a power-on reset circuit, which is applied to a low-power electronic device. The low-power electronic device includes an analog power supply, a digital power supply voltage circuit, an analog circuit, and a digital circuit. The analog power supply is respectively connected to the digital power supply voltage circuit and the analog circuit, and is used to generate an analog voltage; the digital power supply voltage circuit is used to generate a digital voltage. The power-on reset circuit is provided with an analog voltage input terminal and a digital voltage input terminal; the analog voltage input terminal of the power-on reset circuit is connected to the analog voltage; the digital voltage input terminal of the power-on reset circuit is connected to the digital voltage; the output terminal of the power-on reset circuit is connected to the digital circuit;

[0006] When the analog voltage rises to a first preset voltage value, the digital voltage reaches a second preset voltage value, and the digital voltage is less than a third preset voltage value, the output terminal of the upper-level reset circuit outputs a power-on reset voltage to perform a power-on reset on the digital circuit; wherein, the first preset voltage value is the operating voltage when the analog circuit operates normally, the second preset voltage value is the operating voltage when the digital circuit operates normally, and the third preset voltage value is the power-on reset trigger voltage of the upper-level reset circuit.

[0007] In the second aspect, this application provides an overall reset circuit, including: the above-mentioned power-on reset circuit, a power-down reset circuit, a NAND gate, and an inverter;

[0008] The digital voltage input terminal of the power-down reset circuit is connected to a digital voltage;

[0009] The output terminal of the power-down reset circuit is connected to the first input terminal of the NAND gate; the output terminal of the power-on reset circuit is connected to the second input terminal of the NAND gate; the output terminal of the NAND gate is connected to the input terminal of the inverter;

[0010] When the analog voltage rises to a first preset voltage value, the digital voltage reaches a second preset voltage value, and the digital voltage is less than a third preset voltage value, the output terminal of the inverter outputs a power-on reset voltage to perform a power-on reset on the digital circuit;

[0011] When the digital voltage drops out of power and the digital voltage drops to a fourth preset voltage value, the output terminal of the inverter outputs a power-down reset voltage to perform a power-down reset on the digital circuit; wherein, the fourth preset voltage value is greater than the second preset voltage value.

[0012] According to the specific embodiments provided by the present application, the present application discloses the following technical effects:

[0013] The present application provides a power-on reset circuit and an overall reset circuit. The power-on reset circuit is simultaneously provided with an analog voltage input terminal and a digital voltage input terminal. The analog voltage input terminal is connected to an analog voltage, and the digital voltage input terminal is connected to a digital voltage. When the analog voltage rises to a first preset voltage value and the digital voltage reaches a second preset voltage value, the output terminal of the upper-level reset circuit outputs a power-on reset voltage to act on the digital circuit to perform a power-on reset on the digital circuit, so that the digital circuit has a stable operating voltage when entering the working state; when performing the upper-level power-on operation, the analog voltage has reached the operating voltage when the analog circuit is working normally, and the digital voltage has also reached the operating voltage when the digital circuit is working normally. Therefore, after performing the upper-level power-on operation, both the digital circuit and the analog circuit enter a stable working state, avoiding performing a power-on reset operation when only the analog voltage meets the operating voltage of the analog circuit working normally while the digital voltage has not reached the operating voltage of the digital circuit working normally, resulting in the digital circuit being unable to work stably, thereby causing the working state of the low-power electronic device to be unstable. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0015] Figure 1 It is a schematic diagram of the connection relationship of a power-on reset circuit in an embodiment of the present application;

[0016] Figure 2 The structural diagram of a power-on reset circuit provided by an embodiment of the present application;

[0017] Figure 3 The schematic diagram of the functional modules of an overall reset circuit provided by an embodiment of the present application;

[0018] Figure 4 The structural diagram of a startup circuit and a self-biased current generation circuit provided by an embodiment of the present application;

[0019] Figure 5 The structural diagram of a second comparator and a second inverter group provided by an embodiment of the present application;

[0020] Figure 6 The waveform schematic diagram of the simulation result of the overall reset circuit provided by an embodiment of the present application. Detailed implementation manners

[0021] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0022] To make the objectives, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0023] A power-on reset circuit provided by an embodiment of the present application is applied to low-power electronic devices, such as Figure 1 As shown, the low-power electronic device includes an analog power supply 1, a digital power supply voltage circuit 2, an analog circuit 3, and a digital circuit 4. The analog power supply 1 is respectively connected to the digital power supply voltage circuit 2 and the analog circuit 3. The analog power supply 1 is used to generate an analog voltage VDD; the digital power supply voltage circuit 2 is used to generate a digital voltage VDDD. The power-on reset circuit 5 is provided with an analog voltage input terminal and a digital voltage input terminal. The analog voltage input terminal of the power-on reset circuit 5 is connected to the analog voltage VDD; the digital voltage input terminal of the power-on reset circuit 5 is connected to the digital voltage VDDD; the output terminal of the power-on reset circuit is connected to the digital circuit 4.

[0024] When the analog voltage VDD rises to the first preset voltage value and the digital voltage VDDD reaches the second preset voltage value, the output terminal of the upper power-on reset circuit 5 outputs a power-on reset voltage to perform a power-on reset on the digital circuit 4; wherein, the first preset voltage value is the operating voltage when the analog circuit 3 operates normally, and the second preset voltage value is the operating voltage when the digital circuit 4 operates normally.

[0025] In this embodiment, the power-on reset circuit 5 takes into account the analog voltage VDD and the digital voltage VDDD, and performs a power-on reset only when the analog voltage VDD reaches the operating voltage when the analog circuit operates normally and the digital voltage VDDD reaches the operating voltage when the digital circuit operates normally, enabling the digital circuit 4 to stably enter the operating state and ensuring the stability of the operating state of the low-power electronic device.

[0026] In an exemplary embodiment, as Figure 2 shown, the power-on reset circuit 5 specifically includes: a bias voltage generation circuit 51, an upper power-on trigger voltage generation circuit 52, a first comparator 53, and a first inverter group 54.

[0027] The analog voltage input terminal of the bias voltage generation circuit 51, the input terminal of the upper power-on trigger voltage generation circuit 52, and the first terminal of the first comparator 53 are the analog voltage input terminals of the power-on reset circuit 5; the input terminal of the upper power-on trigger voltage generation circuit 52 and the third terminal of the first comparator 53 are the digital voltage input terminals of the power-on reset circuit 5; the output terminal of the first inverter group 54 is the output terminal of the power-on reset circuit 5. The external bias current input terminal of the bias voltage generation circuit 51 is connected to an external bias current IB. Specifically, the bias current IB is given by a bias current generation circuit in the bandgap reference circuit of the low-power electronic device. The first voltage output terminal Vbp1 of the bias voltage generation circuit 51 is connected to the second terminal of the first comparator 53; the second voltage output terminal Vbn1 of the bias voltage generation circuit 51 is connected to the fifth terminal of the first comparator 53. As Figure 2 shown, the output terminal of the upper power-on trigger voltage generation circuit 52 is the node B terminal, and the node B terminal is connected to the fourth terminal of the first comparator 53; the sixth terminal of the first comparator 53 is connected to the input terminal of the first inverter group 54. Specifically, the first inverter group 54 includes three inverters, namely a first inverter A11, a second inverter A12, and a third inverter A13. The input terminal of the first inverter A11 is the input terminal of the first inverter group 54. The output terminal of the first inverter A11 is connected to the input terminal of the second inverter A12. The output terminal of the second inverter A12 is connected to the input terminal of the third inverter A13. The output terminal of the third inverter A13 is the output terminal of the first inverter group 54.

[0028] In an exemplary embodiment, the bias voltage generation circuit 51 specifically includes: a first P-type field effect transistor MP1, a second P-type field effect transistor MP2, and a first N-type field effect transistor MN1.

[0029] The source electrodes of the first P-type field effect transistor MP1 and the second P-type field effect transistor MP2 are the analog voltage input terminals of the bias voltage generation circuit 51; the gate electrode of the first P-type field effect transistor MP1, the drain electrode of the first P-type field effect transistor MP1, and the gate electrode of the second P-type field effect transistor MP2 are connected to an external bias current IB; the connection node between the drain electrode of the first P-type field effect transistor MP1 and the gate electrode of the second P-type field effect transistor MP2 is the first voltage output terminal Vbp1 of the bias voltage generation circuit 51.

[0030] The drain electrode of the second P-type field effect transistor MP2 is respectively connected to the drain electrode of the first N-type field effect transistor MN1 and the gate electrode of the first N-type field effect transistor MN1. The connection node between the drain electrode of the second P-type field effect transistor MP1 and the drain electrode of the first N-type field effect transistor MN1 and the gate electrode of the first N-type field effect transistor MN1 is the second voltage output terminal Vbn1 of the bias voltage generation circuit 51. The source electrode of the first N-type field effect transistor MN1 is grounded.

[0031] The upper power-on trigger voltage generation circuit 52 specifically includes: a third P-type field effect transistor MP3, a second N-type field effect transistor MN2, and a third N-type field effect transistor MN3.

[0032] The source electrode of the third P-type field effect transistor MP3 is the input terminal of the upper power-on trigger voltage generation circuit 52; the gate electrode of the third P-type field effect transistor MP3 is respectively connected to the drain electrode of the third P-type field effect transistor MP3, the drain electrode of the second N-type field effect transistor MN2, and the gate electrode of the third N-type field effect transistor MN3; the connection node between the gate electrode of the third P-type field effect transistor MP3, the drain electrode of the third P-type field effect transistor MP3, the drain electrode of the second N-type field effect transistor MN2, and the gate electrode of the third N-type field effect transistor MN3 is the output terminal of the upper power-on trigger voltage generation circuit 52, that is, the node B terminal.

[0033] The gate electrode of the second N-type field effect transistor MN2 is connected to the digital voltage VDDD; the source electrode of the second N-type field effect transistor MN2, the source electrode of the third N-type field effect transistor MN3, and the drain electrode of the third N-type field effect transistor MN3 are all grounded.

[0034] The first comparator 53 specifically includes: a fourth P-type field effect transistor MP4, a fifth P-type field effect transistor MP5, a sixth P-type field effect transistor MP6, a seventh P-type field effect transistor MP7, an eighth P-type field effect transistor MP8, a fourth N-type field effect transistor MN4, a fifth N-type field effect transistor MN5, a sixth N-type field effect transistor MN6, a seventh N-type field effect transistor MN7, an eighth N-type field effect transistor MN8, a ninth N-type field effect transistor MN9, and a tenth N-type field effect transistor MN10.

[0035] The source electrodes of the fourth P-type field effect transistor MP4, the seventh P-type field effect transistor MP7, and the eighth P-type field effect transistor MP8 are the first terminal of the first comparator 53; the gate electrode of the fourth P-type field effect transistor MP4 is the second terminal of the first comparator 53; the gate electrode of the sixth P-type field effect transistor MP6 is the third terminal of the first comparator 53; the gate electrode of the fifth P-type field effect transistor MP5 is the fourth terminal of the first comparator 53; the gate electrode of the tenth N-type field effect transistor MN10 is the fifth terminal of the first comparator 53; the gate electrodes of the eighth P-type field effect transistor MP8 and the ninth N-type field effect transistor MN9 are the sixth terminal of the first comparator 53.

[0036] The drain electrode of the fourth P-type field effect transistor MP4 is respectively connected to the source electrodes of the fifth P-type field effect transistor MP5 and the sixth P-type field effect transistor MP6.

[0037] The drain electrode of the fifth P-type field effect transistor MP5 is respectively connected to the gate electrode of the eighth N-type field effect transistor MN8, the gate electrode of the fourth N-type field effect transistor MN4, the drain electrode of the fourth N-type field effect transistor MN4, the drain electrode of the sixth N-type field effect transistor MN6, and the gate electrode of the seventh N-type field effect transistor MN7; the drain electrode of the sixth P-type field effect transistor MP6 is respectively connected to the gate electrode of the ninth N-type field effect transistor MN9, the gate electrode of the fifth N-type field effect transistor MN5, the drain electrode of the fifth N-type field effect transistor MN5, the gate electrode of the sixth N-type field effect transistor MN6, and the drain electrode of the seventh N-type field effect transistor MN7.

[0038] The drain electrode of the seventh P-type field effect transistor MP7 is respectively connected to the gate electrode of the seventh P-type field effect transistor MP7, the gate electrode of the eighth P-type field effect transistor MP8, and the drain electrode of the eighth N-type field effect transistor MN8; the source electrode of the ninth N-type field effect transistor MN9 is respectively connected to the source electrode of the eighth N-type field effect transistor MN8 and the drain electrode of the tenth N-type field effect transistor MN10;

[0039] The sources of the fourth N-type field effect transistor MN4, the sixth N-type field effect transistor MN6, the seventh N-type field effect transistor MN7, the fifth N-type field effect transistor MN5, and the tenth N-type field effect transistor MN10 are all grounded.

[0040] In this embodiment, the bias voltage generation circuit 51 is used to provide a bias voltage for the first comparator 53. The bias voltages are the voltages of nodes Vbp1 and Vbn1. The upper power-on reset trigger voltage generation circuit 52 is used to generate the power-on reset trigger voltage for the upper power-on reset circuit 5. The voltage at the B terminal of the node is the power-on reset trigger voltage. When VDD is rising, only when VDDD also rises and exceeds the turn-on voltage V of the second N-type field effect transistor MN2 thn，MN2 (VDDD > V thn，MN2 ), the power-on reset circuit 5 outputs a power-on reset voltage, thereby excluding the situation where VDD rises to the operating voltage when the analog circuit is working properly, but VDDD does not rise to the operating voltage when the digital circuit is working properly. Specifically, V thn，MN2 is the turn-on voltage of MN2, and V thn，MN2 is a fixed value. For example, in this embodiment, the turn-on voltage of the second N-type field effect transistor MN2 used is about 0.7V. Only when the digital voltage is greater than 0.7V, the second N-type field effect transistor MN2 will turn on, and the power-on reset circuit 5 will work. When the power-on reset circuit 5 works, it also ensures that the digital voltage VDDD must be greater than 0.7V.

[0041] By adjusting the capacitance of the MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) capacitor composed of the third N-type field effect transistor MN3, the threshold of the rising voltage can be adjusted. The threshold of the rising voltage is the value that makes the digital voltage VDDD equal to the voltage at the B terminal of the node.

[0042] The voltage at the B terminal of the node and VDDD are compared by the first comparator 53. The comparison process is as follows: When the voltage at the B terminal of the node > VDDD, MP5 turns off and MP6 turns on. The node N is at a low level, and the node M is charged through the path of MP4, MP6, and MN5. Through the positive feedback circuit composed of MN6 and MN7, the voltages of points N and M finally reach stability. Subsequently, the comparison result is amplified by the amplifier circuit composed of MP7, MP8, MN8, MN9, and MN10, and buffered and inverted by the first inverter group 54 to obtain the power-on reset voltage. When the voltage at the B terminal of the node > VDDD, the output of the first comparator is at a low level, otherwise, it is at a high level. Therefore, when the voltage at the B terminal of the node > VDDD, the power-on reset operation is triggered to achieve the effect of power-on reset.

[0043] In an exemplary embodiment, an overall reset circuit is provided, as Figure 3 shown. The overall reset circuit includes a power-on reset circuit 5, a power-off reset circuit 6, a NAND gate 7, and an inverter 8.

[0044] The digital voltage input terminal of the power-off reset circuit 6 is connected to a digital voltage VDDD; the output terminal of the power-off reset circuit 6 is connected to the first input terminal of the NAND gate 7; the output terminal of the power-on reset circuit 5 is connected to the second input terminal of the NAND gate 7; the output terminal of the NAND gate 7 is connected to the input terminal of the inverter 8.

[0045] When the analog voltage VDD rises to a first preset voltage value, the digital voltage VDDD reaches a second preset voltage value, and the digital voltage is less than a third preset value, the output terminal of the inverter 8 outputs a power-on reset voltage to perform a power-on reset on the digital circuit 4.

[0046] When the digital voltage VDDD loses power and the digital voltage VDDD drops to a fourth preset voltage value, the output terminal of the inverter 8 outputs a power-off reset voltage to perform a power-off reset on the digital circuit 4; wherein, the fourth preset voltage value is greater than the second preset voltage value.

[0047] In this embodiment, the overall reset circuit has both a power-on reset function and a power-off reset function, and can ensure the stability of low-power electronic devices during power-on or power-off.

[0048] In an exemplary embodiment, the power-off reset circuit 6 specifically includes: a startup circuit 61, a self-biased current generation circuit 62, a second comparator 63, and a second inverter group 64.

[0049] The first startup terminal of the startup circuit 61, the first terminal of the self-biased current generation circuit 62, and the first terminal of the second comparator 63 are the digital voltage input terminals of the power-off reset circuit 6; the output terminal of the second inverter group 64 is the output terminal of the power-off reset circuit 6. Specifically, the second inverter group 64 includes three inverters, namely a fourth inverter A14, a fifth inverter A15, and a sixth inverter A16. The input terminal of the fourth inverter A14 is the input terminal of the second inverter group 64. The output terminal of the fourth inverter A14 is connected to the input terminal of the fifth inverter A15. The output terminal of the fifth inverter A15 is connected to the input terminal of the sixth inverter A16. The output terminal of the sixth inverter A16 is the output terminal of the second inverter group 64.

[0050] The second startup terminal of the startup circuit 61 is respectively connected to the second terminal Vbn of the self - bias current generation circuit 62, the second terminal of the second comparator 63, the third terminal of the second comparator 63, and the fifth terminal of the second comparator 63; the third startup terminal of the startup circuit 61 is respectively connected to the third terminal Vbp of the self - bias current generation circuit 62 and the fourth terminal of the second comparator 63.

[0051] The fourth startup terminal of the startup circuit 61, the fourth terminal of the self - bias current generation circuit 62, and the seventh terminal of the second comparator 63 are all grounded. The sixth terminal of the second comparator 63 is connected to the input terminal of the second inverter group 64.

[0052] As Figure 4 shown, the startup circuit 61 specifically includes: a field - effect transistor group, an eleventh N - type field - effect transistor MN11, and a twelfth N - type field - effect transistor MN12.

[0053] The input terminal of the field - effect transistor group is the first startup terminal of the startup circuit 61; the gate of the eleventh N - type field - effect transistor MN11 is the second startup terminal of the startup circuit 61; the drain of the twelfth N - type field - effect transistor MN12 is the third startup terminal of the startup circuit 61; the source of the eleventh N - type field - effect transistor MN11, the source of the twelfth N - type field - effect transistor MN12, and the control terminal of the field - effect transistor group are the fourth startup terminal of the startup circuit 61.

[0054] The output terminal of the field - effect transistor group is respectively connected to the drain of the eleventh N - type field - effect transistor MN11 and the gate of the twelfth N - type field - effect transistor MN12.

[0055] The field - effect transistor group includes a plurality of P - type field - effect transistors, namely, an eighteenth P - type field - effect transistor MP18 to a twenty - ninth P - type field - effect transistor MP29.

[0056] The source of the eighteenth P - type field - effect transistor MP18 is the input terminal of the field - effect transistor group, the drain of the twenty - ninth P - type field - effect transistor MP29 is the output terminal of the field - effect transistor group, and the gates of the eighteenth P - type field - effect transistor MP18, the nineteenth P - type field - effect transistor MP19, the twentieth P - type field - effect transistor MP20, the twenty - first P - type field - effect transistor MP21, the twenty - second P - type field - effect transistor MP22, the twenty - third P - type field - effect transistor MP23, the twenty - fourth P - type field - effect transistor MP24, the twenty - fifth P - type field - effect transistor MP25, the twenty - sixth P - type field - effect transistor MP26, the twenty - seventh P - type field - effect transistor MP27, the twenty - eighth P - type field - effect transistor MP28, and the twenty - ninth P - type field - effect transistor MP29 are the control terminals of the field - effect transistor group.

[0057] The gates of the eighteenth P-type field effect transistor MP18 are respectively connected to the gates of the nineteenth P-type field effect transistor MP19, the gates of the twentieth P-type field effect transistor MP20, the gates of the twenty-first P-type field effect transistor MP21, the gates of the twenty-second P-type field effect transistor MP22, the gates of the twenty-third P-type field effect transistor MP23, the gates of the twenty-fourth P-type field effect transistor MP24, the gates of the twenty-fifth P-type field effect transistor MP25, the gates of the twenty-sixth P-type field effect transistor MP26, the gates of the twenty-seventh P-type field effect transistor MP27, the gates of the twenty-eighth P-type field effect transistor MP28, and the gates of the twenty-ninth P-type field effect transistor MP29.

[0058] The drain of the eighteenth P-type field effect transistor MP18 is connected to the source of the nineteenth P-type field effect transistor MP19, the drain of the nineteenth P-type field effect transistor MP19 is connected to the source of the twentieth P-type field effect transistor MP20, the drain of the twentieth P-type field effect transistor MP20 is connected to the source of the twenty-first P-type field effect transistor MP21, the drain of the twenty-first P-type field effect transistor MP21 is connected to the source of the twenty-second P-type field effect transistor MP22, the drain of the twenty-second P-type field effect transistor MP22 is connected to the source of the twenty-third P-type field effect transistor MP23, the drain of the twenty-third P-type field effect transistor MP23 is connected to the source of the twenty-fourth P-type field effect transistor MP24, the drain of the twenty-fourth P-type field effect transistor MP24 is connected to the source of the twenty-fifth P-type field effect transistor MP25, the drain of the twenty-fifth P-type field effect transistor MP25 is connected to the source of the twenty-sixth P-type field effect transistor MP26, the drain of the twenty-sixth P-type field effect transistor MP26 is connected to the source of the twenty-seventh P-type field effect transistor MP27, the drain of the twenty-seventh P-type field effect transistor MP27 is connected to the source of the twenty-eighth P-type field effect transistor MP28, and the drain of the twenty-eighth P-type field effect transistor MP28 is connected to the source of the twenty-ninth P-type field effect transistor MP29.

[0059] The self-biased current generating circuit 62 specifically includes: a thirteenth N-type field effect transistor MN13, a fourteenth N-type field effect transistor MN14, a fifteenth N-type field effect transistor MN15, a ninth P-type field effect transistor MP9, a tenth P-type field effect transistor MP10, an eleventh P-type field effect transistor MP11, and a resistor R.

[0060] The source of the ninth P-type field effect transistor MP9, the source of the tenth P-type field effect transistor MP10, the drain of the eleventh P-type field effect transistor MP11, and the source of the eleventh P-type field effect transistor MP11 are the first end of the self-biased current generating circuit 62.

[0061] The drain of the ninth P-type field effect transistor MP9 is respectively connected to the gate of the thirteenth N-type field effect transistor MN13, the drain of the thirteenth N-type field effect transistor MN13, the gate of the fifteenth N-type field effect transistor MN15, and the gate of the fourteenth N-type field effect transistor MN14; the connection node of the drain of the ninth P-type field effect transistor MP9, the gate of the thirteenth N-type field effect transistor MN13, the drain of the thirteenth N-type field effect transistor MN13, the gate of the fifteenth N-type field effect transistor MN15, and the gate of the fourteenth N-type field effect transistor MN14 is the second terminal Vbn of the self-biased current generation circuit 62.

[0062] The gate of the ninth P-type field effect transistor MP9 is respectively connected to the gate of the eleventh P-type field effect transistor MP11, the gate of the tenth P-type field effect transistor MP10, the drain of the tenth P-type field effect transistor MP10, and the drain of the fourteenth N-type field effect transistor MN14; the connection node of the gate of the ninth P-type field effect transistor MP9, the gate of the eleventh P-type field effect transistor MP11, the gate of the tenth P-type field effect transistor MP10, the drain of the tenth P-type field effect transistor MP10, and the drain of the fourteenth N-type field effect transistor MN14 is the third terminal Vbp of the self-biased current generation circuit 62.

[0063] The source of the fourteenth N-type field effect transistor MN14 is connected to one end of the resistor R. The drain of the fifteenth N-type field effect transistor MN15, the source of the fifteenth N-type field effect transistor MN15, the source of the thirteenth N-type field effect transistor MN13, and the other end of the resistor R are all grounded.

[0064] As Figure 5 shown, the second comparator 63 specifically includes: the twelfth P-type field effect transistor MP12, the thirteenth P-type field effect transistor MP13, the fourteenth P-type field effect transistor MP14, the fifteenth P-type field effect transistor MP15, the sixteenth P-type field effect transistor MP16, the seventeenth P-type field effect transistor MP17, the sixteenth N-type field effect transistor MN16, the seventeenth N-type field effect transistor MN17, the eighteenth N-type field effect transistor MN18, the nineteenth N-type field effect transistor MN19, the twentieth N-type field effect transistor MN20, the twenty-first N-type field effect transistor MN21, the twenty-second N-type field effect transistor MN22, and the twenty-third N-type field effect transistor MN23.

[0065] The sources of the twelfth P-type field effect transistor MP12, the thirteenth P-type field effect transistor MP13, the sixteenth P-type field effect transistor MP16, and the seventeenth P-type field effect transistor MP17 are the first terminal of the second comparator 63; the gate of the sixteenth N-type field effect transistor MN16 is the second terminal of the second comparator 63; the gate of the fifteenth P-type field effect transistor MP15 is the third terminal of the second comparator 63; the gate of the fourteenth P-type field effect transistor MP14 is the fourth terminal of the second comparator 63; the gate of the twenty-third N-type field effect transistor MN23 is the fifth terminal of the second comparator 63; the drains of the seventeenth P-type field effect transistor MP17 and the twenty-second N-type field effect transistor MN22 are the sixth terminal of the second comparator 63.

[0066] The gate of the twelfth P-type field effect transistor MP12 is connected to the drain of the twelfth P-type field effect transistor MP12, the gate of the thirteenth P-type field effect transistor MP13, and the drain of the sixteenth N-type field effect transistor MN16 respectively.

[0067] The drain of the thirteenth P-type field effect transistor MP13 is connected to the source of the fourteenth P-type field effect transistor MP14 and the source of the fifteenth P-type field effect transistor MP15 respectively; the drain of the fourteenth P-type field effect transistor MP14 is connected to the gate of the twenty-first N-type field effect transistor MN21, the drain of the seventeenth N-type field effect transistor MN17, the gate of the seventeenth N-type field effect transistor MN17, the drain of the nineteenth N-type field effect transistor MN19, and the gate of the twentieth N-type field effect transistor MN20 respectively.

[0068] The drain of the fifteenth P-type field effect transistor MP15 is connected to the gate of the twenty-second N-type field effect transistor MN22, the gate of the eighteenth N-type field effect transistor MN18, the drain of the eighteenth N-type field effect transistor MN18, the gate of the nineteenth N-type field effect transistor MN19, and the drain of the twentieth N-type field effect transistor MN20 respectively.

[0069] The gate of the seventeenth P-type field effect transistor MP17 is connected to the gate of the sixteenth P-type field effect transistor MP16, the drain of the sixteenth P-type field effect transistor MP16, and the drain of the twenty-first N-type field effect transistor respectively.

[0070] The source of the twenty-second N-type field effect transistor MN22 is connected to the source of the twenty-first N-type field effect transistor MN21 and the drain of the twenty-third N-type field effect transistor MN23 respectively.

[0071] The sources of the sixteenth N-type field effect transistor MN16, the seventeenth N-type field effect transistor MN17, the nineteenth N-type field effect transistor MN19, the twentieth N-type field effect transistor MN20, the eighteenth N-type field effect transistor MN18, and the twenty-third N-type field effect transistor MN23 are all grounded.

[0072] The bias current I of the self-biased current generation circuit 62 in this embodiment bias is calculated by the formula:

[0073] I bias =(V GS13 -V GS14 )÷R;

[0074] where V GS13 , V GS14 are the gate-source voltage differences of MN13 and MN14.

[0075] The startup circuit 61 can enable the self-biased current generation circuit 62 to eliminate the degeneracy point (the bias current of the self-biased circuit is 0). Specifically, when the digital power supply VDDD is powered on and the startup circuit 61 starts to work, point A is at a high level. At this time, the MN12 transistor conducts, pulling down the voltage of the Vbp node in the self-biased current generation circuit 62 to generate a ground path. When the startup circuit 61 works normally, the voltage of the Vbn node will turn on MN11, thereby turning off MN12, and the startup circuit 61 is turned off, finally achieving the function of eliminating the degeneracy point. The two MOS transistors MN15 and MP11 in the self-biased current generation circuit 62 act as MOS capacitors, causing the voltages of the Vbn node and the Vbp node to slowly drop during the process of the digital voltage VDDD decreasing.

[0076] The voltages of the Vbn node and the Vbp node are compared by the second comparator 63. The comparison process is as follows: when the voltage of the Vbp node > the voltage of the Vbn node, MP14 is turned off and MP15 is turned on, and node X is at a low level. Node Y is charged through the path of MP15 and MN18. Through the positive feedback circuit composed of MN19 and MN20, the voltages of points X and Y finally reach stability. Subsequently, the result of the comparator is amplified by the amplifier circuit composed of MP16, MP17, MN21, MN22, and MN23, buffered and inverted by the second inverter group 63, and the power-down reset voltage is output to achieve the power-down reset function.

[0077] When the voltage of the Vbp node > the voltage of the Vbn node, the output of the second comparator 62 is at a low level; conversely, it is at a high level. After being inverted by the second inverter group 63, finally, when the voltage of the Vbn node > the voltage of the Vbp node, the power-down reset effect is achieved; among them, the threshold of the power-down reset can be adjusted by adjusting the sizes of the two MOS capacitors MN15 and MP11.

[0078] The overall reset circuit has both power-on reset function and power-down reset function, and the overall simulation result is as Figure 4 shown. The power-down reset circuit 6 meets the condition: it is triggered when the voltage of the Vbp node < the voltage of the Vbn node; the power-on reset circuit 5 meets the condition: VDDD meets the operating voltage when the digital circuit works normally, and it is triggered when the voltage at the B end of the node > VDDD.

[0079] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0080] In this article, specific examples are used to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A power-on reset circuit, applied to low-power electronic equipment, the low-power electronic equipment comprising an analog power supply, a digital power supply voltage circuit, an analog circuit and a digital circuit, the analog power supply being connected to the digital power supply voltage circuit and the analog circuit, respectively, for generating an analog voltage; the digital power supply voltage circuit being used to generate a digital voltage, characterized in that: The power-on reset circuit is provided with an analog voltage input terminal and a digital voltage input terminal; the analog voltage input terminal of the power-on reset circuit is connected to the analog voltage; the digital voltage input terminal of the power-on reset circuit is connected to the digital voltage; the output terminal of the power-on reset circuit is connected to the digital circuit; When the analog voltage rises to a first preset voltage value, the digital voltage reaches a second preset voltage value, and the digital voltage is less than a third preset voltage value, the output end of the upper reset circuit outputs a power-on reset voltage to power-on reset the digital circuit; wherein the first preset voltage value is the operating voltage when the analog circuit works normally, the second preset voltage value is the operating voltage when the digital circuit works normally, and the third preset voltage value is the power-on reset trigger voltage of the upper reset circuit.

2. The power-on reset circuit according to claim 1, characterized in that: The power-on reset circuit specifically includes: a bias voltage generating circuit, an upper power-on trigger voltage generating circuit, a first comparator and a first inverter group; The analog voltage input terminal of the bias voltage generating circuit, the input terminal of the upper power-on trigger voltage generating circuit and the first terminal of the first comparator are the analog voltage input terminals of the power-on reset circuit; the input terminal of the upper power-on trigger voltage generating circuit and the third terminal of the first comparator are the digital voltage input terminals of the power-on reset circuit; the output terminal of the first inverter group is the output terminal of the power-on reset circuit; The external bias current input terminal of the bias voltage generating circuit is connected to the external bias current; the first voltage output terminal of the bias voltage generating circuit is connected to the second terminal of the first comparator; the second voltage output terminal of the bias voltage generating circuit is connected to the fifth terminal of the first comparator; The output end of the upper power recovery trigger voltage generating circuit is connected to the fourth end of the first comparator; the sixth end of the first comparator is connected to the input end of the first inverter group.

3. The power-on reset circuit according to claim 2, characterized in that: The bias voltage generating circuit specifically includes: a first P-type field effect transistor, a second P-type field effect transistor and a first N-type field effect transistor; The source of the first P-type field effect transistor and the source of the second P-type field effect transistor are analog voltage input terminals of the bias voltage generating circuit; The gate of the first P-type field effect transistor, the drain of the first P-type field effect transistor, and the gate of the second P-type field effect transistor are connected to an external bias current; A connection node between the drain of the first P-type field effect transistor and the gate of the second P-type field effect transistor is a first voltage output terminal of the bias voltage generating circuit; The drain of the second P-type field effect transistor is respectively connected to the drain of the first N-type field effect transistor and the gate of the first N-type field effect transistor, and the connection node between the drain of the second P-type field effect transistor and the drain of the first N-type field effect transistor and the gate of the first N-type field effect transistor is the second voltage output end of the bias voltage generating circuit; the source of the first N-type field effect transistor is grounded.

4. The power-on reset circuit according to claim 2, characterized in that: The upper power recovery trigger voltage generating circuit specifically includes: a third P-type field effect transistor, a second N-type field effect transistor and a third N-type field effect transistor; The source of the third P-type field effect transistor is the input end of the upper power recovery trigger voltage generating circuit; the gate of the third P-type field effect transistor is respectively connected to the drain of the third P-type field effect transistor, the drain of the second N-type field effect transistor and the gate of the third N-type field effect transistor; the connection node of the gate of the third P-type field effect transistor, the drain of the third P-type field effect transistor, the drain of the second N-type field effect transistor and the gate of the third N-type field effect transistor is the output end of the upper power recovery trigger voltage generating circuit; The gate of the second N-type field effect transistor is connected to the digital voltage; The source of the second N-type field effect transistor, the source of the third N-type field effect transistor, and the drain of the third N-type field effect transistor are all grounded.

5. The power-on reset circuit according to claim 2, characterized in that: The first comparator specifically includes: a fourth P-type field effect transistor, a fifth P-type field effect transistor, a sixth P-type field effect transistor, a seventh P-type field effect transistor, an eighth P-type field effect transistor, a fourth N-type field effect transistor, a fifth N-type field effect transistor, a sixth N-type field effect transistor, a seventh N-type field effect transistor, an eighth N-type field effect transistor, a ninth N-type field effect transistor and a tenth N-type field effect transistor; The source of the fourth P-type field effect transistor, the source of the seventh P-type field effect transistor and the source of the eighth P-type field effect transistor are the first end of the first comparator; the gate of the fourth P-type field effect transistor is the second end of the first comparator; the gate of the sixth P-type field effect transistor is the third end of the first comparator; the gate of the fifth P-type field effect transistor is the fourth end of the first comparator; the gate of the tenth N-type field effect transistor is the fifth end of the first comparator; the gate of the eighth P-type field effect transistor and the gate of the ninth N-type field effect transistor are the sixth end of the first comparator; The drain of the fourth P-type field effect transistor is connected to the source of the fifth P-type field effect transistor and the source of the sixth P-type field effect transistor respectively; The drain of the fifth P-type field effect transistor is respectively connected to the gate of the eighth N-type field effect transistor, the gate of the fourth N-type field effect transistor, the drain of the fourth N-type field effect transistor, the drain of the sixth N-type field effect transistor and the gate of the seventh N-type field effect transistor; the drain of the sixth P-type field effect transistor is respectively connected to the gate of the ninth N-type field effect transistor, the gate of the fifth N-type field effect transistor, the drain of the fifth N-type field effect transistor, the gate of the sixth N-type field effect transistor and the drain of the seventh N-type field effect transistor; The drain of the seventh P-type field effect transistor is respectively connected to the gate of the seventh P-type field effect transistor, the gate of the eighth P-type field effect transistor and the drain of the eighth N-type field effect transistor; the source of the ninth N-type field effect transistor is respectively connected to the source of the eighth N-type field effect transistor and the drain of the tenth N-type field effect transistor; The source of the fourth N-type field effect transistor, the source of the sixth N-type field effect transistor, the source of the seventh N-type field effect transistor, the source of the fifth N-type field effect transistor and the source of the tenth N-type field effect transistor are all grounded.

6. An overall reset circuit, characterized in that: The method comprises the power-on reset circuit, the power-off reset circuit, the NAND gate and the inverter according to any one of claims 1 to 5; The digital voltage input terminal of the power-off reset circuit is connected to the digital voltage; The output end of the power-off reset circuit is connected to the first input end of the NAND gate; the output end of the power-on reset circuit is connected to the second input end of the NAND gate; the output end of the NAND gate is connected to the input end of the inverter; When the analog voltage rises to a first preset voltage value, the digital voltage reaches a second preset voltage value, and the digital voltage is less than a third preset voltage value, the output end of the inverter outputs a power-on reset voltage to power-on reset the digital circuit; When the digital voltage is powered off and drops to a fourth preset voltage value, the output end of the inverter outputs a power-off reset voltage to reset the digital circuit; wherein the fourth preset voltage value is greater than the second preset voltage value.

7. The overall reset circuit according to claim 6, characterized in that: The power-off reset circuit specifically includes: a startup circuit, a self-bias current generating circuit, a second comparator and a second inverter group; The first start-up terminal of the start-up circuit, the first terminal of the self-bias current generating circuit and the first terminal of the second comparator are the digital voltage input terminals of the power-off reset circuit; the output terminal of the second inverter group is the output terminal of the power-off reset circuit; The second startup terminal of the startup circuit is respectively connected to the second terminal of the self-bias current generating circuit, the second terminal of the second comparator, the third terminal of the second comparator and the fifth terminal of the second comparator; the third startup terminal of the startup circuit is respectively connected to the third terminal of the self-bias current generating circuit and the fourth terminal of the second comparator; The fourth start-up terminal of the start-up circuit, the fourth terminal of the self-bias current generating circuit and the seventh terminal of the second comparator are all grounded; The sixth terminal of the second comparator is connected to the input terminal of the second inverter group.

8. The overall reset circuit according to claim 7, characterized in that: The startup circuit specifically includes: a field effect tube group, an eleventh N-type field effect tube and a twelfth N-type field effect tube; The input end of the field effect tube group is the first start-up end of the start-up circuit; the gate of the eleventh N-type field effect is the second start-up end of the start-up circuit; the drain of the twelfth N-type field effect is the third start-up end of the start-up circuit; the source of the eleventh N-type field effect tube, the source of the twelfth N-type field effect tube and the control end of the field effect tube group are the fourth start-up end of the start-up circuit; The output end of the field effect tube group is respectively connected to the drain of the eleventh N-type field effect tube and the gate of the twelfth N-type field effect tube.

9. The overall reset circuit according to claim 7, characterized in that: The self-bias current generating circuit specifically includes: a thirteenth N-type field effect transistor, a fourteenth N-type field effect transistor, a fifteenth N-type field effect transistor, a ninth P-type field effect transistor, a tenth P-type field effect transistor, an eleventh P-type field effect transistor and a resistor; The source of the ninth P-type field effect transistor, the source of the tenth P-type field effect transistor, the drain of the eleventh P-type field effect transistor and the source of the eleventh P-type field effect transistor are the first end of the self-bias current generating circuit; The drain of the ninth P-type field effect transistor is respectively connected to the gate of the thirteenth N-type field effect transistor, the drain of the thirteenth N-type field effect transistor, the gate of the fifteenth N-type field effect transistor, and the gate of the fourteenth N-type field effect transistor; the connection node of the drain of the ninth P-type field effect transistor, the gate of the thirteenth N-type field effect transistor, the drain of the thirteenth N-type field effect transistor, the gate of the fifteenth N-type field effect transistor, and the gate of the fourteenth N-type field effect transistor is the second end of the self-bias current generating circuit; The gate of the ninth P-type field effect transistor is respectively connected to the gate of the eleventh P-type field effect transistor, the gate of the tenth P-type field effect transistor, the drain of the tenth P-type field effect transistor, and the drain of the fourteenth N-type field effect transistor; the connection node of the gate of the ninth P-type field effect transistor, the gate of the eleventh P-type field effect transistor, the gate of the tenth P-type field effect transistor, the drain of the tenth P-type field effect transistor, and the drain of the fourteenth N-type field effect transistor is the third end of the self-bias current generating circuit; The source of the fourteenth N-type field effect transistor is connected to one end of the resistor; The drain of the fifteenth N-type field effect transistor, the source of the fifteenth N-type field effect transistor, the source of the thirteenth N-type field effect transistor and the other end of the resistor are all grounded.

10. The overall reset circuit according to claim 7, characterized in that: The second comparator specifically includes: a twelfth P-type field effect transistor, a thirteenth P-type field effect transistor, a fourteenth P-type field effect transistor, a fifteenth P-type field effect transistor, a sixteenth P-type field effect transistor, a seventeenth P-type field effect transistor, a sixteenth N-type field effect transistor, a seventeenth N-type field effect transistor, an eighteenth N-type field effect transistor, a nineteenth N-type field effect transistor, a twentieth N-type field effect transistor, a twenty-first N-type field effect transistor, a twenty-second N-type field effect transistor and a twenty-third N-type field effect transistor; The source of the twelfth P-type field effect transistor, the source of the thirteenth P-type field effect transistor, the source of the sixteenth P-type field effect transistor and the source of the seventeenth P-type field effect transistor are the first end of the second comparator; the gate of the sixteenth N-type field effect transistor is the second end of the second comparator; the gate of the fifteenth P-type field effect transistor is the third end of the second comparator; the gate of the fourteenth P-type field effect transistor is the fourth end of the second comparator; the gate of the twenty-third N-type field effect transistor is the fifth end of the second comparator; the drain of the seventeenth P-type field effect transistor and the drain of the twenty-second N-type field effect transistor are the sixth end of the second comparator; The gate of the twelfth P-type field effect transistor is respectively connected to the drain of the twelfth P-type field effect transistor, the gate of the thirteenth P-type field effect transistor and the drain of the sixteenth N-type field effect transistor; The drain of the thirteenth P-type field effect transistor is respectively connected to the source of the fourteenth P-type field effect transistor and the source of the fifteenth P-type field effect transistor; the drain of the fourteenth P-type field effect transistor is respectively connected to the gate of the twenty-first N-type field effect transistor, the drain of the seventeenth N-type field effect transistor, the gate of the seventeenth N-type field effect transistor, the drain of the nineteenth N-type field effect transistor and the gate of the twentieth N-type field effect transistor; The drain of the fifteenth P-type field effect transistor is respectively connected to the gate of the twenty-second N-type field effect transistor, the gate of the eighteenth N-type field effect transistor, the drain of the eighteenth N-type field effect transistor, the gate of the nineteenth N-type field effect transistor and the drain of the twentieth N-type field effect transistor; The gate of the seventeenth P-type field effect transistor is respectively connected to the gate of the sixteenth P-type field effect transistor, the drain of the sixteenth P-type field effect transistor and the drain of the twenty-first N-type field effect transistor; The source of the twenty-second N-type field effect transistor is respectively connected to the source of the twenty-first N-type field effect transistor and the drain of the twenty-third N-type field effect transistor; The source of the sixteenth N-type field effect transistor, the source of the seventeenth N-type field effect transistor, the source of the nineteenth N-type field effect transistor, the source of the twentieth N-type field effect transistor, the source of the eighteenth N-type field effect transistor and the source of the twenty-third N-type field effect transistor are all grounded.

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