Combined feedforward and fixed time delay

Abstract

Embodiments of the present disclosure relate to a combined feedforward and fixed time delay. According to an embodiment, a delay circuit for control logic in a converter is provided. The delay circuit includes a first timer circuit having a transconductance amplifier and a first capacitor. The delay circuit includes a second timer circuit coupled with the first timer circuit. The second timer circuit includes a first current generator, a second current generator, and a second capacitor. The second timer circuit is configured to receive an output signal from the first timer circuit to modify a charging current provided by the second current generator or a sum of the first current generator and the second current generator to charge a second capacitor in the second timer circuit.

Description

Technical Field

[0001] The present disclosure generally relates to electronic circuits, and in particular embodiments, to delay circuits. Background Art

[0002] Switching DC-DC converters are an integral part of modern power electronics, converting one DC voltage level to another through fast switching. This switching is typically facilitated by pulse width modulation (PWM), enabling precise control of the output voltage. Generally, a delay circuit is coupled to the control logic, which provides a timing signal to the control logic. The control logic generates a control signal at the control terminal of the switch based on the timing signal from the delay circuit.

[0003] In synchronous switching converters, the control logic plays an important role in determining the operating efficiency and safety of the circuit. The core of this control logic is a pulse width modulation (PWM) controller. It is responsible for generating a primary control signal for the high-side switch. The width of the pulses generated by the PWM determines the ON time of the high-side switch and subsequently the duty cycle of the converter.

[0004] However, smooth and safe operation is not only a matter of the high-side switch itself. The converter also includes a low-side switch, which needs to operate in coordination with the high-side switch.

[0005] To achieve this precise delay, a timing delay circuit becomes indispensable. Although a simple delay can be generated using a basic RC network with the time constant produced by resistors and capacitors, precision usually requires a more complex solution. Specialized delay ICs or digital delay elements are typically employed to ensure that the delay is precise and adjustable to meet specific requirements. Summary of the Invention

[0006] Technical advantages are generally achieved through embodiments of the present disclosure, which describe a delay circuit.

[0007] A first aspect relates to a delay circuit for control logic in a converter. The delay circuit includes a first timer circuit having a transconductance amplifier and a first capacitor. The first timer circuit includes a first transfer characteristic that is equal to Or where α is a first multiplier factor associated with the transconductance amplifier, V in is the supply voltage for the converter, and V outis the output voltage of the converter. The delay circuit includes a second timer circuit coupled to the first timer circuit. The second timer circuit includes a first current generator, a second current generator, and a second capacitor. The second timer circuit is configured to receive an output signal from the first timer circuit to modify a charging current provided by the second current generator or the sum of the first current generator and the second current generator, thereby charging the second capacitor in the second timer circuit. The second timer circuit has a second transfer characteristic that is equal to or where β is a second multiplication factor associated with the first current generator.

[0008] A second aspect relates to a method of operating a delay circuit for control logic in a converter. The method includes: receiving, by the delay circuit, a start command signal from the control logic; generating, by a first timer circuit of the delay circuit, a first delay signal, the first timer circuit including a transconductance amplifier and a first capacitor, the first timer circuit having a first transfer characteristic that is equal to or where α is a first multiplication factor associated with the transconductance amplifier, V in is the supply voltage for the converter, and V out is the output voltage of the converter; receiving, by a second timer circuit of the delay circuit, the first delay signal and the start command signal from the first timer circuit, the second timer circuit including a first current generator, a second current generator, and a second capacitor; modifying, based on the first delay signal, a charging current provided by the second current generator or the sum of the first current generator and the second current generator, the charging current being used to charge the second capacitor in the second timer circuit; and generating, by the second timer circuit, a second delay signal that is used by the control logic to generate a control signal for a switching element of the converter, the second timer circuit having a second transfer characteristic that is equal to or where β is a second multiplication factor associated with the first current generator.

[0009] A third aspect relates to a converter. The converter includes: a switching element; control logic configured to control a switching operation of the switching element; and a delay circuit coupled to the control logic. The delay circuit includes a first timer circuit that includes a transconductance amplifier and a first capacitor. The first timer circuit has a first transfer characteristic that is equal to or where α is a first multiplication factor associated with the transconductance amplifier, V in is the supply voltage for the converter, and V outis the output voltage of the converter. The delay circuit further includes a second timer circuit coupled to the first timer circuit. The second timer circuit includes a first current generator, a second current generator, and a second capacitor. The second timer circuit is configured to receive an output signal from the first timer circuit to modify a charging current provided by the second current generator or the sum of the first current generator and the second current generator, so as to charge the second capacitor in the second timer circuit. The second timer circuit has a second transfer characteristic, and the second transfer characteristic is equal to or where β is a second multiplication factor associated with the first current generator.

[0010] Embodiments may be implemented in hardware, software, or any combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more fully understand the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic diagram of a feed-forward delay circuit;

[0013] Figure 2 is a schematic diagram of a fixed-time delay circuit;

[0014] Figure 3 is a block diagram of an embodiment delay circuit;

[0015] Figure 4 is a schematic diagram of an embodiment feed-forward delay circuit;

[0016] Figure 5 is a schematic diagram of an embodiment fixed-time delay circuit;

[0017] Figure 6 is a timing diagram that details the operation of the fixed-time delay circuit of Figure 5 ;

[0018] Figure 7 is a schematic diagram of an embodiment converter of a buck (step-down) converter type represented as a switched-mode power supply (SMPS);

[0019] Figure 8 is a schematic diagram of an embodiment converter represented as a full-bridge converter without synchronous rectification;

[0020] Figure 9 is Figure 8 the inductor current (I L ) of the inductor (L) of the converter of

[0021] Figure 10It is a flowchart of an exemplary method of an operation delay circuit. Detailed Description

[0022] The present disclosure provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments merely illustrate specific configurations and do not limit the scope of the claimed embodiments. Unless otherwise specified, features from different embodiments can be combined to form additional embodiments. Various embodiments are illustrated in the drawings, where the same components and elements are identified by the same reference numerals, and repeated descriptions are omitted for brevity.

[0023] The variations or modifications described in one embodiment can also be applicable to other embodiments. Additionally, various changes, substitutions, and variations can be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0024] Although the inventive aspects are mainly described in the context of a timing circuit for a buck converter, it should be understood that these inventive aspects can also be applicable to any other circuit that can employ a timing circuit.

[0025] Figure 1 A schematic diagram of a feed - forward delay circuit 100 is illustrated. The feed - forward delay circuit 100 includes a transconductance amplifier 102, a first switch 104, a second switch 106, a capacitor (C1) 108, and a comparator 110. In an embodiment, the feed - forward delay circuit 100 is used by control logic in a converter for a constant ON - time (COT) control mechanism to have a constant steady - state frequency.

[0026] In the COT control mechanism, the switch of the voltage regulator (usually a MOSFET) is activated for a fixed duration during each cycle. This duration remains constant regardless of variations in the input or output voltage. The unique characteristic of COT is that when the ON period is kept constant, the OFF period is adjusted based on feedback from the output to ensure that the output voltage remains regulated.

[0027] The transconductance amplifier 102 (also known as a voltage - to - current converter) takes an input voltage (V in ) and produces an output current (I in ) that is proportional to the input voltage (V out ). The transconductance amplifier 102 includes a feed - forward resistor (R f ). The proportionality constant (g m ) of the transconductance amplifier 102, also known as the transconductance, is inversely proportional to the feed - forward resistor (R f ): g m ≈1 / R f . The transconductance (g m ) represents the output current (Iout ) Rate of change with respect to the input voltage (V in ): where ΔI out is the change in the output current and ΔV in is the change in the input voltage.

[0028] The operation of the first switch 104 is controlled by a start command signal (START). The start command signal (START) may be associated with the start sequence of the DC-DC converter. In an embodiment, the start command signal (START) is connected to a control signal coupled to the control terminal of the high-side switch in the dual-switch power converter.

[0029] In a first configuration, corresponding to the start command signal (START) being at a low logic level, the first switch 104 is configured to couple the output of the transconductance amplifier 102 to the reference ground. In a second configuration, corresponding to the start command signal (START) being at a high logic level, the first switch 104 is configured to couple the output of the transconductance amplifier 102 to the non-inverting input of the comparator 110.

[0030] The operation of the second switch 106 is controlled by the inverted value of the start command signal . In a first configuration, corresponding to the inverted value of the start command signal being at a high logic level, the second switch 106 is in the closed (CLOSED) position and the non-inverting input of the comparator 110 is coupled to the reference ground. In a second configuration, corresponding to the inverted value of the start command signal being at a low logic level, the second switch 106 is in the open (OPEN) position and the non-inverting input of the comparator 110 is coupled to the output of the transconductance amplifier 102.

[0031] In operation, when the start command signal (START) rises, the feed-forward delay circuit 100 is configured to couple the transconductance amplifier 102 to the non-inverting input of the comparator 110. The output current (I out ) from the transconductance amplifier 102 starts to charge the capacitor (C1) 108. When the charge stored in the capacitor (C1) 108 (having a terminal coupled to node 112) exceeds the output voltage (V out ), the output signal (OUT1) of the comparator 110 rises, where the delay (T delay1 ) from the initial start time is represented by Equation (1):

[0032] Figure 2FIG. illustrates a schematic diagram of a fixed time delay circuit 200. The fixed time delay circuit 200 includes a current generator 202, a first switch 204, a second switch 206, a capacitor (C2) 208, and a comparator 210. The current generator 202 is configured to generate a current (I0). In an embodiment, the fixed time delay circuit 200 is used by control logic in a converter for a constant OFF (turn-off) time (COF) control mechanism.

[0033] In the COF control mechanism, compared to the COT control mechanism, the OFF period remains constant. Once the high-side switch is turned off, it remains OFF or for a fixed period. The ON time varies based on feedback to ensure that the output voltage (V out ) is maintained at a desired level.

[0034] When the duty cycle is low, the COT control mechanism is beneficial; however, when the duty cycle is high, it is disadvantageous. For example, COT cannot have a 100% duty cycle because there is a fixed ON time and a minimum OFF time for stability reasons. Therefore, maximum discharge cannot be 100%. In applications where the output voltage (V out ) is as high as the input voltage (V in ), COT is not used. In COF, it is difficult to achieve a substantially constant switching frequency while changing the input voltage (V in ) and the output voltage (V out ).

[0035] The operation of the first switch 204 is controlled by a start command signal (START). In a first configuration, corresponding to the start command signal (START) being at a low logic level, the first switch 204 is configured to couple the output of the current generator 202 to a reference ground. In a second configuration, corresponding to the start command signal (START) being at a high logic level, the first switch 204 is configured to couple the output of the current generator 202 to the non-inverting input of the comparator 210.

[0036] The operation of the second switch 206 is controlled by the inverted value of the start command signal . In a first configuration, corresponding to the inverted value of the start command signal being at a high logic level, the second switch 206 is in a closed position and the non-inverting input of the comparator 210 is coupled to a reference ground. In a second configuration, corresponding to the inverted value of the start command signal being at a low logic level, the second switch 206 is in an open position and the non-inverting input of the comparator 110 is coupled to the output of the current generator 202 via a node 212 (V c ).

[0037] In operation, when the start command signal (START) rises, the fixed-time delay circuit 200 is configured to couple the current generator 202 to the non-inverting input of the comparator 210 by means of the first switch 204. The current (I0) from the current generator 202 starts charging the capacitor 208. When the charge stored in the capacitor (C2) 208 (having a terminal coupled to node 212) exceeds the reference voltage (V ref ), the output signal (OUT2) of the comparator 210 rises, where the delay (T delay2 ) from the initial start time is represented by Equation (2):

[0038]

[0039] Figure 3 The block diagram of an embodiment delay circuit 300 is illustrated. The delay circuit 300 includes a first timer circuit 302, and the first timer circuit 302 is coupled to a second timer circuit 304. Advantageously, the delay circuit 300 allows the control logic to operate under the COF control mechanism to achieve a constant steady-state switching frequency.

[0040] The first timer circuit 302 receives the output voltage (V out ), the start command signal (START), and the input voltage (V in ). The first timer circuit 302 generates an output signal (OUT3), and the output signal (OUT3) is fed to the second timer circuit 304. The second timer circuit 304 receives the output signal (OUT3), the start command signal (START), and the reference voltage (V ref ). The second timer circuit 304 generates an output signal (OUT4). In an embodiment, the output signal (OUT4) is provided from the delay circuit 300 to the control logic of the switching converter to generate control signals for ON and OFF switching of the switch of the switching converter.

[0041] The output signal (OUT3) of the first timer circuit 302 is used to configure the charging current of the second timer circuit 304. The delay circuit 300 is configured to have a time delay, and the delay time is represented by Equation (3):

[0042] In an embodiment, the first timer circuit 302 has or transfer characteristics, where α is a first multiplier factor associated with the first timer circuit 302. In an embodiment, the first multiplier factor is a fixed constant value. The second timer circuit 304 has or Transfer characteristics, where β is a second multiplication factor associated with the second timer circuit 304. In an embodiment, the second multiplication factor is a fixed constant value.

[0043] Figure 4 FIG. illustrates a schematic diagram of an embodiment of a feed - forward delay circuit 400. In an embodiment, the feed - forward delay circuit 400 is implemented as the first timer circuit 302 of the delay circuit 300. The feed - forward delay circuit 400 includes a transconductance amplifier 402, a first switch 104, a second switch 106, a capacitor (C1) 108, and a comparator 110 that may (or may not) be arranged as shown. The feed - forward delay circuit 400 may include additional components not shown. For example, the feed - forward delay circuit 400 may include one or more inverters or other types of logic gates to invert the start command signal (START).

[0044] In the feed - forward delay circuit 400, the transconductance (g m ) of the transconductance amplifier 402 includes a K multiplication factor such that the transconductance (g m ) of the transconductance amplifier 402 is proportional to the K multiplication factor and the feed - forward resistor (R f ): g m ≈K / R f . In an embodiment, the K multiplication factor is a fixed constant value.

[0045] In operation, when the start command signal (START) rises, the feed - forward delay circuit 400 is configured to couple the output of the transconductance amplifier 402 to the non - inverting input of the comparator 110. The output current (I out ) from the transconductance amplifier 402 starts to charge the capacitor (C1) 108. When the charge stored in the capacitor (C1) 108 (with a terminal coupled to node 112) exceeds the output voltage (V out ), the output signal (OUT3) of the comparator 110 rises, where the time delay (T delay4 ) from the initial start time is represented by Equation (4): where C1 is the capacitance of the capacitor 108.

[0046] Figure 5 FIG. illustrates a schematic diagram of an embodiment of a fixed - time delay circuit 500. Figure 6FIG. 600 is a timing diagram illustrating the operation of the fixed time delay circuit 500 in detail. In an embodiment, the fixed time delay circuit 500 is implemented as the second timer circuit 304 of the delay circuit 300. The fixed time delay circuit 500 includes a current generator 202, a first switch 204, a second switch 206, a capacitor (C2) 208, a comparator 210, a second current generator 502, a third switch 504, and an OR gate 506, which may (or may not) be arranged as shown. The fixed time delay circuit 500 may include additional components not shown. For example, the fixed time delay circuit 500 may include one or more inverters or other types of logic gates to invert the start command signal (START) and the output signal (OUT3) from the feedforward delay circuit 400.

[0047] The operation of the third switch 504 is controlled by the OR gate 506 through the inverted value of the start command signal and the inverted output signal of the feedforward delay circuit 400 by OR gate logic.

[0048] In operation, at time t0, the start command signal (START) 602 and the output signal (OUT3) 604 of the feedforward delay circuit 400 are at a low logic level. The fixed time delay circuit 500 is configured to couple the output of the transconductance amplifier 502 to the reference ground by means of the first switch 204, arrange the second switch 206 in the closed position, and arrange the third switch 504 in the closed position.

[0049] At time t1, the start command signal (START) 602 transitions from a low logic level to a high logic level. Accordingly, the inverted value of the start command signal transitions from a high logic level to a low logic level. The fixed time delay circuit 500 is configured to arrange the second switch 206 in the open position. Since the inverted value of the start command signal at the first input of the OR gate 406 is at a low logic level and the inverted output signal of the feedforward delay circuit 400 at the second input of the OR gate 506 is at a high logic level (i.e., the output signal (OUT3) 604 is at a low logic level), the output of the OR gate 506 is at a high logic level and the third switch 504 is arranged in the closed position.

[0050] The fixed time delay circuit 500 is also configured to couple the node 212 at the non-inverting input of the comparator 210 to the current generator 202 and the second current generator 502 via the first switch 204 and the third switch 504, respectively. The capacitor (C2) 208 starts charging through the sum of the current (I0) provided by the current generator 202 and the current (K×I0) provided by the second current generator 502, i.e., the total current of (K + 1)×I0, which is reflected by the voltage (V c ) 608 at the node 112.

[0051] At time t2, the output signal (OUT3) from the feedforward delay circuit 400 changes from the low logic level to the high logic level. Therefore, the inverted output signal at the second input of the OR gate 506 is at the low logic level. The inverted value of the start command signal at the first input of the OR gate 506 is also at the low logic level. Therefore, the third switch 504 changes to the open position. The fixed time delay circuit 500 is configured to couple the node 212 at the non-inverting input of the comparator 210 to the current generator 202 via the first switch 204. Therefore, the capacitor (C2) 208 continues to charge only through the current (I0) provided by the current generator 202, which is reflected by the voltage (V c ) 608 at the node 112.

[0052] At time t3, the voltage (V c ) 608 at the node 112 exceeds the reference voltage (V ref ). Therefore, the output signal (OUT4) of the comparator 210 rises. Since the current ((K + 1)×I0) that charges the capacitor (C2) 208 between time t1 and time t2 is greater than the current (I0) that charges the capacitor (C2) 208 between time t2 and time t3, the ratio of the charge stored in the capacitor (C2) 208 decreases after time t2, which is reflected in Figure 6 the change in the slope of the voltage (V c ) 608 at the node 112.

[0053] The relationship between the charge (Q) injected into the capacitor from the current (I) and time (t) can be expressed by Equation (5): Q = I×t. Therefore, the charge (Q1) injected into the capacitor (C2) 208 from time t1 to time t2 can be calculated using Equation (5): Q1 = ((K + 1)×I0)×T delay4 , and Equation (5) can be shown as Equation (6) according to Equation (4):

[0054] At time t3, the charge (QTOT ) can be calculated using Equation (6): Q TOT = Q1 + I0 × (T delay5 - T delay4 ), where T delay5 is the time from time t1 to time t3 (the delay of the combined feedforward delay circuit 400 and the fixed time delay circuit 500), and the charge (Q TOT ) can be shown as Equation (7) according to Equation (6) and Equation (4):

[0055] When the voltage across the capacitor is voltage (V), the relationship between the charge (Q) injected into the capacitor and the capacitance (C) can be represented by Equation (8): Q = C × V. Therefore, at time t3, the time delay (T delay5 ) can be calculated by using V ref × C2 to replace the total charge (Q TOT ).

[0056] Based on Equation (8) and Equation (7), the charge (Q TOT ) injected into the capacitor 208 at time t3 can be represented by Equation (9): V ref × C2 = Q TOT , and Equation (9) can be rewritten as Equation (10):

[0057] Equation (10) can be simplified to Equation (11):

[0058] As shown in Equation (10), the K multiplier factor does not affect the time delay (T delay5 ) value. However, Equation (10) is only valid when the time delay (T delay5 ) is greater than or equal to the delay (T delay4 ) of the feedforward delay circuit 400 (i.e., T delay5 ≥ T delay4 ). The operating range of the timer circuit of the combined feedforward delay circuit 400 and the fixed time delay circuit 500 can be improved by increasing the K multiplier factor. Unfortunately, by doing so, the influence of the delay of the comparator 208 on the timer linearity with respect to the input voltage (V in ) is greater.

[0059] Considering T delay5 ≥ T delay4 , the operating range of the timer circuit of the combined feedforward delay circuit 400 and the fixed time delay circuit 500 can be expressed as Equation (12):

[0060] Equation (12) can be rewritten as Equation (13):

[0061] Considering T delay5 ≥ 0, Equation (14): ensures that Equation (13) is feasible, and for large values of K, T delay5 can be as low as zero. By using a large value for the K multiplier factor, the operating range of the timer circuit can be reduced to T delay5 ≈ 0.

[0062] In one embodiment, the feedforward delay circuit 400 is implemented as the first timer circuit 302 of the delay circuit 300, and the fixed-time delay circuit 500 is implemented as the second timer circuit 304 of the delay circuit 300.

[0063] Figure 7 FIG. illustrates a schematic diagram of an embodiment converter 700, which is represented as a buck (step-down) converter type of a switched-mode power supply (SMPS). The converter 700 includes a delay circuit 300, a control logic 702, a switching element 720, an inductor (L) 708, an optional input capacitor (C in ) 710, an output capacitor (C out ) 712, a first comparator 714, and a second comparator 716, which may (or may not) be arranged as shown. The converter 700 may include other components not shown. For example, the converter 700 may include a circuit that provides a minimum ON time to the control logic 702 for one or more switching elements of the switching element 720. As another example, the converter 700 may include corresponding gate drivers coupled between the output of the control logic 702 and each switching element of the switching element 720.

[0064] The switching element 720 includes a first transistor (Q1) 704 (i.e., a high-side switch) and a second transistor (Q2) 706 (i.e., a low-side switch). The first transistor (Q1) 704 is coupled between the input source (V in ) and the switching node (SW). The second transistor (Q2) 706 is coupled between the switching node (SW) and the reference ground. The first transistor (Q1) 704 and the second transistor (Q2) 706 may be of the metal-oxide silicon field-effect transistor (MOSFET) type. The first transistor (Q1) 704 and the second transistor (Q2) 706 may be n-channel MOSFETs.

[0065] The inductor (L) 708 is coupled between the switching node (SW) and the output terminal of the conventional converter 700, and the output terminal of the conventional converter 700 is typically coupled to the output capacitor (C out)712. Optionally, the input capacitor (C in )710 is coupled between the input source (V in ) and the reference ground.

[0066] In an embodiment, the control logic 702 provides complementary control signals with the same duty cycle to the gate terminals of the first transistor (Q1) 704 and the second transistor (Q2) 706. During the ON period (T ON,HS ) of the first transistor (Q1) 704, the second transistor (Q2) 706 is in the OFF condition. The inductor (L) 708 is charging, the output capacitor (C out )712 is charging, and current (I L ) is provided to the output terminal of the conventional converter 700. Conversely, during the ON period (T ON,LS ) of the second transistor (Q2) 706, the first transistor (Q1) 704 is in the OFF condition, the inductor (L) 708 is coupled to the reference ground via the second transistor (Q2) 706, the inductor (L) 708 is discharging and providing current (I L ) to the output terminal of the conventional converter 700.

[0067] Thus, the voltage at the switching node voltage (SW) alternates between the voltage at the input source (V in ) and the reference ground. The controlled ON and OFF switching of the first transistor (Q1) 704 and the second transistor (Q2) 706 generates a fixed duty cycle square wave, which, when filtered by the inductor (L) 708 and the output capacitor (C out )712, provides the output voltage (V out ) for the load.

[0068] In an embodiment, the first input of the delay circuit 300 is coupled to the output of the converter 700 to provide the output voltage (V out ) of the converter 700 as the input voltage of the delay circuit 300. In an embodiment, the control logic 702 provides a start command signal (START) to the delay circuit 300 as an input signal. In an embodiment, the supply voltage is provided to the delay circuit 300 as the input source (V in ). In an embodiment, before the input source (V in ) is provided to the delay circuit 300, the input source (V in ) is regulated. In an embodiment, when the output voltage (V out ) is fixed, it is not necessary to provide the output voltage (V out ) to the delay circuit 300.

[0069] The first timer circuit 302 receives a start command signal (START) as an input signal and receives an input source (V in ), and generates an output signal (OUT3), and the output signal (OUT3) is fed to the second timer circuit 304. The second timer circuit 304 receives the output signal (OUT3), the start command signal (START), and a reference voltage (V ref ). The second timer circuit 304 generates an output signal (OUT4). In an embodiment, the output signal (OUT4) is provided from the delay circuit 300 to the control logic 702 to generate control signals for ON and OFF switching of the switch of the switched converter.

[0070] The control logic 702 operates based on voltage mode control and current mode control to provide a balance between load responsiveness and input voltage variations.

[0071] In voltage mode control, a first comparator 714 (i.e., a pulse width modulation (PWM) comparator) continuously measures the output voltage (V ref ) of the converter 700 against a predetermined reference voltage (V out ). The first comparator 714 acts as a primary sensor for the output difference. If there is any difference between the output voltage (V out ) and the reference voltage (V ref ), the first comparator 714 responds quickly by generating a first signal. This first signal acts as a road sign indicating whether the output voltage (V out ) needs to rise or fall to align with the reference voltage (V ref ).

[0072] In current mode control, a second comparator 716 monitors the inductor current (I L ). By setting a limit current (I LIM ), the second comparator 716 ensures that the inductor current (I L ) remains within a safe range. If the inductor current (I L ) starts to approach the limit current (I LIM ), the second comparator 716 generates a second signal indicating that control is needed before the inductor current (I L ) breaches the safe level.

[0073] The convergence of the first signal and the second signal is managed in control logic 702. The control logic 702 orchestrates the feedback from the first comparator 714 and the second comparator 716. On the one hand, it receives the first signal from the first comparator 714, urging voltage adjustment, and on the other hand, it obtains a warning alert related to the current limit as the second signal from the second comparator 716. By navigating these dual inputs, the control logic 702 adjusts the duty cycle of the PWM signal, which in turn modulates the switches in the switching element 720.

[0074] In an embodiment, each switching time cycle (TSW) of the converter 700 is equal to the ON period (T ON,HS ) of the first transistor (Q1) 704 and the ON period (T ON,LS ) of the second transistor (Q2) 706, and the sum is expressed as Equation (15): T SW = T ON,HS + T ON,LS .

[0075] Since the first transistor (Q1) 704 is in the OFF condition during the ON period (T ON,LS ) of the second transistor (Q2) 706, we can utilize the OFF period (T OFF,HS ) of the first transistor (Q1) 704 to replace the ON period (T ON,LS ) of the second transistor (Q2) 706 to simplify the discussion.

[0076] Therefore, Equation (15) can be written as Equation (16): T SW = T ON,HS + T OFF,HS .

[0077] To have a constant steady-state switching time cycle (T SW ), the following conditions can be asserted: Based on Equation (16), the condition can be expressed as Equation (17): Equation (17) can be simplified to Equation (18):

[0078] Figure 8 Illustrated is a schematic diagram of an embodiment converter 800, which is represented as a full-bridge converter without synchronous rectification. The converter 800 includes a delay circuit 300, which may (or may not) be arranged as shown, control logic 802, a first transistor (Q1) 804 (i.e., high-side switch), a second transistor (Q2) 806 (i.e., low-side switch), an inductor (L) 808, an optional input capacitor (C in ) 810, an optional output capacitor (C out)Comparator 812, comparator 814, first rectifier diode (D1) 816, and second rectifier diode (D2) 818. The delay circuit 300 is configured to provide a fixed OFF time (i.e., T OFF ). Embodiments of the present disclosure provide a set value for the fixed OFF time.

[0079] Converter 800 may include additional components not shown. For example, converter 800 may include respective gate drivers coupled between the output of control logic 802 and each switching element of first transistor (Q1) 804 and second transistor (Q2) 806.

[0080] The first transistor (Q1) 804 is coupled between the input source (V in ) and the switching node (SW). The switching node (SW) is coupled to the cathode of the second rectifier diode (D2) 818. The anode of the second rectifier diode (D2) 818 is coupled to the reference ground.

[0081] The inductor (L) 808 has a first terminal coupled to the switching node (SW). The second transistor (Q2) 806 is coupled between the second terminal of the inductor (L) 808 and the reference ground. The first transistor (Q1) 804 and the second transistor (Q2) 806 may be of the metal oxide silicon field effect transistor (MOSFET) type. The first transistor (Q1) 804 and the second transistor (Q2) 806 may be n-channel MOSFETs.

[0082] The second terminal of the inductor (L) 808 is coupled to the anode of the first rectifier diode (D1) 816. The cathode of the first rectifier diode (D1) 816 is coupled to the output capacitor (C out ) 812. Optionally, an input capacitor (C in ) 810 is coupled between the input source (V in ) and the reference ground.

[0083] In an embodiment, the control logic 802 provides control signals with the same duty cycle to the gate terminals of the first transistor (Q1) 804 and the second transistor (Q2) 806 to activate or deactivate the first transistor (Q1) 804 and the second transistor (Q2) 806. The first transistor (Q1) 804 and the second transistor (Q2) 806 operate in cooperation based on the control signals received at their respective control terminals within each cycle.

[0084] Figure 9 A timing diagram of the inductor current (IL) of the inductor (L) 808 of the converter 800 during an operating cycle is illustrated. Embodiments of the present disclosure are directed to regulating the operation of the output current (I out ).

[0085] Comparator 814 works in concert with control logic 802 and delay circuit 300 to ensure that converter 800 operates safely within discontinuous conduction mode (DCM) parameters by regulating the switching of first transistor (Q1) 804 and second transistor (Q2) 806 based on real-time current readings. This not only ensures efficient energy transfer but also protects the components from potential damage.

[0086] Control logic 802 operates based on peak current mode control, where the operation of first transistor (Q1) 804 (i.e., high-side switch) and second transistor (Q2) 806 (i.e., low-side switch) is based on the comparison of inductor current (I L ) with a peak current (I PEAK ) reference value. In an embodiment, converter 800 operates in DCM. The first input of comparator 814 is fed by inductor current (I L ). The second input of comparator 814 is fed by a set peak current (I PEAK ) reference value. Comparator 814 continuously (i.e., constantly) compares the real-time value of the converter's current with the reference current.

[0087] During the ON time (T ON ), the inductor current (I L ) ramps up (i.e., charges) from time t0 to time t1. At time t0, control logic 802 simultaneously activates first transistor (Q1) 804 and second transistor (Q2) 806. At time t1, when the inductor current (I L ) reaches the fixed peak current (I PEAK ) reference value, control logic 802 deactivates first transistor (Q1) 804 and second transistor (Q2) 806 simultaneously to avoid saturation of inductor (L) 808. Using the voltage-current relationship of inductor (L) 808, the ON time (T ON ) from time t0 to time t1 can be represented by Equation (18):

[0088] At the end of the ON time (T ON ), when the inductor current (I L ) reaches the peak current (I PEAK ) reference value, comparator 814 outputs a signal indicating that the threshold has been reached. This signal is sent to control logic 802. Control logic 802 interprets the signal from comparator 814 as an indication to turn off the high-side switch (i.e., first transistor (Q1) 804) and the low-side switch (i.e., second transistor (Q2) 806), thus terminating the upward ramp of inductor current (I L ).

[0089] Embodiments of the present disclosure provide a delay circuit 300 that allows a fixed OFF time (T) that starts at time t1 and ends at time t3. OFF Between time t1 and time t2, the inductor current (I L ) is positive. The duration of the constant OFF time (T OFFC ) is such that the inductor current (I L ) reaches zero. Between time t2 and time t3, due to the presence of the rectifier diode, the inductor current (I L ) oscillates near zero. At time t3, the next cycle of the converter 800 begins.

[0090] Note that charge is only transferred to the output during the fixed OFF time from time t1 to time t3. This is because during the ON time (T ON ), when the first transistor (Q1) 804 and the second transistor (Q2) 806 are turned on from time t0 to time t1, the inductor (L) 808 is coupled to the input voltage (V in ) and the reference ground. Thus, no charge is transferred to the output during the ON time. For the switching time cycle (T SW ), the inductor (L) 808 will have an ON time (T ON ) and an OFF time (T OFF ), during which it will store energy and release energy to the load during the OFF time. The switching time cycle (T SW ) can be written as equation (19): where Q OUT is the output charge injected at each cycle.

[0091] The duration (T L ) of the inductor current (I PEAK ) from the fixed peak current (I OFFC ) reference value to zero (i.e., time t1 to time t2) depends on the output voltage (V out ) and the inductance of the inductor (L) 808. Using the voltage-current relationship of the inductor, the duration (T OFFC ) can be expressed by equation (20): Since the output voltage (V out ) and the inductance of the inductor (L) 808 are fixed values, the output charge (Q out ) injected at each cycle is constant, and the output charge (Q out ) can be expressed as equation (21):

[0092]

[0093] To cause an average constant current to be delivered to the output, the switching time cycle (T SW ) must be constant. Given equations (19) and (21), the switching time cycle (T SW ) can be written as equation (22): Given equations (18) and (22), the fixed OFF time (T OFF ) can be written as equation (23): In an embodiment, the control logic 802 provides a start command signal (START) as an input signal to the delay circuit 300. In an embodiment, a supply voltage is provided as an input source (V in ) to the delay circuit 300. In an embodiment, before the input source (V in ) is provided to the delay circuit 300, the input source (V in ) is regulated.

[0094] The first timer circuit 302 generates an output signal (OUT3), and the output signal (OUT3) is fed to the second timer circuit 304. The second timer circuit 304 receives the output signal (OUT3), the start command signal (START), and a reference voltage (V ref ). The second timer circuit 304 generates an output signal (OUT4). In an embodiment, the output signal (OUT4) is provided from the delay circuit 300 to the control logic 802 to generate a control signal for ON and OFF switching of a switch of the switched converter.

[0095] As shown in equation (23), since the output voltage (V out ) is a fixed value, only the input source (V in ) is used, resulting in being a fixed duration.

[0096] Figure 10 FIG. 1000 is a flowchart of an exemplary method of operating a delay circuit. In an embodiment, the delay circuit is the delay circuit 300. In an embodiment, the delay circuit is a delay circuit used in combination with the control logic of a converter. In such an embodiment, the control logic uses a time delay signal generated by the delay circuit to control the operation of a switching element of the converter.

[0097] At step 1002, the delay circuit receives a start command signal from the control logic.

[0098] At step 1004, a first timer circuit of the delay circuit generates a first delay signal. In an embodiment, the first timer circuit includes a transconductance amplifier and a first capacitor. In an embodiment, the first timer circuit has a first transfer characteristic that is equal to or where K1 is a first multiplication factor associated with the transconductance amplifier, V in is the supply voltage for the converter, and V out is the output voltage of the converter.

[0099] At step 1006, the second timer circuit of the delay circuit receives a first delay signal and a start command signal (START) from the first timer circuit. The second timer circuit includes a first current generator, a second current generator, and a second capacitor.

[0100] At step 1008, the charging current for charging the second capacitor in the second timer circuit, provided by the second current generator or the sum of the first current generator and the second current generator, is modified based on the first delay signal.

[0101] At step 1010, the second timer circuit generates a delay signal that is used by the control logic to generate a control signal for the switching element of the converter. The second timer circuit has a second transfer characteristic that is equal to or where K2 is a second multiplication factor associated with the first current generator.

[0102] Note that not all steps outlined in the flowchart of method 1000 are necessarily required and can be optional. Additionally, changes to the step arrangement, deletion of one or more steps and path connections, and addition of steps and path connections are similarly considered.

[0103] A first aspect relates to a delay circuit for control logic in a converter. The delay circuit includes a first timer circuit that has a transconductance amplifier and a first capacitor. The first timer circuit includes a first transfer characteristic that is equal to or where α is a first multiplication factor associated with the transconductance amplifier, V in is the supply voltage for the converter, and V out is the output voltage of the converter. The delay circuit includes a second timer circuit coupled to the first timer circuit. The second timer circuit includes a first current generator, a second current generator, and a second capacitor. The second timer circuit is configured to receive an output signal from the first timer circuit to modify the charging current provided by the second current generator or the sum of the first current generator and the second current generator, thereby charging the second capacitor in the second timer circuit. The second timer circuit has a second transfer characteristic that is equal to or where β is a second multiplication factor associated with the first current generator.

[0104] In a first implementation form of the delay circuit, according to such a first aspect, the first timer circuit is a feed - forward timer circuit. The output signal from the first timer circuit has a time delay (T delay ), and the time delay (T delay ) is equal to where C1 is the capacitance of the first capacitor, R f is the feed - forward resistor of the transconductance amplifier, and K is a third multiplication factor.

[0105] In a second implementation form of the delay circuit, according to such a first aspect or any previous implementation form of the first aspect, the second timer circuit is a fixed - delay timer circuit. The second output signal from the second timer circuit has a time delay (T delay ), and the time delay (T delay ) is equal to where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V ref is the reference voltage, I0 is the current value generated by the second current generator, and R f is the feed - forward resistor of the transconductance amplifier.

[0106] In a third implementation form of the delay circuit, according to such a first aspect or any previous implementation form of the first aspect, the second timer circuit is a fixed - delay timer circuit. The second output signal from the second timer circuit has a time delay (T delay ), and the time delay (T delay ) is equal to where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V ref is the reference voltage, I0 is the current value generated by the second current generator, and R f is the feed - forward resistor of the transconductance amplifier.

[0107] In a fourth implementation form of the delay circuit, according to such a first aspect or any previous implementation form of the first aspect, the first timer circuit is a feed - forward timer circuit. The second timer circuit is a fixed - delay timer circuit.

[0108] In a fifth implementation form of the delay circuit, according to such a first aspect itself or any previous implementation form of the first aspect, the delay circuit starts generating a delay signal at the output of the second timer circuit in response to a change in the logic of the start command signal transmitted from the control logic. The control logic is configured to generate a control signal for the switching element of the converter based on the delay signal received from the delay circuit.

[0109] In a sixth implementation form of the delay circuit, according to such a first aspect or any previous implementation form of the first aspect, the delay signal has a first slope, and the first slope corresponds to a first charging current provided by the sum of a first current generator and a second current generator. The delay signal has a second slope, and the second slope corresponds to a second charging current provided only by the second current generator.

[0110] A second aspect relates to a method of operating a delay circuit for control logic in a converter. The method includes: receiving, by the delay circuit, a start command signal from the control logic; generating, by a first timer circuit of the delay circuit, a first delay signal, the first timer circuit including a transconductance amplifier and a first capacitor, the first timer circuit having a first transfer characteristic that is equal to or where α is a first multiplication factor associated with the transconductance amplifier, V in is the supply voltage for the converter, and V out is the output voltage of the converter; receiving, by a second timer circuit of the delay circuit, the first delay signal and the start command signal from the first timer circuit, the second timer circuit including a first current generator, a second current generator, and a second capacitor; modifying, based on the first delay signal, a charging current provided by the second current generator or the sum of the first current generator and the second current generator, the charging current being used to charge the second capacitor in the second timer circuit; and generating, by the second timer circuit, a second delay signal that is used by the control logic to generate a control signal for a switching element of the converter, the second timer circuit having a second transfer characteristic that is equal to or where β is a second multiplication factor associated with the first current generator.

[0111] In a first implementation form of the method, according to such a second aspect, the first timer circuit is a feed-forward timer circuit. The first delay signal from the first timer circuit has a time delay (T delay ), and the time delay (T delay ) is equal to where C1 is the capacitance of the first capacitor, and R f is the feed-forward resistor of the transconductance amplifier.

[0112] In a second implementation form of the method, according to such a second aspect or any previous implementation form of the second aspect, the second timer circuit is a fixed-delay timer circuit. The second delay signal from the second timer circuit has a time delay (T delay ), and the time delay (T delay ) is equal to where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, Vref is a reference voltage, I0 is a current value generated by a second current generator, and R f is a feedforward resistor of the transconductance amplifier.

[0113] In a third implementation form of the method, according to such a second aspect or any previous implementation form of the second aspect, the second timer circuit is a fixed-delay timer circuit. The second delay signal from the second timer circuit has a time delay (T delay ), and the time delay (T delay ) is equal to where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V ref is a reference voltage, I0 is a current value generated by a second current generator, and R f is a feedforward resistor of the transconductance amplifier.

[0114] In a fourth implementation form of the method, according to such a second aspect or any previous implementation form of the second aspect, the first timer circuit is a feedforward timer circuit. The second timer circuit is a fixed-delay timer circuit.

[0115] In a fifth implementation form of the method, according to such a second aspect or any previous implementation form of the second aspect, the delay circuit starts generating a second delay signal at the output of the second timer circuit in response to a change in the logic of a start command signal transmitted from the control logic. The control logic is configured to generate a control signal for a switching element of the converter based on the second delay signal received from the delay circuit.

[0116] In a sixth implementation form of the method, according to such a second aspect or any previous implementation form of the second aspect, the second delay signal has a first slope, and the first slope corresponds to a first charging current provided by the sum of the first current generator and the second current generator. The second delay signal has a second slope, and the second slope corresponds to a second charging current provided only by the second current generator.

[0117] A third aspect relates to a converter. The converter includes: a switching element; control logic configured to control the switching operation of the switching element; and a delay circuit coupled to the control logic. The delay circuit includes a first timer circuit, and the first timer circuit includes a transconductance amplifier and a first capacitor. The first timer circuit has a first transfer characteristic, and the first transfer characteristic is equal to or where α is a first multiplication factor associated with the transconductance amplifier, V in is the supply voltage for the converter, and V outis the output voltage of the converter. The delay circuit further includes a second timer circuit coupled to the first timer circuit. The second timer circuit includes a first current generator, a second current generator, and a second capacitor. The second timer circuit is configured to receive an output signal from the first timer circuit to modify a charging current provided by the second current generator or the sum of the first current generator and the second current generator, so as to charge the second capacitor in the second timer circuit. The second timer circuit has a second transfer characteristic, and the second transfer characteristic is equal to or where β is a second multiplication factor associated with the first current generator.

[0118] In a first implementation form of the converter, according to such a third aspect, the first timer circuit is a feed-forward timer circuit. The output signal from the first timer circuit has a time delay (T delay ), and the time delay (T delay ) is equal to where C1 is the capacitance of the first capacitor, and R f is the feed-forward resistor of the transconductance amplifier.

[0119] In a second implementation form of the converter, according to such a third aspect or any previous implementation form of the third aspect, the second timer circuit is a fixed-delay timer circuit. The second output signal from the second timer circuit has a time delay (T delay ), and the time delay (T delay ) is equal to where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V ref is the reference voltage, I0 is the current value generated by the second current generator, and R f is the feed-forward resistor of the transconductance amplifier.

[0120] In a third implementation form of the converter, according to such a third aspect or any previous implementation form of the third aspect, the second timer circuit is a fixed-delay timer circuit. The second output signal from the second timer circuit has a time delay (T delay ), and the time delay (T delay ) is equal to where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V ref is the reference voltage, I0 is the current value generated by the second current generator, and R f is the feed-forward resistor of the transconductance amplifier.

[0121] In a fourth implementation form of the converter, according to such a third aspect or any previous implementation form of the third aspect, the first timer circuit is a feed-forward timer circuit, and the second timer circuit is a fixed-delay timer circuit.

[0122] In a fifth implementation form of the converter, according to such a third aspect or any previous implementation form of the third aspect, the delay circuit starts generating a delay signal at the output of the second timer circuit in response to a change in the logic of a start command signal transmitted from the control logic. The control logic is configured to generate a control signal for the switching element of the converter based on the delay signal received from the delay circuit.

[0123] Although the present description has been described in detail, it should be understood that various changes, substitutions, and variations can be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. In different figures, the same elements are designated by the same reference numerals. Furthermore, the scope of the present disclosure is not intended to be limited to the specific embodiments described herein, as those of ordinary skill in the art will readily understand from the present disclosure that processes, machines, manufactures, compositions of matter, devices, methods, or steps that exist currently or will be developed later can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, devices, methods, or steps within their scope.

[0124] The specification and the drawings should therefore be regarded simply as illustrative of the present disclosure as defined by the appended claims, and it is contemplated to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present disclosure.

Claims

1. A delay circuit for a control logic in a converter, the delay circuit comprising: A first timer circuit includes a transconductance amplifier and a first capacitor, and the first timer circuit has a first transfer characteristic, and the first transfer characteristic is equal to or Where α is the first multiplication factor associated with the transconductance amplifier, V in is the supply voltage for the converter, and V out is the output voltage of the converter; as well as a second timer circuit, the second timer circuit being coupled to the first timer circuit, the second timer circuit comprising a first current generator, a second current generator and a second capacitor, the second timer circuit being configured to receive an output signal from the first timer circuit to modify a charging current so as to charge the second capacitor in the second timer circuit, the charging current being provided by the second current generator or the sum of the first current generator and the second current generator, the second timer circuit having a second transfer characteristic, the second transfer characteristic being equal to or wherein β is a second multiplication factor associated with the first current generator.

2. The delay circuit of claim 1 , wherein the first timer circuit is a feed-forward timer circuit, and wherein the output signal from the first timer circuit has a time delay T delay , the time delay is equal to Where C1 is the capacitance of the first capacitor, R f is the feed-forward resistor of the transconductance amplifier, and K is the third multiplication factor.

3. The delay circuit of claim 1 , wherein the second timer circuit is a fixed delay timer circuit, and wherein the second output signal from the second timer circuit has a time delay T delay , the time delay is equal to Where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V ref is the reference voltage, I0 is the current value generated by the second current generator, and R f is the feed-forward resistor of the transconductance amplifier.

4. The delay circuit of claim 1 , wherein the second timer circuit is a fixed delay timer circuit, and wherein the second output signal from the second timer circuit has a time delay T delay , the time delay is equal to Where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V ref is the reference voltage, I0 is the current value generated by the second current generator, and R f is the feed-forward resistor of the transconductance amplifier.

5. The delay circuit of claim 1, wherein the first timer circuit is a feed-forward timer circuit, and wherein the second timer circuit is a fixed delay timer circuit.

6. The delay circuit of claim 1 , wherein the delay circuit begins generating a delay signal at an output of the second timer circuit in response to a change in logic of a start command signal transmitted from the control logic, the control logic being configured to generate a control signal for a switching element of the converter based on the delay signal received from the delay circuit.

7. The delay circuit of claim 6 , wherein the delay signal has a first slope corresponding to a first charging current provided by the sum of the first current generator and the second current generator, and wherein the delay signal has a second slope corresponding to a second charging current provided only by the second current generator.

8. A method of operating a delay circuit for control logic in a converter, the method comprising: receiving a start command signal from the control logic by the delay circuit; A first delay signal is generated by a first timer circuit of the delay circuit, the first timer circuit includes a transconductance amplifier and a first capacitor, the first timer circuit has a first transfer characteristic, and the first transfer characteristic is equal to or Where α is the first multiplication factor associated with the transconductance amplifier, V in is the supply voltage for the converter, and V out is the output voltage of the converter; receiving the first delay signal and the start command signal from the first timer circuit by a second timer circuit of the delay circuit, the second timer circuit comprising a first current generator, a second current generator and a second capacitor; modifying a charging current based on the first delay signal, the charging current being provided by the second current generator or the sum of the first current generator and the second current generator, the charging current being used to charge the second capacitor in the second timer circuit; as well as A second delayed signal is generated by the second timer circuit, the second delayed signal is used by the control logic to generate a control signal for a switching element of the converter, the second timer circuit having a second transfer characteristic, the second transfer characteristic being equal to or wherein β is a second multiplication factor associated with the first current generator.

9. The method of claim 8, wherein the first timer circuit is a feed-forward timer circuit, and wherein the first delayed signal from the first timer circuit has a time delay T delay , the time delay is equal to where C1 is the capacitance of the first capacitor, and R f is the feed-forward resistor of the transconductance amplifier.

10. The method of claim 8, wherein the second timer circuit is a fixed delay timer circuit, and wherein the second delayed signal from the second timer circuit has a time delay T delay , the time delay is equal to Where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V ref is the reference voltage, I0 is the current value generated by the second current generator, and R f is the feed-forward resistor of the transconductance amplifier.

11. The method of claim 8, wherein the second timer circuit is a fixed delay timer circuit, and wherein the second delayed signal from the second timer circuit has a time delay T delay , the time delay is equal to Where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V ref is the reference voltage, I0 is the current value generated by the second current generator, and R f is the feed-forward resistor of the transconductance amplifier.

12. The method of claim 8, wherein the first timer circuit is a feed-forward timer circuit, and wherein the second timer circuit is a fixed delay timer circuit.

13. The method of claim 8 , wherein the delay circuit begins generating the second delay signal at the output of the second timer circuit in response to a change in logic of a start command signal transmitted from the control logic, the control logic being configured to generate a control signal for a switching element of the converter based on the second delay signal received from the delay circuit.

14. The method of claim 13 , wherein the second delayed signal has a first slope corresponding to a first charging current provided by the sum of the first current generator and the second current generator, and wherein the second delayed signal has a second slope corresponding to a second charging current provided only by the second current generator.

15. A converter comprising: Switching elements; control logic configured to control a switching operation of the switching element; as well as a delay circuit coupled to the control logic, the delay circuit comprising: A first timer circuit includes a transconductance amplifier and a first capacitor, and the first timer circuit has a first transfer characteristic, and the first transfer characteristic is equal to or Where α is the first multiplication factor associated with the transconductance amplifier, V in is the supply voltage for the converter, and V out is the output voltage of the converter; as well as a second timer circuit, the second timer circuit being coupled to the first timer circuit, the second timer circuit comprising a first current generator, a second current generator and a second capacitor, the second timer circuit being configured to receive an output signal from the first timer circuit to modify a charging current so as to charge the second capacitor in the second timer circuit, the charging current being provided by the second current generator or the sum of the first current generator and the second current generator, the second timer circuit having a second transfer characteristic, the second transfer characteristic being equal to or wherein β is a second multiplication factor associated with the first current generator.

16. The converter of claim 15, wherein the first timer circuit is a feed-forward timer circuit, and wherein the output signal from the first timer circuit has a time delay T delay , the time delay is equal to where C1 is the capacitance of the first capacitor, and R f is the feed-forward resistor of the transconductance amplifier.

17. The converter of claim 15, wherein the second timer circuit is a fixed delay timer circuit, and wherein the second output signal from the second timer circuit has a time delay T delay , the time delay is equal to Where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V ref is the reference voltage, I0 is the current value generated by the second current generator, and R f is the feed-forward resistor of the transconductance amplifier.

18. The converter of claim 15, wherein the second timer circuit is a fixed delay timer circuit, and wherein the second output signal from the second timer circuit has a time delay T delay , the time delay is equal to Where C1 is the capacitance of the first capacitor, C2 is the capacitance of the second capacitor, V ref is the reference voltage, I0 is the current value generated by the second current generator, and R f is the feed-forward resistor of the transconductance amplifier.

19. The converter of claim 15, wherein the first timer circuit is a feed-forward timer circuit, and wherein the second timer circuit is a fixed delay timer circuit.

20. The converter of claim 15, wherein the delay circuit begins generating a delay signal at the output of the second timer circuit in response to a change in logic of a start command signal transmitted from the control logic, and the control logic is configured to generate a control signal for a switching element of the converter based on the delay signal received from the delay circuit.

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