D-GaN drive circuit

Abstract

The invention relates to the technical field of integrated circuits, and discloses a D-GaN drive circuit and a segmented drive module, a weak drive-strong drive segmented control strategy is adopted, the drive intensity is dynamically adjusted in combination with a time delay circuit, the voltage break rate in the switching process is reduced, and therefore EMI is restrained. The proportional sampling module is used for scaling down the current of a main power tube and then sampling the current based on operational amplifier feedback and a current mirror structure, so that the loss of a sampling resistor is close to zero, the conversion efficiency of the system is improved, the degradation of a dynamic conduction resistor is relieved, and low-loss current sampling is realized; according to the rapid discharge module, a TVS device is adopted to discharge residual charges in the turn-off stage, an accurate rapid discharge voltage clamping circuit is adopted, grid charges are rapidly discharged in the turn-off stage through a transient voltage suppressor (TVS), device breakdown caused by voltage overshoot is avoided, and the reliability of the device is improved. The problems of poor gate reliability, serious EMI interference, dynamic on-resistance deterioration and the like in the prior art are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a D-GaN driving circuit. Background Art

[0002] GaN technology is accelerating its penetration into communications, new energy, AI and other fields by virtue of its advantages of "high frequency, high efficiency and miniaturization".

[0003] GaN (depletion gallium nitride) has been widely used in many fields such as fast charging adapters, data center power supplies, photovoltaic inverters, energy storage systems, 5G base stations, etc. due to its characteristics such as high frequency, high power density and low on-resistance.

[0004] GaN is gradually replacing SiC in new energy vehicle OBCs (on-board chargers) and high-voltage inverters. Currently, mainstream manufacturers at home and abroad are focusing on optimizing D-GaN cascade structures, but they still face challenges in solving gate reliability and EMI problems. Problems such as dynamic on-resistance degradation, gate reliability defects, and insufficient dynamic avalanche tolerance need to be avoided in applications.

[0005] Based on this, the present invention proposes a D-GaN driving circuit. Summary of the invention

[0006] The object of the present invention is to provide a D-GaN driving circuit, which realizes low EMI, high reliability and high efficiency power control through segmented driving, proportional sampling and fast discharge voltage clamping technology.

[0007] The purpose of the present invention can be achieved through the following technical solutions: A first aspect: The present invention provides a D-GaN driving circuit, comprising: Segmented drive module, used to adjust the drive strength in stages according to the PWM signal; Ratio sampling module for low-loss current sampling via current mirror and op amp feedback; The fast discharge module uses TVS devices to discharge residual charge during the shutdown phase.

[0008] As a further solution of the present invention: the segmented driving module includes: Inverter INV1, weak drive unit and strong drive unit; The input end of the inverter INV1 is connected to a PWM signal; The weak drive unit includes an NMOS tube MN1 and a PMOS tube MP1; The strong driving unit includes an NMOS tube MN2 and a PMOS tube MP2; The weak driving unit and the strong driving unit are connected in time-sharing manner through a delay circuit; The delay circuit includes delay circuit Delay1 and delay circuit Delay2.

[0009] As a further solution of the present invention: the output terminal of the inverter INV1 is connected to the gates of the PMOS transistor MP1 and the NMOS transistor MN1, and the output terminal of the inverter INV1 is also connected to the inputs of the delay circuit Delay1 and the delay circuit Delay2; The PMOS transistor MP2 and the NMOS transistor MN2 are respectively connected to the outputs of the delay circuit Delay1 and the delay circuit Delay2; The drain terminals of the PMOS transistor MP1, the PMOS transistor MP2, the NMOS transistor MN1, and the NMOS transistor MN2 are commonly connected to the gates of the driving transistor M1 and the proportional transistor M2.

[0010] As a further solution of the present invention: the delay times of the delay circuit Delay1 and the delay circuit Delay2 are 50 - 200 ns As a further solution of the present invention: the proportional sampling module includes: a driving transistor M1, a proportional transistor M2, an operational amplifier OP1, a source follower M3, a current mirror M4, a current mirror M5, and a sampling resistor Rcs; The drain terminals of the driving transistor M1 and the proportional transistor M2 are respectively connected to the positive input terminal and the negative input terminal of the operational amplifier OP1; The output terminal of the operational amplifier OP1 is connected to the gate of the source follower M3, the source of the source follower M3 is connected to the drain of the proportional transistor M2, and the drain of the source follower M3 is connected to the current mirror M4 and the current mirror M5, and the outputs of the current mirror M4 and the current mirror M5 are connected to the resistor Rcs1.

[0011] As a further solution of the present invention: the size ratio of the driving transistor M1 to the proportional transistor M2 is k:1, and the value range of k is 500 ≤ k ≤ 2000.

[0012] As a further solution of the present invention: the mirror ratio of the current mirror M4 to the current mirror M5 is m:1, and the value range of m is 1 ≤ m ≤ 10.

[0013] As a further solution of the present invention: the TVS breakdown voltage of the fast discharge module is set to 1.2 - 1.5 times the turn-off threshold voltage of D-GaN.

[0014] In a second aspect, the present invention provides a flyback switching power supply, including the above-mentioned D-GaN driving circuit.

[0015] The beneficial effects of the present invention: The present invention provides a D-GaN driving circuit, which adopts a weak drive - strong drive segmented control strategy, combines a delay circuit to dynamically adjust the driving strength, reduces the voltage mutation rate during the switching process, and thus suppresses EMI; A proportional sampling circuit is adopted. Based on the operational amplifier feedback and current mirror structure, the current of the main power transistor is sampled after being scaled down proportionally, making the loss of the sampling resistor approach zero, improving the system conversion efficiency, and alleviating the deterioration of the dynamic on-resistance. A precise fast-discharge voltage clamping circuit is adopted. During the turn-off stage, the gate charge is quickly discharged through a transient voltage suppressor (TVS), avoiding device breakdown caused by voltage overshoot and solving the gate reliability problem. TVS: Suppress voltage spikes, avoid abnormal switching and damage of D-GaN due to breakdown of the lower driving transistor; Charge balance, adapt to D-GaN devices with different parasitic junction capacitances. Brief Description of the Drawings

[0016] The present invention will be further described below in conjunction with the drawings.

[0017] Figure 1 It is a schematic structural diagram of the D-GaN driving circuit of the present invention; Figure 2 It is a schematic structural diagram of the discharge transistor and the driving transistor of the present invention; Figure 3 It is a schematic structural diagram of a typical application circuit of D-GaN driving. Detailed Embodiments

[0018] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0019] As Figure 3 shown is a typical application circuit of D-GaN driving, including a driving circuit, a transformer, an output rectifying circuit D1, a D-GaN power transistor, a driving transistor M1, and a power transistor current sampling circuit Rcs. The drain of the D-GaN power transistor is connected to the primary winding, the source of the D-GaN power transistor is connected to the driving transistor M1, the source of the driving transistor M1 is connected to the sampling resistor Rcs, and the output rectifying circuit is connected to the secondary winding. This part is a conventional circuit of the prior art and will not be elaborated.

[0020] Please refer to Figure 1 shown. The present invention is a D-GaN driving circuit, including a segmented driving module. The segmented driving module is used to adjust the driving strength in stages according to the PWM signal; Specifically: The segmented driving module includes an inverter INV1, an NMOS transistor MN1, an NMOS transistor MN2, a PMOS transistor MP1, a PMOS transistor MP2, a delay circuit Delay1, and a delay circuit Delay2; The input terminal of the inverter INV1 is connected to the PWM signal, and the output terminal of the inverter INV1 is connected to the gates of the PMOS transistor MP1 and the NMOS transistor MN1, the inputs of the delay circuits Delay1 and Delay2; The PMOS transistor MP2 and the NMOS transistor MN2 are respectively connected to the outputs of the delay circuits Delay1 and Delay2. The drain terminals of the PMOS transistor MP1, the PMOS transistor MP2, the NMOS transistor MN1, and the NMOS transistor MN2 are commonly connected to the gates of the driving transistor M1 and the proportional transistor M2; The working process of the segmented driving module circuit is as follows: When the PWM signal changes from a low level to a high level, the output of the inverter INV1 changes from a high level to a low level. The NMOS transistors MN1 and MN2 are turned off, and the weak PMOS transistor MP1 is turned on. The gate voltage VG1 of the driving transistor M1 gradually rises, and the driving transistor M1 and the proportional transistor M2 are gradually turned on. After the driving transistor M1 pulls down the source voltage VD1 of the D-GaN, the D-GaN is turned on. After a delay of about 100 ns through the delay circuit Delay1, the strong driving transistor MP2 is turned on, and the gate voltage VG1 is quickly raised after being pulled up by the PMOS transistor MP2, and the driving transistor M1 and the proportional transistor M2 are fully turned on; When the PWM signal changes from a high level to a low level, the output of the inverter INV1 changes from a low level to a high level. The PMOS transistors MP1 and MP2 are turned off, and the weak NMOS transistor MN1 is turned on. The gate voltage VG1 of the driving transistor M1 gradually decreases, and the driving transistor M1 and the proportional transistor M2 are gradually turned off. The source voltage VD1 of the D-GaN is pulled up by the D-GaN. When the gate-source voltage of the D-GaN is reverse-biased, the D-GaN is turned off. After a delay of about 100 ns through the delay circuit Delay2, the strong driving transistor MN2 is turned on, and the driving transistor M1 and the proportional transistor M2 are fully turned off; Among them, the delay circuit Delay1 is a low-level delay, and the delay circuit Delay2 is a high-level delay.

[0021] The proportional sampling module is used to achieve low-loss current sampling through a current mirror and operational amplifier feedback; Specifically: The proportional sampling module includes a driving transistor M1, a proportional transistor M2, an operational amplifier OP1, a source follower M3, a current mirror M4, a current mirror M5, and a sampling resistor Rcs; The drain terminals of the driving transistor M1 and the proportional transistor M2 are respectively connected to the positive input terminal and the negative input terminal of the operational amplifier OP1. The output terminal of the operational amplifier OP1 is connected to the gate of the source follower M3. The source of the source follower M3 is connected to the drain of the proportional transistor M2. The drain of the source follower M3 is connected to the current mirror M4 and the current mirror M5. The outputs of the current mirror M4 and the current mirror M5 are connected to the resistor Rcs1; The proportional sampling module circuit operates when the power transistor is turned on. When VG1 is at a high level, the driving transistor M1 and the proportional transistor M2 are turned on, and the D-GaN power transistor is turned on. The current I1 passing through the D-GaN power transistor generates a voltage drop across the driving transistor M1, and its value is

[0022] where Rdson_M1 is the on-resistance of the driving transistor M1. When the positive input terminal of the operational amplifier OP1 is greater than the negative input terminal, the output terminal of the operational amplifier OP1 raises to turn on the transistor M3, generating a current I2 that flows through the proportional transistor M2 to form a voltage drop and is fed back to the negative input terminal of the operational amplifier OP1. Eventually, the positive input terminal of the operational amplifier OP1 is equal to the negative input terminal, and we get

[0023] We get

[0024] Assume that the size of the driving transistor M1 is k times the size of the proportional transistor M2, and we get

[0025] We get

[0026] Since the current mirrors M4 and M5 are in an m:1 relationship, we get

[0027] It can be seen that the current decreases by a factor of 1 / (k*m) from I1 to I3. Under the condition of the same Vcs voltage, the loss of the sampling resistor decreases by a factor of 1 / (k*m).

[0028] Fast discharge module, fast discharge voltage clamping circuit TVS; The fast discharge voltage clamping circuit TVS is connected to the common terminal of the driving transistor M1 and D-GaN.

[0029] The TVS of the fast discharge voltage clamping circuit operates when the power transistor is turned off. When VG1 is at a low level, the driving transistor M1 is turned off, and the source potential VD1 of the D-GaN power transistor rises. When the potential of VD1 reaches the turn-off threshold voltage of the D-GaN power transistor, the D-GaN power transistor turns off. During the turn-off process of the D-GaN power transistor, the voltage at its drain terminal rises, causing the source potential VD1 to further rise. When the potential of VD1 exceeds the breakdown voltage of the driving transistor M1, the driving transistor M1 is broken down, resulting in the D-GaN turning on again. This abnormal turn-on will cause damage to the D-GaN power transistor. Therefore, the TVS of the fast discharge voltage clamping circuit needs to operate before the driving transistor M1 is broken down. Usually, the operating voltage of the TVS of the fast discharge voltage clamping circuit can be set between the turn-off threshold voltage of the D-GaN and the breakdown voltage of the driving transistor M1.

[0030] As Figure 2 shown, it is a schematic diagram of the discharge tube and the driving transistor of the present invention. PAD_A is the PAD position connected to the D-GaN power transistor, PAD_B is the PAD position connected to the ground, TVS is the position of the fast discharge voltage clamping circuit, and M1 is the position of the driving transistor. According to the current direction, it is required that the position of the fast discharge voltage clamping circuit is before the position of the driving transistor; Among them, for the CUP (circuit placed under the PAD) structure, the position of PAD_A can be stacked on the position of the TVS of the fast discharge voltage clamping circuit, and the position of PAD_B can be stacked on the position of the driving transistor M1.

[0031] Merely by way of example, the present invention has been applied to a flyback power converter. However, it will be recognized that the present invention has a wider scope of application.

[0032] The above has described in detail an embodiment of the present invention, but the content described is only the preferred embodiment of the present invention and cannot be considered as used to limit the scope of implementation of the present invention. All equal changes and improvements made according to the scope of the application of the present invention should still fall within the scope covered by the patent of the present invention.

Claims

1. A D-GaN drive circuit, characterized in that, include: Segmented drive module, used to adjust the drive strength in stages according to the PWM signal; Ratio sampling module for low-loss current sampling via current mirror and op amp feedback; The fast discharge module uses TVS devices to discharge residual charge during the shutdown phase; The segmented driving module is electrically connected to the gates of the driving tube M1 and the proportional tube M2 of the proportional sampling module; The driving tube M1 of the proportional sampling module is electrically connected to the fast discharge module.

2. The D-GaN drive circuit according to claim 1, characterized in that, The segmented driving module comprises: Inverter INV1, weak drive unit and strong drive unit; The input end of the inverter INV1 is connected to a PWM signal; The weak drive unit includes an NMOS tube MN1 and a PMOS tube MP1; The strong driving unit includes an NMOS tube MN2 and a PMOS tube MP2; The weak driving unit and the strong driving unit are connected in time-sharing manner through a delay circuit; The delay circuit includes a delay circuit Delay1 and a delay circuit Delay2.

3. The D-GaN drive circuit according to claim 2, characterized in that, The output end of the inverter INV1 is connected to the gates of the PMOS tube MP1 and the NMOS tube MN1, and the output end of the inverter INV1 is also connected to the inputs of the delay circuit Delay1 and the delay circuit Delay2; The PMOS tube MP2 and the NMOS tube MN2 are connected to the outputs of the delay circuit Delay1 and the delay circuit Delay2 respectively; The drain ends of the PMOS tube MP1, the PMOS tube MP2, the NMOS tube MN1, and the NMOS tube MN2 are connected to the gates of the driving tube M1 and the proportional tube M2.

4. The D-GaN drive circuit according to claim 2, characterized in that, The delay time of the delay circuit Delay1 and the delay circuit Delay2 is 50-200ns.

5. The D-GaN drive circuit according to claim 1, characterized in that, The proportional sampling module comprises: Driving tube M1, proportional tube M2, operational amplifier OP1, source follower M3, current mirror M4, current mirror M5 and sampling resistor Rcs; The drain ends of the driving tube M1 and the proportional tube M2 are respectively connected to the positive input end and the negative input end of the operational amplifier OP1; The output terminal of the operational amplifier OP1 is connected to the gate of the source follower M3, the source of the source follower M3 is connected to the drain of the proportional tube M2, the drain of the source follower M3 is connected to the current mirror M4 and the current mirror M5, and the outputs of the current mirror M4 and the current mirror M5 are connected to the resistor Rcs1.

6. The D-GaN drive circuit according to claim 5, characterized in that, The size ratio of the driving tube M1 and the proportional tube M2 is k:1, and the value range of k is 500≤k≤2000.

7. The D-GaN drive circuit according to claim 5, characterized in that, The mirror ratio of the current mirror M4 to the current mirror M5 is m:1, and the value range of m is 1≤m≤10.

8. The D-GaN drive circuit according to claim 1, characterized in that, The TVS breakdown voltage of the fast discharge module is set to 1.2-1.5 times the D-GaN turn-off threshold voltage.

9. A flyback switching power supply, characterized in that, A D-GaN driving circuit comprising any one of claims 1 to 8.

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