A D-GaN drive circuit

Abstract

The present invention relates to the field of integrated circuit technology, and discloses a D-GaN drive circuit, a segmented drive module, which adopts a weak drive-strong drive segmented control strategy, combines a delay circuit to dynamically adjust the drive strength, reduces the voltage mutation rate during the switching process, thereby suppressing EMI; a proportional sampling module, based on the operational amplifier feedback and current mirror structure, samples the main power transistor current after reducing it proportionally, making the sampling resistor loss approach zero, improving the system conversion efficiency, alleviating the deterioration of the dynamic on-resistance, and achieving low-loss current sampling; a fast discharge module, which uses a TVS device to discharge the residual charge during the turn-off stage, and adopts a precise fast discharge voltage clamping circuit to quickly discharge the gate charge through a transient voltage suppressor (TVS) during the turn-off stage, avoiding device breakdown caused by voltage overshoot, and solving the problems of poor gate reliability, serious EMI interference, and deterioration of the dynamic on-resistance in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a D-GaN drive circuit. Background Art

[0002] Thanks to the advantages of "high frequency, high efficiency, and miniaturization", GaN technology is accelerating its penetration into fields such as communication, new energy, and AI.

[0003] Due to its characteristics such as high frequency, high power density, and low on-resistance, GaN (depletion-mode gallium nitride) has been widely used in multiple fields such as fast charging adapters, data center power supplies, photovoltaic inverters, energy storage systems, and 5G base stations.

[0004] GaN is gradually replacing SiC in the on-board charger (OBC) and high-voltage inverter of new energy vehicles. Currently, mainstream domestic and foreign manufacturers are focusing on optimizing the D-GaN cascade structure, but still face challenges in solving gate reliability and EMI problems. Issues such as dynamic on-resistance degradation, gate reliability defects, and insufficient dynamic avalanche tolerance need to be avoided in applications.

[0005] Based on this, the present invention proposes a D-GaN drive circuit. Summary of the Invention

[0006] The purpose of the present invention is to provide a D-GaN drive circuit, which realizes low-EMI, high-reliability, and high-efficiency power control through segmented driving, proportional sampling, and fast-discharge voltage clamping techniques.

[0007] The purpose of the present invention can be achieved through the following technical solutions:

[0008] First aspect: The present invention provides a D-GaN drive circuit, including:

[0009] A segmented driving module for adjusting the driving strength in stages according to the PWM signal;

[0010] A proportional sampling module for realizing low-loss current sampling through current mirror and operational amplifier feedback;

[0011] A fast-discharge module that uses a TVS device to discharge residual charges during the turn-off stage.

[0012] As a further solution of the present invention: The segmented driving module includes:

[0013] An inverter INV1, a weak driving unit, and a strong driving unit;

[0014] The input end of the inverter INV1 is connected to the PWM signal;

[0015] The weak driving unit includes an NMOS transistor MN1 and a PMOS transistor MP1;

[0016] The strong driving unit includes an NMOS transistor MN2 and a PMOS transistor MP2;

[0017] The weak driving unit and the strong driving unit are time-sharingly conducted via a delay circuit;

[0018] The delay circuit includes a delay circuit Delay1 and a delay circuit Delay2.

[0019] As a further solution of the present invention: the output end of the inverter INV1 is connected to the gates of the PMOS transistor MP1 and the NMOS transistor MN1, and the output end of the inverter INV1 is also connected to the inputs of the delay circuit Delay1 and the delay circuit Delay2;

[0020] The PMOS transistor MP2 and the NMOS transistor MN2 are connected to the outputs of the delay circuit Delay1 and the delay circuit Delay2 respectively;

[0021] The drain ends of the PMOS transistor MP1, the PMOS transistor MP2, the NMOS transistor MN1, and the NMOS transistor MN2 are connected to the gates of the driving transistor M1 and the proportional transistor M2.

[0022] As a further solution of the present invention: the delay time of the delay circuit Delay1 and the delay circuit Delay2 is 50-200ns

[0023] As a further solution of the present invention: the proportional sampling module includes:

[0024] Driving tube M1, proportional tube M2, operational amplifier OP1, source follower M3, current mirror M4, current mirror M5 and sampling resistor Rcs;

[0025] The drain terminals of the driving tube M1 and the proportional tube M2 are connected to the positive input terminal and the negative input terminal of the operational amplifier OP1 respectively;

[0026] The output of the operational amplifier OP1 is connected to the gate of the source follower M3, the source of the source follower M3 is connected to the drain of the proportional tube M2, the drain of the source follower M3 is connected to the current mirror M4 and the current mirror M5, and the outputs of the current mirror M4 and the current mirror M5 are connected to the resistor Rcs1.

[0027] As a further solution of the present invention: the size ratio of the driving tube M1 and the proportional tube M2 is k:1, and the value range of k is 500≤k≤2000.

[0028] As a further solution of the present invention: the mirror ratio of the current mirror M4 to the current mirror M5 is m:1, and the value range of m is 1≤m≤10.

[0029] As a further solution of the present invention: the breakdown voltage of the TVS in the fast discharge module is set to 1.2 - 1.5 times the turn-off threshold voltage of D-GaN.

[0030] In a second aspect, the present invention provides a flyback switching power supply, including the above-mentioned D-GaN drive circuit.

[0031] Advantages of the present invention: The present invention provides a D-GaN drive circuit, which adopts a weak drive - strong drive segmented control strategy, combines a delay circuit to dynamically adjust the drive strength, reduces the voltage mutation rate during the switching process, thereby suppressing EMI;

[0032] Adopts a proportional sampling circuit, based on the operational amplifier feedback and current mirror structure, samples the main power transistor current after reducing it proportionally, making the sampling resistor loss approach zero, improving the system conversion efficiency, and alleviating the deterioration of the dynamic on-resistance;

[0033] Adopts an accurate fast discharge voltage clamping circuit, and quickly discharges the gate charge through a transient voltage suppressor (TVS) during the turn-off stage, avoiding device breakdown caused by voltage overshoot, and solving the gate reliability problem;

[0034] TVS: Suppresses voltage spikes, avoids abnormal switching and damage of D-GaN after the lower drive transistor breaks down; charge balance, adapts to D-GaN devices with different parasitic junction capacitances. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present invention will be further described below with reference to the accompanying drawings.

[0036] Figure 1 is a schematic structural diagram of the D-GaN drive circuit of the present invention;

[0037] Figure 2 is a schematic structural diagram of the discharge tube and the drive tube of the present invention;

[0038] Figure 3 is a schematic structural diagram of a typical application circuit of D-GaN drive. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0040] Such as Figure 3The figure shows a typical application circuit for D-GaN drive, including a drive circuit, a transformer, an output rectifier circuit D1, a D-GaN power transistor, a drive transistor M1, and a power transistor current sampling circuit Rcs. The drain of the D-GaN power transistor is connected to the primary winding, the source of the D-GaN power transistor is connected to the drive transistor M1, the source of the drive transistor M1 is connected to the sampling resistor Rcs, and the output rectifier circuit is connected to the secondary winding. This part is a conventional circuit of the prior art and will not be elaborated.

[0041] Please refer to Figure 1 As shown in the figure, the present invention is a D-GaN drive circuit, including a segmented drive module, and the segmented drive module is used to adjust the drive strength in stages according to the PWM signal;

[0042] Specifically: the segmented drive module includes an inverter INV1, an NMOS transistor MN1, an NMOS transistor MN2, a PMOS transistor MP1, a PMOS transistor MP2, a delay circuit Delay1, and a delay circuit Delay2;

[0043] The input terminal of the inverter INV1 is connected to the PWM signal, and the output terminal of the inverter INV1 is connected to the gates of the PMOS transistor MP1 and the NMOS transistor MN1, and the inputs of the delay circuit Delay1 and the delay circuit Delay2;

[0044] The PMOS transistor MP2 and the NMOS transistor MN2 are respectively connected to the outputs of the delay circuit Delay1 and the delay circuit Delay2, and the drains of the PMOS transistor MP1, the PMOS transistor MP2, the NMOS transistor MN1, and the NMOS transistor MN2 are commonly connected to the gates of the drive transistor M1 and the proportional transistor M2;

[0045] The working process of the segmented drive module circuit is as follows:

[0046] When the PWM signal changes from low level to high level, the output of the inverter INV1 changes from high level to low level, the NMOS transistors MN1 and MN2 are turned off, the weak PMOS transistor MP1 is turned on, the gate voltage VG1 of the drive transistor M1 is gradually raised, the drive transistor M1 and the proportional transistor M2 are gradually turned on, the drive transistor M1 pulls down the source voltage VD1 of the D-GaN and then the D-GaN is turned on. After a delay of about 100 ns by the delay circuit Delay1, the strong drive transistor MP2 is turned on, and the gate voltage VG1 is pulled up by the PMOS transistor MP2 and then quickly becomes high, and the drive transistor M1 and the proportional transistor M2 are fully turned on;

[0047] When the PWM signal changes from high level to low level, the output of the inverter INV1 changes from low level to high level, the PMOS transistors MP1 and MP2 are turned off, and the weak NMOS transistor MN1 is turned on. The gate voltage VG1 of the driving transistor M1 gradually decreases, and the driving transistor M1 and the proportional transistor M2 are gradually turned off. The source voltage VD1 of the D-GaN is pulled up by the D-GaN. When the gate-source voltage of the D-GaN is reverse-biased, the D-GaN is turned off. After a delay of about 100 ns through the delay circuit Delay2, the strong driving transistor MN2 is turned on, and the driving transistor M1 and the proportional transistor M2 are fully turned off;

[0048] Among them, the delay circuit Delay1 is a low-level delay, and the delay circuit Delay2 is a high-level delay.

[0049] The proportional sampling module is used to achieve low-loss current sampling through current mirror and operational amplifier feedback;

[0050] Specifically: the proportional sampling module includes a driving transistor M1, a proportional transistor M2, an operational amplifier OP1, a source follower M3, a current mirror M4, a current mirror M5, and a sampling resistor Rcs;

[0051] The drain terminals of the driving transistor M1 and the proportional transistor M2 are respectively connected to the positive input terminal and the negative input terminal of the operational amplifier OP1. The output terminal of the operational amplifier OP1 is connected to the gate of the source follower M3. The source of the source follower M3 is connected to the drain of the proportional transistor M2. The drain of the source follower M3 is connected to the current mirror M4 and the current mirror M5. The outputs of the current mirror M4 and the current mirror M5 are connected to the resistor Rcs1;

[0052] The proportional sampling module circuit works when the power transistor is turned on. When VG1 is at a high level, the driving transistor M1 and the proportional transistor M2 are turned on, and the D-GaN power transistor is turned on. The current I1 passing through the D-GaN power transistor generates a voltage drop on the driving transistor M1, and its value is

[0053]

[0054] In the formula, Rdson_M1 is the on-resistance of the driving transistor M1. When the positive input terminal of the operational amplifier OP1 is greater than the negative input terminal, the output terminal of the operational amplifier OP1 raises and the M3 transistor turns on, generating an I2 current that flows through the proportional transistor M2 to form a voltage drop and is fed back to the negative input terminal of the operational amplifier OP1. Finally, the positive input terminal of the operational amplifier OP1 is equal to the negative input terminal, and we get

[0055]

[0056] We get

[0057]

[0058] Assuming that the size of the driving transistor M1 is k times the size of the proportional transistor M2, we get

[0059]

[0060] obtain

[0061]

[0062] Since the current mirrors M4 and M5 are in an m:1 relationship, obtain

[0063]

[0064] Thus, it can be seen that the current decreases by a factor of 1 / (k*m) from I1 to I3. Under the condition of the same Vcs voltage, the loss of the sampling resistor decreases by a factor of 1 / (k*m).

[0065] Fast discharge module, fast discharge voltage clamping circuit TVS;

[0066] The fast discharge voltage clamping circuit TVS is connected to the common terminal of the driving transistor M1 and D-GaN.

[0067] The fast discharge voltage clamping circuit TVS operates when the power transistor is turned off. When VG1 is at a low level, the driving transistor M1 is turned off, and the source potential VD1 of the D-GaN power transistor rises. When the potential of VD1 reaches the turn-off threshold voltage of the D-GaN power transistor, the D-GaN power transistor is turned off. During the turn-off process of the D-GaN power transistor, the voltage at its drain terminal rises, resulting in a further rise in the source potential VD1. When the potential of VD exceeds the breakdown voltage of the driving transistor M1, the driving transistor M1 is broken down, causing D-GaN to conduct again. This abnormal conduction will cause damage to the D-GaN power transistor. Therefore, the fast discharge voltage clamping circuit TVS needs to operate before the driving transistor M1 is broken down. Usually, the operating voltage of the fast discharge voltage clamping circuit TVS can be set between the turn-off threshold voltage of D-GaN and the breakdown voltage of the driving transistor M1.

[0068] As Figure 2 shown, the schematic diagram of the discharge transistor and the driving transistor of the present invention. PAD_A is the PAD position connected to the D-GaN power transistor, PAD_B is the PAD position connected to the ground, TVS is the position of the fast discharge voltage clamping circuit, and M1 is the position of the driving transistor. According to the current direction, it is required that the position of the fast discharge voltage clamping circuit is before the position of the driving transistor;

[0069] Among them, for the CUP (circuit placed under the PAD) structure, the position of PAD_A can be stacked on the position of the fast discharge voltage clamping circuit TVS, and the position of PAD_B can be stacked on the position of the driving transistor M1.

[0070] Merely by way of example, the present invention has been applied to a flyback power converter. However, it will be recognized that the present invention has a wider scope of application.

[0071] The above has described in detail an embodiment of the present invention. However, the above content is only a preferred embodiment of the present invention and should not be considered as limiting the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the application of the present invention should still fall within the scope covered by the patent of the present invention.

Claims

1. A D-GaN drive circuit, characterized in that, include: Segmented drive module, used to adjust the drive strength in stages according to the PWM signal; Ratio sampling module for low-loss current sampling through current mirror and op amp feedback; Fast discharge module, using TVS devices to discharge residual charge during the shutdown phase; The segmented driving module is electrically connected to the gates of the driving tube M1 and the proportional tube M2 of the proportional sampling module; The driving tube M1 of the proportional sampling module is electrically connected to the fast discharge module; The segmented driving module includes: Inverter INV1, weak drive unit and strong drive unit; The input end of the inverter INV1 is connected to a PWM signal; The weak drive unit includes an NMOS transistor MN1 and a PMOS transistor MP1; The strong driving unit includes an NMOS transistor MN2 and a PMOS transistor MP2; The weak driving unit and the strong driving unit are time-sharingly conducted via a delay circuit; The delay circuit includes a delay circuit Delay1 and a delay circuit Delay2.

2. The D-GaN drive circuit according to claim 1, wherein The output end of the inverter INV1 is connected to the gates of the PMOS transistor MP1 and the NMOS transistor MN1, and the output end of the inverter INV1 is also connected to the inputs of the delay circuit Delay1 and the delay circuit Delay2; The PMOS transistor MP2 and the NMOS transistor MN2 are connected to the outputs of the delay circuit Delay1 and the delay circuit Delay2 respectively; The drain ends of the PMOS transistor MP1, the PMOS transistor MP2, the NMOS transistor MN1, and the NMOS transistor MN2 are connected to the gates of the driving transistor M1 and the proportional transistor M2.

3. The D-GaN drive circuit according to claim 1, characterized in that, The delay time of the delay circuit Delay1 and the delay circuit Delay2 is 50-200ns.

4. The D-GaN drive circuit according to claim 1, characterized in that, The proportional sampling module includes: Driving tube M1, proportional tube M2, operational amplifier OP1, source follower M3, current mirror M4, current mirror M5 and sampling resistor Rcs; The drain terminals of the driving tube M1 and the proportional tube M2 are connected to the positive input terminal and the negative input terminal of the operational amplifier OP1 respectively; The output of the operational amplifier OP1 is connected to the gate of the source follower M3, the source of the source follower M3 is connected to the drain of the proportional tube M2, the drain of the source follower M3 is connected to the current mirror M4 and the current mirror M5, and the outputs of the current mirror M4 and the current mirror M5 are connected to the resistor Rcs1.

5. The D-GaN driving circuit according to claim 4, wherein The size ratio of the driving tube M1 and the proportional tube M2 is k:1, and the value range of k is 500≤k≤2000.

6. The D-GaN driving circuit according to claim 4, characterized in that The mirror ratio of the current mirror M4 to the current mirror M5 is m:1, and the value range of m is 1≤m≤10.

7. The D-GaN driving circuit according to claim 1, characterized in that The TVS breakdown voltage of the fast discharge module is set to 1.2-1.5 times the D-GaN turn-off threshold voltage.

8. A flyback switching power supply, characterized in that A D-GaN driving circuit comprising the D-GaN driving circuit according to any one of claims 1 to 7.

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