Sensor pixel unit, signal processing circuit and electronic equipment

Abstract

The embodiment of the invention discloses a sensor pixel unit, a signal processing circuit and electronic equipment, and the sensor pixel unit comprises a signal collection module, a transmission tube, a signal processing module and a signal output module. The signal acquisition module is used for receiving an optical signal to generate photoelectric charges and executing a reset operation according to the control of a first feedback signal; the transmission tube is used for transmitting the photoelectric charge generated by the signal acquisition module to the signal processing module according to the control of an external transmission signal; the signal processing module is used for generating a first output signal when the transmission tube is not conducted; when the transmission tube is conducted, a second output signal is generated by the photoelectric charges accumulated in the exposure duration and transmitted by the signal acquisition module; and the signal output module is used for outputting the first output signal or the second output signal according to the control of an external control signal.

Description

Technical Field

[0001] The present disclosure relates to the technical field of image sensors, and in particular, to a sensor pixel unit, a signal processing circuit, and an electronic device. Background Art

[0002] Image sensors have been widely used in fields such as digital cameras, mobile phones, medical, automotive, drones, and machine recognition. In particular, the rapid development of complementary metal oxide semiconductor (CMOS) image sensor technology has led to higher requirements for the output image quality of image sensors. Dynamic range is an important evaluation index of optoelectronic image sensors. Summary of the Invention

[0003] According to one aspect of an embodiment of the present disclosure, there is provided a sensor pixel unit, including: a signal acquisition module, a transfer tube, a signal processing module, and a signal output module;

[0004] The signal acquisition module is configured to receive an optical signal to generate photoelectric charges, and perform a reset operation under the control of a first feedback signal;

[0005] The transfer tube is configured to transfer the photoelectric charges generated by the signal acquisition module to the signal processing module under the control of an external transfer signal;

[0006] The signal processing module is configured to generate a first output signal when the transfer tube is not conducting, and generate a second output signal based on the photoelectric charges accumulated during an exposure period transmitted by the signal acquisition module when the transfer tube is conducting;

[0007] The signal output module is configured to output the first output signal or the second output signal under the control of an external control signal.

[0008] Optionally, the signal acquisition module includes: a photodiode and a first reset tube;

[0009] The anode terminal of the photodiode is grounded, and the cathode terminal is connected to the source terminal of the first reset tube;

[0010] The drain terminal of the first reset tube receives a power supply signal, and the gate terminal receives the first feedback signal, and is configured to perform a reset on the photodiode under the control of the first feedback signal.

[0011] Optionally, the signal acquisition module further includes: a first switching transistor;

[0012] The source terminal of the first switching transistor is connected to the gate terminal of the first reset transistor, the drain terminal is connected to the first feedback signal, and the gate terminal receives a first switching signal. The first switching transistor is configured to conduct or turn off according to the control of the first switching signal. When the first switching transistor is conducting, the first feedback signal is transmitted to the first reset transistor.

[0013] Optionally, the signal processing module includes: a floating diffusion region, a second reset transistor, and a second switching transistor;

[0014] One end of the floating diffusion region is grounded, and the other end is connected to the source terminal of the second reset transistor as the connection terminal of the signal processing module; the connection terminal is connected to the transfer transistor and the signal output module;

[0015] The source terminal of the second reset transistor is connected to the floating diffusion region, the drain terminal receives a power supply signal, and the gate terminal receives a second feedback signal through the second switching transistor, and is configured to reset the floating diffusion region according to the second feedback signal;

[0016] The second switching transistor is configured to conduct or turn off according to the control of a second switching signal. When the second switching transistor is conducting, the second feedback signal is introduced into the second reset transistor.

[0017] Optionally, the floating diffusion region performs reset when the second reset transistor is conducting; when the second reset transistor is off and the transfer transistor is conducting, the floating diffusion region receives and stores the photo-generated charges generated by the photodiode in the signal acquisition module; and outputs the second output signal based on the stored photo-generated charges according to the control of the external control signal.

[0018] Optionally, the signal output module includes: a source follower transistor and a selection transistor;

[0019] The gate terminal of the source follower transistor is connected to the signal processing module, the source terminal is connected to the selection transistor, and the drain terminal receives a power supply signal; it is configured to detect and follow the charge change of the floating diffusion region to determine the first output signal or the second output signal;

[0020] The drain terminal of the selection transistor is connected to the source terminal of the source follower transistor, the source terminal is connected to the signal quantization module, and the gate terminal receives an external control signal, and determines whether to output the first output signal or the second output signal according to the control of the external control signal.

[0021] According to another aspect of the embodiments of the present disclosure, a signal processing circuit is provided, including: a pixel array composed of sensor pixel units of m rows * n columns as described in any of the above embodiments, and n column processors; wherein, each of the column processors corresponds to m of the sensor pixel units in one column; m and n are integers greater than or equal to 1 respectively.

[0022] The pixel array is configured to quantize pixel signals row by row for each row of the sensor pixel units according to the control of an external control signal, output n first output signals or second output signals, and send them to the n column processors respectively.

[0023] The column processor is configured to determine an encoded signal corresponding to the sensor pixel unit according to the received first output signal and second output signal, and obtain a first feedback signal and a second feedback signal based on the encoded signal, and control the operation of the sensor pixel unit through the first feedback signal and the second feedback signal.

[0024] Optionally, the column processor includes: a comparator, a first feedback circuit, and a second feedback circuit.

[0025] The negative input terminal of the comparator is connected to the output terminal of the sensor pixel unit, configured to receive the first output signal or the second output signal, the positive input terminal receives a reference signal, the output terminal outputs the encoded signal, and the output terminal is respectively connected to the input terminals of the first feedback circuit and the second feedback circuit.

[0026] The input terminal of the first feedback circuit is connected to the output terminal of the comparator, and the output terminal outputs the first feedback signal.

[0027] The input terminal of the second feedback circuit is connected to the output terminal of the comparator, and the output terminal outputs the second feedback signal.

[0028] Optionally, the first feedback circuit includes a first AND logic circuit and a first OR logic circuit.

[0029] One input terminal of the first AND logic circuit serves as the input terminal of the first feedback circuit and is connected to the output terminal of the comparator; the other input terminal receives a first AND signal; the output terminal is connected to one input terminal of the first OR logic circuit.

[0030] One input terminal of the first OR logic circuit is connected to the output terminal of the first AND logic circuit, the other input terminal receives a first OR signal; the output terminal outputs the first feedback signal.

[0031] Optionally, the second feedback circuit includes a second AND logic circuit and a second OR logic circuit.

[0032] One input terminal of the second AND logic circuit serves as the input terminal of the second feedback circuit and is connected to the output terminal of the comparator; the other input terminal receives a second AND signal; the output terminal is connected to one input terminal of the second OR logic circuit;

[0033] One input terminal of the second OR logic circuit is connected to the output terminal of the second AND logic circuit, and the other input terminal receives a second OR signal; the output terminal outputs the second feedback signal.

[0034] Optionally, it further includes: n digital readout circuits, and each of the digital readout circuits corresponds to one of the column processors;

[0035] The input terminal of the digital readout circuit is connected to the output terminal of the comparator in the corresponding column processor, and is used to read out the encoded signal output by the comparator at every preset time interval to obtain a digital sequence.

[0036] Optionally, it further includes: n digital encoding circuits, and each of the digital encoding circuits corresponds to one of the digital readout circuits;

[0037] The input terminal of the digital encoding circuit is connected to the output terminal of the corresponding digital readout circuit, and receives the digital sequence output by the digital readout circuit for signal compression processing to obtain an encoded value.

[0038] Optionally, it further includes: n double-sampling readout circuits, and each of the double-sampling readout circuits corresponds to m of the sensor pixel units in one column;

[0039] The input terminal of the double-sampling readout circuit is connected to the output terminal of the sensor pixel unit. When the sensor pixel unit is in the signal readout state, it continuously reads out the first output signal and the second output signal at adjacent moments, and determines and outputs the exposure charge amount based on the first output signal and the second output signal.

[0040] According to another aspect of the embodiments of the present disclosure, there is provided an electronic device, including: a processor, and a memory communicatively connected to the processor, and further including the sensor pixel unit described in any one of the above embodiments or the signal processing circuit described in any one of the above embodiments;

[0041] The memory stores computer-executable instructions;

[0042] The processor executes the computer-executable instructions stored in the memory to control the sensor pixel unit or the signal processing circuit.

[0043] Optionally, the electronic device is incorporated as any one of the following: a pulsed camera, a high-speed camera, an audio / video player, a navigation device, a fixed-position terminal, an entertainment unit, a smart phone, a communication device, a device in a motor vehicle, a camera, a sports or wearable camera, a detection device, a flight device, a medical device, a security device.

[0044] A sensor pixel unit, a signal processing circuit, and an electronic device provided according to the above embodiments of the present disclosure include: a signal acquisition module, a transfer tube, a signal processing module, and a signal output module; the signal acquisition module is configured to receive an optical signal to generate photoelectric charges and perform a reset operation under the control of a first feedback signal; the transfer tube is configured to transfer the photoelectric charges generated by the signal acquisition module to the signal processing module under the control of an external transfer signal; the signal processing module is configured to generate a first output signal when the transfer tube is not conducting; and generate a second output signal from the photoelectric charges accumulated during an exposure duration transferred by the signal acquisition module when the transfer tube is conducting; the signal output module is configured to output the first output signal or the second output signal under the control of an external control signal; in this embodiment, the exposure time of the sensor pixel unit is adjustable through the first feedback signal and the second feedback signal, whether to read out the charges stored in the signal acquisition module is determined by the amount of signal change caused by the charge change in the signal processing module, and the efficiency of analog signal processing is improved by synchronously outputting the amount of signal accumulated on the signal acquisition module.

[0045] The technical solutions of the present disclosure will be further described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0046] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0047] Referring to the drawings, the present disclosure can be more clearly understood from the following detailed description, where:

[0048] Figure 1 is a schematic circuit diagram of a sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0049] Figure 2 is a schematic circuit diagram of a signal acquisition module in a sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0050] Figure 3 is a schematic circuit diagram of a signal processing module in a sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0051] Figure 4It is a schematic diagram of an optional circuit structure of a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0052] Figure 5 It is a schematic diagram of the circuit structure of a signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0053] Figure 6a It is a schematic diagram of the circuit structure of a column processor in the signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0054] Figure 6b It is a schematic diagram of the circuit structure of a column processor in the signal processing circuit provided by another exemplary embodiment of the present disclosure;

[0055] Figure 7a It is a schematic diagram of the circuit structure of a signal processing circuit provided by another exemplary embodiment of the present disclosure;

[0056] Figure 7b It is a schematic diagram of the connection between a column processor and other circuits in the signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0057] Figure 8a It is a schematic diagram of the timing of multiple signals received in a pixel unit in the signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0058] Figure 8b It is a timing diagram of the imaging partition control of the m-row pixel units in the signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0059] Figure 8c It is a schematic diagram of the digital and analog outputs in the signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0060] Figure 9 It is a diagram of the original data format output by any pixel in the signal processing circuit provided by an exemplary embodiment of the present disclosure;

[0061] Figure 10 The figure illustrates a block diagram of an electronic device according to an embodiment of the present disclosure. Detailed implementation manners

[0062] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. It should be understood that the present disclosure is not limited by the exemplary embodiments described herein.

[0063] It should be noted that: unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and values set forth in these embodiments do not limit the scope of the present disclosure.

[0064] Those skilled in the art can understand that terms such as "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate an inevitable logical order between them.

[0065] It should also be understood that in the embodiments of the present disclosure, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0066] It should also be understood that for any component, data or structure mentioned in the embodiments of the present disclosure, in the absence of a clear limitation or a contrary indication in the context, it is generally understood to be one or more.

[0067] In addition, the term "and / or" in the present disclosure is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present disclosure generally represents an "or" relationship between the associated objects before and after. The data referred to in the present disclosure may include unstructured data such as text, images, videos, etc., or may also be structured data.

[0068] It should also be understood that the description of each embodiment in the present disclosure emphasizes the differences between the embodiments, and their similarities or similarities can be referred to each other. For the sake of brevity, they will not be elaborated one by one.

[0069] At the same time, it should be understood that for the convenience of description, the dimensions of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0070] The following description of at least one exemplary embodiment is actually merely illustrative and in no way limits the present disclosure and its application or use.

[0071] Technologies, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the said technologies, methods and devices should be regarded as part of the specification.

[0072] It should be noted that like reference numerals and letters indicate similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0073] In the process of implementing the present disclosure, the inventors found that in order to improve the dynamic range of an optoelectronic image sensor, there are currently three main methods: The first method is multi-frame exposure synthesis, where images from under-exposure to over-exposure are continuously output in time and then fused to obtain a high-dynamic-range image. When the image sensor or the shooting object moves, since the images from under-exposure to over-exposure are obtained at different time points, motion artifacts, blurring, etc. may occur in the synthesized image. The second method is to set two photodiodes (PDs) of different sizes in the pixel, and the accumulated charge amounts in the two photodiodes of different sizes are read out each time, so as to take into account the imaging of low-dark regions and high-brightness regions. However, since two photodiodes of different sizes are separately integrated in the pixel, the pixel area and the complexity of preparation in the process are increased, and the signals in the two photodiodes of different sizes need to be read out simultaneously each time, which increases the time for each signal readout and limits the imaging speed. The third method is the LOFIC (Lateral Over Flow Integration Capacitor) technology. During exposure, as long as the PD reaches half of the saturation well capacity, the relevant circuit will be triggered to transfer the charge on the PD to a separately added storage capacitor, increasing the charge storage capacity of the pixel, thereby achieving high-dynamic-range imaging. The main challenge of this technology lies in efficiently manufacturing a large-capacity storage capacitor, so new pixel preparation processes need to be developed.

[0074] The technical approaches for the above three methods to achieve high dynamic range mainly include the synthesis of exposure images at different times, and the addition of PDs or capacitors in the pixel to adjust the sensitivity of the pixel, which pose relatively high requirements for algorithms and pixel preparation processes.

[0075] Figure 1 It is a schematic circuit diagram of a sensor pixel unit provided by an exemplary embodiment of the present disclosure. As Figure 1 shown, it includes: a signal acquisition module 11, a transfer tube 12, a signal processing module 13, and a signal output module 14.

[0076] The signal acquisition module 11 is configured to receive an optical signal to generate photoelectric charges and perform a reset operation under the control of a first feedback signal.

[0077] Optionally, the main components in the signal acquisition module 11 can be optoelectronic conversion components (e.g., photodiodes, etc.), which can receive optical signals during the exposure time and convert the optical signals into photoelectric charges; and store the photoelectric charges before transmitting them to the signal processing module, and characterize the light intensity through the number of generated photoelectric charges. Before the transmission tube 12 is turned on, the photoelectric charges are stored in the signal acquisition module. Among them, the first feedback signal can be determined through processing the signal output by the signal output module 14, that is, the automatic reset control of the signal acquisition module 11 is formed. When the first feedback signal is at a high level, the signal acquisition module 11 is controlled to perform a reset operation; when the first feedback signal is at a low level, the signal acquisition module 11 does not perform a reset operation.

[0078] The transmission tube 12 is used to transmit the photoelectric charges generated by the signal acquisition module 11 to the signal processing module 13 according to the control of an external transmission signal.

[0079] In this embodiment, the transmission tube 12 is turned on or off according to the control of the external transmission signal Φ TX When it is turned on, it connects the signal acquisition module 11 and the signal processing module 13, so that the photoelectric charges collected by the signal acquisition module 11 after the last reset before the conduction moment are transmitted to the signal processing module 13, realizing that the exposure time of the signal acquisition module 11 is determined according to the light intensity. The stronger the light intensity, the more frequently the reset of the signal acquisition module 11 is controlled by the first feedback signal determined according to the signal output by the sensor pixel unit, and the shorter the time between the last reset and the conduction moment of the transmission tube 12. Therefore, high-dynamic-range imaging is achieved through the control of the exposure time in this embodiment.

[0080] The signal processing module 13 is used to generate a first output signal when the transmission tube 12 is not turned on, and generate a second output signal based on the photoelectric charges accumulated during the exposure time transmitted by the signal acquisition module 11 when the transmission tube is turned on.

[0081] Optionally, in the case of light illumination, the signal processing module 13 also generates photoelectric charges to realize the light detection function, and is reset when receiving an externally input reset signal. For example, the first output signal output during reset is at a high level, and when no reset is performed, the first output signal output is at a low level. When the transmission tube 12 is turned on, the accumulated photoelectric charges in the signal acquisition module 11 are read. Optionally, the reset signal can be a second feedback signal obtained through processing the signal output by the signal output module 14. When the second feedback signal is at a high level, the signal processing module 13 performs a reset; when the second feedback signal is at a low level, the signal processing module 13 sequentially reads the photoelectric charges generated by each of the k signal acquisition modules 11 in the signal acquisition module 11.

[0082] A signal output module 14, configured to output a first output signal or a second output signal based on an external control signal.

[0083] Optionally, the first output signal and the second output signal may include at least one of the following signals: a pulse signal, a potential signal, a numerical value with a limited range, etc.

[0084] A sensor pixel unit provided by the above embodiments of the present disclosure includes: a signal acquisition module, a transfer tube, a signal processing module, and a signal output module; the signal acquisition module is configured to receive an optical signal to generate photoelectric charges, and perform a reset operation according to the control of a first feedback signal; the transfer tube is configured to transfer the photoelectric charges generated by the signal acquisition module to the signal processing module according to the control of an external transfer signal; the signal processing module is configured to generate a first output signal when the transfer tube is not conducting; when the transfer tube is conducting, generate a second output signal based on the photoelectric charges accumulated by the signal acquisition module during the exposure duration; the signal output module is configured to output the first output signal or the second output signal according to the control of an external control signal; in this embodiment, the exposure time of the sensor pixel unit is adjustable through the first feedback signal and the second feedback signal, and it is determined whether to read the charges stored in the signal acquisition module according to the signal change amount caused by the charge change in the signal processing module, and the efficiency of analog signal processing is improved by synchronously outputting the signal amount accumulated on the signal acquisition module.

[0085] Figure 2 It is a schematic circuit diagram of the signal acquisition module in the sensor pixel unit provided by an exemplary embodiment of the present disclosure. As Figure 2 shown, the signal acquisition module 11 includes: a photodiode 111 and a first reset tube 112;

[0086] The anode terminal of the photodiode 111 is grounded to GND, and the cathode terminal is connected to the source terminal of the first reset tube 112.

[0087] Optionally, the photodiode 111 may also be other optoelectronic conversion components that can achieve optoelectronic conversion to convert an optical signal into photoelectric charges. Under light illumination conditions, the photodiode 111 generates photoelectric charges, and before the transfer tube is conducting, the photoelectric charges are confined in the depletion region of the photodiode 111 by an energy potential well, and the photoelectric charges in the photodiode 111 gradually accumulate.

[0088] The drain terminal of the first reset tube 112 receives a power supply signal VDD, and the gate terminal receives a first feedback signal configured to perform a reset on the photodiode 111 according to the control of the first feedback signal

[0089] ​Optionally, when the photodiode 111 is reset, the cathode terminal is connected to the power supply signal VDD, and the voltage on the photodiode 111 is charged to a high level.

[0090] In this embodiment, the first reset transistor 112 is used to connect the photodiode 111 to the power supply signal VDD. When the first reset transistor 112 is turned off, the photo-generated charges obtained by converting the optical signal accumulated by the photodiode 111 are generated. When the first reset transistor 112 is closed, the photodiode 111 is turned on to the power supply signal VDD to perform reset.

[0091] As Figure 2 shown, the signal acquisition module 11 further includes: a first switching transistor 113;

[0092] The source terminal of the first switching transistor 113 is connected to the gate terminal of the first reset transistor 112, and the drain terminal is connected to the first feedback signal connection, and the gate terminal receives the first switching signal The first switching transistor 113 is configured to conduct or disconnect according to the control of the first switching signal . When the first switching transistor 113 is turned on, the first feedback signal is transmitted to the first reset transistor 112.

[0093] In this embodiment, by adding the first switching transistor 113, the control of the transmission of the first feedback signal to the first reset transistor 112 is realized. Only when the first switching signal is at a high level, the first switching transistor 113 is turned on. At this time, the first feedback signal is transmitted to the gate terminal of the first reset transistor 112 to realize the on-control of the first reset transistor 112. When the first feedback signal is at a high level, the first reset transistor 112 is turned on, and the photodiode 111 performs reset; when the first feedback signal is at a low level, the first reset transistor 112 is turned off. In this embodiment, by adding the first switching transistor 113, it is realized that the first feedback signal transmitted externally controls the first reset transistor 112, and the reset of the photodiode 111 is controlled.

[0094] Figure 3 is a schematic circuit diagram of a signal processing module in a sensor pixel unit provided by an exemplary embodiment of the present disclosure. As Figure 3 shown, the signal processing module 13 includes: a floating diffusion region 131, a second reset transistor 132, and a second switching transistor 133.

[0095] One end of the floating diffusion region 131 is grounded to GND, and the other end is connected to the source end of the second reset transistor 132 as the connection end of the signal processing module; it is connected to the transfer transistor 12 and the signal output module 13 through the connection end.

[0096] Optionally, the floating diffusion region 131 performs reset when the second reset transistor 132 is turned on; when the second reset transistor 132 is turned off and the transfer transistor 12 is turned on, the floating diffusion region 131 receives the photoelectric charges generated by the photodiode 111 of the signal acquisition module 11 to generate a second output signal.

[0097] In this embodiment, the floating diffusion region 131 is a common structure in the pixel unit of the 5T structure. The light detection function is realized through the floating diffusion region 131, and when the photodiode 111 is turned on with the signal processing module 13, the photoelectric charges generated in the photodiode 111 are read into the floating diffusion region 131.

[0098] The source end of the second reset transistor 132 is connected to the floating diffusion region 131, the drain end receives the power supply signal VDD, and the gate end receives the second feedback signal through the second switching transistor 133 for controlling the reset of the floating diffusion region 131 according to the second feedback signal

[0099] Optionally, when the second reset transistor 132 is turned on, the floating diffusion region 131 is turned on with the power supply signal VDD to realize the reset of the floating diffusion region 131, and the voltage on the floating diffusion region 131 is charged to a high level. Under the illumination condition, photoelectric charges are generated in both the photodiode 111 and the floating diffusion region 131. Among them, the voltage on the floating diffusion region 131 will gradually decrease under the action of the photoelectric charges. Usually, the floating diffusion region 131 performs reset before generating photoelectric charges.

[0100] The second switching transistor 133 is used to be turned on or off according to the control of the second switching signal When the second switching transistor 133 is turned on, the second feedback signal is introduced into the second reset transistor.

[0101] The source end of the second switching transistor 133 receives the second feedback signal the gate end receives the second switching signal and the drain end is connected to the gate end of the second reset transistor 132.

[0102] This embodiment uses the change amount of the voltage signal caused by the photoelectric charges in the floating diffusion region 131 to determine whether to reset the photoelectric charges stored in the photodiode, and synchronously outputs the signal amount accumulated on the photodiode 111 through the floating diffusion region 131.

[0103] ​The floating diffusion region 131 performs reset when the second reset transistor 132 is turned on; when the second reset transistor 132 is turned off and the transfer transistor 12 is turned on, the floating diffusion region 131 receives and stores the photo-generated charges generated by the photodiode 111 in the signal acquisition module 11; and outputs a second output signal based on the stored photo-generated charges according to the control of an external control signal Φ TX of.

[0104] Optionally, when the transfer transistor 12 is not turned on, the floating diffusion region 131 outputs a first output signal. When the floating diffusion region 131 is reset, the first output signal is a high-level first output signal, and when not reset, the first output signal is a low-level first output signal. When the transfer transistor 12 is turned on, the floating diffusion region 131 receives the photo-generated charges collected by the photodiode 111. Therefore, the second output signal output at this time corresponds to the amount of charge accumulated by the photodiode during the exposure time.

[0105] In this embodiment, whether the second reset transistor 132 is turned on depends on whether the level received at the gate terminal is high level. Only when the second feedback signal received at the gate terminal is high level, the second reset transistor 132 is turned on. And whether the second feedback signal can be transmitted to the gate terminal of the second reset transistor 132 depends on whether the second switching transistor 133 is turned on. When the second switching signal is high level, the second switching transistor 133 is turned on. By providing the second switching transistor 133 in this embodiment, it is realized to allow the externally input second feedback signal to control the second reset transistor 132; it is realized to control the reset or charge reading of the floating diffusion region 131 through the second switching signal and the second feedback signal . The transfer transistor 12 receives an external transfer signal Φ TX at every preset time interval (the preset time interval can be set according to specific application scenarios), and ends the exposure of the photodiode 111 according to the control of the external transfer signal Φ TX . At this time, the duration from the moment of the last reset (outputting high level) of the photodiode 111 before the end of the exposure moment to the end of the exposure moment is the exposure duration of the photodiode 111. That is, in this embodiment, through the first feedback signal and the second feedback signal , the reset of the photodiode 111 and the floating diffusion region 131 is controlled, the adaptive adjustment of the exposure duration of the photodiode 111 is realized, the expression ability of the pixel unit to light intensity is expanded, and thus high dynamic range imaging is realized. By adaptively adjusting the exposure duration of the photodiode 111 in this embodiment, the exposure time of the sensor pixel unit in the dark area can be adaptively increased, the signal-to-noise ratio is improved, and the quality of the collected image is enhanced.

[0106] Figure 4 is an optional circuit structure diagram of a sensor pixel unit provided by another exemplary embodiment of the present disclosure. As Figure 4 shown, in this embodiment, the signal output module 14 includes: a source follower transistor 141 and a selection transistor 142;

[0107] The gate terminal of the source follower transistor 141 is connected to the signal processing module 13, the source terminal is connected to the selection transistor 142, and the drain terminal receives the power supply signal VDD; it is used to detect and follow the charge change of the floating diffusion region 131 to determine the first output signal or the second output signal.

[0108] The drain terminal of the selection transistor 142 is connected to the source terminal of the source follower transistor 141, the source terminal is connected to the signal quantization module 13, and the gate terminal receives the external control signal Φ sel , and determines whether to output the first output signal or the second output signal according to the control of the external control signal Φ sel .

[0109] In this embodiment, the gate terminal of the source follower transistor 141 is connected to the signal processing module 13, and follows the potential change of the floating diffusion region 131 to obtain a potential signal. This process does not affect the photoelectric conversion of the photodiode 111. On the premise that the transfer tube 12 is disconnected, the source follower transistor 141 reads the potential change of the floating diffusion region 131, while the photodiode 111 continues to perform photoelectric conversion to collect charges. The selection transistor 142 selects whether to output the target signal according to the control of the external control signal Φ sel . The external control signal Φ sel can be an external clock signal or an external pulse signal, etc.; the timing of the external control signal Φ sel is set according to the specific scenario. Optionally, based on the external clock circuit, the external control signal Φ sel can be sent regularly to control the pixel selection transistor to output the first output signal or the second output signal.

[0110] Figure 5 is a circuit structure diagram of a signal processing circuit provided by an exemplary embodiment of the present disclosure. As Figure 5 shown, the signal processing circuit provided in this embodiment includes: a pixel array 510 composed of m rows * n columns of sensor pixel units 511, and n column processors 520; wherein, each column of m sensor pixel units 511 in the pixel array 510 corresponds to one column processor; each column processor 520 corresponds to each sensor pixel unit 511 among the m sensor pixel units 511 in one column; m and n are integers greater than or equal to 1 respectively.

[0111] Optionally, the signal acquisition module 11 in each sensor pixel unit 511 corresponds to a column processor 520.

[0112] The pixel array 510 is configured to quantize pixel signals row by row for each row of sensor pixel units 511 under the control of an external control signal, output n first output signals or second output signals, and send them to n column processors respectively.

[0113] In this embodiment, the signal acquisition modules 11 in each sensor pixel unit 511 output signals in sequence.

[0114] The column processor 520 is configured to determine an encoded signal corresponding to the sensor pixel unit 510 based on the received first output signal and second output signal, obtain a first feedback signal and a second feedback signal based on the encoded signal, and control the operation of the sensor pixel unit through the first feedback signal and the second feedback signal.

[0115] In this embodiment, by arranging a first switching transistor and a second switching transistor inside the sensor pixel unit (hereinafter referred to as the pixel unit) 511, the pixel unit can implement reset control according to the first feedback signal and the second feedback signal fed back by the column processor 520, thereby realizing adjustable exposure time, adaptively increasing the exposure time of the sensor pixel units in the dark area, improving the signal-to-noise ratio, and enhancing the quality of the acquired image. Moreover, by controlling the output of the pixel unit through the first feedback signal and the second feedback signal fed back by the column processor 520, the input of external signals is reduced, and the reset efficiency of the pixel unit is improved; and the number of components in the pixel unit is reduced, the size of the pixel unit is reduced, and the resolution of the image acquired by the sensor using this pixel unit is enhanced.

[0116] Figure 6a It is a schematic circuit diagram of a column processor in a signal processing circuit provided by an exemplary embodiment of the present disclosure. As Figure 6a shown, the column processor 520 includes: a comparator 521, a first feedback circuit 522, and a second feedback circuit 523.

[0117] The negative input terminal of the comparator 521 is connected to the output terminal of the sensor pixel unit 511, configured to receive the first output signal or the second output signal, the positive input terminal receives a reference signal Vth, and the output terminal outputs an encoded signal; and the output terminal is respectively connected to the input terminals of the first feedback circuit 522 and the second feedback circuit 523.

[0118] The input terminal of the first feedback circuit 522 is connected to the output terminal of the comparator 521, and the output terminal outputs a first feedback signal

[0119] The input end of the second feedback circuit 523 is connected to the output end of the comparator 521, and the output end outputs a second feedback signal

[0120] In this embodiment, the AND logic circuit determines the corresponding first feedback signal output based on the encoded signal output by the comparator and the second feedback signal to implement the control of the exposure time in the sensor pixel unit by the column processor 520.

[0121] Figure 6b is a schematic circuit diagram of the column processor in the signal processing circuit provided by another exemplary embodiment of the present disclosure. As Figure 6b shown, in this embodiment, the first feedback circuit 522 includes a first AND logic circuit 5221 and a first OR logic circuit 5222;

[0122] One input end of the first AND logic circuit 5221 serves as the input end of the first feedback circuit 522 and is connected to the output end of the comparator 521; the other input end receives the first AND signal Φ and1 ; the output end is connected to one input end of the first OR logic circuit 5222.

[0123] One input end of the first OR logic circuit 5222 is connected to the output end of the first AND logic circuit 5221, and the other input end receives the first OR signal Φ OR1 ; the output end outputs the first feedback signal

[0124] Optionally, the first AND logic circuit 5221 can perform AND logic processing on the output signal. Based on the processing logic of AND logic, it can be known that only when both inputs are high level, a high level is output, otherwise a low level is output. That is, only when the comparison result output by the comparator and the first AND signal Φ and1 are both high level, the first AND logic circuit 5221 outputs a high level. Therefore, through the first AND signal Φ and1 the output of the first AND logic circuit 5221 can be adjusted to implement the determination of the first feedback signal based on the signal output by the pixel unit And the first OR logic circuit 5222 can perform OR logic processing on the input signal. Based on the processing logic of OR logic, it can be known that when there is a high level in the two input signals, a high level is output, and only when both input signals are low level, a low level is output. Therefore, through the first OR signal Φ OR1 the level of the output first feedback signal can be directly controlled. When it is necessary to reset the photodiode, a high level signal can be directly given to the second OR signal Φ OR1 to output a high level first feedback signal

[0125] Similarly to the structure of the first feedback circuit, the second feedback circuit 523 includes a second AND logic circuit 5231 and a second OR logic circuit 5232;

[0126] One input terminal of the second AND logic circuit 5231 serves as the input terminal of the second feedback circuit 523 and is connected to the output terminal of the comparator 521; the other input terminal receives the second AND signal Φ and2 ; the output terminal is connected to one input terminal of the second OR logic circuit 5232.

[0127] One input terminal of the second OR logic circuit 5232 is connected to the output terminal of the second AND logic circuit 5231, and the other input terminal receives the second OR signal Φ OR2 ; the output terminal outputs the second feedback signal

[0128] Optionally, the second AND logic circuit 5231 can perform AND logic processing on the output signal. Based on the processing logic of the AND logic, it can be known that only when both inputs are high level, a high level is output, otherwise a low level is output. That is, only when the comparison result output by the comparator and the second AND signal Φ and2 are both high level, the second AND logic circuit 5231 outputs a high level. Therefore, through the second AND signal Φ and2 the output of the second AND logic circuit 5231 can be adjusted to implement determining the second feedback signal based on the signal output by the pixel unit And the second OR logic circuit 5232 can perform OR logic processing on the input signal. Based on the processing logic of the OR logic, it can be known that when there is one high-level input signal among the two input signals, a high level is output, and only when both input signals are low level, a low level is output. Therefore, through the second OR signal Φ OR2 the level of the output second feedback signal Φ rsty can be directly controlled. When it is necessary to reset the photodiode, a high-level signal can be directly given to the second OR signal Φ OR2 to output a high-level second feedback signal

[0129] Figure 7a is a schematic circuit diagram of a signal processing circuit provided by another exemplary embodiment of the present disclosure. As Figure 7a shown, the signal processing circuit provided in this embodiment may further include: n digital readout circuits 530, and each digital readout circuit 530 corresponds to a column processor 520.

[0130] The input end of the digital readout circuit 530 is connected to the output end of the comparator in the corresponding column processor, and is used to read out the encoded signal output by the comparator at every preset time interval to obtain a digital sequence.

[0131] Optionally, the digital sequence output by the digital readout circuit 530 is a sequence composed of 0 and 1, where 1 and 0 represent the digital output signals in the exposure control stage of the pixel unit, 1 represents the reset operation, and 0 represents not performing the reset operation.

[0132] As Figure 7a shown in the embodiment, the signal processing circuit provided in this embodiment further includes: n dual-sampling readout circuits 540, and each dual-sampling readout circuit 540 corresponds to m sensor pixel units 511 in a column;

[0133] The input end of the dual-sampling readout circuit 540 is connected to the output end of the sensor pixel unit 511. When the sensor pixel unit 511 is in the signal readout state, the first output signal and the second output signal at adjacent moments are continuously read out, and the exposure charge amount is determined based on the first output signal and the second output signal and output.

[0134] Optionally, the exposure charge amount can be determined based on the difference between the first output signal output at the previous moment of the output of the second output signal and the second output signal.

[0135] Optionally, as Figure 7a shown in the embodiment, it may further include a row control unit 550 that provides an external transfer signal Φ TX , a first switch signal , a second switch signal , and an external control signal Φ SEL for each row of pixel units. Optionally, the external transfer signal Φ TX , the first switch signal , the second switch signal , and the external control signal Φ SEL can respectively be clock signals with different periods. The row control unit 550 sequentially sends the first switch signal , the second switch signal , and the external control signal Φ SEL with a preset time sequence to each row of pixel units through preset logic. The row control unit 550 sends the external control signal Φ SEL to a row of pixel units every first preset time to implement the output control of the first output signal and the second output signal output by the pixel unit. The row control unit 550 sends the external transfer signal Φ TX to a row of pixel units every second preset time to control the conduction of the transfer tube in the pixel unit and implement the control of the output timing of the second output signal. And, the row control unit 550 passes the first switch signal and the second switching signal to implement exposure control of the photodiode and the floating diffusion region in the pixel unit. Optionally, the first switching signal and the second switching signal can be clock signals with the same period. In this embodiment, the signals output by the row control unit 550 are used to implement exposure and reset control of the pixel units in the corresponding row. Figure 7b is a schematic connection diagram of the column processor and other circuits in the signal processing circuit provided by an exemplary embodiment of the present disclosure.

[0136] Figure 8a is a schematic timing diagram of multiple signals received in the pixel unit in the signal processing circuit provided by an exemplary embodiment of the present disclosure. As Figure 8a shown, the working time of the pixel unit is divided into two intervals. The first interval is the exposure control interval, and the second interval is the signal readout interval. The interval duration between the two intervals is controlled by the input period of the external transmission signal Φ TX . Among them, in the first interval, the exposure signal is controlled. When the voltage on the floating diffusion region drops below the threshold voltage (i.e., Figure 8a the case of reaching the threshold in), the photodiode and the floating diffusion region in the pixel unit are reset. If the voltage signal does not reach the threshold voltage, no operation is performed on the photodiode and the floating diffusion region (for example, Figure 8a at time T2 in, although the first switching signal and the second switching signal are at high level, but since the first feedback signal and the second feedback signal are at low level, therefore, the photodiode and the floating diffusion region do not perform reset). In the second interval, the accumulated charge amount in the photodiode is read out by means of double sampling (determined based on the signal difference between times T5 and T6). After reading the charge amount, the photodiode and the floating diffusion region are reset (corresponding to time T6).

[0137] In the exposure control interval, the row control unit is responsible for applying Φ SEL , Φ FRx , Φ PRx , Φ TX and other signals to each pixel unit. These signals issued by the row control unit do not change with Vout and are output sequentially for each row. The column readout and control unit determines the levels of the applied Φ SEL , Φ FRy signals according to the magnitude of the voltage signal (Vout) read out when applying the Φ PRy signal. The digital output module is responsible for outputting the comparison result between the Vout signal and the threshold voltage signal.

[0138] During the signal readout period, each control voltage signal input into the pixel unit (including: external transfer signal Φ TX , first switch signal , second switch signal and external control signal Φ SEL ) are all input according to the set timing and do not change with the output signal. The signal on the photodiode is output through the double-sampling readout circuit 540.

[0139] Optionally, in an alternative embodiment, the double-sampling readout circuit 540 is controlled by an externally input clock control signal Φ READ , and cooperates with the first AND signal Φ and1 , first OR signal Φ OR1 , second AND signal Φ and2 and second OR signal Φ OR2 to read out the signal in the photodiode at a fixed frequency. As shown in Figure 8a , the reset signal V RST in the floating diffusion region is read out during the T4 period, and the signal V sig after the photoelectric charge accumulated by the photodiode in the floating diffusion region is reduced is read out during the T5 period. Optionally, during the T4 period, the second OR signal Φ OR2 is set to high level, and the second AND signal Φ and2 can be high level or low level (at this time, since the second OR signal Φ OR2 is high level, the second OR logic circuit 5232 will necessarily output high level, and the first feedback signal is high level, realizing the reset of the floating diffusion region. Therefore, the second AND signal Φ and2 can be in any situation), the first AND signal Φ and1 and the first OR signal Φ OR1 are set to low level (to make the first feedback signal low level and control the photodiode not to perform reset). After the floating diffusion region is reset, the signal on the floating diffusion region is read out, that is, the signal V RST is obtained. During the T5 period, the second AND signal Φ and2 and the second OR signal Φ OR2 are set to low level, the first AND signal Φ and1 and the first OR signal Φ OR1 are set to low level, that is, at this time, neither the photodiode nor the floating diffusion region performs reset, and the external transfer signal Φ TX is set to high level (to turn on the transfer transistor). After the charge on the photodiode is transferred to the floating diffusion region, the signal V sig is read out. During the T6 period, the first OR signal Φ OR1 and the second OR signal Φ OR2Set to high (at this time, regardless of whether the second output signal is high or low, after being processed by the first OR logic circuit and the second OR logic circuit, both the first feedback signal and the second feedback signal are at a high level), to reset the photodiode and the floating diffusion region. Optionally, in the above example, the exposure charge determined by the dual-sampling readout circuit 540 can be determined based on the difference between the first output signal output during the T4 period and the second output signal output during the T5 period, that is, exposure charge = V RST -V sig .

[0140] Figure 8b is the imaging partition control timing diagram of the m-row pixel units in the signal processing circuit provided by an exemplary embodiment of the present disclosure. As Figure 8b shown, each pixel unit 511 includes two intervals of exposure control and signal readout during image acquisition. There is an exposure control interval between every two signal readout intervals. The exposure control interval is responsible for reading out the signal of the floating diffusion region and determining whether to reset the photodiode signal, and determines the exposure time on the photodiode at the signal readout stage. The row controller sequentially performs signal readout on each row of pixel units row by row. Usually, after performing signal readout on a row of pixel units, the photodiode and the floating diffusion region are reset, and then the exposure control interval.

[0141] According to Figure 8b shown, for a specific point X in the imaging array, its corresponding digital and analog outputs are as Figure 8c shown,[[]] Figure 8c is the digital and analog output schematic diagram of the signal processing circuit provided by an exemplary embodiment of the present disclosure. Among them, 1 and 0 represent the digital output signals in the exposure control stage, 1 represents the reset operation, 0 represents not performing the reset operation, and N represents the analog output signal. The t0 moment represents the initial moment. The transfer of the signal of the photodiode (PD) in the pixel unit and the reset action of the floating diffusion region (FD) are both completed, so that the signals in the PD and FD are both cleared. The time interval between adjacent sampling and reset times in the exposure control stage is Δt2. Assuming the number of samplings in the exposure control stage is N rst , the time interval between the reset moment closest to the signal readout in the exposure control stage is Δt1. In one frame, the longest exposure time is N rst *Δt2 + Δt1, and the shortest exposure time is Δt1. For V s1 , its exposure time is the longest, and the signal light intensity it represents is V s1 / (Δt1 + Nrst*Δt2) (that is, it represents a weaker light intensity). For V s4 , its exposure time is the shortest, and the signal light intensity it represents is V s4 / (Δt1), and the exposure time difference is (Δt1 + N rst*(Δt2) / Δt1 times. Therefore, compared with the traditional method of using the same exposure time for all pixel units within one frame, the light intensity range that can be expressed in this embodiment is improved by (Δt1 + N Figure 8c *(Δt2) / Δt1 times as shown in the illustrated embodiment. rst *(Δt2) / Δt1 times.

[0142] For a single pixel unit, the signal finally output within one frame includes the digital signal (e.g., digital voltage signal) output by the digital readout circuit 530 and the analog signal (e.g., analog voltage signal) output by the double-sampling readout circuit 540. Optionally, assuming the number of bits after quantization of the analog voltage signal is N ana , the digital readout circuit 530 converts the voltage signal output by the pixel unit into a digital signal through AD conversion, and the number of sampling times (which can be set according to the application scenario and is a preset value) within the exposure control area is N rst , so the number of bits of the digital signal is N rst . In some alternative examples, within one frame time, the original data output by a single pixel unit is as Figure 9 shown, Figure 9 which is the original data format diagram output by any pixel in the signal processing circuit provided by an exemplary embodiment of the present disclosure. Assume that the last 1 in the digital signal is at the i-th bit (0 ≤ i ≤ N rst - 1), the leftmost is the (N rst - 1)-th bit, and the rightmost is the 0-th bit. Then the exposure time is Δt1 + i×Δt2 (refer to Figure 8c , the interval between every two outputs in the digital signal is Δt2, and since the last 1 is at the i-th bit, the interval between this 1 and the analog signal is Δt1, so the exposure time can be obtained). Based on the above exposure time calculation formula, it is also possible to add a corresponding digital encoding circuit after the digital readout circuit to compress the N rst -bit digital exposure control signal to log2(N rst ), and the size of the compressed value represents the position of the last 1. Through the processing of the digital encoding circuit, the output bandwidth of the digital signal is reduced. For example, the 1024-bit output signal is compressed to 10 bits, greatly reducing the output bandwidth.

[0143] Based on the above theory, optionally, in some alternative embodiments, the signal processing circuit may further include: n digital encoding circuits, and each digital encoding circuit corresponds to a digital readout circuit;

[0144] The input end of the digital encoding circuit is connected to the output end of the corresponding digital readout circuit, receives the digital sequence output by the digital readout circuit for signal compression processing, and obtains the encoded value.

[0145] The electronic device provided by the present disclosure can be incorporated into any one of the following: pulse camera, high-speed camera, audio / video player, navigation device, fixed-position terminal, entertainment unit, smart phone, communication device, device in a motor vehicle, camera, sports or wearable camera, detection device, flight device, medical device, security device, etc.

[0146] The electronic device provided by the present disclosure can be applied to any one of the following: pulse camera, high-speed camera, audio / video player, navigation device, fixed-position terminal, entertainment unit, smart phone, communication device, device in a motor vehicle, camera, sports or wearable camera, detection device, flight device, medical device, security device, etc.

[0147] Next, refer to Figure 10 to describe the electronic device according to an embodiment of the present disclosure. The electronic device can be either one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device can communicate with the first device and the second device to receive the input signals collected from them.

[0148] Figure 10 The block diagram of the electronic device according to an embodiment of the present disclosure is illustrated.

[0149] As Figure 10 shown, the electronic device includes one or more processors and a memory.

[0150] The processor can be a central processing unit (CPU) or other forms of processing units with data processing capabilities and / or instruction execution capabilities, and can control other components in the electronic device to perform desired functions.

[0151] The memory can store one or more computer program products. The memory can include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory can include, for example, random access memory (RAM) and / or cache memory, etc. The non-volatile memory can include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program products can be stored on the computer-readable storage media, and the processor can run the computer program products to implement the sensor pixel units of the various embodiments of the present disclosure described above and / or other desired functions.

[0152] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0153] In addition, the input device may further include, for example, a keyboard, a mouse, etc.

[0154] The output device can output various information to the outside, including the determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network, and a remote output device connected thereto, etc.

[0155] Of course, for simplicity, Figure 10 only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application scenarios, the electronic device may further include any other appropriate components.

[0156] In addition to the above methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions that, when run by a processor, cause the processor to execute the steps in the sensor pixel unit according to various embodiments of the present disclosure described in the above part of this specification.

[0157] The computer program product can be written in any combination of one or more programming languages to write program code for performing the operations of the embodiments of the present disclosure. The programming languages include object-oriented programming languages such as Java, C++, etc., and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, executed as an independent software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0158] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium, on which computer program instructions are stored, and the computer program instructions, when run by a processor, cause the processor to execute the sensor pixel unit according to various embodiments of the present disclosure described in the above part of this specification.

[0159] The computer-readable storage medium may adopt any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0160] The basic principles of the present disclosure have been described in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present disclosure. In addition, the above-mentioned specific details are only for illustrative and easy-to-understand purposes, rather than limitations. The above details do not limit the present disclosure to necessarily adopt the above specific details for implementation.

[0161] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For system embodiments, since they basically correspond to method embodiments, the description is relatively simple, and reference can be made to the relevant parts of the method embodiments for the relevant content.

[0162] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present disclosure are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open-ended terms, meaning "including but not limited to", and can be used interchangeably with each other. The word "or" and "and" used herein refer to the word "and / or", and can be used interchangeably with each other, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to", and can be used interchangeably with each other.

[0163] The methods and apparatuses of the present disclosure can be implemented in many ways. For example, the methods and apparatuses of the present disclosure can be implemented through software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of the steps for the method is only for illustration, and the steps of the method of the present disclosure are not limited to the above specifically described order, unless otherwise specifically stated in other ways. In addition, in some embodiments, the present disclosure can also be implemented as a program recorded in a recording medium, and these programs include machine-readable instructions for implementing the methods according to the present disclosure. Therefore, the present disclosure also covers the recording medium storing the programs for executing the methods according to the present disclosure.

[0164] It should also be noted that in the apparatuses, equipment, and methods of the present disclosure, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present disclosure.

[0165] The foregoing description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0166] The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the present disclosure to the form disclosed herein. Although several example aspects and embodiments have been discussed above, those skilled in the art will recognize some of their variations, modifications, alterations, additions, and subcombinations.

Claims

1. A sensor pixel unit, characterized in that, Comprising: a signal acquisition module, a transfer tube, a signal processing module, and a signal output module; the signal acquisition module is configured to receive an optical signal to generate photoelectric charges, and perform a reset operation under the control of a first feedback signal; the transfer tube is configured to transfer the photoelectric charges generated by the signal acquisition module to the signal processing module under the control of an external transfer signal; the signal processing module is configured to generate a first output signal when the transfer tube is not conducting, and generate a second output signal based on the photoelectric charges accumulated during an exposure duration and transferred by the signal acquisition module when the transfer tube is conducting; the signal output module is configured to output the first output signal or the second output signal under the control of an external control signal.

2. The pixel unit according to claim 1, characterized in that, The signal acquisition module includes: a photodiode and a first reset tube; the anode terminal of the photodiode is grounded, and the cathode terminal is connected to the source terminal of the first reset tube; the drain terminal of the first reset tube receives a power signal, and the gate terminal receives the first feedback signal, and is configured to perform a reset on the photodiode under the control of the first feedback signal.

3. The pixel unit according to claim 2, characterized in that, The signal acquisition module further includes: a first switching transistor; the source terminal of the first switching transistor is connected to the gate terminal of the first reset tube, the drain terminal is connected to the first feedback signal, and the gate terminal receives a first switching signal. The first switching transistor is configured to conduct or disconnect under the control of the first switching signal. When the first switching transistor conducts, the first feedback signal is transmitted to the first reset tube.

4. The pixel unit according to any one of claims 1-3, characterized in that, The signal processing module includes: a floating diffusion region, a second reset tube, and a second switching transistor; one end of the floating diffusion region is grounded, and the other end is connected to the source terminal of the second reset tube as the connection terminal of the signal processing module; and is connected to the transfer tube and the signal output module through the connection terminal; the source terminal of the second reset tube is connected to the floating diffusion region, the drain terminal receives a power signal, and the gate terminal receives a second feedback signal through the second switching transistor, and is configured to control the reset of the floating diffusion region according to the second feedback signal; the second switching transistor is configured to conduct or disconnect under the control of a second switching signal. When the second switching transistor conducts, the second feedback signal is introduced into the second reset tube.

5. The pixel unit according to claim 4, characterized in that, the floating diffusion region performs a reset when the second reset tube conducts; when the second reset tube is off and the transfer tube is on, the floating diffusion region receives and stores the photoelectric charges generated by the photodiode in the signal acquisition module; and outputs the second output signal generated based on the stored photoelectric charges under the control of the external control signal.

6. The pixel unit according to any one of claims 1-5, characterized in that, The signal output module includes: a source follower transistor and a selection transistor; the gate terminal of the source follower transistor is connected to the signal processing module, the source terminal is connected to the selection transistor, and the drain terminal receives a power signal; and is configured to detect and follow the charge change of the floating diffusion region to determine the first output signal or the second output signal; The drain terminal of the selection transistor is connected to the source terminal of the source follower transistor. The source terminal is connected to the signal quantization module. The gate terminal receives an external control signal and determines whether to output the first output signal or the second output signal according to the control of the external control signal.

7. A signal processing circuit, characterized in that, Comprising: A pixel array composed of sensor pixel units of m rows * n columns as described in any one of claims 1-6, and n column processors; wherein each of the column processors corresponds to m of the sensor pixel units in one column; m and n are integers greater than or equal to 1 respectively; The pixel array is configured to quantize pixel signals row by row for each row of the sensor pixel units according to the control of an external control signal, output n first output signals or second output signals, and send them to the n column processors respectively; The column processor is configured to determine the encoded signal corresponding to the sensor pixel unit according to the received first output signal and second output signal, and obtain a first feedback signal and a second feedback signal based on the encoded signal, and control the operation of the sensor pixel unit through the first feedback signal and the second feedback signal.

8. The signal processing circuit according to claim 7, characterized in that, The column processor includes: a comparator, a first feedback circuit, and a second feedback circuit; The negative input terminal of the comparator is connected to the output terminal of the sensor pixel unit for receiving the first output signal or the second output signal. The positive input terminal receives a reference signal, and the output terminal outputs the encoded signal, and the output terminal is respectively connected to the input terminals of the first feedback circuit and the second feedback circuit; The input terminal of the first feedback circuit is connected to the output terminal of the comparator, and the output terminal outputs the first feedback signal; The input terminal of the second feedback circuit is connected to the output terminal of the comparator, and the output terminal outputs the second feedback signal.

9. The signal processing circuit according to claim 8, characterized in that, The first feedback circuit includes a first AND logic circuit and a first OR logic circuit; One input terminal of the first AND logic circuit serves as the input terminal of the first feedback circuit and is connected to the output terminal of the comparator; the other input terminal receives a first AND signal; the output terminal is connected to one input terminal of the first OR logic circuit; One input terminal of the first OR logic circuit is connected to the output terminal of the first AND logic circuit, and the other input terminal receives a first OR signal; the output terminal outputs the first feedback signal.

10. The signal processing circuit according to claim 8 or 9, wherein The second feedback circuit includes a second AND logic circuit and a second OR logic circuit; One input terminal of the second AND logic circuit serves as the input terminal of the second feedback circuit and is connected to the output terminal of the comparator; the other input terminal receives a second AND signal; the output terminal is connected to one input terminal of the second OR logic circuit; One input terminal of the second OR logic circuit is connected to the output terminal of the second AND logic circuit, and the other input terminal receives a second OR signal; the output terminal outputs the second feedback signal.

11. The signal processing circuit according to any one of claims 8 - 10, wherein Further comprising: n digital readout circuits, each of the digital readout circuits corresponding to one of the column processors; The input end of the digital readout circuit is connected to the output end of the comparator in the corresponding column processor, and is used to read out the encoded signal output by the comparator at every preset time interval to obtain a digital sequence.

12. The signal processing circuit according to claim 11, wherein It further includes: n digital encoding circuits, each of the digital encoding circuits corresponding to one of the digital readout circuits; The input end of the digital encoding circuit is connected to the output end of the corresponding digital readout circuit, and receives the digital sequence output by the digital readout circuit to perform signal compression processing to obtain an encoded value.

13. The signal processing circuit according to any one of claims 7 - 12, wherein It further includes: n double-sampling readout circuits, each of the double-sampling readout circuits corresponding to m of the sensor pixel units in one column; The input end of the double-sampling readout circuit is connected to the output end of the sensor pixel unit. When the sensor pixel unit is in the signal readout state, the first output signal and the second output signal at adjacent moments are continuously read out, and the exposure charge amount is determined based on the first output signal and the second output signal and output.

14. An electronic device, wherein It includes: a processor, and a memory communicatively connected to the processor, and further includes the sensor pixel unit according to any one of claims 1-6 or the signal processing circuit according to any one of claims 7-13; The memory stores computer execution instructions; The processor executes the computer execution instructions stored in the memory to control the sensor pixel unit or the signal processing circuit.

15. The electronic device according to claim 14, wherein The electronic device is incorporated into any one of the following: a pulsed camera, a high-speed camera, an audio / video player, a navigation device, a fixed-position terminal, an entertainment unit, a smart phone, a communication device, a device in a motor vehicle, a camera, a sports or wearable camera, a detection device, a flight device, a medical device, a security device.

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