Quantization circuit, image sensor and image data acquisition method

Abstract

The invention provides a quantization circuit, an image sensor and an image data acquisition method, the quantization circuit comprises N quantization units, each quantization unit at least comprises a counting storage multiplexing unit, and the counting storage multiplexing unit comprises a counting main module, a storage main module and a storage control module which are coupled in sequence, the quantization circuit realizes counting and obtains a counting result based on the counting main module and the storage main module, and realizes storage of the counting result based on the storage main module and the storage control module; according to the invention, the counting in the quantization process and the storage of the obtained counting result are multiplexed, so that the area occupied by the quantization circuit on the layout can be reduced, and the power consumption is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of image acquisition, and particularly relates to a quantization circuit, an image sensor, and an image data acquisition method. Background Art

[0002] CMOS image sensors have advantages such as low voltage, low power consumption, low cost, and high integration, and have important application values in the fields of machine vision, consumer electronics, high-definition monitoring, and medical imaging. An analog-to-digital converter (ADC) is an important component of the readout circuit of a CMOS image sensor, and is responsible for converting the analog signal output by a pixel into a digital signal.

[0003] Column-level ADCs are generally used in CMOS image sensors. Common ones include single-slope ADC (SSSDC), successive approximation ADC (SAR ADC), and cyclic ADC (Cyclic ADC). Among them, the circuit of SS ADC is simple. Generally, only one comparator and one counter are required for each column, and all columns share the ramp signal, and the column consistency is relatively good. Therefore, SS ADC is the most widely used column-level ADC in CMOS image sensors.

[0004] However, traditional counting methods generally require configuring corresponding storage units for data storage and reading them out through the readout circuit under the control of the readout signal, and the circuit structure is complex. In an image sensor using column-level SS ADC, generally each column of pixels corresponds to at least one column of ADC, and each column of ADC contains multi-bit counters (generally ranging from 10 to 15 bits), which means that SS ADC occupies a relatively large area on the entire image sensor chip layout and also has relatively high power consumption. At the same time, the more bits of the ADC, the higher the resolution, the higher the quantization accuracy, and the better the quality of the generated image. However, the area and power consumption will limit the expansion of the ADC bits.

[0005] Therefore, it is necessary to provide a quantization circuit, an image sensor, an image data acquisition method, and an electronic device to solve the problems of complex circuit structure, large occupied area, and high power consumption in the prior art.

[0006] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part. Summary of the Invention

[0007] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a quantization circuit, an image sensor, and an image data acquisition method, which are used to solve the problems of complex structure of the quantization circuit of the image sensor, large layout occupation area of the quantization circuit, and high power consumption in the prior art.

[0008] To achieve the above object and other related objects, the present invention provides a quantization circuit, the quantization circuit includes N quantization units, the quantization unit at least includes a counting and storage multiplexing unit, and N is an integer greater than or equal to 1; wherein:

[0009] The counting and storage multiplexing unit includes a counting main module, a storage main module, and a storage control module connected in sequence. Among them, the counting and storage multiplexing units are cascaded, the quantization circuit realizes counting and obtains a counting result based on the counting main module and the storage main module in each quantization unit, and realizes the storage of the counting result based on the storage main module and the storage control module in each quantization unit.

[0010] Optionally, the counting main module includes an input stage module and a first transmission module, the storage main module includes a receiving stage module, a second transmission module, and a storage stage module, and the receiving stage module receives the output data of the counting main module, wherein:

[0011] The input stage module includes a first clock connection end and a data end, and is used to transmit the first data signal input at the data end and generate a second data signal under the control of the input clock at the first clock connection end;

[0012] The first transmission module is connected to the output end of the input stage module, and is used to transmit the second data signal and generate a third data signal, and its output end serves as the output end of the counting main module;

[0013] The receiving stage module includes a second clock connection end and a data receiving end, the data receiving end is connected to the output end of the counting main module, and is used to transmit the third data signal received at the data receiving end and generate a fourth data signal under the control of the input clock at the second clock connection end;

[0014] The second transmission module is connected to the output end of the receiving stage module, and is used to transmit the fourth data signal and generate a fifth data signal;

[0015] The storage stage module is connected in parallel at both ends of the second transmission module, and the storage stage module includes a third clock connection end, and is used to store the fourth data signal and the fifth data signal under the control of the input clock at the third clock connection end to realize the storage of the counting result.

[0016] Optionally, the memory control module is connected to the output end of the second transmission module and the input end of the storage level module, and includes a data control end for outputting a signal corresponding to the fifth data signal under the control of a read control signal at the data control end.

[0017] Optionally, the memory control module includes a read control module, which is cut off when the read control signal received at the read control end is at a first level, and conducts when the read control signal is at a second level different from the first level to realize data output.

[0018] Optionally, the memory control module includes a storage signal control module for processing the fifth data signal and outputting a signal corresponding to the processed fifth data signal through the memory control module.

[0019] Optionally, the read control module includes a second transmission control gate.

[0020] Optionally, the storage signal control module includes a third reverse logic gate to realize output after inverting the fifth data signal.

[0021] Optionally, the counting main module further includes a latch module connected in parallel at both ends of the first transmission module, including a fourth clock connection end for latching the second data signal and the third data signal under the control of an input clock at the fourth clock connection end.

[0022] Optionally, the quantization unit further includes a reset module arranged in the second transmission module.

[0023] Optionally, the input stage module includes a first tri-state inverter, which is in an operating state when the received input clock is at a first level and in a high-impedance state when the received input clock is at a second level different from the first level; the first transmission module includes a first reverse logic gate; the receiving stage module includes a first transmission control gate, which conducts when the received input clock is at a first level and cuts off when the received input clock is at a second level; the second transmission module includes a second reverse logic gate; the storage level module includes a second tri-state inverter, which is in an operating state when the received input clock is at a first level and in a high-impedance state when the received input clock is at a second level.

[0024] Optionally, the reset module includes a first reset transistor and a second reset transistor for realizing reset under the control of a reset signal reverse signal received by the gates of the first reset transistor and the second reset transistor.

[0025] Optionally, the quantization unit further includes a selection element, which includes a first selection input terminal, a second selection input terminal, and an output terminal. The output terminal is connected to the clock input terminal of the corresponding quantization unit. The first selection input terminal is connected to the positive output terminal of the previous quantization unit, and the second selection input terminal is connected to the inverted output terminal of the previous quantization unit. Wherein, the first selection input terminal of the selection element of the first-stage quantization unit receives an initial logic signal, and the second selection input terminal receives the initial logic signal through an inverted logic.

[0026] Optionally, the quantization unit further includes a holding element, which includes a first selection input terminal, a second selection input terminal, and an output terminal. The first selection input terminal of the holding element is connected to the positive output terminal of the corresponding quantization unit, the second selection input terminal is connected to the inverted output terminal of the corresponding quantization unit, and the output terminal of the holding element is connected to the data terminal of the corresponding quantization unit.

[0027] Optionally, the quantization unit further includes a control logic gate. Wherein, the first input terminal of the control logic gate is connected to the data output terminal of the previous quantization unit, the second input terminal of the control logic gate is connected to a read enable signal, and the output terminal of the control logic gate is connected to the clock input terminal of the corresponding quantization unit.

[0028] Optionally, the control logic gate includes a NOR gate. The first input terminal of the NOR gate is the data output terminal of the previous quantization unit, the second input terminal is connected to the read enable signal, and the output terminal of the NOR gate is connected to the clock input terminal of the corresponding quantization unit.

[0029] The present invention also provides an image sensor, which includes a data readout circuit and a quantization circuit as described in any one of the above solutions. The data readout circuit is coupled to the output terminal of the quantization circuit. The data readout circuit includes a plurality of cascaded shift units, and the shift units correspond to the quantization units.

[0030] Optionally, the shift unit includes a shift selection switch and a D flip-flop. When the shift selection switch is in the first state, the shift unit is coupled to the output terminal of the quantization unit to receive the corresponding count storage result. When in the second state, the shift unit is coupled to the output terminal of the previous shift unit to realize the shift readout of the count storage result. The output terminal of the D flip-flop is used as the output terminal of the shift unit.

[0031] The present invention also provides an image data acquisition method, which is implemented based on the quantization circuit as described in any one of the above solutions, or the present invention also provides an image data acquisition method based on the image sensor as described in any one of the above solutions. The image data acquisition method includes:

[0032] Reset the quantization circuit;

[0033] Based on the count enable signal and the clock control signal, perform counting through the count storage multiplexing unit to obtain the count result;

[0034] Store the count result through the count storage multiplexing unit; and

[0035] Based on the read control signal, read the stored count result from the quantization circuit to achieve the acquisition of image data.

[0036] Optionally, the image data includes first data and second data, and target data is obtained based on the difference between the first data and the second data. Wherein, the method for obtaining the target data specifically includes the following steps:

[0037] Reset the quantization circuit;

[0038] Obtain a reference signal based on the pixel circuit, and quantize the reference signal to obtain the first data;

[0039] Obtain an image signal based on the pixel circuit, and adjust the quantization circuit to perform counting on the basis of the first data, and quantize the image signal to obtain target data;

[0040] Wherein, the image signal is quantized on the basis of the first data, and the target data is obtained based on the first data corresponding to the reference signal and the second data corresponding to the image signal;

[0041] Store the target data based on the quantization circuit; and

[0042] Read out the target data based on the data readout circuit.

[0043] Optionally, the pixel circuit provides first data and second data under different gains, or the pixel circuit provides first data and second data under different phases, and the quantization circuit is used to obtain target data corresponding to the corresponding gain or phase.

[0044] Optionally, when the quantization circuit includes the holding element and the control logic gate, the method further includes:

[0045] When the counting ends, turn on the holding element to perform data holding;

[0046] During the data holding process, turn on the control logic gate to perform mode switching..

[0047] As described above, the quantization circuit, image sensor, and image data acquisition method of the present invention multiplex the counting in the quantization process and the storage of the obtained counting results, which can reduce the number of circuit transistors, reduce the area occupied by the quantization circuit on the layout, further reduce the power consumption of the image sensor, and at the same time, is beneficial to improving the quantization data bit width, thereby improving the image quality. In addition, since the layout of the quantization circuit is reduced, the corresponding wiring will also be shortened, the capacitance of the metal wire will be reduced, and the charging and discharging current of the metal wire capacitance by the quantization circuit during operation will be reduced, further achieving power consumption reduction. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It shows a basic structural block diagram of an image sensor system.

[0049] Figure 2 It shows a schematic diagram of a pixel circuit of an image sensor.

[0050] Figure 3 It shows a schematic diagram of a quantization circuit provided in an embodiment of the prior art.

[0051] Figure 4 It shows Figure 3 A schematic diagram of the working principle corresponding to data quantization of the shown quantization circuit.

[0052] Figure 5 It shows a schematic diagram of a quantization circuit provided in an embodiment of the present application.

[0053] Figure 6 It shows Figure 5 A circuit diagram corresponding to a specific implementation manner of the described quantization circuit.

[0054] Figure 7 It shows Figure 5 A circuit diagram corresponding to another specific implementation manner of the described quantization circuit.

[0055] Figure 8 It shows Figure 5 A circuit diagram corresponding to yet another specific implementation manner of the described quantization circuit.

[0056] Figure 9 It shows a schematic diagram of an example corresponding to the quantization circuit and data readout circuit in an embodiment of the present application.

[0057] Figure 10 It shows another example illustration corresponding to the quantization circuit and data readout circuit in an embodiment of the present application.

[0058] Figure 11 It shows a schematic diagram of an implementation manner of the data readout circuit in the embodiment.

[0059] Figure 12 It shows a schematic diagram of the image data acquisition process in an embodiment of the present application.

[0060] Figure 13 It shows a schematic diagram of an operation timing of image data acquisition in an embodiment of the present application.

[0061] Figure 14 It shows another schematic diagram of an operation timing of image data acquisition in an embodiment of the present application.

[0062] Description of component labels

[0063] 1 Quantization circuit

[0064] 2 Data readout circuit

[0065] 10 Quantization unit

[0066] 20 Count storage multiplexing unit

[0067] 21 Count main module

[0068] 211 Input stage module

[0069] 212 First transmission module

[0070] 213 Latch module

[0071] 22 Storage main module

[0072] 221 Reception stage module

[0073] 222 Second transmission module

[0074] 223 Storage stage module

[0075] 23 Storage control module

[0076] 231 Storage signal control module

[0077] 232 Readout control module

[0078] 30 Selection element

[0079] 401 NAND gate

[0080] 402 Inverting logic

[0081] 50 Holding element

[0082] 60 Control logic gate

[0083] 70 Shifting unit

[0084] 70a Shifting selection switch

[0085] 70b D flip-flop Detailed implementation manners

[0086] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0087] It should be emphasized that the term "including / comprising" when used herein refers to the presence of features, whole things, steps or components, but does not exclude the presence or addition of one or more other features, whole things, steps or components.

[0088] Features described and / or illustrated for one implementation manner can be used in the same or similar manner in one or more other implementation manners, combined with features in other implementation manners, or replace features in other implementation manners.

[0089] When detailing the embodiments of the present invention, for the convenience of description, the cross-sectional views showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.

[0090] For the convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" etc. may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intervening layers.

[0091] In the context of the present application, the structure in which the first feature is "above" the second feature described may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0092] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The types, quantities and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0093] The content proposed by the present invention will be described in detail below in conjunction with the accompanying drawings of the present invention.

[0094] Figure 1 It is shown as a basic structural block diagram of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to a pixel array. The functional logic unit is connected to the readout circuit, and the readout circuit and the control circuit are connected to a status register to implement the control of the pixel array. The pixel array includes a plurality of pixels (P1, P2, P3) arranged in rows (R1, R2, R3... Ry) and columns (C1, C2, C3... Cx). The pixel signals output by the pixel array are output to the readout circuit via the column lines. In one embodiment, after the pixels acquire image data, the image data is read out in the readout mode specified by the status register and then transmitted to the functional logic unit. In a specific application, the readout circuit may include an analog-to-digital conversion (ADC) circuit and others.

[0095] In some applications, the status register may include a programmed selection system for determining whether the readout system reads through a rolling shutter mode or a global shutter mode. The functional logic unit may store the image data or the image data processed through image effects applications. In one embodiment, the readout circuit may read out one row of image data along the readout column lines at a time. Of course, other methods may also be used to read out the image data. The operation of the control circuit can be determined by the current settings of the status register. For example, the control circuit generates a shutter signal for controlling image acquisition. In some applications, this shutter signal may be a global exposure signal, such that all pixels of the pixel array simultaneously acquire their image data through a single acquisition window. In other applications, this shutter signal may also be a rolling exposure signal, such that the pixels of each pixel row of the pixel array continuously perform read operations through the acquisition window.

[0096] Figure 2 It is shown as a schematic connection diagram of a pixel circuit in an image sensor. As Figure 2As shown, each pixel circuit includes a photoelectric conversion element (e.g., a photodiode) and a pixel circuit (such as the transistors shown within the dashed box in the figure). The photodiode can be a buried photodiode (PPD) applied in the current image sensor. In an application example, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel selection transistor (RS), which are connected to a transfer transistor (TX) and a photodiode as shown in the figure. In an application example of a stacked structure, the pixel circuit includes a reset transistor, a source follower transistor, and a pixel selection transistor disposed on a circuit chip, and is connected to a photodiode in another chip based on the transfer transistor. In a further application example, the pixel circuit may further include a gain control transistor (DCG) connected between a floating diffusion region (FD) and the reset transistor. During operation, the photoelectric conversion element generates photo-charge in response to incident light during the exposure process. The transfer transistor is connected to a transfer signal, which controls the transfer transistor to transfer the charge accumulated in the photoelectric conversion element to the floating diffusion region. The reset transistor is connected between VDD and the floating diffusion region, and responds to a reset signal to reset the sensor pixel circuit (e.g., discharge or charge the floating diffusion region and the photodiode to the current voltage). The floating diffusion region is connected to the gate of the source follower transistor, and the source follower transistor is connected between VDD and the pixel selection transistor to respond to and output the potential of the floating diffusion region. The pixel selection transistor connects the source follower transistor and the pixel circuit bit line, and responds to a pixel selection control signal to implement pixel selection readout and output it to the readout column.

[0097] As Figure 3 and Figure 4 shown, a working schematic diagram of an SS ADC is provided, and the circuit structure is as Figure 3 shown, and the working principle is as Figure 4 shown. The ramp generator generates a ramp signal and samples it through a capacitor to the positive input terminal of each column comparator. The negative input terminal of the comparator samples the pixel signals of each column. Taking the first column as an example, the ramp signal Vramp traverses the entire quantization voltage range and is compared with the pixel signal Vin1. At the same time, the counter starts counting. When the ramp signal Vramp is greater than the pixel signal Vin1, the comparator flips, and the counter stops counting. At this time, the counting result is the digital code value after quantization of the pixel signal Vin1.

[0098] However, in the above-mentioned SS ADC, after the counter counts, generally the current count value is written into the corresponding storage unit mem, and then the value stored in mem is read out through the readout circuit. The overall circuit is complex, occupies a large area on the entire image sensor chip layout, and has high power consumption. Moreover, the area and power consumption will limit the expansion of the ADC bit number, thereby limiting the quantization accuracy and the improvement of the image quality. The quantization circuit of the present application can effectively solve the above problems, which will be described below in conjunction with specific embodiments.

[0099] Embodiment 1:

[0100] Please refer to Figure 5 As shown, this embodiment provides a quantization circuit 1. The quantization circuit 1 includes N quantization units 10, where N is an integer greater than or equal to 1. Each quantization unit 10 at least includes a counting and storage multiplexing unit 20. The counting and storage multiplexing unit 20 includes a counting main module 21, a storage main module 22, and a storage control module 23 that are sequentially coupled. Among them, the counting and storage multiplexing units 20 corresponding to each quantization unit 10 are cascaded. The quantization circuit 1 realizes counting to obtain a counting result based on the counting main module 21 and the storage main module 22 in each counting and storage multiplexing unit 20 corresponding to each quantization unit 10. The quantization circuit 1 realizes the storage of the counting result based on the storage main module 22 and the storage control module 23 in each counting and storage multiplexing unit 20 corresponding to each quantization unit 10.

[0101] In one implementation, the quantization circuit 1 corresponds one-to-one with the pixel columns in the pixel array to realize the quantization of the pixels in this column. Of course, in other implementations, at least two pixel columns can correspond to one quantization circuit 1, or at least two quantization circuits 1 can be set for one pixel column, which is set according to actual needs. In addition, the number N of quantization units 10 in each quantization circuit 1 can be set according to the bit width of the data to be quantized. For example, for 12-bit data, N is 12, and 12 quantization units 10 are set. N can be 8 - 20 bits.

[0102] Based on the above design, the multiplexing of counting and the storage of the obtained counting results in the quantization process can reduce the number of circuit transistors, reduce the area occupied by the quantization circuit layout, further reduce the power consumption of the image sensor, and at the same time, is beneficial to the improvement of the quantization data bit width, thereby improving the image quality. In addition, since the layout of the quantization circuit is reduced, the corresponding wiring will also be shortened, the capacitance of the metal wire will be reduced, and the charging and discharging current of the metal wire capacitance by the quantization circuit during operation will be reduced, which can further reduce the power consumption.

[0103] Please refer to Figure 6As shown, an implementation of the counting storage multiplexing unit 20 is provided. In this implementation, for the counting storage multiplexing unit 20, the counting main module 21 includes an input stage module 211 and a first transmission module 212, and the storage main module 22 includes a receiving stage module 221, a second transmission module 222, and a storage stage module 223; wherein, the receiving stage module 221 receives the output data of the counting main module 21.

[0104] In this implementation, the input stage module 211 includes a first clock connection terminal CK and a data terminal D, and is used to transmit the first data signal input at the data terminal D and generate a second data signal under the control of the input clock at the first clock connection terminal CK;

[0105] The first transmission module 212 is connected to the output terminal of the input stage module 211, and is used to transmit the second data signal and generate a third data signal, and its output terminal serves as the output terminal of the counting main module 21;

[0106] The receiving stage module 221 includes a second clock connection terminal CK and a data receiving terminal. The data receiving terminal is connected to the output terminal of the counting main module 21, and is used to transmit the third data signal received at the data receiving terminal and generate a fourth data signal under the control of the input clock at the second clock connection terminal CK;

[0107] The second transmission module 222 is connected to the output terminal of the receiving stage module 221, and is used to transmit the fourth data signal and generate a fifth data signal;

[0108] The storage stage module 223 is connected in parallel at both ends of the second transmission module 222, and the storage stage module 223 includes a third clock connection terminal CK. The storage stage module 223 is used to store the fourth data signal and the fifth data signal under the control of the input clock at the third clock connection terminal CK to implement the storage of the counting result.

[0109] It should be noted that the first clock connection terminal CK, the second clock connection terminal CK, and the third clock connection terminal CK described in this embodiment are all the clock connection terminals of the corresponding quantization unit 10, and receive the same input clock. For the sake of distinction, different names are used in different modules, which can be understood by those skilled in the art.

[0110] Continue to refer to Figure 6 As shown, in a specific implementation, the input stage module 211 includes a first tri-state inverter TSINV1. The first tri-state inverter TSINV1 is in the working state when the received input clock is at the first level (such as low level), and is in the high-impedance state when the received input clock is at the second level (such as high level), that is, when the input clock is at the low level, the first data signal is inverted to generate the second data signal.

[0111] In a specific example, the first tri-state inverter TSINV1 includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4; the gate of the first MOS transistor M1 is connected to the gate of the fourth MOS transistor M4 and serves as the input terminal of the first tri-state inverter TSINV1 to connect to the first data signal, the source is connected to the reference voltage, and the drain is connected to the source of the second MOS transistor M2; the gate of the second MOS transistor M2 is connected to the input clock, and the drain is connected to the drain of the third MOS transistor M3 and serves as the output terminal of the first tri-state inverter TSINV1 to generate the second data signal; the gate of the third MOS transistor M3 is connected to the inverted signal of the input clock, and the source is connected to the drain of the fourth MOS transistor M4; the source of the fourth MOS transistor M4 is connected to the reference ground; wherein, the first MOS transistor M1 and the second MOS transistor M2 are PMOS transistors, and the third MOS transistor M3 and the fourth MOS transistor M4 are NMOS transistors.

[0112] The first transmission module 212 includes a first inverse logic gate MINV1, which is used to invert the second data signal to generate a third data signal.

[0113] In a specific example, the first inverse logic gate MINV1 includes a fifth MOS transistor M5 and a sixth MOS transistor M6; the gate of the fifth MOS transistor M5 is connected to the gate of the sixth MOS transistor M6 and serves as the input terminal of the first inverse logic gate MINV1, the source is connected to the reference voltage, and the drain is connected to the drain of the sixth MOS transistor M6 and serves as the output terminal of the first inverse logic gate MINV1; the source of the sixth MOS transistor M6 is connected to the reference ground. Wherein, the fifth MOS transistor M5 is a PMOS transistor, and the sixth MOS transistor M6 is an NMOS transistor.

[0114] The receiving stage module 221 includes a first transmission control gate TGK1, which conducts when the input clock received at the second clock connection terminal CK is at the first level (low level), transmits the received third data signal and generates a fourth data signal, and cuts off when the received input clock is at a second level (high level) different from the first level.

[0115] In a specific example, the first transmission control gate TGK1 includes a seventh MOS transistor M7 and an eighth MOS transistor M8; the gate of the seventh MOS transistor M7 is connected to the inverted signal of the input clock, the gate of the eighth MOS transistor M8 is connected to the input clock, one end after the seventh MOS transistor M7 and the eighth MOS transistor M8 are connected in parallel serves as the input terminal of the first transmission control gate TGK1 to connect to the third data signal, and the other end serves as the output terminal of the first transmission control gate TGK1 to generate the fourth data signal; wherein, the seventh MOS transistor M7 is a PMOS transistor, and the eighth MOS transistor M8 is an NMOS transistor.

[0116] The second transmission module 222 includes a second inverse logic gate MINV2, which is used to invert the fourth data signal to generate a fifth data signal.

[0117] In a specific example, the second inverter MINV2 includes a ninth MOS transistor M9 and a tenth MOS transistor M10; the gate of the ninth MOS transistor M9 is connected to the gate of the tenth MOS transistor M10 and serves as the input terminal of the second inverter MINV2, the source is connected to a reference voltage, and the drain is connected to the drain of the tenth MOS transistor M10 and serves as the output terminal of the second inverter MINV2; the source of the tenth MOS transistor M10 is connected to the reference ground. Among them, the ninth MOS transistor M9 is a PMOS transistor, and the tenth MOS transistor M10 is an NMOS transistor.

[0118] The storage-level module 223 includes a second tri-state inverter TSINV2. The second tri-state inverter TSINV2 is in an operating state when the input clock received at the third clock connection terminal CK is at a first level (such as a low level), and is in a high-impedance state when the received input clock is at a second level (such as a high level). That is, it can store the fourth data signal and the fifth data signal under the control of the input clock to realize the storage of the counting result. Among them, the fourth data signal corresponds to the output terminal of the storage-level module 223, and the fifth data signal corresponds to the input terminal of the storage-level module 223. Of course, other clock control designs can also be used to realize the storage of the corresponding data signal.

[0119] In a specific example, the second tri-state inverter TSINV2 includes an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a fourteenth MOS transistor M14; the gate of the eleventh MOS transistor M11 is connected to the gate of the fourteenth MOS transistor M14 and serves as the input terminal of the second tri-state inverter TSINV2, the source of the eleventh MOS transistor M11 is connected to a reference voltage, and the drain is connected to the source of the twelfth MOS transistor M12; the gate of the twelfth MOS transistor M12 is connected to the control clock, and the drain is connected to the drain of the thirteenth MOS transistor M13 and serves as the output terminal of the second tri-state inverter TSINV2; the gate of the thirteenth MOS transistor M13 is connected to the inverted signal of the control clock, the source is connected to the drain of the fourteenth MOS transistor M14; the source of the fourteenth MOS transistor M14 is connected to the reference ground; among them, the eleventh MOS transistor M11 and the twelfth MOS transistor M12 are PMOS transistors, and the thirteenth MOS transistor M13 and the fourteenth MOS transistor M14 are NMOS transistors. In addition, in this embodiment, the reference voltage can be the power supply voltage VDD.

[0120] Please refer to Figure 7As shown, in a further embodiment, the counting main module 21 further includes a latching module 213. The latching module 213 is connected in parallel at both ends of the first transmission module 212, and the latching module 213 includes a fourth clock connection terminal CK, which is used to latch the second data signal and the third data signal under the control of the input clock at the fourth clock connection terminal CK. Here, the principle of the fourth clock connection terminal CK is similar to that of the previous three clock connection terminals CK.

[0121] In this embodiment, the latching module 213 includes a third tri-state inverter TSINV3, which is used to store the second data signal and the third data signal under the control of the input clock at the fourth clock connection terminal CK. The second data signal corresponds to the output terminal of the latching module 213, and the third data signal corresponds to the input terminal of the latching module 213.

[0122] In a specific example, the third tri-state inverter TSINV3 includes a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, and a twenty-second MOS transistor M22; the gate of the nineteenth MOS transistor M19 is connected to the gate of the twenty-second MOS transistor M22 and serves as the input terminal of the third tri-state inverter TSINV3. The source of the nineteenth MOS transistor M19 is connected to the reference voltage, and the drain is connected to the source of the twentieth MOS transistor M20; the gate of the twentieth MOS transistor M20 is connected to the control clock, and the drain is connected to the drain of the twenty-first MOS transistor M21 and serves as the output terminal of the third tri-state inverter TSINV3; the gate of the twenty-first MOS transistor M21 is connected to the inverted signal of the control clock, and the source is connected to the drain of the twenty-second MOS transistor M22; the source of the twenty-second MOS transistor M22 is connected to the reference ground; among them, the nineteenth MOS transistor M19 and the twentieth MOS transistor M20 are PMOS transistors, and the twenty-first MOS transistor M21 and the twenty-second MOS transistor M22 are NMOS transistors.

[0123] Continue to refer to Figure 6 and Figure 7 As shown, in an embodiment, the memory control module 23 is connected to the output terminal of the second transmission module 222 and the input terminal of the memory stage module 223. The memory control module 23 includes a read control terminal, which is used to output a signal corresponding to the fifth data signal under the control of the read control signal RD at the read control terminal.

[0124] In this embodiment, the memory control module 23 includes a read control module 232. The read control module 232 is cut off when the read control signal received at the read control terminal RD is at a first level (such as a low level), and is turned on when the read control signal is at a second level (such as a high level) different from the first level, and outputs the corresponding data. In one implementation, the read control module 232 includes a second transmission control gate TGK2.

[0125] In a specific example, the second transmission gate TGK2 includes a seventeenth MOS transistor M17 and an eighteenth MOS transistor M18; the gate of the seventeenth MOS transistor M17 is connected to the inverted signal RDB of the read control signal, the gate of the eighteenth MOS transistor M18 is connected to the read control signal RD, one end after the parallel connection of the seventeenth MOS transistor M17 and the eighteenth MOS transistor M18 serves as the input end of the second transmission gate TGK2 to connect the fifth data signal or other signals corresponding to the fifth data signal, such as the inverted signal of the fifth data signal, and the other end serves as the output end of the second transmission gate TGK2; wherein, the seventeenth MOS transistor M17 is a PMOS transistor, and the eighteenth MOS transistor M18 is an NMOS transistor.

[0126] In an example, the memory control module 23 further includes a storage signal control module 231 for processing and outputting the fifth data signal. Further, the storage signal control module 231 is connected to the read control module 232 for outputting the processed data; for example, the storage signal control module 231 can be an inversion logic circuit for inverting the fifth data signal for data output. In one implementation, the storage signal control module 231 includes a third inverter gate MINV3 for inverting the fifth data signal for data output and outputting it through the read control module 232.

[0127] In a specific example, the third inverter gate MINV3 includes a fifteenth MOS transistor M15 and a sixteenth MOS transistor M16; the gates of the fifteenth MOS transistor M15 and the sixteenth MOS transistor M16 are connected and serve as the input end of the third inverter gate MINV3, the source is connected to the reference voltage, and the drain is connected to the drain of the sixteenth MOS transistor M16 and serves as the output end of the third inverter gate MINV3; the source of the sixteenth MOS transistor M16 is connected to the reference ground. Wherein, the fifteenth MOS transistor M15 is a PMOS transistor, and the sixteenth MOS transistor M16 is an NMOS transistor.

[0128] Please refer to Figure 8 As shown, in one embodiment, the quantization unit 10 further includes a reset module, and the reset module is arranged in the second transmission module 222 to implement the reset of the quantization unit 10.

[0129] In a specific example, the reset module includes reset transistors, which are selected as the first reset transistor M23 and the second reset transistor M24 in this example. Further, the first reset transistor M23 is connected between the reference voltage (such as the power supply voltage VDD) and the output end of the second transmission module 222, and the second reset transistor M24 is connected between the second transmission module 222 and the reference ground. For example, in Figure 8In the example shown, the first reset transistor M23 is connected between the reference voltage and the output terminal of the second inverter MINV2, and the second reset transistor M24 is connected between the source of the tenth MOS transistor M10 and the reference ground. In this example, the first reset transistor M23 is a PMOS transistor, the second reset transistor M24 is an NMOS transistor, and the gates of the first reset transistor M23 and the second reset transistor M24 both receive the inverted signal RSTB of the reset signal to achieve reset.

[0130] Please refer to Figure 9 As shown, in one implementation, the counting storage multiplexing unit 20 in the quantization unit 10 can be implemented in a cascaded manner based on DFF (D flip-flop). A D flip-flop can be regarded as composed of two levels of storage units. The storage unit can be an existing bistable structure, and functionally includes parts such as a write switch, a read drive, and a read switch. In this implementation, the D flip-flop and the storage unit are multiplexed, and the counting part is composed of cascaded D flip-flops. In this implementation, the output terminal of each level of D flip-flop is connected to the subsequent data readout circuit through a CMOS switch (such as the second transmission control gate TGK2 of the read control module 232). The CMOS switch is controlled by a pair of opposite signals mem_rd (read control signal RD) and mem_rdb (RDB) to achieve storage. The specific corresponding circuit connection structure can be seen in Figures 6 - 8 as shown.

[0131] Please continue to refer to Figure 9 As shown, in one implementation, the quantization unit 10 further includes a selection element 30. The selection element 30 includes a first selection input terminal 0, a second selection input terminal 1, and an output terminal. The selection element 30 can be a selection switch MUX. The output terminal of the selection element 30 is connected to the clock input terminal CK of the corresponding quantization unit 10. Based on the working principle of the DFF, it can be understood that the clock input terminal CK here corresponds to the first four clock connection terminals CK to receive the corresponding input clock signal; the first selection input terminal 0 is connected to the positive output terminal Q of the previous-level quantization unit 10, and the second selection input terminal 1 is connected to the inverted output terminal QB of the previous-level quantization unit 10. Among them, the first selection input terminal 0 of the selection element 30 of the first-level quantization unit 10 receives an initial logic signal, and the second selection input terminal 1 receives the initial logic signal through the inverter 402.

[0132] In one example, the quantization circuit 1 includes a NAND gate 401. The first input terminal of the NAND gate 401 receives the initial clock count_clk, the second input terminal of the NAND gate 401 receives the count enable signal count_en, and the output terminal of the NAND gate 401 generates an initial logic signal to be provided to the first selection input terminal 0 of the selection element 30 of the first stage of the quantization unit 10. Additionally, in an alternative example, the reverse logic 402 is an inverter that receives the initial logic signal and provides the inverted initial logic signal it receives to the second selection input terminal 1 of the selection element 30 of the first stage of the quantization unit 10. In this example, the inverter is connected between the output terminal of the NAND gate 401 and the second selection input terminal 1 of the selection element 30 to invert the signal.

[0133] It should be noted that the selection element 30 also has a count control terminal that receives the count control signal count_up and can switch between the up-counting and down-counting of the counter. For example, Figure 9 in the example shown, when the first selection input terminal 0 of the selection element 30 is connected to the clock input terminal CK of the DFF, it is up-counting, and when the second selection input terminal 1 is connected to the clock input terminal CK of the DFF, it is down-counting.

[0134] Furthermore, the DFF corresponding to the quantization unit 10 also has a reset terminal that receives the reset signal count_rst. In one implementation, referring to Figure 8 RSTB in, the connection and control corresponding to the reset signal count_rst are for the first reset transistor M23 and the second reset transistor M24, and the reset is achieved through its reverse signal.

[0135] Please refer to Figure 10 as shown. In one implementation, the quantization unit 10 further includes a holding element 50. The holding element 50 includes a first selection input terminal 0, a second selection input terminal 1, and an output terminal. The holding element 50 can be a selection switch MUX. The first selection input terminal 0 of the holding element 50 is connected to the positive output terminal Q of the corresponding stage of the quantization unit 10, the second selection input terminal 1 is connected to the reverse output terminal QB of the corresponding stage of the quantization unit 10, and the output terminal of the holding element 50 is connected to the data terminal D of the corresponding quantization unit 10.

[0136] Specifically, in this embodiment, during the process of switching the selection element 30 for up - counting and down - counting, it may cause the clock signal of the DFF to jump, generating a rising edge or a falling edge. A holding element 50 is set between the D and Q / QB of the DFF. Before the counting control signal (such as count_up) is switched, the quantization circuit can be switched to the keep mode, which is controlled by the holding signal count_keep. In the keep mode, the Q of the DFF is connected to the D terminal. That is, through count_keep, the first selection input terminal 0 of the holding element 50 connects the positive output terminal Q and the data terminal D of the DFF together. Even if there is a rising - edge pulse at the clock input terminal of the DFF, it will not affect the latching result of the DFF, preventing the DFF from counting one more number. After the counting control signal switching is completed, through the count_keep signal, the second selection input terminal 1 of the holding element 50 connects the inverted output terminal QB and the data terminal D of the DFF together, forming a counter mode for normal counting.

[0137] Continue to refer to Figure 10 As shown, in one embodiment, the quantization unit 10 further includes a control logic gate 60. The first input terminal of the control logic gate 60 is connected to the data output terminal of the previous - stage quantization unit 10, which can be the positive output terminal Q or the inverted output terminal QB of the DFF. When there is a selection element 30, the first input terminal of the control logic gate 60 is connected to the output terminal of the selection element 30 to achieve the control of up - counting or down - counting. In addition, the second input terminal of the control logic gate 60 is connected to the read - enable signal read_en, and the output terminal of the control logic gate 60 is connected to the clock input terminal CK of the corresponding quantization unit 10.

[0138] In a specific example, the control logic gate 60 includes a NOR gate. That is, a NOR gate is added before the clock signal of each - stage DFF. One input terminal of the NOR gate (the first input terminal of the control logic gate 60) is connected to the output terminal of the selection element 30 or the data output terminal of the previous - stage quantization unit 10, and the other input terminal of the NOR gate (the second input terminal of the control logic gate 60) is connected to a read - enable signal read_en. The output terminal of the NOR gate is connected to the clock input terminal CK of the corresponding quantization unit 10.

[0139] In this example, by controlling the design of the logic gate 60, it is beneficial to achieve control during the process of counting based on the quantization circuit and storing the counting result. For example, during counting, the read enable signal read_en is 0, and the output of the NOR gate is the Q or QB of the previous-stage DFF, that is, the normal counting mode; after counting ends, read_en is 1, and the output of the NOR gate is 0, which has nothing to do with the previous-stage DFF. At this time, the clock input terminals of each stage of DFF are all 0, and the slave stage of the DFF is in the latch state, latching the current counting result. The design of the logic gate 60 can be beneficial to improving the accuracy of storing the counting result and enhancing the overall quantization effect.

[0140] Please refer to Figure 11 as shown, and refer to Figure 9 and Figure 10 In one embodiment, the data readout circuit 2 is coupled to the output terminal of the quantization circuit 1 to read out the counting result. In an example, one data readout circuit 2 corresponds to one quantization circuit 1, and each data readout circuit 2 corresponds to a column of pixel columns; wherein, the data readout circuit 2 includes a plurality of cascaded shift units 70, and the shift units 70 correspond to the quantization units 10 one by one. In addition, the number of shift units 70 can be designed according to the bit width of the quantization data.

[0141] As an example, the shift unit 70 includes a shift selection switch 70a and a D flip-flop 70b to achieve shift readout. Among them, the shift selection switch 70a couples the shift unit 70 to the output terminal of the quantization unit 10 to receive the corresponding counting result in the first state φ1, and couples the shift unit 70 to the output terminal of the previous-stage shift unit 70 in the second state φ2. For example, the data terminal D of the current-stage D flip-flop 70b receives the positive output terminal Q of the previous-stage D flip-flop 70b, and the output terminal of the D flip-flop serves as the output terminal of the shift unit 70. Among them, the shift selection switch 70a can adopt any switch in the prior art that realizes the above functions.

[0142] Embodiment 2:

[0143] The present invention also provides an image sensor, including the quantization circuit described in any one of the above solutions. The image sensor can be a CMOS image sensor. It can be understood that the image sensor in this Embodiment 2 can include a quantization circuit and a data readout circuit, which have been described in Embodiment 1 and will not be elaborated here.

[0144] The present invention also provides an electronic device, including the image sensor described in any one of the above solutions. The electronic device can be devices such as security monitoring, vehicle-mounted electronics, mobile phone cameras, and machine vision. Based on the image sensor of the present invention, high-quality image information can be obtained.

[0145] Embodiment 3:

[0146] As Figure 12 shown and referring to Figure 9 and 10 , this embodiment provides an image data acquisition method. The image data acquisition method of this embodiment is implemented based on any one of the quantization circuits in Embodiment 1, or based on any one of the image sensors in Embodiment 2. Among them, the image data acquisition method includes:

[0147] S1: Reset the quantization circuit 1;

[0148] S2: Based on the count enable signal and the clock control signal (such as the initial clock signal), perform counting through the count storage multiplexing unit;

[0149] S3: After the counting ends, store the counting result through the count storage multiplexing unit;

[0150] S4: Based on the read control signal, read the counting result from the quantization circuit.

[0151] Based on the above method, device multiplexing can be performed for the counting during the quantization process and the storage of the obtained counting results, which can reduce the number of circuit transistors, reduce the area occupied by the quantization circuit on the layout, further reduce the power consumption of the image sensor, be beneficial to the improvement of the quantization data bit width, and thus improve the image quality. In addition, since the layout of the quantization circuit is reduced, the corresponding wiring will also be shortened, the capacitance of the metal wire will be reduced, and the charging and discharging current of the metal wire capacitance by the quantization circuit during operation will be reduced, which can further reduce the power consumption.

[0152] In a specific operation mode, the timing control is as Figure 13 shown:

[0153] From time t0 to t1, the reset signal count_rst enables the reset of all counters (quantization units);

[0154] At time t2, the count enable signal count_en becomes high level, and the high-speed clock signal initial clock signal count_clk starts to take effect. At this time, the counter performs counting during the normal quantization process;

[0155] At time t3, the count enable signal count_en becomes low level, the counting stops, and the counting result is latched;

[0156] During the time period from t4 to t5, the read control signal RD (shown as mem_rd in the figure) is at high level. Then, the read control signal RDB (shown as mem_rdb in the figure) is at low level, which makes the cmos switches connecting each stage of D flip-flop and the read module conduct. The read module reads the quantization result of this time to the subsequent digital processing module;

[0157] So far, a complete quantization and readout process has been completed.

[0158] In one embodiment, as shown in Figure 10 When there is a control logic gate (NAND gate) 60 in the quantization circuit, the following steps are included in the process of acquiring image data:

[0159] During the counting process of step S2, the read enable signal read_en received by the control logic gate (NAND gate) 60 is 0. At this time, the output of the control logic gate (NAND gate) 60 is QB of the previous-stage DFF, that is, the normal counting mode; during the storage process of step S3, after the counting ends, the read enable signal read_en received by the control logic gate (NAND gate) 60 is 1, and the output of the control logic gate (NAND gate) 60 is 0, which has nothing to do with the previous-stage DFF. At this time, the clock input terminal of each stage of DFF is 0, and the slave stage of the DFF is in the latch state, latching the result of the current count.

[0160] In a further embodiment, as shown in Figure 10 When there is a holding element 50 in the quantization circuit, the following steps are included in the process of acquiring image data:

[0161] During the switching process of the read enable signal read_en received by the control logic gate (NAND gate) 60, it may cause the clock signal of the DFF to jump, generating a rising edge or a falling edge. For example, in this embodiment, the DFF is triggered by a rising edge. A holding element 50 is set between the D and Q / QB of the DFF. After the counting ends and before the read enable signal read_en switches, the quantization circuit can be switched to the keep mode, controlled by the hold signal count_keep. In the keep mode, the Q of the DFF is connected to the D terminal, and even if there is a rising edge pulse at the clock input terminal of the DFF, it will not affect the result latched by the DFF, preventing the DFF from counting one more number. In addition, in this example, the holding element 50 can be used during the up / down counting mode switching process and the counting storage / data readout process, which can further save the circuit area and improve the overall performance.

[0162] In a specific operation mode, the timing control is as shown in Figure 14 shown:

[0163] Before quantization starts, at the time t0 - t1, the reset signal count_rst enables the reset of all counters;

[0164] At the time t2, the count enable signal count_en becomes high level, and the high-speed clock signal count_clk starts to take effect. At this time, the counter performs counting during the normal quantization process;

[0165] At time t3, the counting enable signal count_en goes low to stop counting. Meanwhile, the hold signal count_keep goes high to enable data holding.

[0166] Between t3 and t4, the read enable signal read_en goes high, and the clock inputs of all DFFs are set to 0, causing the current count value to be latched in the slave stage of the DFFs.

[0167] During the time period from t4 to t5, the read control signal RD (shown as mem_rd) is high, and the read control signal RDB (shown as mem_rdb) is low, turning on the CMOS switches connecting each stage of D flip - flops and the readout module. The readout module reads out the quantization result of this time to the subsequent digital processing module.

[0168] Thus, a complete process of quantization and readout is completed.

[0169] In addition, after t5, the read enable signal read_en can be further set low first, or the hold signal count_keep can be further set low to perform the next quantization operation.

[0170] In one embodiment, the image data includes first data and second data, and target data is obtained based on the difference between the first data and the second data. In a specific application, the first data is the data obtained by quantifying the reset signal provided by the pixel circuit, the second data is the data obtained by quantifying the image signal provided by the pixel circuit, and the target data is the difference between the two, which is the result after noise reduction by correlated double sampling (CDS). The method for obtaining the target data includes the following steps:

[0171] S21: Reset the quantization circuit;

[0172] S22: Obtain a reference signal based on the pixel circuit and quantify the reference signal to obtain the first data (VRST);

[0173] S23: Obtain an image signal based on the pixel circuit, adjust the quantization circuit, count on the basis of the first data, and quantify the image signal to obtain the target data (VCDS);

[0174] Among them, the image signal is quantified on the basis of the first data (VRST), and the target data is obtained based on the first data (VRST) corresponding to the reference signal and the second data (VSIG) corresponding to the image signal;

[0175] S24: Store the target data (VCDS) based on the quantization circuit;

[0176] S25: Read out the target data (VCDS) based on the data readout circuit.

[0177] In one embodiment, the way to adjust the quantization circuit in step S23 may be to switch the up-down counting mode of the counting circuit. For example, the reference signal is quantized based on the up-counting method to obtain the first data (VRST). In this step, the quantization circuit is switched to the down-counting mode and continues to count down, that is, the image signal is quantized based on the down-counting method. At this time, the data corresponding to the image signal is the second data (VSIG), and the counting result is the total result of the two counts (up-counting and down-counting), that is, the target data (VCDS), so as to obtain the final quantization result, that is, the counting result to be stored.

[0178] It should be noted that in this embodiment, the counting order corresponding to the prior art in steps S21 - S25 can be adjusted according to the actual situation, as long as the technical effect of the present application can be achieved.

[0179] In other embodiments, the pixel circuit provides the first data and the second data at different gains, or the pixel circuit provides the first data and the second data at different phases, and the target data at the corresponding gain or the corresponding phase is obtained based on the quantization circuit.

[0180] In one example, the different gains may be high gain (HCG) and low gain (LCG), and the high gain and the low gain can be realized by controlling the on and off of the gain control transistor DCG in the pixel circuit. For example, the gain control transistor is turned on to quantize the data at low gain, and the data at low gain includes the first data (reset signal) and the second data (image signal) at low gain. Similarly, the gain control transistor is turned off to quantize the data at high gain, and the data at high gain includes the first data (reset signal) and the second data (image signal) at high gain, so as to realize correlated double sampling under dual gains.

[0181] In one example, the different phases may be left phase and right phase, and the left phase and the right phase can be realized by controlling the transmission control transistor in the pixel circuit or directly physically blocking the corresponding pixels, so as to obtain different phase information to achieve phase focusing. For example, the data of the left phase information includes the first data (reset signal) and the second data (image signal) at the left phase. Similarly, the data of the right phase information includes the first data (reset signal) and the second data (image signal) at the right phase, so as to realize correlated double sampling under the left and right phase information. Of course, it can also be the up and down phases or both groups.

[0182] In summary, the present invention simplifies the counter in the SS ADC, can eliminate the storage unit mem in the traditional solution, and enables the D flip-flop to realize the function of storing the quantization result after counting. The number of transistors in each stage of the counter can be reduced, and the layout area can be decreased, which is very significant for reducing the area of the entire ADC array. At the same time, since the layout of each stage of the counter is reduced, the wiring will also be shortened, the capacitance of the metal wire will be decreased, the charging and discharging current of the metal wire capacitance by the counter during counting will be reduced, and the power consumption of the counter will be decreased. When the normal analog-to-digital conversion function is realized, the chip area and power consumption can be reduced. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0183] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. All equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A quantization circuit, characterized in that, The quantization circuit includes N quantization units, and each quantization unit includes at least a counting and storage multiplexing unit, where N is an integer greater than or equal to 1; wherein: The counting and storage multiplexing unit includes a counting main module, a storage main module, and a storage control module connected in sequence. Among them, the counting and storage multiplexing units are cascaded. The quantization circuit realizes counting and obtains a counting result based on the counting main module and the storage main module in each quantization unit, and stores the counting result based on the storage main module and the storage control module in each quantization unit.

2. The quantization circuit according to claim 1, characterized in that, The counting main module includes an input stage module and a first transmission module. The storage main module includes a receiving stage module, a second transmission module, and a storage stage module. The receiving stage module receives the output data of the counting main module, where: The input stage module includes a first clock connection terminal and a data terminal, and is used to transmit the first data signal input at the data terminal and generate a second data signal under the control of the input clock at the first clock connection terminal; The first transmission module is connected to the output terminal of the input stage module, and is used to transmit the second data signal and generate a third data signal, and its output terminal serves as the output terminal of the counting main module; The receiving stage module includes a second clock connection terminal and a data receiving terminal. The data receiving terminal is connected to the output terminal of the counting main module, and is used to transmit the third data signal received at the data receiving terminal and generate a fourth data signal under the control of the input clock at the second clock connection terminal; The second transmission module is connected to the output terminal of the receiving stage module, and is used to transmit the fourth data signal and generate a fifth data signal; The storage stage module is connected in parallel at both ends of the second transmission module. The storage stage module includes a third clock connection terminal, and is used to store the fourth data signal and the fifth data signal under the control of the input clock at the third clock connection terminal to realize the storage of the counting result.

3. The quantization circuit according to claim 2, characterized in that, The storage control module is connected to the output terminal of the second transmission module and the input terminal of the storage stage module, and includes a data control terminal, and is used to output a signal corresponding to the fifth data signal under the control of the read control signal at the data control terminal.

4. The quantization circuit according to claim 3, characterized in that, The storage control module includes a read control module, which is used to cut off when the read control signal received at the read control terminal is at a first level, and conduct when the read control signal is at a second level different from the first level to realize data output; and / or, the storage control module includes a storage signal control module, which is used to process the fifth data signal and output a signal corresponding to the processed fifth data signal through the storage control module.

5. The quantization circuit according to claim 4, characterized in that, The read control module includes a second transmission control gate; and / or, the storage signal control module includes a third reverse logic gate to realize output after inverting the fifth data signal.

6. The quantization circuit according to claim 2, characterized in that, The counting main module further includes a latching module, which is connected in parallel at both ends of the first transmission module, and includes a fourth clock connection terminal for latching the second data signal and the third data signal under the control of the input clock at the fourth clock connection terminal; and / or, the quantization unit further includes a reset module, and the reset module is arranged in the second transmission module.

7. The quantization circuit according to claim 6, characterized in that, The input stage module includes a first tri-state inverter, which is in an operating state when the received input clock is at a first level and in a high-impedance state when the received input clock is at a second level different from the first level; the first transmission module includes a first reverse logic gate; the receiving stage module includes a first transmission control gate, which is turned on when the received input clock is at the first level and turned off when the received input clock is at the second level; the second transmission module includes a second reverse logic gate; the storage stage module includes a second tri-state inverter, which is in an operating state when the received input clock is at the first level and in a high-impedance state when the received input clock is at the second level. and / or, the reset module includes a first reset transistor and a second reset transistor, and is used to implement reset under the control of the inverted reset signal received by the gates of the first reset transistor and the second reset transistor.

8. The quantization circuit according to claim 1, characterized in that, The quantization unit further includes a selection element, the selection element includes a first selection input terminal, a second selection input terminal and an output terminal, the output terminal is connected to the clock input terminal of the corresponding quantization unit, the first selection input terminal is connected to the positive output terminal of the previous quantization unit, the second selection input terminal is connected to the inverted output terminal of the previous quantization unit, wherein, the first selection input terminal of the selection element of the first-stage quantization unit receives an initial logic signal, and the second selection input terminal receives the initial logic signal through reverse logic; and / or, the quantization unit further includes a holding element, the holding element includes a first selection input terminal, a second selection input terminal and an output terminal, the first selection input terminal of the holding element is connected to the positive output terminal of the corresponding quantization unit, the second selection input terminal of the holding element is connected to the inverted output terminal of the corresponding quantization unit, and the output terminal of the holding element is connected to the data terminal of the corresponding quantization unit.

9. The quantization circuit according to any one of claims 1-8, characterized in that, The quantization unit further includes a control logic gate, wherein, the first input terminal of the control logic gate is connected to the data output terminal of the previous quantization unit, the second input terminal of the control logic gate is connected to the read enable signal, and the output terminal of the control logic gate is connected to the clock input terminal of the corresponding quantization unit.

10. The quantization circuit according to claim 9, characterized in that, The control logic gate includes a NOR gate, the first input terminal of the NOR gate is the data output terminal of the previous quantization unit, the second input terminal is connected to the read enable signal, and the output terminal of the NOR gate is connected to the clock input terminal of the corresponding quantization unit.

11. An image sensor, characterized in that, Comprising a data readout circuit and a quantization circuit as described in any one of claims 1 - 10, the data readout circuit being coupled to the output terminal of the quantization circuit, the data readout circuit including a plurality of cascaded shift units, the shift units corresponding to the quantization units.

12. The image sensor according to claim 11, characterized in that, The shift unit includes a shift selection switch and a D flip - flop. When the shift selection switch is in the first state, the shift unit is coupled to the output terminal of the quantization unit to receive the corresponding count storage result. When in the second state, the shift unit is coupled to the output terminal of the previous - stage shift unit to achieve the shift readout of the count storage result. The output terminal of the D flip - flop serves as the output terminal of the shift unit.

13. An image data acquisition method, implemented based on the quantization circuit according to any one of claims 1-10, or, implemented based on the image sensor according to any one of claims 11 or 12, characterized in that, The method for obtaining image data includes: Resetting the quantization circuit; Based on a count enable signal and a clock control signal, performing counting through the count storage multiplexing unit to obtain the count result; Storing the count result through the count storage multiplexing unit; and Based on a read - out control signal, reading the stored count result from the quantization circuit to achieve the acquisition of image data.

14. The image data acquisition method according to claim 13, characterized in that, The image data includes first data and second data, and target data is obtained based on the difference between the first data and the second data. The method for obtaining the target data specifically includes the following steps: Resetting the quantization circuit; Obtaining a reference signal based on a pixel circuit and quantizing the reference signal to obtain the first data; Obtaining an image signal based on a pixel circuit, adjusting the quantization circuit, performing counting on the basis of the first data, and quantizing the image signal to obtain target data; Wherein, quantizing the image signal on the basis of the first data, the target data is obtained based on the first data corresponding to the reference signal and the second data corresponding to the image signal; Storing the target data based on the quantization circuit; and Reading out the target data based on a data readout circuit.

15. The image data acquisition method according to claim 14, wherein The pixel circuit provides first data and second data under different gains, or the pixel circuit provides first data and second data under different phases, and target data corresponding to the corresponding gain or phase is obtained based on the quantization circuit.

16. The image data acquisition method according to any one of claims 13 - 15, wherein When the quantization circuit includes the holding element and the control logic gate, the method further includes: When the counting ends, turning on the holding element to perform data holding; During the data holding process, turning on the control logic gate to perform mode switching.

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