Semiconductor device

Abstract

A semiconductor device may include: a bit line structure extending in a first direction; a channel layer on the bit line structure; a gate structure on the bit line structure and extending in a second direction crossing the first direction; and a data storage structure electrically connected to the channel layer. The bit line structure may include a first side surface parallel to the first direction and a second side surface parallel to the first direction, and the channel layer may include a first side surface parallel to the first direction and a second side surface parallel to the first direction. A first side surface of the bit line structure may be coplanar with a first side surface of the channel layer, and a second side surface of the bit line structure may be coplanar with a second side surface of the channel layer.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2023-0185721, filed with the Korean Intellectual Property Office on December 19, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including a bit line structure. Background Art

[0003] Due to the small size, multi-functionality, and / or low cost characteristics of semiconductor devices, semiconductor devices are considered important components in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including both memory elements and logic elements.

[0004] With the latest trends of high speed and low power consumption in electronic devices, semiconductor devices in electronic devices may also need to have high operating speed and / or low operating voltage, and in order to meet this requirement, increasing the integration degree of semiconductor devices can be beneficial. However, as the integration degree of semiconductor devices increases, semiconductor devices may suffer from deteriorated electrical characteristics and low product yield. Therefore, many studies are being conducted to improve the electrical characteristics and product yield of semiconductor devices. Summary of the Invention

[0005] Embodiments of the inventive concept provide semiconductor devices having improved electrical characteristics and increased integration degree.

[0006] According to an embodiment of the inventive concept, a semiconductor device may include: a bit line structure extending in a first direction; a channel layer on the bit line structure; a gate structure on the bit line structure and extending in a second direction intersecting the first direction; and a data storage structure electrically connected to the channel layer. The bit line structure may include a first side surface parallel to the first direction and a second side surface parallel to the first direction, and the channel layer may include a first side surface parallel to the first direction and a second side surface parallel to the first direction. The first side surface of the bit line structure may be coplanar with the first side surface of the channel layer, and the second side surface of the bit line structure may be coplanar with the second side surface of the channel layer.

[0007] According to an embodiment of the inventive concept, a semiconductor device may include: a gate-connected transistor; a shielding layer positioned at a height higher than that of the gate-connected transistor; a shielding insulating layer on the shielding layer; a gate-connected contact in the shielding insulating layer; a bit line structure on a top surface of the shielding insulating layer; a gate-connected pad on the top surface of the shielding insulating layer and on a top surface of the gate-connected contact; and a gate structure on the bit line structure. One of the gate structures in the gate structure may be electrically connected to the gate-connected transistor through the gate-connected pad and the gate-connected contact.

[0008] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate; a bit line-connected transistor on the substrate; a gate-connected transistor on the substrate; a peripheral circuit insulating layer on the substrate; a shielding layer on the peripheral circuit insulating layer; a shielding insulating layer on the shielding layer; a bit line structure on the shielding insulating layer; a gate-connected pad on the shielding insulating layer; a first gate-connected contact extending in the shielding insulating layer; a bit line-connected contact extending in the shielding insulating layer; a gate structure on the bit line structure; a channel layer on the bit line structure; a pad structure on the channel layer; and a data storage structure electrically connected to the pad structure. The gate structure may be electrically connected to the gate-connected transistor through the gate-connected pad and the first gate-connected contact, and the bit line structure may be electrically connected to the bit line-connected transistor through the bit line-connected contact.

[0009] According to an embodiment of the inventive concept, a method of manufacturing a semiconductor device may include: forming a shielding layer, forming a shielding insulating layer on the shielding layer, forming a preliminary bit line structure and a material layer on the shielding insulating layer, patterning the material layer and the preliminary bit line structure to respectively form a preliminary channel layer and a bit line structure, and patterning the preliminary channel layer to form a channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram showing a semiconductor device according to an embodiment of the inventive concept.

[0011] Figure 2 and Figure 3 is a perspective view schematically showing a semiconductor device according to an embodiment of the inventive concept.

[0012] Figure 4A is a plan view showing a semiconductor device according to an embodiment of the inventive concept.

[0013] Figure 4B is Figure 4A a cross-sectional view taken along line A-A' of

[0014] Figure 4C is Figure 4A a cross-sectional view taken along line B-B' of

[0015] Figure 4D Yes Figure 4B is an enlarged cross-sectional view of part “E”.

[0016] Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B and Figure 9 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0017] Figure 10A and Figure 10B are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0018] Figure 11A and Figure 11B are cross-sectional views showing a semiconductor device according to an embodiment of the inventive concept.

[0019] Figure 12A and Figure 12B are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. Detailed Description

[0020] Figure 1 is a block diagram showing a semiconductor device according to an embodiment of the inventive concept.

[0021] Referring to Figure 1 , the semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and a control logic 5.

[0022] The memory cell array 1 may include a plurality of memory cells MC arranged two-dimensionally or three-dimensionally. Each memory cell MC may be disposed between a word line WL and a bit line BL that cross each other and connected to the word line WL and the bit line BL that cross each other.

[0023] Each memory cell MC may include a selection element TR and a data storage device (or data storage element) DS. The selection element TR and the data storage element DS may be electrically connected to each other. The selection element TR may be connected to both the word line WL and the bit line BL. In other words, the selection element TR may be disposed at the intersection of the word line WL and the bit line BL.

[0024] The selection element TR may include a field effect transistor. The data storage element DS may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. As an example, the selection element TR may be a transistor whose gate terminal, source terminal, and drain terminal are connected to the word line WL, the bit line BL, and the data storage device DS, respectively.

[0025] The row decoder 2 may be configured to decode address information input from the outside (i.e., from outside the row decoder 2 and / or the semiconductor device), and select one word line among the word lines WL of the memory cell array 1 based on the decoded address information. The address information decoded by the row decoder 2 may be provided to a row driver (not shown), and in this case, the row driver may supply a corresponding voltage to the selected word line and the unselected word lines among the word lines WL in response to the control of the control circuit.

[0026] The sense amplifier 3 may be configured to sense, amplify, and output the voltage difference between "one bit line selected based on the address information decoded by the column decoder 4 in the bit line BL" and the reference bit line.

[0027] The column decoder 4 may establish a data transfer path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 may be configured to decode address information input from the outside (e.g., from an external device), and select one bit line among the bit lines BL based on the decoded address information.

[0028] The control logic 5 may generate a control signal for controlling an operation of writing data to the memory cell array 1 or reading data from the memory cell array 1.

[0029] Figure 2 and Figure 3 is a perspective view schematically showing a semiconductor device according to an embodiment of the inventive concept.

[0030] Referring to Figure 2 and Figure 3 , the semiconductor device may include a peripheral circuit structure PS and a cell array structure CS connected to the peripheral circuit structure PS.

[0031] The peripheral circuit structure PS may include a core circuit and a peripheral circuit formed on a substrate SUB. The core circuit and the peripheral circuit may include the row decoder 2, the column decoder 4, the sense amplifier 3, and the control logic 5 described with reference to Figure 1 .

[0032] The cell array structure CS may include Figure 1 in which memory cells MC are two-dimensionally or three-dimensionally arranged Figure 1Memory cell array 1. As described above, each memory cell MC may include a selection element TR and a data storage device DS.

[0033] In one embodiment, Figure 1 The selection element TR of each memory cell MC may include a vertical channel transistor (VCT). The vertical channel transistor may have a channel region whose length direction is substantially perpendicular to the top surface of the substrate SUB. Figure 1 The data storage device DS of each memory cell MC may include a capacitor.

[0034] In Figure 2 the embodiment, a peripheral circuit structure PS may be disposed on the substrate SUB, and a cell array structure CS may be disposed on the peripheral circuit structure PS.

[0035] In Figure 3 the embodiment, the peripheral circuit structure PS may be disposed on a first substrate SUB1, and the cell array structure CS may be disposed on a second substrate SUB2 disposed facing the first substrate SUB1.

[0036] A first metal pad (or called a bonding pad) LMP may be disposed at the uppermost part of the peripheral circuit structure PS. The first metal pad LMP may be electrically connected to the core circuit and the peripheral circuit (e.g., Figure 1 the row decoder 2, the sense amplifier 3, the column decoder 4, and the control logic 5).

[0037] A second metal pad UMP may be disposed at the lowermost part of the cell array structure CS. The second metal pad UMP may be electrically connected to Figure 1 the memory cell array 1. The second metal pad UMP may be directly bonded to the first metal pad LMP of the peripheral circuit structure PS (i.e., in direct contact with the first metal pad LMP of the peripheral circuit structure PS).

[0038] Figure 4A is a plan view of a semiconductor device according to an embodiment of the inventive concept. Figure 4B is Figure 4A a cross-sectional view taken along line A - A' of Figure 4C is Figure 4A a cross-sectional view taken along line B - B' of Figure 4D is Figure 4B an enlarged cross-sectional view of part "E" of

[0039] Referring to Figures 4A to 4D , a substrate 100 may be provided. The substrate 100 may be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0040] The substrate 100 may be a plate-like structure extending parallel to a plane defined by a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may not be parallel to each other. As an example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other. Further, depending on the context, the first direction D1 and the second direction D2 may be referred to herein as the "second" direction and the "first" direction, respectively (such as when the direction D2 is mentioned before the direction D1).

[0041] The peripheral transistors PTR may be disposed on the substrate 100. Each peripheral transistor PTR may include an impurity region 111, a peripheral gate insulating layer 112, a first peripheral gate electrode layer 113, and a second peripheral gate electrode layer 114. The impurity region 111 may be formed by doping the substrate 100 with impurities. The peripheral gate insulating layer 112 may include an insulating material. The first peripheral gate electrode layer 113 and the second peripheral gate electrode layer 114 may include a conductive material. In one embodiment, the first peripheral gate electrode layer 113 may be formed of or include polysilicon, and the second peripheral gate electrode layer 114 may be formed of or include a metal material.

[0042] The peripheral transistors PTR may include a gate connection transistor GTR and a bit line connection transistor BTR. The gate connection transistor GTR may be electrically connected to a gate structure GS to be described below. In one embodiment, the gate connection transistor GTR may be a transistor that serves as part of a sub-word line driver. The bit line connection transistor BTR may be electrically connected to a bit line structure BS to be described below. In one embodiment, the bit line connection transistor BTR may be a transistor that serves as part of a sense amplifier.

[0043] A peripheral circuit insulating layer 120 may be disposed on the substrate 100. The peripheral circuit insulating layer 120 may cover the peripheral transistors PTR. The peripheral circuit insulating layer 120 may include an insulating material. In one embodiment, the peripheral circuit insulating layer 120 may have a multi-layer structure including a plurality of insulating layers.

[0044] A peripheral conductive structure 130 may be disposed in the peripheral circuit insulating layer 120. At least one of the peripheral conductive structures 130 may be electrically connected to the peripheral transistors PTR. The peripheral conductive structure 130 may include a conductive material. The peripheral conductive structure 130 may be formed of or include at least one of, for example, a conductive contact, a wire, and a conductive pad.

[0045] A shielding layer SL may be disposed on the peripheral circuit insulating layer 120. The shielding layer SL may include a conductive material. A shielding insulating layer SI may be disposed on the shielding layer SL. The shielding insulating layer SI may include an insulating material. In one embodiment, the shielding insulating layer SI may have a multi-layer structure including a plurality of insulating layers.

[0046] The shielding insulating layer SI can be in contact with the top surface of the shielding layer SL, the side surface of the shielding layer SL, and the top surface of the peripheral circuit insulating layer 120. The shielding layer SL and the shielding insulating layer SI can be disposed at a height higher than that of the substrate 100 and the peripheral transistors PTR.

[0047] The first gate connection contact GC1 can be disposed in the shielding insulating layer SI (e.g., is disposed to penetrate the shielding insulating layer SI). The first gate connection contact GC1 can extend in the third direction D3 through the shielding insulating layer SI. The third direction D3 may not be parallel to the first direction D1 and the second direction D2. As an example, the third direction D3 can be a vertical direction orthogonal to the first direction D1 and the second direction D2. The first gate connection contact GC1 can include a conductive material.

[0048] The bottom surface of the first gate connection contact GC1 can be in contact with the top surface of the peripheral conductive structure 130. In the third direction D3, the height of the bottom surface of the first gate connection contact GC1 can be lower than the height of the bottom surface of the shielding layer SL and the height of the bottom surface of the shielding insulating layer SI. Thus, the distance in the third direction D3 from the bottom surface of the first gate connection contact GC1 to the substrate 100 can be less than the distance in the third direction D3 from the bottom surface of the shielding layer SL to the substrate 100 and the distance in the third direction D3 from the bottom surface of the shielding insulating layer SI to the substrate 100. The top surface of the first gate connection contact GC1 can be coplanar with the top surface SI_T of the shielding insulating layer SI. Thus, the top surface of the first gate connection contact GC1 can be at the same height as the top surface SI_T of the shielding insulating layer SI.

[0049] The gate connection pad GA can be disposed on the first gate connection contact GC1 and the shielding insulating layer SI. The gate connection pad GA can be disposed at a height higher than that of the shielding insulating layer SI in the third direction D3. The bottom surface GA_B of the gate connection pad GA can be in contact with the top surface SI_T of the shielding insulating layer SI and the top surface of the first gate connection contact GC1. In the third direction D3, the height of the top surface of the gate connection pad GA can be lower than the height of the top surface of the bit line structure BS to be described below. The gate connection pad GA can include a conductive material.

[0050] The gate connection pad GA and the first gate connection contact GC1 can be electrically connected to the gate connection transistor GTR through the peripheral conductive structure 130.

[0051] The bit line connection contact BO can be disposed in the shielding insulating layer SI (e.g., is disposed to penetrate the shielding insulating layer SI). The bit line connection contact BO can extend in the third direction D3 through the shielding insulating layer SI. The bit line connection contact BO can include a conductive material.

[0052] The bottom surface of the bit line connecting contact BO can be in contact with the top surface of the peripheral conductive structure 130. In the third direction D3, the height of the bottom surface of the bit line connecting contact BO can be lower than the height of the bottom surface of the shielding layer SL and the height of the bottom surface of the shielding insulating layer SI. The top surface of the bit line connecting contact BO can be coplanar with the top surface SI_T of the shielding insulating layer SI.

[0053] The bit line connecting contact BO can be electrically connected to the bit line connecting transistor BTR through the peripheral conductive structure 130. The bit line connecting contact BO can be disposed between the bit line connecting transistor BTR and the bit line structure BS.

[0054] The bit line structure BS can be disposed on the shielding insulating layer SI. The bit line structure BS can extend in the second direction D2 (e.g., longitudinally). The bit line structures BS can be spaced apart from each other in the first direction D1.

[0055] Each bit line structure BS can include a first portion P1 that overlaps with the shielding layer SL in the third direction D3 and a second portion P2 that does not overlap with the shielding layer SL in the third direction D3. The second portion P2 of the bit line structure BS can be in contact with the bit line connecting contact BO. The length of the bit line structure BS in the second direction D2 can be greater than the length of the shielding layer SL in the second direction D2.

[0056] The bottom surface BS_B of the bit line structure BS can be coplanar with the bottom surface GA_B of the gate connection pad GA. The bottom surface BS_B of the bit line structure BS can be in contact with the top surface SI_T of the shielding insulating layer SI and the top surface of the bit line connecting contact BO. The bit line structure BS can be electrically connected to the bit line connecting transistor BTR through the bit line connecting contact BO and the peripheral conductive structure 130. In the third direction D3, the height of the top surface of the bit line structure BS can be higher than the height of the top surface of the gate connection pad GA.

[0057] Each bit line structure BS can include a first bit line layer BC1 on the shielding insulating layer SI, a second bit line layer BC2 on the first bit line layer BC1, and a third bit line layer BC3 on the second bit line layer BC2. The third bit line layer BC3 can include a conductive material different from the first bit line layer BC1 and the second bit line layer BC2. In one embodiment, the third bit line layer BC3 can be formed of or include polysilicon, and the first bit line layer BC1 and the second bit line layer BC2 can be formed of or include a metal material.

[0058] The number of the bit line layers BC1, BC2, and BC3 included in the bit line structure BS is not limited to the illustrated example. In one embodiment, the number of the bit line layers BC1, BC2, and BC3 included in the bit line structure BS can be less than or equal to two, or can be greater than or equal to four.

[0059] The shielding pattern SP may be disposed on the shielding layer SL. The shielding pattern SP may extend in the second direction D2. The shielding patterns SP may be spaced apart from each other in the first direction D1. The shielding patterns SP may be disposed between two bit line structures BS adjacent to each other in the first direction D1. The bottom surface of the shielding pattern SP may be in contact with the top surface of the shielding layer SL. The shielding pattern SP may extend in the shielding insulating layer SI (e.g., through the shielding insulating layer SI). The shielding pattern SP may include a conductive material.

[0060] The shielding spacers SS may be disposed on the shielding insulating layer SI. The shielding spacers SS may extend in the second direction D2. The shielding spacers SS may be arranged to be spaced apart from each other in the first direction D1. Two shielding spacers SS may be disposed between two bit line structures BS adjacent to each other in the first direction D1. The shielding pattern SP may be disposed between two shielding spacers SS spaced apart from each other in the first direction D1. In one embodiment, two shielding spacers SS may be disposed on the back-to-back side surfaces of the shielding pattern SP.

[0061] The shielding spacers SS may be disposed between the bit line structure BS and the shielding pattern SP in the first direction D1. The shielding pattern SP may be spaced apart from the bit line structure BS by the shielding spacers SS. The bottom surface SS_B of the shielding spacer SS may be in contact with the top surface SI_T of the shielding insulating layer SI. In the third direction D3, the height of the bottom surface SS_B of the shielding spacer SS may be higher than the height of the bottom surface of the shielding pattern SP. The shielding spacers SS may include an insulating material.

[0062] The first interlayer insulating layer 140 may be disposed on the shielding insulating layer SI. The gate connection pad GA may be disposed in the first interlayer insulating layer 140. The first interlayer insulating layer 140 may be arranged to surround the gate connection pad GA. The first interlayer insulating layer 140 may be in contact with the side surfaces of the bit line structure BS and the side surfaces of the gate connection pad GA. The first interlayer insulating layer 140 may include an insulating material. In one embodiment, the first interlayer insulating layer 140 may have a multilayer structure including a plurality of insulating layers.

[0063] The channel layer CL may be provided. A plurality of channel layers CL may be disposed on one bit line structure BS. The channel layers CL disposed on one bit line structure BS may be spaced apart from each other in the second direction D2. The channel layer CL may include a semiconductor material. For example, the channel layer CL may be formed of or include silicon or germanium.

[0064] Each channel layer CL may include a first side surface CL_S1 and a second side surface CL_S2 parallel to the second direction D2. The first side surface CL_S1 and the second side surface CL_S2 of the channel layer CL may face away from each other.

[0065] The bit line structure BS may include a first side surface BS_S1 and a second side surface BS_S2 parallel to the second direction D2. The first side surface BS_S1 and the second side surface BS_S2 may be two opposite surfaces of the bit line structure BS.

[0066] The first side surface CL_S1 of the channel layer CL and the first side surface BS_S1 of the bit line structure BS may be coplanar with each other. The first side surface CL_S1 of the channel layer CL and the first side surface BS_S1 of the bit line structure BS may be arranged on a single straight line (e.g., extending in the third direction D3). The first side surface CL_S1 of the channel layer CL and the first side surface BS_S1 of the bit line structure BS may be connected to each other. For example, the highest point of the first side surface BS_S1 may contact the lowest point of the first side surface CL_S1.

[0067] The second side surface CL_S2 of the channel layer CL and the second side surface BS_S2 of the bit line structure BS may be coplanar with each other. The second side surface CL_S2 of the channel layer CL and the second side surface BS_S2 of the bit line structure BS may be arranged on a single straight line (e.g., extending in the third direction D3). The second side surface CL_S2 of the channel layer CL and the second side surface BS_S2 of the bit line structure BS may be connected to each other. For example, the highest point of the second side surface BS_S2 may contact the lowest point of the second side surface CL_S2.

[0068] In one embodiment, the distance between the first side surface CL_S1 and the second side surface CL_S2 of the channel layer CL in the first direction D1 may be substantially equal to the distance between the first side surface BS_S1 and the second side surface BS_S2 of the bit line structure BS in the first direction D1. In one embodiment, the width W1 of the channel layer CL in the first direction D1 may be equal to the width W2 of the bit line structure BS in the first direction D1. In addition, the channel layer CL may be thicker than the bit line structure BS in the third direction D3.

[0069] The shielding spacer SS may include a first side surface SS_S1 in contact with the side surface BS_S1 or BS_S2 of the bit line structure BS and a second side surface SS_S2 in contact with the side surface SP_S of the shielding pattern SP. The upper part of the side surface SP_S of the shielding pattern SP may be in contact with the second side surface SS_S2 of the shielding spacer SS. The lower part of the side surface SP_S of the shielding pattern SP may be in contact with the side surface of the shielding insulating layer SI.

[0070] A gate structure GS may be provided. The gate structure GS may be provided on the bit line structure BS. The gate structure GS may extend in the first direction D1. The gate structures GS may be arranged to be spaced apart from each other in the second direction D2.

[0071] The gate structure GS may include two gate insulating layers GI, two gate electrode layers GE, two lower gate insulating layers LGI, an intermediate gate insulating layer IGI, and a gate capping layer GP.

[0072] The two gate electrode layers GE, the two lower gate insulating layers LGI, and the intermediate gate insulating layer IGI may be disposed between the two gate insulating layers GI. The intermediate gate insulating layer IGI may be disposed between the two gate electrode layers GE and between the two lower gate insulating layers LGI.

[0073] The gate insulating layer GI, the lower gate insulating layer LGI, and the intermediate gate insulating layer IGI may be disposed on the bit line structure BS. The gate electrode layer GE may be disposed on the lower gate insulating layer LGI. The gate capping layer GP may be disposed on the gate insulating layer GI, the gate electrode layer GE, and the intermediate gate insulating layer IGI. The gate insulating layer GI may be in contact with the side surfaces CL_S1 or CL_S2 of the channel layer CL, the side surface of the gate electrode layer GE, and the side surface of the lower gate insulating layer LGI. The bottom surface of the gate insulating layer GI may be in contact with the top surface of the shielding spacer SS. The bottom surface of the lower gate insulating layer LGI may be in contact with the top surface of the shielding pattern SP.

[0074] The gate electrode layer GE may include a conductive material. Each of the gate insulating layer GI, the lower gate insulating layer LGI, the intermediate gate insulating layer IGI, and the gate capping layer GP may include an insulating material.

[0075] A back gate structure BGS may be provided. The back gate structure BGS may be disposed on the bit line structure BS. The back gate structure BGS and the gate structure GS may be alternately arranged in the second direction D2. Each back gate structure BGS may include two back gate spacers BSP, a lower back gate insulating layer BGI1, a back gate electrode layer BGE, and an upper back gate insulating layer BGI2.

[0076] The lower back gate insulating layer BGI1, the back gate electrode layer BGE, and the upper back gate insulating layer BGI2 may be disposed between the two back gate spacers BSP. The back gate spacers BSP and the lower back gate insulating layer BGI1 may be disposed on the bit line structure BS. The back gate electrode layer BGE may be disposed on the lower back gate insulating layer BGI1. The upper back gate insulating layer BGI2 may be disposed on the back gate electrode layer BGE.

[0077] The back gate electrode layer BGE may include a conductive material. Each of the back gate spacers BSP, the lower back gate insulating layer BGI1, and the upper back gate insulating layer BGI2 may include an insulating material.

[0078] A settable pad structure PA and an insulating pattern IP can be provided. The pad structure PA can be provided on the gate structure GS, the channel layer CL, and the back gate structure BGS. The insulating pattern IP can be provided between the pad structures PA. The pad structures PA can be spaced apart from each other by the insulating pattern IP. The pad structure PA can include a conductive material. In one embodiment, the pad structure PA can include a plurality of conductive layers. The insulating pattern IP can include an insulating material. In one embodiment, the insulating pattern IP can include a plurality of insulating layers.

[0079] A data storage structure DA can be provided on the pad structure PA and the insulating pattern IP. The data storage structure DA can be electrically connected to the channel layer CL through the pad structure PA. In one embodiment, the data storage structure DA can be a capacitor. In this case, the data storage structure DA can include a bottom electrode, a top electrode, and a capacitor dielectric layer disposed between the bottom electrode and the top electrode. In one embodiment, the data storage structure DA can be a variable resistance pattern whose resistance can be switched to one of at least two states by an electrical pulse applied thereto. For example, the data storage structure DA can be formed of or include at least one of a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, and an antiferromagnetic material, and the crystallization state of the phase change material can be changed according to the amount of current applied thereto.

[0080] A second interlayer insulating layer 150 can be provided on the first interlayer insulating layer 140 and the bit line structure BS. The second interlayer insulating layer 150 can include an insulating material. In one embodiment, the second interlayer insulating layer 150 can have a multilayer structure including a plurality of insulating layers.

[0081] A second gate connection contact GC2, a third gate connection contact GC3, and a gate connection line GL can be provided. The second gate connection contact GC2 can extend in a third direction D3 (e.g., through the first interlayer insulating layer 140 and the second interlayer insulating layer 150) in the first interlayer insulating layer 140 and the second interlayer insulating layer 150. The bottom surface of the second gate connection contact GC2 can be in contact with the top surface of the gate connection pad GA. The third gate connection contact GC3 can extend in the third direction D3 in the gate covering layer GP and the second interlayer insulating layer 150 (e.g., through the gate covering layer GP and the second interlayer insulating layer 150). The bottom surface of the third gate connection contact GC3 can be in contact with the top surface of the gate electrode layer GE. The bottom surface of the gate connection line GL can be in contact with the top surfaces of the second gate connection contact GC2 and the third gate connection contact GC3.

[0082] The gate electrode layer GE of the gate structure GS can be electrically connected to the gate connection pad GA through the third gate connection contact GC3, the gate connection line GL, and the second gate connection contact GC2. Each of the third gate connection contact GC3, the gate connection line GL, and the second gate connection contact GC2 may include a conductive material.

[0083] In a semiconductor device according to an embodiment of the inventive concept, since the bit line connection contact BO is directly bonded to the bit line structure BS (i.e., in contact with the bit line structure BS), an additional interconnection line for electrically connecting the bit line structure BS to the bit line connection contact BO can be omitted. This can increase the degree of freedom in designing the semiconductor device, simplify the manufacturing process of the semiconductor device, and reduce the size of the semiconductor device.

[0084] In a semiconductor device according to an embodiment of the inventive concept, since the gate connection pad GA is disposed on the shielding insulating layer SI, the gate connection pad GA can be electrically connected to the gate structure GS relatively easily, and the size of the gate connection pad GA can be reduced.

[0085] Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B and Figure 9 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0086] Referring to Figure 5A and Figure 5B ,peripheral transistors PTR can be formed on the substrate 100. A peripheral circuit insulating layer 120 can be formed on the substrate 100. Peripheral conductive structures 130 can be formed in the peripheral circuit insulating layer 120.

[0087] A shielding layer SL can be formed on the peripheral circuit insulating layer 120. A shielding insulating layer SI can be formed on the shielding layer SL. A first gate connection contact GC1 and a bit line connection contact BO can be formed. Forming the first gate connection contact GC1 and the bit line connection contact BO may include: forming a hole in the shielding insulating layer SI (e.g., forming a hole to penetrate the shielding insulating layer SI), and forming the first gate connection contact GC1 and the bit line connection contact BO in the hole. The top surfaces of the first gate connection contact GC1 and the bit line connection contact BO can be exposed to the outside of the shielding insulating layer SI. For example, the top surfaces of the first gate connection contact GC1 and the bit line connection contact BO can be exposed through the top surface of the shielding insulating layer SI.

[0088] Referring to Figure 6A andFigure 6B A preliminary bit line structure pBS can be formed. The preliminary bit line structure pBS may include a first preliminary bit line layer pBC1, a second preliminary bit line layer pBC2 on the first preliminary bit line layer pBC1, and a third preliminary bit line layer pBC3 on the second preliminary bit line layer pBC2. The first preliminary bit line layer to the third preliminary bit line layers pBC1, pBC2, and pBC3 can be sequentially formed by a deposition process.

[0089] The bottom surface of the first preliminary bit line layer pBC1 of the preliminary bit line structure pBS can be in contact with the top surface of the first gate connection contact GC1, the top surface of the bit line connection contact BO, and the top surface of the shielding insulating layer SI.

[0090] Referring Figure 7A and Figure 7B , a material layer ML can be formed on the preliminary bit line structure pBS. The material layer ML can be bonded to the third preliminary bit line layer pBC3 of the preliminary bit line structure pBS through a wafer bonding process. The material layer ML can be a semiconductor substrate. For example, the material layer ML can be a silicon substrate or a germanium substrate.

[0091] In one embodiment, the material layer ML can be formed on the third preliminary bit line layer pBC3 of the preliminary bit line structure pBS by a deposition process.

[0092] Referring Figure 8A and Figure 8B , the material layer ML and the preliminary bit line structure pBS can be patterned. As a result of the patterning step, the material layer ML can form separated preliminary channel layers pCL. Similarly, the preliminary bit line structure pBS can form separated bit line structures BS. The preliminary channel layers pCL can extend in the second direction D2.

[0093] In one embodiment, patterning the material layer ML and the preliminary bit line structure pBS may include: forming a mask pattern on the material layer ML, and using the mask pattern as an etching mask to pattern the material layer ML and the preliminary bit line structure pBS.

[0094] In one embodiment, patterning the material layer ML and the preliminary bit line structure pBS may include: forming a mask pattern on the material layer ML, using the mask pattern as an etching mask to pattern the material layer ML to form the preliminary channel layers pCL, and using the preliminary channel layers pCL as an etching mask to pattern the preliminary bit line structure pBS.

[0095] The side surfaces of the preliminary channel layers pCL can be coplanar with the side surfaces of the bit line structures BS. In one embodiment, the width of the preliminary channel layers pCL in the first direction D1 can be equal to the width of the bit line structures BS in the first direction D1.

[0096] As a result of patterning the preliminary bit line structure pBS, the top surface of the first gate connection contact GC1 may be exposed to the outside.

[0097] Referring to Figure 9 , a shielding pattern SP and shielding spacers SS may be formed. Forming the shielding pattern SP and the shielding spacers SS may include: conformally forming a shielding spacer layer on a side surface of the bit line structure BS and a top surface of the shielding insulating layer SI, forming trenches in the shielding spacer layer and the shielding insulating layer SI (e.g., forming trenches in the shielding spacer layer and the shielding insulating layer SI to penetrate the shielding spacer layer and the shielding insulating layer SI), and forming the shielding pattern SP in the trenches. As a result of forming the trenches, the shielding spacer layer may be divided into two shielding spacers SS.

[0098] A gate connection pad GA may be formed on the first gate connection contact GC1. A first interlayer insulating layer 140 may be formed on the gate connection pad GA.

[0099] Referring to Figures 4A to 4D , the preliminary channel layer pCL may be patterned. As a result, the preliminary channel layer pCL may form channel layers CL separated from each other. In addition, a back gate structure BGS and a gate structure GS may be formed. Thereafter, a pad structure PA, an insulating pattern IP, and a data storage structure DA may be formed. A second interlayer insulating layer 150 may be formed on the first interlayer insulating layer 140. In addition, a second gate connection contact GC2, a third gate connection contact GC3, and a gate connection line GL may be formed.

[0100] In a manufacturing method according to an embodiment of the inventive concept, a preliminary bit line structure pBS and a material layer ML may be formed on a shielding insulating layer SI, and then, the channel layer CL and the bit line structure BS may be formed by patterning the material layer ML and the preliminary bit line structure pBS. Since a wafer bonding process is not performed after forming the channel layer CL and the bit line structure BS, it may not be necessary to form relatively large pads to reduce misalignment problems that may be caused by the wafer bonding process, and the size of the gate connection pad GA may be reduced. Accordingly, the size of the semiconductor device may be reduced.

[0101] In a manufacturing method according to an embodiment of the inventive concept, since the bit line structure BS is formed on a bit line connection contact BO through a deposition process, additional interconnection lines for connecting the bit line structure BS to the bit line connection contact BO may be omitted. Accordingly, the degree of freedom in designing the semiconductor device may be increased and the size of the semiconductor device may be reduced.

[0102] Figure 10A and Figure 10B are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0103] Referring toFigure 10A and Figure 10B , it can be formed into a shielding layer SL, a shielding insulating layer SI, a first gate connection contact GC1, and a bit line connection contact BO similar to the embodiments of Figure 5A and Figure 5B .

[0104] A first preliminary bit line layer pBC1 can be formed on the shielding insulating layer SI, the first gate connection contact GC1, and the bit line connection contact BO. The first preliminary bit line layer pBC1 can be formed by a deposition process.

[0105] A third preliminary bit line layer pBC3 can be formed on the material layer ML, and a second preliminary bit line layer pBC2 can be formed on the third preliminary bit line layer pBC3. The third preliminary bit line layer pBC3 and the second preliminary bit line layer pBC2 can be formed by a deposition process.

[0106] A wafer bonding process can be performed to bond the second preliminary bit line layer pBC2 to the first preliminary bit line layer pBC1.

[0107] Thereafter, the remaining subsequent processes can be performed in a manner similar to the embodiments of Figure 8A , Figure 8B , Figure 9 , Figure 4A , Figure 4B , Figure 4C and Figure 4D .

[0108] Figure 11A and Figure 11B are cross-sectional views showing semiconductor devices according to embodiments of the inventive concept. Except for the features described below, Figure 11A and Figure 11B The semiconductor devices can have features similar to those of the semiconductor devices of Figures 4A to 4D .

[0109] Referring to Figure 11A and Figure 11B , a first bonding insulating layer BI1 can be provided on the shielding insulating layer SI. A second bonding insulating layer BI2 can be provided on the first bonding insulating layer BI1. A bit line structure BS and a first interlayer insulating layer 140 can be provided on the second bonding insulating layer BI2. A shielding pattern SP can be in the second bonding insulating layer BI2, the first bonding insulating layer BI1, and the shielding insulating layer SI (e.g., can penetrate the second bonding insulating layer BI2, the first bonding insulating layer BI1, and the shielding insulating layer SI). The bottom surface of the shielding spacer SS can be in contact with the top surface of the second bonding insulating layer BI2. Each of the first bonding insulating layer BI1 and the second bonding insulating layer BI2 can include an insulating material.

[0110] The first gate connection pad GA1 and the first bit line connection pad BA1 may be disposed in the first bonding insulating layer BI1. The second gate connection pad GA2 and the second bit line connection pad BA2 may be disposed in the second bonding insulating layer BI2.

[0111] The bottom surface of the first gate connection pad GA1 may be in contact with the top surface of the first gate connection contact GC1. The top surface of the first gate connection pad GA1 may be in contact with the bottom surface of the second gate connection pad GA2. The top surface of the second gate connection pad GA2 may be in contact with the bottom surface of the second gate connection contact GC2.

[0112] The gate electrode layer GE of the gate structure GS may be electrically connected to the gate connection transistor GTR through the third gate connection contact GC3, the gate connection line GL, the second gate connection contact GC2, the second gate connection pad GA2, the first gate connection pad GA1, the first gate connection contact GC1, and the peripheral conductive structure 130.

[0113] The bottom surface of the first bit line connection pad BA1 may be in contact with the top surface of the bit line connection contact BO. The top surface of the first bit line connection pad BA1 may be in contact with the bottom surface of the second bit line connection pad BA2. The top surface of the second bit line connection pad BA2 may be in contact with the bottom surface of the first bit line layer BC1 of the bit line structure BS.

[0114] The bit line structure BS may be electrically connected to the bit line connection transistor BTR through the second bit line connection pad BA2, the first bit line connection pad BA1, the bit line connection contact BO, and the peripheral conductive structure 130.

[0115] Figure 12A and Figure 12B is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0116] Referring to Figure 12A and Figure 12B it is possible to form the shielding layer SL, the shielding insulating layer SI, the first gate connection contact GC1, and the bit line connection contact BO similar to the embodiments of Figure 5A and Figure 5B The first bonding insulating layer BI1 may be formed on the shielding insulating layer SI. The first bonding insulating layer BI1 may be formed through a deposition process. The first gate connection pad GA1 and the first bit line connection pad BA1 may be formed in the first bonding insulating layer BI1.

[0117]

[0118] ​A third preliminary bit line layer pBC3 may be formed on the material layer ML. A second preliminary bit line layer pBC2 may be formed on the third preliminary bit line layer pBC3. A first preliminary bit line layer pBC1 may be formed on the second preliminary bit line layer pBC2. A second bonding insulation layer BI2 may be formed on the first preliminary bit line layer pBC1. The first preliminary bit line layer to the third preliminary bit line layer pBC1, pBC2, and pBC3 and the second bonding insulation layer BI2 may be formed by a deposition process.

[0119] A second gate connection pad GA2 and a second bit line connection pad BA2 may be formed in the second bonding insulation layer BI2.

[0120] A hybrid wafer bonding process may be performed. As a result of the wafer bonding process, the first bonding insulation layer BI1 may be bonded to the second bonding insulation layer BI2. The first gate connection pad GA1 may be bonded to the second gate connection pad GA2 through the wafer bonding process. The first bit line connection pad BA1 may be bonded to the second bit line connection pad BA2 through the wafer bonding process.

[0121] In a semiconductor device according to an embodiment of the inventive concept, since the bit line structure is directly bonded to the bit line connection contact, an additional interconnection line for electrically connecting the bit line structure to the bit line connection contact may be omitted.

[0122] In a method of manufacturing a semiconductor device according to an embodiment of the inventive concept, since a wafer bonding process is not performed after forming the channel layer and the bit line structure, a relatively large pad does not need to be formed to reduce misalignment problems caused by the wafer bonding process, and the size of the gate connection pad may be reduced.

[0123] Although example embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device, comprising: A bit line structure extending in a first direction; Channel layer, on the bit line structure; a gate structure on the bit line structure and extending in a second direction intersecting the first direction; as well as The data storage structure is electrically connected to the channel layer, The bit line structure includes a first side surface parallel to the first direction and a second side surface parallel to the first direction. The channel layer includes a first side surface parallel to the first direction and a second side surface parallel to the first direction. The first side surface of the bit line structure is coplanar with the first side surface of the channel layer, and The second side surface of the bit line structure is coplanar with the second side surface of the channel layer.

2. The semiconductor device according to claim 1, in, The width of the bit line structure in the second direction is equal to the width of the channel layer in the second direction, and The channel layer is thicker than the bit line structure in the vertical direction.

3. The semiconductor device according to claim 1, further comprising: a shielding pattern spaced apart from the bit line structure in the second direction; a shielding spacer between the bit line structure and the shielding pattern in the second direction, wherein the shielding spacer contacts a side surface of the shielding pattern and a first side surface or a second side surface of the bit line structure; and a shielding layer, contacting a bottom surface of the shielding pattern, The bit line structure is overlapped with the shielding layer in a vertical direction.

4. The semiconductor device according to claim 3, wherein: The gate structure includes: a lower gate insulating layer on the shielding pattern; a gate electrode layer on the lower gate insulating layer; and The gate insulating layer contacts a side surface of the gate electrode layer and a first side surface or a second side surface of the channel layer.

5. The semiconductor device according to claim 1, further comprising: a shielding insulating layer in contact with a bottom surface of the bit line structure; as well as The bit line connection contact, in the shielding insulating layer, The top surface of the bit line connection contact is in contact with the bottom surface of the bit line structure.

6. The semiconductor device according to claim 5, further comprising: substrate; A bit line connected transistor is on the substrate; as well as A peripheral conductive structure electrically connected to the bit line connection transistor, wherein the bit line connection contact is electrically connected to the bit line connection transistor through a peripheral conductive structure, and The bottom surface of the bit line connection contact is in contact with the peripheral conductive structure.

7. The semiconductor device according to claim 1, further comprising: substrate; A gate is connected to the transistor, on the substrate; as well as a gate connection pad to electrically connect the gate connection transistor to the gate structure, The bottom surface of the gate connection pad is coplanar with the bottom surface of the bit line structure.

8. The semiconductor device according to claim 7, further comprising: Shielding layer; as well as Shield insulation layer, on the shield layer, wherein the top surface of the shielding insulating layer contacts the bottom surface of the bit line structure and the bottom surface of the gate connection pad, and The top surface of the gate connection pad is at a height lower than the top surface of the bit line structure.

9. A semiconductor device comprising: A gate connected transistor; a shield layer, which is at a higher level than the gate-connected transistor; Shield insulation layer, on the shielding layer; a gate connection contact in the shield insulating layer; a plurality of bit line structures on a top surface of the shielding insulating layer; a gate connection pad on a top surface of the shield insulating layer and a top surface of the gate connection contact; as well as a plurality of gate structures, on the plurality of bit line structures, Among them, one gate structure among the plurality of gate structures is electrically connected to the gate connection transistor through a gate connection pad and a gate connection contact.

10. The semiconductor device according to claim 9, wherein A bottom surface of the gate connection pad is coplanar with a bottom surface of each of the plurality of bit line structures.

11. The semiconductor device according to claim 9, wherein: A top surface of the gate connection contact is coplanar with a top surface of the shielding insulating layer.

12. The semiconductor device according to claim 9, further comprising: Interlayer insulation layer, on the shield insulation layer, The interlayer insulating layer contacts a side surface of the gate connection pad and a side surface of one of the plurality of bit line structures.

13. The semiconductor device according to claim 9, further comprising: a shielding spacer between the plurality of bit line structures in a horizontal direction; as well as The shield pattern, in the horizontal direction between the shield spacers, Wherein, a bottom surface of each shielding spacer contacts a top surface of the shielding insulation layer.

14. The semiconductor device according to claim 9, wherein: A top surface of the gate connection pad has a height lower than a top surface of each of the plurality of bit line structures.

15. The semiconductor device according to any one of claims 9 to 14, further comprising: a bit line connection contact in contact with a bottom surface of one of the plurality of bit line structures; as well as A bit line connection transistor is electrically connected to a bit line connection contact, The bit line connection contact extends in the shielding insulating layer.

16. A semiconductor device comprising: substrate; A bit line connected transistor is on the substrate; A gate is connected to the transistor, on the substrate; A peripheral circuit insulating layer, on the substrate; Shielding layer, on the peripheral circuit insulation layer; Shield insulation layer, on the shielding layer; A bit line structure,on the shielding insulating layer; a gate connection pad on the shield insulating layer; a first gate connection contact extending in the shielding insulating layer; A bit line connection contact extending in the shielding insulating layer; Gate structure, on the bit line structure; Channel layer, on the bit line structure; a pad structure on the channel layer; as well as The data storage structure is electrically connected to the pad structure, wherein the gate structure is electrically connected to the gate connection transistor via a gate connection pad and a first gate connection contact, and The bit line structure is electrically connected to the bit line connection transistor through a bit line connection contact.

17. The semiconductor device according to claim 16, wherein: The width of the channel layer is equal to the width of the bit line structure.

18. The semiconductor device according to claim 16, in, The bit line structure includes a first portion overlapping the shielding layer in a vertical direction and a second portion not overlapping the shielding layer in the vertical direction, and The bit line connection contact is in contact with the second portion of the bit line structure.

19. The semiconductor device according to claim 16, further comprising: a second gate connection contact in contact with a top surface of the gate connection pad, The height of the bottom surface of the second gate connection contact is higher than the height of the bottom surface of the bit line structure.

20. The semiconductor device according to any one of claims 16 to 19, further comprising: a shielding pattern, contacting the shielding layer and the gate structure; as well as A shield spacer is on the opposite side surface of the shield pattern.

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