Semiconductor device

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a first active region defined by a first device isolation film; a bit line contact in the first active region; and a bit line extending in a first direction on the substrate, where the bit line includes: a lower conductive layer on the substrate and surrounding at least a portion of a sidewall of the bit line contact; a metal silicide film on the lower conductive layer and the bit line contact; and an adhesive layer and a conductive layer sequentially disposed on the metal silicide film in a vertical direction perpendicular to the substrate, and wherein the adhesive layer includes a tantalum (Ta) alloy.

Description

[0001] Cross - reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2023 - 0187519, filed with the Korean Intellectual Property Office on December 20, 2023, the entire disclosure of which is hereby incorporated by reference in its entirety. Technical field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including bit lines. Background art

[0004] As the size of semiconductor devices shrinks, the size of individual micro - circuit patterns for implementing semiconductor devices further decreases. As integrated circuit devices become more highly integrated, the line width of bit lines decreases, and the pitch between bit lines also decreases. Therefore, defects may occur in the process of forming bit lines with a reduced line width. Summary of the invention

[0005] A semiconductor device with improved reliability is provided.

[0006] According to an aspect of the present disclosure, a semiconductor device includes: a substrate including a first active region defined by a first device isolation film; a bit - line contact in the first active region; and a bit line extending on the substrate in a first direction, wherein the bit line includes: a lower conductive layer on the substrate and surrounding at least a part of the sidewall of the bit - line contact; a metal silicide film on the lower conductive layer and the bit - line contact; and an adhesion layer and a conductive layer sequentially disposed on the metal silicide film in a vertical direction perpendicular to the substrate, and wherein the adhesion layer includes a tantalum (Ta) alloy.

[0007] According to an aspect of the present disclosure, a semiconductor device includes: a substrate including a first active region and a second active region; a bit - line contact in the first active region; a peripheral - circuit gate stack in the second active region; and a bit line extending on the substrate in a first direction, wherein the bit line includes a lower conductive layer on the substrate and surrounding at least a part of the sidewall of the bit - line contact, and a metal - wire stack on the lower conductive layer, and wherein the metal - wire stack includes a barrier metal layer, an adhesion layer on the barrier metal layer, and a conductive layer on the adhesion layer.

[0008] According to one aspect of the present disclosure, a semiconductor device includes: a substrate including an active region defined by a device isolation film; a bit line contact in a bit line contact hole extending into the substrate, wherein the bit line contact is connected to the active region; a bit line extending on the substrate in a first direction, and the bit line includes: a lower conductive layer on the substrate and surrounding at least a part of the sidewall of the bit line contact, a metal silicide film on the lower conductive layer, and a metal line stack on the metal silicide film; a bit line spacer on the sidewall of the bit line and extending in the first direction; a word line in a word line trench and extending in a second direction intersecting the first direction, wherein the word line intersects the active region, wherein the metal line stack includes a barrier metal layer, an adhesion layer, and a conductive layer sequentially arranged in a direction perpendicular to the substrate, and wherein the adhesion layer includes tantalum boride (TaB), and the conductive layer includes ruthenium (Ru).

[0009] The present disclosure is not limited to the above technical purposes, and those skilled in the art will clearly understand other purposes not stated herein according to the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] According to the following description in conjunction with the drawings, the above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent, in the drawings:[[]]END]]

[0011] Figure 1 is a layout diagram showing a semiconductor device according to one or more embodiments;

[0012] Figure 2 is Figure 1 an enlarged layout diagram of region P of

[0013] Figure 3 is a cross-sectional view taken along line A-A' of Figure 2 ;

[0014] Figure 4 is a cross-sectional view taken along line B-B' of Figure 2 ;

[0015] Figure 5 is a cross-sectional view taken along line C-C' of Figure 2 ;

[0016] Figure 6A and Figure 6B are cross-sectional views showing a semiconductor device according to one or more embodiments;

[0017] Figure 7A and Figure 7B are cross-sectional views showing a semiconductor device according to one or more embodiments;

[0018] Figure 8A and Figure 8Bis a cross-sectional view showing a semiconductor device according to one or more embodiments;

[0019] Figure 9A and Figure 9B is a cross-sectional view showing a semiconductor device according to one or more embodiments;

[0020] Figure 10A and Figure 10B is a cross-sectional view showing a semiconductor device according to one or more embodiments; and

[0021] Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 20A and Figure 20B is a cross-sectional view showing a method of manufacturing a semiconductor device according to one or more embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, like components are denoted by like reference numerals, and repeated descriptions thereof will not be given.

[0023] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to the specific embodiments, and it should be clear that the present disclosure covers all changes, equivalents, and / or alternative ways that do not depart from the spirit and technical scope of the present disclosure. In the description of the embodiments, some detailed explanations of related technologies are omitted when they are considered to possibly obscure the gist of the present disclosure unnecessarily.

[0024] As used herein, a plurality of “units”, “modules”, “components”, and “blocks” may be implemented as a single component, or a single “unit”, “module”, “component”, and “block” may include a plurality of components.

[0025] It should be understood that when an element is referred to as being “connected” to another element, the element may be directly or indirectly connected to the other element.

[0026] Moreover, when a component "comprises" or "includes" an element, unless specifically described to the contrary, the component may also include other elements without excluding others.

[0027] Throughout this description, when one component is "on" another component, this includes not only the case where the component is in contact with the other component, but also the case where there is another component between the two components.

[0028] As used herein, the expressions "at least one of a, b, or c" and "at least one of a, b, and c" indicate "only a", "only b", "only c", "both a and b", "both a and c", "both b and c", and "all of a, b, and c".

[0029] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, the present disclosure should not be limited by these terms. These terms are only used to distinguish one element from another.

[0030] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise.

[0031] For any method or process described herein, identification codes may be used for convenience of description, but they are not intended to indicate the order of each step or operation. Unless the context clearly indicates otherwise, each step or operation may be implemented in an order different from the order shown. Unless the context of the present disclosure clearly indicates otherwise, one or more steps or operations may be omitted.

[0032] Figure 1 is a layout diagram showing a semiconductor device according to one or more embodiments. Figure 2 is Figure 1 an enlarged layout diagram of region P of Figure 3 is along Figure 2 a cross-sectional view taken along line A-A' of Figure 4 is along Figure 2 a cross-sectional view taken along line B-B' of Figure 5 is along Figure 2 a cross-sectional view taken along line C-C' of

[0033] Refer to Figures 1 to 5, the semiconductor device 100 may include a substrate 110, which includes a cell array region MCA and a peripheral circuit region PCA. The cell array region MCA may be a storage cell region of a dynamic random access memory (DRAM) device, and the peripheral circuit region PCA may be a core region or a peripheral circuit region of the DRAM device. For example, the cell array region MCA may include cell transistors and capacitor structures CAP connected thereto, and the peripheral circuit region PCA may include peripheral circuit transistors PTR for transmitting signals and / or power to the cell transistors included in the cell array region MCA. In one or more embodiments, the peripheral circuit transistors PTR may constitute various circuits, such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.

[0034] Device isolation trenches 112T may be formed in the substrate 110, and a first device isolation film 112 and a second device isolation film 112P may be formed in the device isolation trenches 112T. A plurality of first active regions AC1 may be defined in the cell array region MCA of the substrate 110 through the first device isolation film 112, and a plurality of second active regions AC2 may be defined in the peripheral circuit region PCA through the second device isolation film 112P.

[0035] As Figure 2 shown, within the cell array region MCA, a plurality of first active regions AC1 may be arranged such that each has a major axis in a first diagonal direction (D1 direction) that is inclined with respect to a first horizontal direction (X direction) and a second horizontal direction (Y direction). A plurality of word lines WL may extend parallel to each other in the first horizontal direction (X direction) across the plurality of first active regions AC1. A plurality of bit lines BL may extend parallel to each other in the second horizontal direction (Y direction) on the plurality of word lines WL. The plurality of bit lines BL may be connected to the plurality of first active regions AC1 through bit line contacts DC.

[0036] A plurality of buried contacts BC may be formed between two adjacent bit lines BL among the plurality of bit lines BL. A plurality of landing pads LP may be formed on the plurality of buried contacts BC. The plurality of buried contacts BC and the plurality of landing pads LP may connect a lower electrode 182 of a capacitor structure CAP formed on the plurality of bit lines BL to the first active region AC1. The plurality of landing pads LP may be arranged to partially overlap the buried contacts BC and the bit lines BL.

[0037] The substrate 110 may include silicon, such as single-crystalline silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In one or more embodiments, the substrate 110 may include a conductive region, such as a well doped with impurities, or a structure doped with impurities.

[0038] The first device isolation film 112 may include an oxide film, a nitride film, or a combination thereof. The first buffer insulating layer 114 and the second buffer insulating layer 116 may be sequentially disposed on the upper surface of the substrate 110. Each of the first buffer insulating layer 114 and the second buffer insulating layer 116 may include silicon oxide, silicon oxynitride, or silicon nitride.

[0039] A plurality of word line trenches 120T extending in a first horizontal direction (X direction) may be provided in the substrate 110, and a buried gate structure 120 may be located within the plurality of word line trenches 120T. The buried gate structure 120 may include a gate dielectric layer 122, a gate electrode 124, and a word line capping layer 126 located within each of the plurality of word line trenches 120T. The plurality of gate electrodes 124 may correspond to Figure 2 the plurality of word lines WL shown in

[0040] The plurality of gate dielectric layers 122 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO) film, or a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film. The plurality of gate electrodes 124 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. The plurality of word line capping layers 126 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a combination thereof.

[0041] A plurality of bit line contact holes DCH may extend into the substrate 110 to pass through the first buffer insulating layer 114 and the second buffer insulating layer 116, and a plurality of bit line contacts DC may be formed in the plurality of bit line contact holes DCH. The plurality of bit line contacts DC may be connected to the plurality of first active regions AC1. The plurality of bit line contacts DC may include doped polysilicon. A bit line contact spacer DCS may cover the lower side of the bit line contact DC within the bit line contact hole DCH.

[0042] A plurality of bit lines BL may extend along a second horizontal direction (Y direction) over a long distance on the substrate 110 and the plurality of bit line contacts DC. The plurality of bit lines BL may each be connected to the first active region AC1 through the bit line contact DC.

[0043] Each of the plurality of bit lines BL may include a lower conductive layer 132, a metal silicide film 134, and a metal line stack MLS.

[0044] The lower conductive layer 132 may extend along a second horizontal direction (Y direction) on the second buffer insulating layer 116, and the lower conductive layer 132 may cover two sidewalls of the bit line contact DC. For example, as Figure 4 shown, the upper surface of the lower conductive layer 132 may be in the same plane as the upper surface of the bit line contact DC, and two sidewalls of the bit line contact DC may be in contact with the lower conductive layer 132. The lower conductive layer 132 may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

[0045] In one or more embodiments, in a process for forming the bit line contact hole DCH, a portion of the lower conductive layer 132, a portion of the second buffer insulating layer 116, a portion of the first buffer insulating layer 114, and a portion of the substrate 110 may be removed, and a bit line contact DC may be formed in the bit line contact hole DCH. Accordingly, the upper side of the bit line contact DC may be in contact with the lower conductive layer 132, and the lower side of the bit line contact DC may be in contact with the substrate 110 (e.g., the first active region AC1).

[0046] A metal silicide film 134 may be disposed on the upper surface of the lower conductive layer 132 and the upper surface of the bit line contact DC and may extend along the second horizontal direction (Y direction). In one or more embodiments, the lower conductive layer 132 may include polysilicon, and the metal silicide film 134 may include at least one of cobalt silicide, nickel silicide, and tungsten silicide. In one or more embodiments, the metal silicide film 134 may be deposited to a thickness of about to about of thickness.

[0047] The metal line stack MLS may include a barrier metal layer 136, an adhesion layer 137, and a conductive layer 138 sequentially disposed on the metal silicide film 134. For example, the metal line stack MLS may have a structure in which the adhesion layer 137 is sandwiched between the barrier metal layer 136 and the conductive layer 138.

[0048] In one or more embodiments, the sum of the thickness of the barrier metal layer 136 and the thickness of the adhesion layer 137 may range from about to about In one or more embodiments, the thickness of the adhesion layer 137 may not exceed 20% of the thickness of the conductive layer 138. In one or more embodiments, the barrier metal layer 136 may include any one of TiN, TaN, WN, TiSiN, or an alloy thereof. In one or more embodiments, the adhesion layer 137 may include any one of TEOS, SiN, TiN, TaB, Ta, TaN, or an alloy thereof. In one or more embodiments, the adhesion layer 137 may include TaB. In this case, the content of B in the composition of TaB included in the adhesion layer 137 may not exceed 30%.

[0049] In one or more embodiments, the conductive layer 138 may include ruthenium (Ru). In one or more embodiments, the conductive layer 138 may have a single component including any one material selected from Rh, Ir, Mo, Cu, Co, and W, and include an alloy material such as any one of RuAl, NiAl, NbB2, MoB2, MoW, or an alloy thereof.

[0050] The semiconductor device 100 according to the present disclosure can suppress the aggregation of materials included in the conductive layer 138 by placing the adhesion layer 137 under the conductive layer 138.

[0051] For example, in the case where the bit line BL includes a single-layer metal material (e.g., Ru), when the bit line BL has a reduced line width, during subsequent high-temperature processes, grain aggregation or grain coalescence may occur in the metal material (e.g., Ru) included in the bit line BL. The bit line BL shown in the present disclosure may be formed as a line pattern extending in the second horizontal direction (Y direction), but after subsequent high-temperature processes, the line width of a part of the bit line BL may locally increase due to grain aggregation. Therefore, the line width of another part of the bit line BL may locally decrease, or a region where the bit line BL is discontinuously disconnected may be formed.

[0052] However, according to one or more embodiments, the adhesion layer 137 may be located between the barrier metal layer 136 and the conductive layer 138, and may serve as an anti-grain aggregation layer that suppresses grain aggregation or grain coalescence of the materials included in the conductive layer 138, and can prevent grain aggregation of the metal materials included in the conductive layer 138 even when the bit line BL has a reduced line width (or a relatively small line width).

[0053] A plurality of bit line capping layers 140 may be provided on each of the plurality of bit lines BL. Each bit line capping layer 140 may include a first capping layer 142, a second capping layer 144, and a third capping layer 146, which are sequentially provided on the upper surface of each of the plurality of bit lines BL. The first capping layer 142, the second capping layer 144, and the third capping layer 146 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0054] The bit line spacers 150 may be located on two sidewalls of each bit line BL. The bit line spacers 150 may include a first spacer layer 152, a second spacer layer 154, and a third spacer layer 156. In one or more embodiments, the first spacer layer 152 and the third spacer layer 156 may each include silicon nitride, and the second spacer layer 154 may include silicon oxide. The first spacer layer 152, the second spacer layer 154, and the third spacer layer 156 may be sequentially located on each of the sidewalls of the bit line BL and the sidewalls of the bit line capping layer 140.

[0055] For example, since the bit line spacers 150 are located on the sidewalls of the bit line BL, the first spacer layer 152 of the bit line spacers 150 may contact the metal line stack MLS of the bit line BL. For example, the first spacer layer 152 may extend in the vertical direction (Z direction) along the sidewalls of the barrier metal layer 136, the adhesion layer 137, and the conductive layer 138 of the metal line stack MLS on the sidewalls of the barrier metal layer 136, the adhesion layer 137, and the conductive layer 138 of the metal line stack MLS.

[0056] A plurality of buried contacts BC may be located between the plurality of bit lines BL. For example, the bottoms of the plurality of buried contacts BC may be located in the buried contact holes BCH in the substrate 110 extending between two adjacent bit lines BL, and the bottoms of the buried contacts BC may contact the first active region AC1. In one or more embodiments, the plurality of buried contacts BC may include doped polysilicon.

[0057] A plurality of insulating fences may be located between two adjacent bit lines BL in the second horizontal direction (Y direction). The plurality of insulating fences may be located at positions vertically overlapping with the plurality of word line trenches 120T. From a plan view, the plurality of buried contacts BC and the plurality of insulating fences may be alternately arranged between two bit lines BL extending in the second horizontal direction (Y direction).

[0058] A plurality of landing pads LP may be provided on the plurality of buried contacts BC. Each of the plurality of landing pads LP may include a conduction barrier film and a landing pad conductive layer. The conduction barrier film may include Ti, TiN, or a combination thereof. The landing pad conductive layer may include a metal, a metal nitride, conductive polysilicon, or a combination thereof. For example, the landing pad conductive layer may include W. From a plan view, the plurality of landing pads LP may have a plurality of island pattern shapes.

[0059] The plurality of landing pads LP may be electrically insulated from each other by an insulating pattern 160 surrounding the plurality of landing pads LP. The insulating pattern 160 may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0060] The etch stop film 180 may be disposed on the insulating pattern 160, and the etch stop film 180 may have an opening 180H. The opening 180H may be located at a position corresponding to the landing pad LP, and the upper surface of the landing pad LP may be located at the bottom of the opening 180H.

[0061] The capacitor structure CAP may be disposed on the etch stop film 180. The capacitor structure CAP may include a lower electrode 182, a capacitor dielectric layer 184, and an upper electrode 186. The bottom of the lower electrode 182 may be located within the opening 180H of the etch stop film 180 and placed on the landing pad LP. The capacitor dielectric layer 184 may be set to be thin to conformally cover the lower electrode 182, and the upper electrode 186 may be disposed on the capacitor dielectric layer 184.

[0062] The peripheral circuit transistor PTR( Figure 5 ) may be disposed in the second active region AC2 of the peripheral circuit area PCA. The peripheral circuit transistor PTR may include a gate dielectric layer 118, a peripheral circuit gate stack PGS, and a gate capping pattern 142P sequentially stacked on the second active region AC2.

[0063] The gate dielectric layer 118 may be disposed on the upper surface of the substrate 110. The gate dielectric layer 118 may include at least one selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO), or a high-k dielectric film having a dielectric constant higher than that of the silicon oxide film. The gate capping pattern 142P may be disposed to cover the upper surface of the peripheral circuit gate stack PGS. In one or more embodiments, the gate capping pattern 142P may include a silicon nitride film.

[0064] The peripheral circuit gate stack PGS may include a peripheral lower conductive layer 132P, a peripheral metal silicide layer 134P, and a peripheral metal wire stack MLSP.

[0065] The peripheral lower conductive layer 132P may be located on the gate dielectric layer 118, and may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. The peripheral metal silicide layer 134P may be located on the upper surface of the peripheral lower conductive layer 132P. In one or more embodiments, the peripheral metal silicide layer 134P may include at least one of cobalt silicide, nickel silicide, and tungsten silicide. In one or more embodiments, a conductive barrier layer of at least one of titanium, titanium nitride, or tantalum nitride may also be optionally disposed on the peripheral metal silicide layer 134P.

[0066] The peripheral metal line stack MLSP may include a peripheral barrier metal layer 136P, a peripheral adhesion layer 137P, and a peripheral conductive layer 138P, which are sequentially disposed on the peripheral metal silicide layer 134P. For example, the peripheral metal line stack MLSP may have a structure in which the peripheral adhesion layer 137P is sandwiched between the peripheral barrier metal layer 136P and the peripheral conductive layer 138P.

[0067] In one or more embodiments, the sum of the thickness of the peripheral barrier metal layer 136P and the thickness of the peripheral adhesion layer 137P may range from about to about In one or more embodiments, the thickness of the peripheral adhesion layer 137P may not exceed 20% of the thickness of the peripheral conductive layer 138P. In one or more embodiments, the peripheral barrier metal layer 136P may include any one of TiN, TaN, WN, TiSiN, or an alloy thereof. In one or more embodiments, the peripheral adhesion layer 137P may include any one of TEOS, SiN, TiN, TaB, Ta, TaN, or an alloy thereof. In one or more embodiments, the peripheral adhesion layer 137P may include TaB. In this case, the content of B in the TaB component included in the peripheral adhesion layer 137P may not exceed 30%.

[0068] In one or more embodiments, the peripheral conductive layer 138P may include ruthenium (Ru). In one or more embodiments, the peripheral conductive layer 138P may have a single component including any one material selected from Rh, Ir, Mo, Cu, Co, and W, and include an alloy material such as any one of RuAl, NiAl, NbB2, MoB2, MoW, or an alloy thereof.

[0069] In one or more embodiments, the materials of the peripheral lower conductive layer 132P, the peripheral metal silicide layer 134P, the peripheral barrier metal layer 136P, the peripheral adhesion layer 137P, and the peripheral conductive layer 138P are the same as the materials of the lower conductive layer 132, the metal silicide film 134, the barrier metal layer 136, the adhesion layer 137, and the conductive layer 138 included in the bit line BL in the cell array region MCA, respectively. For example, the peripheral circuit gate stack PGS may be formed simultaneously in the process of forming the bit line BL. However, the present disclosure is not limited thereto.

[0070] The two sidewalls of the peripheral circuit gate stack PGS and the gate capping pattern 142P can be covered by the insulating spacer 150P. The insulating spacer 150P can include an oxide film, a nitride film, or a combination thereof. The peripheral circuit transistor PTR and the insulating spacer 150P can be covered by the protective layer 144P, and the first interlayer insulating film 148 can be disposed on the protective layer 144P to fill the space between two adjacent peripheral circuit transistors PTR. The capping insulating layer 146P can be disposed on the first interlayer insulating film 148 and the protective layer 144P.

[0071] The contact plug PCT can be formed in the contact hole PCTH formed to penetrate the first interlayer insulating film 148 and the capping insulating layer 146P in the peripheral circuit region PCA. The contact plug PCT can include a conduction blocking film and a contact pad conductive layer, similar to the plurality of contact pads LP formed in the cell array region MCA. The metal silicide film can be located between the second active region AC2 and the contact plug PCT. The upper interlayer insulating film 190 covering the contact plug PCT can be disposed on the capping insulating layer 146P.

[0072] Generally, the resistance of the bit line BL increases as the line width of the plurality of bit lines BL decreases. Therefore, attempts have been made to use a metal material with a low resistivity (e.g., a metal material such as Ru) as the technology for the bit line BL. However, when a metal material such as Ru is patterned to have a relatively small line width, grain aggregation or grain coalescence occurs in subsequent high-temperature processes, so the roughness of the metal material layer increases significantly, the line width locally increases in a specific region, the line width decreases in a specific region, and / or line disconnection occurs in a specific region.

[0073] However, according to an embodiment, in the metal wire stack MLS, the adhesion layer 137 can be further disposed on the barrier metal layer 136, and the Ta alloy included in the adhesion layer 137 can prevent grain aggregation of the metal material included in the conductive layer 138. Therefore, the bit line BL has a low resistance while preventing the generation of regions with increased local line width, regions with decreased line width, and / or regions with line disconnection in the bit line BL during the process of forming the semiconductor device 100. Therefore, the semiconductor device 100 can have excellent electrical characteristics.

[0074] Figure 6A and Figure 6B is a cross-sectional view showing a semiconductor device 100a according to one or more embodiments. It will be understood that Figure 6A and Figure 6B the semiconductor device 100a of Figures 1 to 5The described semiconductor devices 100 are not mutually exclusive, and components with the same reference numerals can be considered the same components. Hereinafter, repeated descriptions of similar components will be omitted, and the differences from the semiconductor device 100 Figures 1 to 5 will be mainly described.

[0075] Referring to Figure 6A and Figure 6B , the metal wire stack MLS may include a first intermediate layer 135a and a conductive layer 138, and the thickness of the first intermediate layer 135a in the vertical direction (Z direction) may range from about to about In one or more embodiments, the first intermediate layer 135a may include TaB. In this case, the content of B in the composition of TaB included in the first intermediate layer 135a may not exceed 30%. Compared with the semiconductor device 100 Figures 1 to 5 , in the semiconductor device 100a Figures 6A to 6B , the first intermediate layer 135a included may replace the barrier metal layer 136 and the adhesion layer 137 of the semiconductor device 100 Figures 1 to 5 .

[0076] Figure 7A and Figure 7B are cross-sectional views showing a semiconductor device 100b according to an embodiment. It will be understood that the semiconductor device 100b in Figure 7A and Figure 7B is not mutually exclusive with the semiconductor device 100 described with reference to Figures 1 to 5 , and components with the same reference numerals can be considered the same components. Hereinafter, repeated descriptions of similar components will be omitted, and the differences from the semiconductor device 100 Figures 1 to 5 will be mainly described.

[0077] Referring to Figure 7A and Figure 7B , the metal wire stack MLS may include a first intermediate layer 135a and a conductive layer 138, and a capping layer 139 may also be provided thereon. The thickness of the first intermediate layer 135a in the vertical direction (Z direction) may range from about to about In one or more embodiments, the first intermediate layer 135a may include TaB. In this case, the content of B in the composition of TaB included in the first intermediate layer 135a may not exceed 30%.

[0078] In one or more embodiments, the thickness of the capping layer 139 in the vertical direction (Z direction) may range from about to about ​​​For example, the capping layer 139 can be deposited to have the same thickness as the first intermediate layer 135a. In one or more embodiments, the capping layer 139 can have the same composition as the first intermediate layer 135a. For example, the capping layer 139 can include a TaB alloy in which the content of B does not exceed 30%. In other embodiments, the capping layer 139 can include at least one of nanocrystalline graphene (NCG), TiN, Ta, TaN, or an alloy thereof.

[0079] Figure 7A and Figure 7B The semiconductor device 100b shown can include a first intermediate layer 135a including TaB and a capping layer 139 respectively on top of and at the bottom of the conductive layer 138 to inhibit grain growth of Ru included in the conductive layer 138.

[0080] Figure 8A and Figure 8B is a cross-sectional view showing a semiconductor device 100c according to an embodiment. It will be understood that Figure 8A and Figure 8B the semiconductor device 100c is not mutually exclusive with the semiconductor device 100 described with reference to Figures 1 to 5 and components having the same reference numerals can be considered the same components. Hereinafter, repeated descriptions of similar components will be omitted, and differences from the semiconductor device 100 of Figures 1 to 5 will be mainly described.

[0081] Referring to Figure 8A and Figure 8B , the metal wire stack MLS can include a second intermediate layer 135b and a conductive layer 138, and the thickness of the second intermediate layer 135b in the vertical direction (Z direction) can range from about to about In one or more embodiments, the second intermediate layer 135b can include a RuTaB alloy. In this case, the content of B in the RuTaB alloy included in the second intermediate layer 135b can not exceed 30%. Compared with the semiconductor device 100 of Figures 1 to 5 , the second intermediate layer 135b included in the semiconductor device 100c of Figures 8A to 8B can replace the barrier metal layer 136 and the adhesion layer 137 of the semiconductor device 100 of Figures 1 to 5 . A capping layer 139 having a thickness of about to about in the vertical direction (Z direction) can also be deposited on the metal wire stack MLS (see Figure 7A and Figure 7B ).

[0082] Figure 9A and Figure 9Bis a cross-sectional view showing a semiconductor device 100d according to an embodiment. It will be understood that Figure 9A and Figure 9B the semiconductor device 100d of Figures 1 to 5 is not mutually exclusive with the semiconductor device 100 described with reference to Figures 1 to 5 , and components having the same reference numerals can be considered the same components. Hereinafter, repeated descriptions of similar components will be omitted, and differences from the

[0083] semiconductor device 100 of Figure 9A and Figure 9B will be mainly described. Referring to and , the metal wire stack MLS may include a third intermediate layer 135c and a conductive layer 138, and the thickness of the third intermediate layer 135c in the vertical direction (Z direction) may not exceed 20% of the thickness of the conductive layer 138. In one or more embodiments, the third intermediate layer 135c may have a stacked structure of a first superalloy layer 135c1 and a second superalloy layer 135c2 stacked layer by layer. In one or more embodiments, each of the first superalloy layer 135c1 and the second superalloy layer 135c2 may have a thickness of about

[0084] to about Figures 1 to 5 . The composition ratio of the entire third intermediate layer 135c can be adjusted by adjusting the thickness ratio of the first superalloy layer 135c1 and the second superalloy layer 135c2. Figures 9A to 9B In one or more embodiments, the first superalloy layer 135c1 may include TaB, and the second superalloy layer 135c2 may include Ru. In this case, the content of B in the composition of TaB included in the first superalloy layer 135c1 may not exceed 30%. Compared with the Figures 1 to 5 semiconductor device 100 of to about of the semiconductor device 100d may replace the barrier metal layer 136 and the adhesion layer 137 of the Figure 7A and Figure 7B semiconductor device 100. A capping layer 139 having a thickness of about

[0085] Figure 10A and Figure 10B is a cross-sectional view showing a semiconductor device 100e according to an embodiment. It will be understood that Figure 10A and Figure 10B the semiconductor device 100e of Figures 1 to 5The described semiconductor devices 100 are not mutually exclusive, and components with the same reference numeral can be considered identical components. Hereinafter, repeated descriptions of similar components will be omitted, and the differences from the semiconductor device 100 Figures 1 to 5 will be mainly described.

[0086] Referring to Figure 10A and Figure 10B , the metal wire stack MLS may include an adhesion layer 137 and a conductive layer 138, and the thickness of the adhesion layer 137 in the vertical direction (Z direction) may range from about to about In one or more embodiments, the adhesion layer 137 may include TaB. In this case, the content of B in the composition of TaB included in the adhesion layer 137 may not exceed 30%. Compared with the bit line contact DC of the semiconductor device 100 shown in Figures 1 to 5 including polysilicon, Figures 10A to 10B the bit line contact DC included in the semiconductor device 100e may include any single metal material selected from W, Ti, TiN, Mo, Ru, Rh, Ir, Cu, Co, and W, or an alloy material selected from RuAl, NiAl, NbB2, MoB2, and MoW. Since the bit line contact DC includes a metal material, the adhesion layer 137 may be provided on the lower conductive layer 132 without a metal silicide film 134 (see Figures 1 to 5 ) and a barrier metal layer 136 (see Figures 1 to 5 ).

[0087] Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A and Figure 20B are cross-sectional views showing a method of manufacturing a semiconductor device 100 according to one or more embodiments. Specifically, Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A, Figure 19A and Figure 20A are cross-sectional views corresponding to Figure 2 of cross-section A–A’, and Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B are cross-sectional views corresponding to Figure 2 of cross-section B–B’.

[0088] Referring to Figure 11A and Figure 11B , a plurality of device isolation trenches 112T can be formed in the substrate 110.

[0089] Then, a first device isolation film 112 can be formed to fill the plurality of device isolation trenches 112T. A plurality of first active regions AC1 can be defined in the substrate 110 by forming the first device isolation film 112. In a plan view, the plurality of first active regions AC1 can extend along a first diagonal direction (D1 direction) that is inclined at a certain angle with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction) (see Figure 2 ).

[0090] In one or more embodiments, the first device isolation film 112 can be formed using silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some examples, the first device isolation film 112 can be formed as a bilayer structure of a silicon oxide layer and a silicon nitride layer, but is not limited thereto.

[0091] A mask pattern can be formed on the substrate 110, and a portion of the substrate 110 can be removed by using the mask pattern as an etching mask to form the word line trench 120T. For example, a mask pattern for forming the word line trench 120T can be formed using double patterning technology (DPT) or quadruple patterning technology (QPT), but the present disclosure is not limited thereto.

[0092] Then, a gate dielectric layer 122, a gate electrode 124, and a word line capping layer 126 can be sequentially formed in the word line trench 120T.

[0093] For example, the gate dielectric layer 122 can conformally lie on the inner walls of the word line trench 120T. The gate electrode 124 can be formed by filling the word line trench 120T with a conductive layer and then back-etching the upper portion of the conductive layer to expose again a portion of the upper side of the word line trench 120T.

[0094] Referring to Figure 12A and Figure 12B, a first buffer insulating layer 114 and a second buffer insulating layer 116 can be formed on the first active region AC1 and the first device isolation film 112. Then, a lower conductive layer 132 can be formed on the first buffer insulating layer 114 and the second buffer insulating layer 116. A bit line contact hole DCH can be formed by removing a portion of the lower conductive layer 132, the first buffer insulating layer 114, the second buffer insulating layer 116, and the substrate 110. Then, a bit line contact DC including doped polysilicon can be formed within the bit line contact hole DCH.

[0095] In one or more embodiments, the lower conductive layer 132 can include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof.

[0096] Reference Figure 13A and Figure 13B , a metal silicide film 134 can be formed on the bit line contact DC and the lower conductive layer 132. The metal silicide film 134 can be formed using at least one of cobalt silicide, nickel silicide, and tungsten silicide. In one or more embodiments, the metal silicide film 134 can be deposited to a thickness of about to about in the vertical direction (Z direction).

[0097] Then, a barrier metal layer 136, an adhesion layer 137, and a conductive layer 138 can be sequentially formed on the metal silicide film 134.

[0098] In one or more embodiments, the barrier metal layer 136 can include any one of TiN, TaN, WN, TiSiN, or an alloy thereof. In one or more embodiments, the adhesion layer 137 can include any one of TEOS, SiN, TiN, TaB, Ta, TaN, or an alloy thereof. In one or more embodiments, the adhesion layer 137 can include TaB. In this case, the content of B in the composition of TaB included in the adhesion layer 137 can not exceed 30%. In one or more embodiments, the conductive layer 138 can include ruthenium (Ru). In one or more embodiments, the conductive layer 138 can have a single component including any one material selected from Rh, Ir, Mo, Cu, Co, and W, and include an alloy material such as any one of RuAl, NiAl, NbB2, MoB2, MoW, or an alloy thereof.

[0099] In one or more embodiments, the sum of the thickness of the barrier metal layer 136 and the thickness of the adhesion layer 137 can range from about to about In one or more embodiments, the thickness of the adhesion layer 137 can not exceed 20% of the thickness of the conductive layer 138.

[0100] Here, the stacked structure of the barrier metal layer 136, the adhesive layer 137, and the conductive layer 138 may be referred to as a preliminary metal line stack MLS'. Then, the bit line capping layer 140 may be formed on the preliminary metal line stack MLS'. Each bit line capping layer 140 may include a first capping layer 142, a second capping layer 144, and a third capping layer 146, which are sequentially disposed on the upper surface of each preliminary metal line stack MLS'. The first capping layer 142, the second capping layer 144, and the third capping layer 146 may be formed of at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0101] Reference Figure 14A and Figure 14B , multiple bit lines BL may be formed by patterning the preliminary metal line stack MLS', the metal silicide film 134, and the lower conductive layer 132 by using the bit line capping layer 140 as an etch mask.

[0102] In the patterning process of forming the multiple bit lines BL, a part of the bit line contact DC located in the bit line contact hole DCH may also be removed. Therefore, as Figure 14A shown, the sidewall of the bit line contact DC may be formed to be aligned with the sidewall of the bit line BL, and the inner wall of the bit line contact hole DCH may be exposed again through both sides of the bit line contact DC.

[0103] Then, the first spacer layer 152 may be formed on the sidewalls of the bit line BL, the bit line capping layer 140, and the bit line contact DC. The first spacer layer 152 may also conformally lie on the inner wall of the bit line contact hole DCH. In one or more embodiments, the first spacer layer 152 may be formed of silicon nitride.

[0104] Reference Figure 15A and Figure 15B , the bit line contact spacer DCS may be formed by filling the remaining portion of the bit line contact hole DCH on the first spacer layer 152. For example, the bit line contact spacer DCS may be formed of silicon nitride or silicon oxide.

[0105] Then, the second spacer layer 154 may be formed on the sidewalls of the bit line BL and the bit line capping layer 140. In one or more embodiments, the second spacer layer 154 may be formed of silicon oxide.

[0106] Then, an anisotropic etching process may be performed on the second spacer layer 154, and the portions of the first buffer insulating layer 114 and the second buffer insulating layer 116 located between the bit lines BL may be removed to expose the upper surface of the substrate 110.

[0107] Then, a third spacer layer 156 can be conformally formed on the upper surfaces of the second spacer layer 154 and the substrate 110. In one or more embodiments, the third spacer layer 156 can be formed of silicon nitride.

[0108] Reference Figure 16A and Figure 16B , the upper side of the substrate 110 exposed in the space between the plurality of bit lines BL can be further removed to form a buried contact hole BCH. In one or more embodiments, the process of forming the buried contact hole BCH can include a wet etching process, a dry etching process, or a combination thereof.

[0109] In the etching process of forming the buried contact hole BCH, a part of the upper portion of the bit line capping layer 140 can also be removed, thereby reducing the upper surface height of the bit line capping layer 140.

[0110] Reference Figure 17A and Figure 17B , a buried contact BC can be formed to fill the interior of the buried contact hole BCH. In one or more embodiments, the buried contact BC can be formed of doped polysilicon.

[0111] In one or more embodiments, the buried contact hole BCH can be formed to have a linear planar shape located between adjacent bit lines BL. Then, a preliminary contact layer having a linear planar shape can be formed in the buried contact hole BCH and patterned to form the buried contact BC. Then, an insulating fence can be formed of an insulating material in the space between the buried contacts BC (e.g., the space where a part of the preliminary contact layer is removed).

[0112] In other embodiments, before forming the buried contact hole BCH, a plurality of insulating fences can be formed of an insulating material at the intersections of the space between the word line trenches 120T and two adjacent bit lines BL. The portion of the substrate 110 between the plurality of bit lines BL and between the plurality of insulating fences can be removed to form the buried contact hole BCH, and then the buried contact BC can be formed in the buried contact hole BCH.

[0113] Reference Figure 18A and Figure 18B , a landing pad conductive layer LPL can be formed on the upper surfaces of the plurality of buried contacts BC. The landing pad conductive layer LPL can be formed to have a sufficient thickness to contact the buried contacts BC and cover the upper surface of the bit line capping layer 140.

[0114] Reference Figure 19A and Figure 19B, a mask pattern can be formed on the landing pad conductive layer LPL, and the landing pad conductive layer LPL can be patterned using the mask pattern as an etching mask to form a landing pad opening LPH. Multiple landing pads LP can be formed on each of the multiple buried contacts BC through the landing pad opening LPH.

[0115] Reference Figure 20A and Figure 20B , an insulating pattern 160 can be formed using an insulating material within the landing pad opening LPH. The insulating pattern 160 can be arranged to cover the sidewalls of the multiple landing pads LP.

[0116] Return to reference Figure 3 and Figure 4 , multiple lower electrodes 182 connected to the landing pads LP can be formed, and a capacitor dielectric layer 184 and an upper electrode 186 can be sequentially formed on the sidewalls of the multiple lower electrodes 182. The semiconductor device 100 shown can be completed by performing the above method. Figures 1 to 5 the semiconductor device 100 shown.

[0117] As described above, embodiments have been described in the drawings and the specification. In this specification, specific terms have been used to describe the embodiments, but this is only for the purpose of illustrating the technical spirit of the present disclosure and not for limiting the meaning or scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments can be achieved therefrom. Therefore, the true technical scope of the present disclosure needs to be determined by the technical spirit of the appended claims.

[0118] Although the present disclosure has been specifically shown and described with reference to embodiments of the present disclosure, it should be understood that various changes in form and detail can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A substrate including a first active region defined by a first device isolation film; a bit line contact in the first active region; as well as A bit line extending along a first direction on the substrate, Wherein, the bit line comprises: a lower conductive layer on the substrate and surrounding at least a portion of a sidewall of the bit line contact; a metal silicide film on the lower conductive layer and the bit line contact; and An adhesive layer and a conductive layer are sequentially arranged on the metal silicide film in a vertical direction perpendicular to the substrate, and Wherein, the bonding layer comprises tantalum Ta alloy.

2. The semiconductor device according to claim 1, in, The thickness of the adhesive layer in the vertical direction does not exceed 20% of the thickness of the conductive layer in the vertical direction, and The tantalum Ta alloy of the bonding layer includes tantalum boron TaB, and the boron B content of the tantalum boron TaB is less than or equal to 30%.

3. The semiconductor device according to claim 1, further comprising: A barrier metal layer is between the adhesion layer and the metal silicide film.

4. The semiconductor device according to claim 3, wherein: The sum of the thickness of the barrier metal layer in the vertical direction and the thickness of the adhesive layer in the vertical direction is to within the range.

5. The semiconductor device according to claim 1, wherein The conductive layer includes ruthenium (Ru).

6. The semiconductor device according to claim 1, in, The bonding layer includes an alloy of ruthenium (Ru) and tantalum boron (TaB), and Wherein, the boron B content of the tantalum boron TaB is less than or equal to 30%.

7. The semiconductor device according to claim 1, wherein The thickness of the metal silicide film in the vertical direction is to within the range.

8. The semiconductor device according to claim 1, further comprising: a capping layer, on the conductive layer, Wherein, the capping layer comprises tantalum Ta alloy.

9. The semiconductor device according to claim 8, wherein: The capping layer comprises tantalum boron TaB, the boron B content of the tantalum boron TaB of the capping layer is less than or equal to 30%, and the thickness of the capping layer in the vertical direction is to within the range.

10. The semiconductor device according to claim 1, in, The bonding layer includes a plurality of first superalloy layers and a plurality of second superalloy layers stacked alternately, and The plurality of first super alloy layers include tantalum boron TaB, and the plurality of second super alloy layers include ruthenium Ru.

11. The semiconductor device according to claim 10, in, The thickness of each of the plurality of first superalloy layers and the plurality of second superalloy layers in the vertical direction is to within the range of The plurality of first super alloy layers include tantalum boron TaB, and the boron B content of tantalum boron TaB is less than or equal to 30%.

12. The semiconductor device according to claim 1, in, The substrate further includes a second active region defined by a second device isolation film, The semiconductor device further comprises a peripheral circuit gate stack in the second active region, and Wherein, the peripheral circuit gate stack includes a peripheral lower conductive layer, a peripheral barrier metal layer, a peripheral adhesive layer and a peripheral conductive layer, wherein the peripheral barrier metal layer, the peripheral adhesive layer and the peripheral conductive layer are sequentially arranged on the peripheral lower conductive layer along the vertical direction.

13. A semiconductor device comprising: a substrate including a first active region and a second active region; a bit line contact in the first active region; A peripheral circuit gate stack in the second active region; as well as A bit line extending along a first direction on the substrate, The bit line comprises a lower conductive layer and a metal line stack, wherein the lower conductive layer is on the substrate and surrounds at least a portion of the sidewall of the bit line contact, and the metal line stack is on the lower conductive layer, and The metal line stack includes a barrier metal layer, an adhesive layer on the barrier metal layer, and a conductive layer on the adhesive layer.

14. The semiconductor device according to claim 13, further comprising: a capping layer, on the conductive layer, The capping layer comprises tantalum boron TaB, and the thickness of the capping layer in a vertical direction perpendicular to the substrate is to within the range.

15. The semiconductor device according to claim 13, in, The sum of the thickness of the barrier metal layer in a vertical direction perpendicular to the substrate and the thickness of the adhesive layer in the vertical direction is to within the range of Wherein, the thickness of the adhesive layer in the vertical direction is less than or equal to 20% of the thickness of the conductive layer in the vertical direction.

16. The semiconductor device according to claim 13, wherein: The adhesion layer includes tantalum boron TaB, and the conductive layer includes ruthenium Ru.

17. The semiconductor device according to claim 13, in, The bonding layer includes a plurality of first super alloy layers and a plurality of second super alloy layers stacked alternately, Wherein, each of the plurality of first superalloy layers and the plurality of second superalloy layers has a thickness in a vertical direction perpendicular to the substrate of to within the range of The plurality of first super alloy layers include tantalum boron TaB, and the plurality of second super alloy layers include ruthenium Ru.

18. The semiconductor device according to claim 13, in, The peripheral circuit gate stack includes a peripheral lower conductive layer and a peripheral metal line stack on the peripheral lower conductive layer. wherein the peripheral metal line stack comprises a peripheral barrier metal layer, a peripheral adhesive layer on the peripheral barrier metal layer, and a peripheral conductive layer on the peripheral adhesive layer, and The peripheral barrier metal layer, the peripheral adhesive layer and the peripheral conductive layer respectively include the same materials as the barrier metal layer, the adhesive layer and the conductive layer of the metal wire stack.

19. A semiconductor device comprising: a substrate including an active region defined by a device isolation film; a bit line contact in a bit line contact hole extending into the substrate, wherein the bit line contact is connected to the active region; A bit line extends along a first direction on the substrate, and the bit line includes: a lower conductive layer on the substrate surrounding at least a portion of a sidewall of the bit line contact; a metal silicide film on the lower conductive layer; and A metal line stack on the metal silicide film; a bit line spacer on a sidewall of the bit line and extending along the first direction; and a word line extending in a word line trench along a second direction intersecting the first direction, wherein the word line intersects the active area, The metal line stack includes a barrier metal layer, an adhesive layer and a conductive layer sequentially arranged in a vertical direction perpendicular to the substrate, and Wherein, the adhesive layer includes tantalum boron TaB, and the conductive layer includes ruthenium Ru.

20. The semiconductor device according to claim 19, further comprising a capping layer on the metal line stack, the capping layer comprising tantalum boron TaB, and the thickness of the capping layer in the vertical direction is between 1000 and 2000 Å. to within the range of in, The thickness of the metal silicide film in the vertical direction is to within the range of The sum of the thickness of the barrier metal layer in the vertical direction and the thickness of the adhesive layer in the vertical direction is to within the range.

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