Semiconductor device

Abstract

The present disclosure relates to a semiconductor device comprising: a substrate; a lower insulating layer over the substrate; a bit line over the lower insulating layer and extending parallel to the substrate in a first direction; a first insulating pattern over the bit line and extending in a second direction intersecting the first direction; a channel pattern electrically connected to the bit line and covering a side surface of the first insulating pattern; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; a second insulating pattern over the word line, the gate insulating pattern, and the first insulating pattern; and a landing pad electrically connected to the channel pattern, in which a portion of the word line is located between a plurality of bit lines arranged spaced apart in the second direction.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2023 - 0185027, filed with the Korean Intellectual Property Office on December 18, 2023, the entire content of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a semiconductor device. Background art

[0004] It is necessary to increase the integration degree of semiconductor memory devices to meet the excellent performance and low price required by consumers. In the case of semiconductor memory devices, an increased integration degree is particularly required because the integration degree is an important factor determining the price of products.

[0005] In the case of two - dimensional or planar semiconductor memory devices, the integration degree is mainly determined by the area occupied by a unit memory cell, and thus is greatly affected by the level of fine pattern formation technology. However, since ultra - expensive equipment is required to refine the pattern, the integration degree of 2D semiconductor memory devices is increasing but still limited. Therefore, semiconductor memory devices including vertical channel transistors with channels extending in the vertical direction are being proposed. Summary of the invention

[0006] Embodiments are directed to providing a semiconductor device having improved electrical characteristics.

[0007] A semiconductor device according to an embodiment includes: a substrate; an under - insulating layer positioned above the substrate; bit lines positioned above the under - insulating layer and extending parallel to the substrate in a first direction; a first insulating pattern positioned above the bit lines and extending in a second direction intersecting the first direction; a channel pattern electrically connected to the bit lines and covering side surfaces of the first insulating pattern;

[0008] word lines extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern positioned between the channel pattern and the word lines; a second insulating pattern positioned above the word lines, the gate insulating pattern, and the first insulating pattern; and landing pads electrically connected to the channel pattern, wherein a portion of the word lines is positioned between a plurality of bit lines spaced apart in the second direction.

[0009] A semiconductor device according to an embodiment includes: a substrate; an under-insulating layer located on the substrate; bit lines located above the under-insulating layer and extending parallel to the substrate in a first direction; a first insulating pattern located above the bit lines and extending in a second direction intersecting the first direction; a channel pattern electrically connected to the bit lines and covering side surfaces of the first insulating pattern; word lines extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern located between the channel pattern and the word lines; a second insulating pattern located on the word lines, the gate insulating pattern, and the first insulating pattern; and landing pads electrically connected to the channel pattern, wherein the word lines include portions protruding toward an upper surface of the under-insulating layer in a third direction perpendicular to the substrate, and each of the protruding portions of the word lines is located between adjacent bit lines in the second direction.

[0010] A semiconductor device according to an embodiment includes: a substrate; an under-insulating layer located on the substrate; bit lines located above the under-insulating layer and extending parallel to the substrate in a first direction; a first insulating pattern located above the bit lines and extending in a second direction intersecting the first direction; a channel pattern electrically connected to the bit lines and covering side surfaces of the first insulating pattern; word lines extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern located between the channel pattern and the word lines; a second insulating pattern located on the word lines, the gate insulating pattern, and the first insulating pattern; and landing pads electrically connected to the channel pattern, wherein the bit lines have upper surfaces located at a vertical level higher than an upper surface of the under-insulating layer, and portions of the bit lines located at the vertical level higher than the upper surface of the under-insulating layer overlap the word lines in the second direction and in a third direction perpendicular to the substrate.

[0011] According to an embodiment, the contact resistance can be reduced by increasing a contact area between the bit lines and the channel pattern.

[0012] In addition, according to an embodiment, the word lines can be used as shielding lines between adjacent bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a layout diagram for explaining a semiconductor device according to an exemplary embodiment.

[0014] Figure 2 is a view showing cross-sections of a semiconductor device according to an exemplary embodiment taken along lines A-A' and B-B'. Figure 1 of

[0015] Figure 3 is Figure 2 an enlarged view of part P1 of

[0016] Figure 4 and Figure 5 are cross-sectional views of a semiconductor device according to an exemplary embodiment.

[0017] Figure 6 is a layout diagram for explaining the layout of a semiconductor device according to an exemplary embodiment.

[0018] Figure 7 is a diagram showing a cross-section of a semiconductor device according to an exemplary embodiment taken along lines A-A' and B-B'. Figure 6 of

[0019] Figure 8 , Figure 11 , Figure 14 , Figure 17 , Figure 20 , Figure 23 , Figure 26 , Figure 29 and Figure 32 are layout diagrams showing a manufacturing method of a semiconductor device according to an exemplary embodiment.

[0020] Figure 9 , Figure 10 , Figure 12 , Figure 13 , Figure 15 , Figure 16 , Figure 18 , Figure 19 , Figure 21 , Figure 22 , Figure 24 , Figure 25 , Figure 27 , Figure 28 , Figure 30 , Figure 31 , Figure 33 and Figure 34 are cross-sectional views showing a manufacturing method of a semiconductor device according to an exemplary embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings in which exemplary embodiments of the present disclosure are shown. As will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure. The same reference numerals always denote the same elements.

[0022] When terms such as "same", "equal", "planar", or "coplanar" as used herein refer to an orientation, layout, position, shape, size, quantity, or other measurement, they do not necessarily denote exactly the same orientation, layout, position, shape, size, quantity, or other measurement, but are intended to encompass nearly the same orientation, layout, position, shape, size, quantity, or other measurement within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning. For example, an item described as "substantially the same", "substantially equal", or "substantially planar" may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

[0023] For clarity of description, parts not relevant to the description of the exemplary embodiments are not shown, and throughout the specification, like reference numerals denote like elements.

[0024] For ease of description, the dimensions and thicknesses of the structures are optionally shown in the drawings, and the present disclosure is not limited to the drawings. In the drawings, for clarity, the thicknesses of layers, films, panels, regions, etc. are exaggerated. In the drawings, for better understanding and ease of description, the thicknesses of some layers and regions are exaggerated.

[0025] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element or "directly contacting" another element or "in direct contact with" another element (or any form of the word "contact" is used), no intervening elements are present. Further, in this specification, the words "on" or "above" mean located on or below a part of an object, and do not necessarily mean located on the upper side of the part of the object based on the direction of gravity.

[0026] Additionally, unless explicitly described to the contrary, the words "comprises" and variations such as "comprising" or "containing" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0027] Furthermore, in this specification, the phrase "in a plane" means when viewing a part of an object from above, and the phrase "in a cross-section" means when viewing a cross-section taken by vertically cutting a part of an object from the side.

[0028] Hereinafter, with reference to Figures 1 to 3 a semiconductor device according to an embodiment will be described.

[0029] Figure 1 is a layout diagram for explaining the layout of a semiconductor device according to an exemplary embodiment. Figure 2is a view showing a cross-section of a semiconductor device according to an exemplary embodiment taken along lines A-A' and B-B'. Figure 1 is a diagram of a cross-section of a semiconductor device according to an exemplary embodiment taken along lines A-A' and B-B'. Figure 3 is Figure 2 an enlarged view of a portion P1 of

[0030] Referring to Figures 1 to 3 a semiconductor device according to an embodiment may include a peripheral circuit structure PS and a cell array structure CS disposed on the peripheral circuit structure PS.

[0031] The peripheral circuit structure PS may include a substrate 100 and a core and peripheral circuit SA integrated on an upper surface of the substrate 100. The substrate 100 may have a structure in which a base substrate and an epitaxial layer are stacked, but the embodiment is not limited thereto. For example, the substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or a semiconductor-on-insulator (SOI) substrate. Hereinafter, the substrate 100 will be described as a silicon substrate.

[0032] The core and peripheral circuit SA may include NMOS transistors and PMOS transistors integrated on the substrate 100. The core and peripheral circuit SA may be electrically connected to bit lines BL through peripheral circuit wires and peripheral circuit contact plugs. For example, a sense amplifier may be electrically connected to the bit lines BL, and each sense amplifier may amplify and output a difference in voltage levels detected in a pair of bit lines BL.

[0033] The cell array structure CS may include memory cells having vertical channel transistors (VCTs). The vertical channel transistor may refer to a structure in which a channel length extends in a vertical direction with respect to the upper surface of the substrate 100.

[0034] In an embodiment, the cell array structure CS may include a lower insulating layer 110, bit lines BL, a first insulating pattern 120, a channel pattern CP, word lines WL, a gate insulating pattern Gox, a second insulating pattern 130, landing pads LP, an interlayer insulating layer 140, and data storage patterns DSP.

[0035] The lower insulating layer 110 may be located above the substrate 100. The lower insulating layer 110 may cover the core and peripheral circuit SA, peripheral circuit wires, and peripheral circuit contact plugs on the substrate 100. The lower insulating layer 110 may include a multi-layer insulating layer. For example, the lower insulating layer 110 may be formed of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric constant layer, or may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and / or a low dielectric constant layer.

[0036] The bit line BL may be located above the lower insulating layer 110. The lower surface of the bit line BL may contact the upper surface of the lower insulating layer 110. The upper surface of the bit line BL may have an upper surface that is higher than the upper surface of the lower insulating layer 110. For example, the upper surface of the bit line BL may be located at a vertical level higher than the upper surface of the lower insulating layer 110. The bit line BL may extend parallel to the substrate 100 in the first direction DR1. The bit lines BL may be arranged to be spaced apart in a second direction DR2 that intersects the first direction DR1. For example, the second direction DR2 may be a direction perpendicular to the first direction DR1.

[0037] According to an embodiment, the bit line BL may be surrounded by the lower insulating layer 110. The bottom surface of the bit line BL may be located at a vertical level lower than the upper surface of the lower insulating layer 110. The portions of the two side surfaces of the bit line BL adjacent to the bottom surface and the bottom surface of the bit line BL may be surrounded by the lower insulating layer 110. For example, the lower insulating layer 110 may contact the side surfaces and the bottom surface of the bit line BL. In other words, the portions of the two side surfaces of the bit line BL extending from the bottom surface and the bottom surface may be surrounded by the lower insulating layer 110. The upper surface of the bit line BL and the upper portions of the two side surfaces extending from the upper surface may be surrounded by a channel pattern CP to be described later.

[0038] The bit line BL may be formed of, or include, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the bit line BL may be formed of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but the embodiments are not limited thereto. The bit line BL may include a single layer or multiple layers of the above materials.

[0039] In some embodiments, the bit line BL may include a two-dimensional semiconductor material, such as graphene, carbon nanotubes, or a combination thereof.

[0040] The first insulating pattern 120 may be located above the bit line BL and extend in the second direction DR2. The lower surface of the first insulating pattern 120 may contact the upper surface of the bit line BL. The first insulating pattern 120 may be arranged to intersect the bit line BL. The first insulating patterns 120 may be arranged to be spaced apart in the first direction DR1.

[0041] The first insulating pattern 120 may be formed of, or include, at least one of, for example, silicon oxide, silicon oxynitride, silicon nitride, and a low dielectric constant (low-k) material having a dielectric constant smaller than that of silicon oxide, but embodiments are not limited thereto.

[0042] For example, the low dielectric constant material may include at least one of flowable oxide (FOX), Toshiba silicon nitride (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorocarbon, organosilicate glass (OSG), parylene, benzocyclobutene (BCB), SiLK, polyimide, porous polymeric materials, and combinations thereof, but embodiments are not limited thereto.

[0043] The channel pattern CP may be located above the bit line BL. The channel pattern CP may be electrically connected to the bit line BL. The channel pattern CP may include a first source / drain region and a second source / drain region. For example, the lower portion of the channel pattern CP is connected to the bit line BL and may serve as the first source / drain region, the upper portion of the channel pattern CP is connected to the landing pad LP and may serve as the second source / drain region, and the portion of the channel pattern CP located between the first source / drain region and the second source / drain region may serve as the channel region.

[0044] The channel pattern CP may be in contact with the bit line BL and the first insulating pattern 120. The channel pattern CP may be in contact with the upper surface of the bit line BL. The channel pattern CP may be in contact with the side surfaces of adjacent first insulating patterns 120 facing each other in the first direction DR1. The channel pattern CP may be located between adjacent first insulating patterns 120 in the first direction DR1. The channel pattern CP and the first insulating pattern 120 may be alternately and repeatedly arranged along the first direction DR1. A plurality of channel patterns CP may be arranged and spaced apart in the first direction DR1. Additionally, a plurality of channel patterns CP may be arranged and spaced apart in the second direction DR2.

[0045] The channel pattern CP may be substantially "U" - shaped in a cross - section cut along the first direction DR1 and the third direction DR3. Each of the channel patterns CP may include a horizontal portion CP_H covering the bit line BL and vertical portions CP_V covering opposite side surfaces of adjacent first insulating patterns 120. The vertical portions of the channel pattern CP may each extend from the horizontal portion CP_H in a third direction DR3 perpendicular to the substrate 100. The vertical portions CP_V may extend along the opposite side surfaces of adjacent first insulating patterns 120 in the third direction DR3. The vertical portions CP_V of the channel pattern CP may be connected to landing pads LP which will be described later.

[0046] The upper surface of the vertical portion CP_V of the channel pattern CP may be at substantially the same vertical level as the upper surface of the first insulating pattern 120, but the embodiments are not limited thereto. In some embodiments, the upper surface of the vertical portion CP_V of the channel pattern CP may be at a vertical level lower than the upper surface of the first insulating pattern 120. In this case, the landing pad LP may include a portion located between the first insulating pattern 120 and the gate insulating pattern Gox which will be described later.

[0047] The channel pattern CP may have a conformal shape. The thickness of the horizontal portion CP_H of the channel pattern CP and the thickness of the vertical portion CP_V may be constant. The thickness of the horizontal portion CP_H may represent the thickness in the third direction DR3, and the thickness of the vertical portion CP_V may represent the thickness in the first direction DR1.

[0048] In a cross - section of the channel pattern CP along the second direction DR2 and the third direction DR3, the channel pattern CP may surround three sides of the bit line BL. The channel pattern CP may surround the upper surface of the bit line BL and portions of the two side surfaces of the bit line BL extending from the upper surface of the bit line BL. According to the above, the upper surface of the lower insulating layer 110 may be at a level between the upper surface and the bottom surface of the bit line BL. The portions of the two side surfaces of the bit line BL may include portions at a vertical level higher than the upper surface of the lower insulating layer 110. For example, the portions of the bit line BL at a vertical level higher than the upper surface of the lower insulating layer 110 may be surrounded by the channel pattern CP.

[0049] The channel pattern CP may contact the upper surface and two side surfaces of the bit line BL. Referring to Figure 3 The channel pattern CP may include a first surface CP_S1 contacting the upper surface of the bit line BL and a second surface CP_S2 contacting the two side surfaces of the bit line BL. The second surfaces CP_S2 of the channel pattern CP may each contact the corresponding side surfaces of the bit line BL at a vertical level higher than the upper surface of the lower insulating layer 110.

[0050] The contact area between the channel pattern CP and the bit line BL can correspond to the areas of the first surface CP_S1 and the second surface CP_S2. For example, since the contact area between the channel pattern CP and the bit line BL increases, the contact resistance can be reduced. According to a comparative example in which the channel pattern CP only contacts the upper surface of the bit line BL, the contact area between the channel pattern CP and the bit line BL can correspond to the area of the first surface CP_S1. According to an embodiment, the contact area between the channel pattern CP and the bit line BL increases by the area of the second surface CP_S2, and thus the contact resistance can be reduced compared to the comparative example.

[0051] The channel pattern CP can cover portions of the upper surface of the lower insulating layer 110 that are located on both sides of the bit line BL. The lower surface of the channel pattern CP can contact a portion of the upper surface of the lower insulating layer 110 that is located on either side of the bit line BL. As Figure 3 shown, the channel pattern CP can include a portion that extends in a third direction DR3 along the side of the bit line BL and a portion that protrudes in a direction away from the bit line BL along the upper surface of the lower insulating layer 110, but the embodiment is not limited thereto. In some embodiments, the portion of the channel pattern CP that extends in the third direction DR3 along the side of the bit line BL may not include a protruding portion. For example, the width of the portion of the channel pattern CP that covers the side of the bit line BL along the first direction DR1 may be constant.

[0052] For example, the channel pattern CP can include an oxide semiconductor material. The oxide semiconductor material can be a combination of at least two of In, Ga, Zn, Al, Sn, and Hf, but the embodiment is not limited thereto. The oxide semiconductor material may also include materials such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, or Mn in the above components.

[0053] For example, the channel pattern CP can include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), zinc oxide nitride (ZnON), zirconium zinc tin oxide (ZZTO), tin oxide (SnO), hafnium indium zinc oxide (HIZO), gallium zinc tin oxide (GZTO), aluminum zinc tin oxide (AZTO), ytterbium gallium zinc oxide (YGZO), indium gallium oxide (IGO), or a combination thereof. However, the embodiment is not limited thereto, and the oxide semiconductor material included in the channel pattern CP can be changed in various ways.

[0054] According to an embodiment, the channel pattern CP can include indium gallium zinc oxide (IGZO).

[0055] The word line WL can be located above the channel pattern CP. The word line WL can be located above the horizontal portion CP_H of the channel pattern CP. The word line WL can be located between the vertical portions CP_V of the channel pattern CP. According to an embodiment, one word line WL can be located between the vertical portions CP_V of the channel pattern CP.

[0056] The word line WL can extend longitudinally in the second direction DR2. The word line WL can be arranged to intersect the bit line BL. The word line WL can be arranged at intervals in the first direction DR1. The word line WL can be spaced apart from the channel pattern CP. The word line WL can be separated from the channel pattern CP by a gate insulating pattern Gox to be described later.

[0057] In a cross-section cut along the first direction DR1 and the third direction DR3, the word line WL can include an upper surface and a bottom surface facing each other in the third direction DR3 and two side surfaces facing each other in the first direction DR1. According to an embodiment, the upper surface of the word line WL can be located at substantially the same vertical level as the upper surface of the channel pattern CP. The bottom surface of the word line WL can face the bit line BL, and the gate insulating pattern Gox and the channel pattern CP are located between the bottom surface of the word line WL and the bit line BL. The two side surfaces of the word line WL can face the vertical portions CP_V of the channel pattern CP, and the gate insulating pattern Gox is located between the two side surfaces of the word line WL and the vertical portions CP_V of the channel pattern CP.

[0058] In a cross-section cut along the second direction DR2 and the third direction DR3, the word line WL can include a first portion WL_P1 and a second portion WL_P2. The first portion WL_P1 covers the upper surface of the bit line BL arranged in the second direction DR2 and extends in the second direction DR2. The second portion WL_P2 extends (or protrudes) from the bottom surface of the first portion WL_P1 toward the upper surface of the lower insulating layer 110 in the third direction DR3. The second portion WL_P2 of the word line WL can be respectively located between the bit lines BL adjacent to each other in the second direction DR2. The second portion WL_P2 of the word line WL can be used as a shielding line between the bit lines BL adjacent to each other in the second direction DR2.

[0059] According to an embodiment, the word line WL can overlap the bit line BL in the second direction DR2 and the third direction DR3. The first portion WL_P1 of the word line WL can overlap the bit line BL in the third direction DR3. The second portion WL_P2 of the word line WL can overlap the bit line BL in the second direction DR2 respectively.

[0060] The word line WL may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the word line WL may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but the embodiments are not limited thereto.

[0061] The word line WL may include a single layer or multiple layers of the above materials. In some embodiments, the word line WL may include a two-dimensional semiconductor material. For example, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0062] The gate insulating pattern Gox may be located between the word line WL and the channel pattern CP. The gate insulating pattern Gox may be located on the channel pattern CP between the first insulating patterns 120 adjacent in the first direction DR1. The gate insulating pattern Gox may be conformally formed on the channel pattern CP.

[0063] In a cross-section cut along the first direction DR1 and the third direction DR3, the gate insulating pattern Gox may conformally cover the horizontal portion CP_H and the vertical portion CP_V of the channel pattern CP. For example, the gate insulating pattern Gox may contact the horizontal portion CP_H and the vertical portion CP_V of the channel pattern CP. According to an embodiment, the word line WL may fill the space left after the gate insulating pattern Gox is formed on the channel pattern CP arranged in the second direction DR2.

[0064] In a cross-section cut along the first direction DR1 and the third direction DR3, the upper surface of the gate insulating pattern Gox located between the side surface of the word line WL and the vertical portion CP_V of the channel pattern CP may be located at substantially the same vertical level as the upper surface of the channel pattern CP, but the embodiments are not limited thereto. In some embodiments, the upper surface of the channel pattern CP may be located at a lower vertical level than the upper surface of the gate insulating pattern Gox.

[0065] In a cross-section cut along the second direction DR2 and the third direction DR3, the gate insulating pattern Gox may conformally cover the channel pattern CP arranged in the second direction DR2 and the lower insulating layer 110 located between the channel patterns CP adjacent in the second direction DR2. For example, the gate insulating pattern Gox may contact the channel pattern CP arranged in the second direction DR2 and the lower insulating layer 110 located between the channel patterns CP adjacent in the second direction DR2.

[0066] The gate insulating pattern Gox may include silicon oxide, silicon oxynitride, a high-k material having a dielectric constant higher than that of silicon oxide, or a combination thereof. The high-k material may include a metal oxide or a metal oxynitride. The high-k material may be, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof. However, the embodiments are not limited thereto, and the materials included in the gate insulating pattern Gox may be changed in various ways.

[0067] The second insulating pattern 130 may be located above the word line WL, the gate insulating pattern Gox, and the first insulating pattern 120. The second insulating pattern 130 may cover the upper surfaces of the word line WL, the gate insulating pattern Gox, and the first insulating pattern 120. For example, the second insulating pattern 130 may contact the upper surfaces of the word line WL, the gate insulating pattern Gox, and the first insulating pattern 120. The upper surface of the vertical portion CP_V of the channel pattern CP may be exposed by the second insulating pattern 130.

[0068] The second insulating pattern 130 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k (low dielectric constant) material having a dielectric constant smaller than that of silicon oxide, but the embodiments are not limited thereto.

[0069] The landing pad LP may be electrically connected to the channel pattern CP. The landing pad LP may contact at least a part of the channel pattern CP. The landing pad LP may contact the upper surface of the vertical portion CP_V of the channel pattern CP exposed by the second insulating pattern 130.

[0070] According to an embodiment, the vertical portion CP_V of the channel pattern CP may be connected to the same landing pad LP. In a cross-section cut along the first direction DR1 and the third direction DR3, the landing pad LP may overlap with the horizontal portion CP_H and the vertical portion CP_V of the channel pattern CP in the third direction DR3, respectively. As Figure 2 shown, the landing pad LP may have a width greater than the width of the channel pattern CP along the first direction DR1, but the embodiments are not limited thereto. In some embodiments, the landing pad LP may have a width substantially the same as the width of the channel pattern CP along the first direction DR1.

[0071] The landing pad LP may contact the vertical portion CP_V of the channel pattern CP by passing through an opening defined by the second insulating pattern 130 in the third direction DR3. In Figure 2In [the figure], the upper surface of the vertical portion CP_V of the channel pattern CP may be located at substantially the same vertical level as the upper surface of the first insulating pattern 120 and the upper surface of the gate insulating pattern Gox. In this case, the contact surface between the landing pad LP and the channel pattern CP may be located at substantially the same vertical level as the upper surface of the first insulating pattern 120 and the upper surface of the gate insulating pattern Gox, but the embodiments are not limited thereto. In some embodiments, the upper surface of the vertical portion CP_V of the channel pattern CP may be located at a vertical level lower than the upper surface of the first insulating pattern 120 and the upper surface of the gate insulating pattern Gox, and in this case, the contact surface between the landing pad LP and the channel pattern CP may be located between the first insulating pattern 120 and the gate insulating pattern Gox. The landing pad LP may also be located between the first insulating pattern 120 and the gate insulating pattern Gox.

[0072] The landing pads LP may be arranged to be spaced apart from each other in a first direction DR1 and a second direction DR2. The landing pads LP may be arranged in a matrix form, but this is only an example and the embodiments are not limited thereto. The landing pads LP may be arranged in various layouts such as a honeycomb shape. The landing pads LP may be spaced apart by the interlayer insulating layer 140 described later.

[0073] The landing pad LP may have a shape such as circular, oval, rectangular, square, diamond or hexagonal in a plane, but the planar shape of the landing pad LP is not limited to these shapes.

[0074] The landing pad LP may include doped polysilicon, metal, conductive metal nitride, conductive metal oxide or a combination thereof. For example, the landing pad LP may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx or a combination thereof, but the embodiments are not limited thereto.

[0075] The interlayer insulating layer 140 may be located above the second insulating pattern 130. The interlayer insulating layer 140 may be in contact with the upper surface of the second insulating pattern 130. The interlayer insulating layer 140 may fill the space between the landing pads LP spaced apart in the first direction DR1 on the second insulating pattern 130. The side surfaces of the landing pads LP may be surrounded by the interlayer insulating layer 140. For example, the interlayer insulating layer 140 may be in contact with the side surfaces of the landing pads LP.

[0076] The interlayer insulating layer 140 may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride and a low dielectric constant (low-k) material having a dielectric constant smaller than that of silicon oxide, but the embodiments are not limited thereto.

[0077] In some embodiments, the interlayer insulating layer 140 may include the same insulating material as the second insulating pattern 130. In this case, the interface between the interlayer insulating layer 140 and the second insulating pattern 130 may not be recognized.

[0078] The data storage pattern DSP may be disposed on the landing pad LP. For example, the lower surface of the data storage pattern DSP may contact the upper surface of the landing pad LP. The data storage pattern DSP may be electrically connected to each channel pattern CP through the landing pad LP. As Figure 1 shown, the data storage pattern DSP may be arranged in a matrix form along the first direction DR1 and the second direction DR2.

[0079] In an embodiment, the data storage pattern DSP may be a capacitor and may include a lower electrode and an upper electrode, and a capacitor dielectric layer interposed between the lower electrode and the upper electrode. If the data storage pattern DSP is a capacitor, the lower electrode may contact the landing pad LP, and the lower electrode may have various shapes such as circular, oval, rectangular, square, diamond, and hexagonal in a plane.

[0080] Conversely, the data storage pattern DSP may be a variable resistor pattern that can be switched between two resistance states by an electrical pulse applied to the memory element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, and a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystal state changes according to the amount of current.

[0081] According to an embodiment of the semiconductor device, the contact resistance can be reduced by increasing the contact area between the bit line BL and the channel pattern CP. In addition, according to an embodiment of the semiconductor device, the word line WL includes a portion located between adjacent bit lines BL, so that the word line WL can be used as a shielding line between adjacent bit lines BL. Therefore, the electrical characteristics of the semiconductor device can be improved.

[0082] Hereinafter, refer to Figure 4 and Figure 5 to describe another exemplary embodiment of the semiconductor device. In the following embodiments, the same components as those in the above embodiments are denoted by the same reference numerals, repeated descriptions are omitted or simplified, and only the differences are mainly explained.

[0083] Figure 4 and Figure 5 are cross-sectional views of a semiconductor device according to other exemplary embodiments. Figure 4 is a view Figure 2 corresponding to the enlarged view of the region of the portion P1. Figure 5 is a view Figure 2 corresponding to the enlarged view of the region of the portion P2.

[0084] Referring to Figure 4 , different from the embodiment of Figures 1 to 3 , the upper surface of the lower insulating layer 110 may be located at substantially the same vertical level as the bottom surface of the bit line BL. For example, the lower insulating layer 110 may contact the bottom surface of the bit line BL and not contact the side surfaces of the bit line BL. Accordingly, the upper surface and the two side surfaces of the bit line BL may be surrounded by the channel pattern CP. The channel pattern CP may completely surround the upper surface and the two side surfaces of the bit line BL. For example, the channel pattern CP may contact the entire upper surface and the two side surfaces of the bit line BL.

[0085] The channel pattern CP may include a first surface CP_S1 that contacts the upper surface of the bit line BL and a second surface CP_S2 that contacts the two side surfaces of the bit line BL. The second surface CP_S2 may each contact the side surface of the bit line BL located at a vertical level higher than the upper surface of the lower insulating layer 110. According to Figure 4 the embodiment of Figures 1 to 3 , different from the embodiment of Figure 4 , the entire side surface of the bit line BL may be located at a vertical level higher than the upper surface of the lower insulating layer 110. Accordingly, Figure 3 the area of the second surface CP_S2 of the embodiment of

[0086] The word line WL may include a first portion WL_P1 and a second portion WL_P2. The first portion WL_P1 covers the upper surface of the bit line BL arranged in the second direction DR2 and extends in the second direction DR2. The second portion WL_P2 extends from the bottom surface of the first portion WL_P1 toward the upper surface of the lower insulating layer 110 in the third direction DR3. The second portion WL_P2 may each be located between the bit lines BL adjacent in the second direction DR2.

[0087] Figure 4 the upper surface of the lower insulating layer 110 of the embodiment of Figure 4 the upper surface of the lower insulating layer 110 of the embodiment of Figures 1 to 3 may be located at a vertical level lower than the upper surface of the lower insulating layer 110 in the embodiment of Figure 4 Accordingly, the width of the second portion WL_P2 of the embodiment of Figures 1 to 3 along the third direction DR3 may be greater than the width of the second portion WL_P2 of the embodiment of Figure 4 In other words, in the embodiment of Figures 1 to 3 , the overlapping area of the bit line BL and the word line WL in the second direction DR2 may be larger than the overlapping area of the bit line BL and the word line WL in the second direction DR2 in the embodiment of

[0088] According to Figure 4 the embodiment of Figures 1 to 3 compared with the contact area between the bit line BL and the channel pattern CP in the embodiment of

[0089] Referring to Figure 5 and different from the embodiment of Figures 1 to 3 the word line WL can be separated from the second insulating pattern 130. The word line WL and the second insulating pattern 130 can be separated in the third direction DR3. The upper surface of the word line WL can be at a vertical level lower than the upper surface of the vertical portion CP_V of the channel pattern CP. The upper surface of the word line WL can be at a vertical level lower than the upper surface of the gate insulating pattern Gox extending in the third direction DR3 along the vertical portion CP_V of the channel pattern CP.

[0090] An additional insulating pattern 150 can be located between the word line WL and the second insulating pattern 130. The additional insulating pattern 150 can be located between portions of the gate insulating pattern Gox at a vertical level higher than the upper surface of the word line WL. The additional insulating pattern 150 can fill the space between the upper surface of the word line WL, the bottom surface of the second insulating pattern 130, and the opposite side surfaces of the gate insulating pattern Gox. The upper surface of the additional insulating pattern 150 can be at the same vertical level as the upper surface of the gate insulating pattern Gox. The additional insulating pattern 150 can extend along the word line WL in the second direction DR2.

[0091] The additional insulating pattern 150 can include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low dielectric constant (low-k) material having a dielectric constant smaller than that of silicon oxide, but the embodiment is not limited thereto.

[0092] In Figures 1 to 3 the embodiment of Figure 5 the second insulating pattern 130 is located on the first insulating pattern 120, the gate insulating pattern Gox, and the word line WL. In Figure 5 the embodiment of

[0093] In Figures 1 to 3In an embodiment, the second insulating pattern 130 contacts the upper surface of the word line WL. In Figure 5 In an embodiment, the second insulating pattern 130 may contact the upper surface of the additional insulating pattern 150.

[0094] In Figures 1 to 3 In an embodiment, although the contact surface of the landing pad LP and the channel pattern CP may be located at substantially the same vertical level as the upper surface of the word line WL, in Figure 5 In an embodiment, the upper surface of the word line WL may be located at a lower vertical level than the contact surface of the landing pad LP and the channel pattern CP. According to Figure 5 In an embodiment, compared to Figures 1 to 3 In an embodiment, the word line WL may be spaced farther apart from the landing pad LP. Therefore, the possibility of a short circuit occurring between the word line WL and the landing pad LP can be reduced.

[0095] Hereinafter, another embodiment of the semiconductor device will be explained with reference to Figure 6 and Figure 7 In the following embodiments, the same components as those in the above embodiments are denoted by the same reference numerals, repeated descriptions are omitted or simplified, and the differences will be mainly explained.

[0096] Figure 6 is a layout diagram for explaining a semiconductor device according to an exemplary embodiment. Figure 7 is a diagram showing a cross-section of a semiconductor device according to an exemplary embodiment taken along lines A-A' and B-B'. Figure 6 of

[0097] Referring to Figure 6 and Figure 7 , similar to Figures 1 to 3 In an embodiment, a plurality of first insulating patterns 120 may be arranged to be spaced apart along a first direction DR1, and the channel pattern CP may be located between the first insulating patterns 120 adjacent in the first direction DR1. The first insulating patterns 120 and the channel pattern CP may be alternately and repeatedly arranged along the first direction DR1.

[0098] In a cross-section cut along the first direction DR1 and the third direction DR3, the channel pattern CP may include a horizontal portion CP_H covering the bit line BL and a vertical portion CP_V extending from the horizontal portion CP_H in the third direction DR3 and facing in the first direction DR1. The horizontal portion CP_H of the channel pattern CP may cover the upper surface of the bit line BL. The vertical portion CP_V of the channel pattern CP may cover the facing side surfaces of the first insulating patterns 120 adjacent in the first direction DR1.

[0099] According to Figure 6 andFigure 7 In the embodiment of Figures 1 to 3 , different from the embodiment of

[0100] , the vertical portions CP_V of the channel pattern CP can each be connected to different landing pads LP spaced apart in the first direction DR1. Adjacent landing pads LP connected to the vertical portions CP_V of the channel pattern CP can be spaced apart in the first direction DR1 by an interlayer insulating layer 140. The landing pads LP can be in contact with the upper surface of any one of the vertical portions CP_V of the channel pattern CP. The landing pads LP can have a width smaller than the width of the channel pattern CP along the first direction DR1.

[0100] According to Figure 6 and Figure 7 In the embodiment of

[0101] , two word lines WL can be located between the vertical portions CP_V of the channel pattern CP. The two word lines WL located between the vertical portions CP_V of the channel pattern CP can include a first word line WL1 and a second word line WL2 spaced apart in the first direction. A third insulating pattern 160 can be located between the first word line WL1 and the second word line WL2.

[0101] The first word line WL1 and the second word line WL2 can each include an upper surface and a bottom surface facing each other in the third direction DR3, and two side surfaces facing each other in the first direction DR1. The bottom surface and one side surface of each of the first word line WL1 and the second word line WL2 can be in contact with the gate insulating pattern Gox. The bottom surface of each of the first word line WL1 and the second word line WL2 can face the horizontal portion CP_H of the channel pattern CP, and the gate insulating pattern Gox is located between the bottom surface of each of the first word line WL1 and the second word line WL2 and the horizontal portion CP_H of the channel pattern CP. One side surface of each of the first word line WL1 and the second word line WL2 can face the vertical portion CP_V of the channel pattern CP, and the gate insulating pattern Gox is located between one side surface of each of the first word line WL1 and the second word line WL2 and the vertical portion CP_V of the channel pattern CP. The upper surface of each of the first word line WL1 and the second word line WL2 can be in contact with the second insulating pattern 130. The upper surfaces of the first word line WL1 and the second word line WL2 can be located at substantially the same vertical level as the upper surface of the vertical portion CP_V of the channel pattern CP. The other side surfaces of the first word line WL1 and the second word line WL2 can face each other. The other side surface of each of the first word line WL1 and the second word line WL2 can be in contact with the third insulating pattern 160.

[0102] The third insulating pattern 160 may be in contact with opposite side surfaces of the first word line WL1 and the second word line WL2. The third insulating pattern 160 may be in contact with an upper surface of the gate insulating pattern Gox positioned between bottom surfaces of the first word line WL1 and the second word line WL2. The third insulating pattern 160 may be in contact with a bottom surface of the second insulating pattern 130 positioned between upper surfaces of the first word line WL1 and the second word line WL2. Although not shown, the third insulating pattern 160 may extend along the first word line WL1 and the second word line WL2 in the second direction DR2.

[0103] In a cross-section cut along the second direction DR2 and the third direction DR3, the first word line WL1 may cover upper surfaces of bit lines BL arranged and spaced apart in the second direction DR2. A portion of the first word line WL1 covering the upper surface of the bit line BL may overlap with the upper surface of the bit line BL in the third direction DR3. The first word line WL1 may include a portion positioned between bit lines BL arranged in the second direction DR2. A portion of the first word line WL1 positioned between bit lines BL arranged in the second direction DR2 may overlap with side surfaces of the bit lines BL in the second direction DR2.

[0104] In Figure 7 it is shown that the first word line WL1 extends in the second direction DR2, covers the upper surface of the bit line BL, and includes a portion positioned between bit lines BL arranged in the second direction DR2, but the above may be equivalently or substantially similarly applied to the second word line WL2 and the third insulating pattern 160.

[0105] According to Figure 6 and Figure 7 embodiments, as in Figures 1 to 3 embodiments, since the contact area between the bit line BL and the channel pattern CP increases, the contact resistance may be reduced. In addition, the first word line WL1 and the second word line WL2 include portions positioned between adjacent bit lines BL, and thus the first word line WL1 and the second word line WL2 may be used as shield lines between adjacent bit lines BL. Accordingly, the electrical characteristics of the semiconductor device may be improved.

[0106] Hereinafter, a method of manufacturing a semiconductor device according to Figures 8 to 34 embodiments will be described with reference to Figures 1 to 3 . In Figures 8 to 34 , for convenience, although the substrate 100 and the core and peripheral circuits SA of Figures 1 to 3 are omitted, the lower insulating layer 110 may be positioned on the substrate 100 and the core and peripheral circuits SA.

[0107] Figure 8 , Figure 11 , Figure 14 , Figure 17 ,Figure 20 , Figure 23 , Figure 26 , Figure 29 and Figure 32 are layout diagrams showing a manufacturing method of a semiconductor device according to an exemplary embodiment. Figure 9 , Figure 10 , Figure 12 , Figure 13 , Figure 15 , Figure 16 , Figure 18 , Figure 19 , Figure 21 , Figure 22 , Figure 24 , Figure 25 , Figure 27 , Figure 28 , Figure 30 , Figure 31 , Figure 33 and Figure 34 are cross-sectional views showing a manufacturing method of a semiconductor device according to an exemplary embodiment. Figure 9 , Figure 12 , Figure 15 , Figure 18 , Figure 21 , Figure 24 , Figure 27 , Figure 30 and Figure 33 are diagrams showing cross-sections taken along lines A-A' and B-B' respectively along Figure 8 , Figure 11 , Figure 14 , Figure 17 , Figure 20 , Figure 23 , Figure 26 , Figure 29 and Figure 32 . Figure 10 , Figure 13 , Figure 16 , Figure 19 , Figure 22 , Figure 25 , Figure 28 , Figure 31 and Figure 34 are diagrams showing cross-sections taken along lines C-C' and D-D' respectively along Figure 8 , Figure 11 , Figure 14 , Figure 17 , Figure 20 , Figure 23 , Figure 26 , Figure 29 and Figure 32 .

[0108] Referring to Figures 8 to 10 , a plurality of bit lines BL surrounded by the lower insulating layer 110 can be formed.

[0109] For example, a bit line BL can be formed by depositing a bit line material layer on an insulating material layer and patterning the bit line material layer. A plurality of bit lines BL can be arranged to be spaced apart along a second direction DR2. Each of the bit lines BL can have a bar shape or a linear shape that extends longitudinally in a first direction DR1.

[0110] Next, a lower insulating layer 110 can be formed by further depositing the same insulating material as the insulating material layer to fill the space between the bit lines BL and cover the upper surface of the bit lines BL. The insulating material can be, for example, silicon nitride, but the embodiments are not limited thereto.

[0111] Next, the upper surface of the lower insulating layer 110 can be planarized to the same vertical level as the upper surface of the bit lines BL. The upper surface of the lower insulating layer 110 and the upper surface of the bit lines BL can be located at substantially the same vertical level.

[0112] Referring to Figures 11 to 13 , a plurality of first insulating patterns 120 extending in the second direction DR2 can be formed on the upper surfaces of the lower insulating layer 110 and the bit lines BL. For example, the second direction DR2 can be perpendicular to the first direction DR1.

[0113] For example, a first insulating material layer can be deposited on the upper surfaces of the lower insulating layer 110 and the bit lines BL, and the first insulating material layer can be patterned to form the first insulating patterns 120. The plurality of first insulating patterns 120 can be arranged to be spaced apart along the first direction DR1. The first insulating patterns 120 can extend across the bit lines BL in the second direction DR2.

[0114] The first insulating material layer can include a material having an etching selectivity with respect to the lower insulating layer 110. The first insulating material layer can be formed of, for example, silicon oxide or include, for example, silicon oxide, but the embodiments are not limited thereto.

[0115] Next, the upper surface of the lower insulating layer 110 can be etched back. For example, an etching solution having an etching selectivity with respect to the material of the first insulating patterns 120 and the material of the lower insulating layer 110 can be used to etch only the upper surface of the lower insulating layer 110. The upper surface of the lower insulating layer 110 can be located at a lower vertical level than the upper surface of the bit lines BL. In an embodiment, the upper surface of the lower insulating layer 110 can be located between the upper surface and the bottom surface of the bit lines BL, but the embodiments are not limited thereto.

[0116] As Figure 4 shown in the embodiments of, the upper surface of the lower insulating layer 110 can be located at substantially the same vertical level as the bottom surface of the bit lines BL. By adjusting the etching degree of the lower insulating layer 110, the height of the upper surface of the lower insulating layer 110 can be adjusted.

[0117] Referring toFigures 14 to 16 The channel material layer CP_L can be formed to conformally cover the first insulating pattern 120, the bit line BL, and the lower insulating layer 110. For example, an atomic layer deposition (ALD) process can be used to deposit the channel material layer CP_L, but the present disclosure is not limited thereto, and various methods can be used to form the channel material layer CP_L.

[0118] The channel material layer CP_L can be formed of, for example, an oxide semiconductor material or include, for example, an oxide semiconductor material. According to an embodiment, the channel material layer CP_L can be formed of indium gallium zinc oxide (IGZO) or include indium gallium zinc oxide (IGZO). However, the embodiments are not limited thereto, and the material included in the channel material layer CP_L can be differently changed to other oxide semiconductor materials or other materials.

[0119] In a cross-section cut along the second direction DR2 and the third direction DR3, the channel material layer CP_L can cover the upper surface and both side surfaces of the first insulating pattern 120. The channel material layer CP_L can cover the upper surface of the bit line BL and the upper portions of both side surfaces of the bit line BL located at a vertical level higher than the upper surface of the lower insulating layer 110. The channel material layer CP_L can cover the upper surface of the lower insulating layer 110 located between the plurality of bit lines BL arranged in the second direction DR2.

[0120] In a cross-section cut along the first direction DR1 and the third direction DR3, the channel material layer CP_L can cover the upper surface and both side surfaces of the first insulating pattern 120. The channel material layer CP_L can cover the upper surface of the bit line BL exposed between the plurality of first insulating patterns 120 arranged in the first direction DR1. The channel material layer CP_L can cover both side surfaces of the portion of the lower insulating layer 110 protruding toward the third direction DR3. The first insulating pattern 120 can be located directly above the protruding portion of the lower insulating layer 110. The protruding portion of the lower insulating layer 110 can be a portion that is not etched because it is covered by the first insulating pattern 120 during the etch-back process of the lower insulating layer 110. The upper surface of the protruding portion of the lower insulating layer 110 can have substantially the same height as the upper surface of the bit line BL. The channel material layer CP_L can cover the upper surface of the lower insulating layer 110 exposed between the plurality of first insulating patterns 120 arranged in the first direction DR1.

[0121] Refer to Figures 17 to 19, an initial channel pattern CP_P can be formed by patterning a channel material layer CP_L. The initial channel pattern CP_P can be arranged to be spaced apart in a second direction DR2. In a plane, the initial channel pattern CP_P can longitudinally extend in a first direction DR1. In a plane, the width of the initial channel pattern CP_P along the second direction DR2 can be greater than the width of the bit line BL along the second direction DR2.

[0122] The initial channel pattern CP_P can surround the upper portion of the bit line BL. The initial channel pattern CP_P can surround the portion of the bit line BL located at a vertical level higher than the upper surface of the lower insulating layer 110. The initial channel pattern CP_P can cover the upper surface of the bit line BL and the portions of the two side surfaces of the bit line BL located at a vertical level higher than the upper surface of the lower insulating layer 110.

[0123] The initial channel pattern CP_P can be arranged to be spaced apart in the second direction DR2 on the upper surface of a first insulating pattern 120 extending along the second direction DR2. In a cross-section cut along the first direction DR1 and a third direction DR3, the initial channel pattern CP_P can cover the upper surface and two side surfaces of the first insulating pattern 120 arranged along the first direction DR1 and the upper surface of the bit line BL.

[0124] Referring to Figures 20 to 22 , a gate insulating material layer Gox_L can be formed to conformally cover the first insulating pattern 120, the initial channel pattern CP_P, and the lower insulating layer 110. For example, an atomic layer deposition (ALD) process can be used to deposit the gate insulating material layer Gox_L, but the method is not limited thereto, and various methods can be used to form the gate insulating material layer Gox_L.

[0125] The gate insulating material layer Gox_L can include silicon oxide, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k material can include a metal oxide or a metal oxynitride. The high-k material can include, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof. However, the embodiments are not limited thereto, and the materials included in the gate insulating material layer Gox_L can be changed in various ways.

[0126] In a cross-section cut along the second direction DR2 and the third direction DR3, the gate insulating material layer Gox_L may cover the upper surface and the side surfaces of the initial channel pattern CP_P disposed in the second direction DR2. The gate insulating material layer Gox_L may cover the upper surface of the first insulating pattern 120 exposed between the initial channel patterns CP_P disposed in the second direction DR2. The gate insulating material layer Gox_L may cover the upper surface of the lower insulating layer 110 exposed between the initial channel patterns CP_P disposed in the second direction DR2.

[0127] In a cross-section cut along the first direction DR1 and the third direction DR3, the gate insulating material layer Gox_L may cover the surface of the initial channel pattern CP_P extending along the first direction DR1. The gate insulating material layer Gox_L may cover the upper surface and the side surfaces of the first insulating pattern 120 that are exposed and not covered by the initial channel pattern CP_P, and the upper surface and the side surfaces of the lower insulating layer 110.

[0128] Referring to Figures 23 to 25 , a word line material layer WL_L may be formed on the gate insulating material layer Gox_L. For example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or ALD processes may be used to deposit the word line material layer WL_L, but the embodiments are not limited thereto.

[0129] The word line material layer WL_L may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the word line material layer WL_L may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but the embodiments are not limited thereto.

[0130] In a cross-section cut along the second direction DR2 and the third direction DR3, the word line material layer WL_L may fill the space remaining after the initial channel pattern CP_P and the gate insulating material layer Gox_L are formed between the bit lines BL adjacent in the second direction DR2. The word line material layer WL_L may be formed to be thicker than the thickness of the first insulating pattern 120 along the third direction DR3. The word line material layer WL_L may be located on the upper surface of the first insulating pattern 120.

[0131] In a cross-section cut along the first direction DR1 and the third direction DR3, the word line material layer WL_L may fill the space remaining after the initial channel pattern CP_P and the gate insulating material layer Gox_L are formed between the first insulating pattern 120 arranged in the first direction DR1. The word line material layer WL_L may be formed to cover the upper surface of the first insulating pattern 120 arranged in the first direction DR1. The word line material layer WL_L may fill the space remaining after the gate insulating material layer Gox_L is formed between the protruding portions of the lower insulating layer 110 arranged in the first direction DR1. The bottom surface of the word line material layer WL_L located between the protruding portions of the lower insulating layer 110 may be at a vertical level lower than the upper surface of the bit line BL.

[0132] Referring to Figures 26 to 28 , the word line material layer WL_L may be etched back to form a plurality of word lines WL.

[0133] For example, the word line material layer WL_L may be etched back so that the word line material layer WL_L has an upper surface located at substantially the same vertical level as the upper surface of the first insulating pattern 120. Thus, the word line material layer WL_L may be disconnected in the first direction DR1.

[0134] The plurality of word lines WL may be arranged to be spaced apart in the first direction DR1.

[0135] In a cross-section cut along the second direction DR2 and the third direction DR3, the word line WL may extend longitudinally in the second direction DR2. The word line WL may cover the upper surface of the bit line BL arranged along the second direction DR2. The word line WL may include portions located between the bit lines BL adjacent in the second direction DR2. Each of the portions of the word line WL located between the adjacent bit lines BL may cover the opposite side surfaces of the adjacent bit lines BL. The word line WL may overlap the bit line BL in the third direction DR3 and the second direction DR2.

[0136] In a cross-section cut along the first direction DR1 and the third direction DR3, the word line WL may be located between the first insulating patterns 120 arranged in the first direction DR1. The word line WL may fill the space remaining after the initial channel pattern CP_P and the gate insulating material layer Gox_L are formed between the first insulating patterns 120 arranged in the first direction DR1. The word line WL may fill the space left after the gate insulating material layer Gox_L is formed between the protruding portions of the lower insulating layer 110 arranged in the first direction DR1. The bottom surface of the word line WL located between the protruding portions of the lower insulating layer 110 may be at a vertical level lower than the upper surface of the bit line BL. The word line WL may fill the space left after the gate insulating material layer Gox_L is formed between the first insulating patterns 120 located above the protruding portions of the lower insulating layer 110.

[0137] According to an embodiment, the upper surface of the word line WL may be at substantially the same vertical level as the upper surface of the first insulating pattern 120, but the embodiment is not limited thereto.

[0138] As Figure 5 shown in the embodiment of, the upper surface of the word line WL may be at a vertical level lower than the upper surface of the first insulating pattern 120. By adjusting the etching degree of the word line WL, the height of the upper surface of the word line WL can be adjusted. In an embodiment where the upper surface of the word line WL is at a vertical level lower than the upper surface of the first insulating pattern 120, an additional insulating pattern (e.g., Figure 5 the additional insulating pattern 150 in) may be formed on the word line WL. At this time, the additional insulating pattern may have an upper surface at substantially the same vertical level as the upper surface of the first insulating pattern 120.

[0139] According to an embodiment, the word line WL may completely fill the space remaining after the initial channel pattern CP_P and the gate insulating material layer Gox_L are formed between the first insulating patterns 120 arranged in the first direction DR1, but the embodiment is not limited thereto.

[0140] As Figure 6 and Figure 7 shown in the embodiments of, the word line WL may be separated in the first direction DR1 between the first insulating patterns 120 arranged in the first direction DR1. The first word line WL1 and the second word line WL2 spaced apart in the first direction DR1 may be formed between the first insulating patterns 120 arranged in the first direction DR1. For example, since the word line material layer WL_L is conformally formed in the process of Figures 23 to 25 and the word line material layer WL_L is patterned in the process of Figures 26 to 28 to be separated between the first insulating patterns 120 arranged in the first direction DR1, Figure 6and Figure 7 the first word line WL1 and the second word line WL2 of the embodiment shown in

[0141] Referring to Figures 29 to 31 , a plurality of gate insulating patterns Gox and a plurality of channel patterns CP can be formed by etching the gate insulating material layer Gox_L and the initial channel pattern CP_P.

[0142] For example, the gate insulating material layer Gox_L can be etched so that the gate insulating material layer Gox_L has an upper surface located at substantially the same vertical level as the upper surface of the first insulating pattern 120. Thus, the gate insulating material layer Gox_L can be separated in the first direction DR1. The plurality of gate insulating patterns Gox can be arranged to be spaced apart in the first direction DR1.

[0143] For example, the initial channel pattern CP_P can be etched so that the initial channel pattern CP_P has an upper surface located at substantially the same vertical level as the upper surface of the first insulating pattern 120. Thus, the initial channel pattern CP_P can be separated not only in the second direction DR2 but also in the first direction DR1. The plurality of channel patterns CP can be spaced apart in the first direction DR1 and the second direction DR2. For example, the plurality of channel patterns CP can be arranged in a matrix form.

[0144] In a cross-section cut along the second direction DR2 and the third direction DR3, the portion of the initial channel pattern CP_P located on the upper surface of the lower insulating layer 110 extending in the second direction DR2 and the portion of the gate insulating material layer Gox_L located on the upper surface of the lower insulating layer 110 extending in the second direction DR2 can be removed. The channel pattern CP can surround three surfaces of the bit line BL. The channel pattern CP can surround the upper surface and two side surfaces of the bit line BL. The channel pattern CP can surround the upper portions of the two side surfaces extending from the upper surface of the bit line BL in the third direction DR3. The upper portions of the two side surfaces of the bit line BL can refer to the portions located at a vertical level higher than the upper surface of the lower insulating layer 110. The channel pattern CP can surround the upper surface of the bit line BL and the portions of the two side surfaces of the bit line BL located at a vertical level higher than the upper surface of the lower insulating layer 110.

[0145] In a cross-section cut along the first direction DR1 and the third direction DR3, a portion of the initial channel pattern CP_P located on the upper surface of the first insulating pattern 120 disposed in the first direction DR1 and a portion of the gate insulating material layer Gox_L located on the upper surface of the first insulating pattern 120 disposed in the first direction DR1 can be removed. The uppermost surfaces of the channel pattern CP and the gate insulating pattern Gox can be located at substantially the same vertical level as the upper surface of the first insulating pattern 120. The channel pattern CP and the gate insulating pattern Gox can be located between the first insulating patterns 120 adjacent to each other in the first direction DR1.

[0146] The channel pattern CP can include a horizontal portion CP_H and a vertical portion CP_V. The horizontal portion CP_H covers the upper surface of the bit line BL, and the vertical portion CP_V extends from the horizontal portion CP_H in the third direction DR3 and covers the facing side surfaces of the first insulating patterns 120 adjacent to each other in the first direction DR1. The vertical portions CP_V can be arranged to face each other between the first insulating patterns 120 adjacent to each other in the first direction DR1.

[0147] The word line WL can be located above the channel pattern CP. The word line WL can be located above the horizontal portion CP_H of the channel pattern CP. The word line WL can be located between the vertical portions CP_V of the channel pattern CP.

[0148] The gate insulating pattern Gox can be located between the channel pattern CP and the word line WL.

[0149] Referring to Figures 32 to 34 , a second insulating pattern 130, a plurality of landing pads LP, an interlayer insulating layer 140, and a data storage pattern DSP can be formed.

[0150] First, a second insulating material layer can be deposited on the word line WL, the gate insulating pattern Gox, and the channel pattern CP, and the second insulating material layer can be patterned to form the second insulating pattern 130 that exposes the upper surface of the vertical portion CP_V of the channel pattern CP. The second insulating material layer can be formed of, for example, silicon nitride or include, for example, silicon nitride, but the embodiments are not limited thereto.

[0151] Next, a landing pad material layer may be deposited. The landing pad material layer may include doped polysilicon, metal, conductive metal nitride, conductive metal oxide, or a combination thereof. For example, the landing pad material layer may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but embodiments are not limited thereto. The landing pad material layer may fill such a recess that includes sidewalls defined by the interlayer insulating layer 140 and a bottom defined by the channel pattern CP. Accordingly, the landing pad material layer may contact an upper surface of the vertical portion CP_V of the channel pattern CP. The landing pad material layer may be formed to cover an upper surface of the second insulating pattern 130.

[0152] Next, after patterning the landing pad material layer to form a hole exposing the upper surface of the second insulating pattern 130, the interlayer insulating layer 140 may be buried in the hole, and then a planarization process may be performed. Accordingly, a landing pad LP may be formed. The landing pad LP may be landing pads LP spaced apart in a first direction DR1 and a second direction DR2. The landing pad LP may be connected to the vertical portion CP_V of the channel pattern CP. The landing pad LP may contact an upper surface of the vertical portion CP_V of the channel pattern CP.

[0153] According to an embodiment, the vertical portion CP_V of the channel pattern CP may be connected to the same landing pad LP, but embodiments are not limited thereto. As in the embodiments shown in Figure 6 and Figure 7 the vertical portions CP_V of the channel pattern CP may each be connected to a different landing pad LP. In this case, in the patterning process of the landing pad material layer, the landing pad material layer may be disconnected between the vertical portions CP_V of the channel pattern CP in a first direction DR1. The landing pads LP connected to each of the vertical portions CP_V of the channel pattern CP may be spaced apart in the first direction DR1, and the interlayer insulating layer 140 may be located between the landing pads LP.

[0154] Subsequently, data storage patterns DSP may be formed on upper surfaces of the landing pads LP, respectively. In an embodiment, the data storage pattern DSP may be a capacitor including a lower electrode, a capacitor dielectric layer, and an upper electrode. In this case, the lower electrode may contact the landing pad LP.

[0155] Although the present disclosure has been described in connection with what are presently considered to be exemplary embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments. On the contrary, the disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: substrate; a lower insulating layer located above the substrate; a bit line located above the lower insulating layer and extending in a first direction parallel to the substrate; a first insulating pattern located above the bit line and extending in a second direction intersecting the first direction; a channel pattern electrically connected to the bit line and covering a side of the first insulating pattern; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern located between the channel pattern and the word line; a second insulating pattern located above the word line, the gate insulating pattern and the first insulating pattern; as well as a landing pad which is electrically connected to the channel pattern, Part of the word line is located between a plurality of bit lines spaced apart from each other in the second direction.

2. The semiconductor device according to claim 1, wherein: The word line includes a first portion and a second portion, the first portion covering an upper surface of the bit line arranged in the second direction and extending in the second direction, the second portion extending from a bottom surface of the first portion toward an upper surface of the lower insulating layer in a third direction perpendicular to the substrate, and The second portions are each located between bit lines adjacent in the second direction.

3. The semiconductor device according to claim 2, wherein: First portions of the word lines overlap the bit lines in the third direction, and second portions of the word lines overlap the bit lines in the second direction, respectively.

4. The semiconductor device according to claim 1, wherein The channel pattern contacts an upper surface and both side surfaces of the bit line.

5. The semiconductor device according to claim 4, wherein: The upper surface of the lower insulating layer is located at a vertical level between the upper surface and the bottom surface of the bit line, The channel pattern surrounds an upper surface of the bit line and portions of both side surfaces of the bit line extending from the upper surface of the bit line, and The portions of both side surfaces of the bit line include portions located at a higher vertical level than an upper surface of the lower insulating layer.

6. The semiconductor device according to claim 4, wherein: An upper surface of the lower insulating layer is located at the same vertical level as a bottom surface of the bit line, and The channel pattern completely surrounds an upper surface of the bit line and both side surfaces of the bit line.

7. The semiconductor device according to claim 1, further comprising: an additional insulating pattern located between the word line and the second insulating pattern, The word line is separated from the second insulating pattern by the additional insulating pattern.

8. The semiconductor device according to claim 1, wherein: The first insulating pattern is a plurality of first insulating patterns, The plurality of first insulation patterns are arranged and spaced apart along the first direction, The channel pattern is located between first insulation patterns adjacent in the first direction among the plurality of first insulation patterns and includes a horizontal portion covering the bit line and a vertical portion extending from the horizontal portion in a third direction perpendicular to the substrate and facing in the first direction, and The vertical portions are connected to the same landing pad.

9. The semiconductor device according to claim 1, wherein: The first insulating pattern is a plurality of first insulating patterns, The plurality of first insulation patterns are arranged and spaced apart along the first direction, The channel pattern is located between first insulation patterns adjacent in the first direction among the plurality of first insulation patterns and includes a horizontal portion covering the bit line and a vertical portion extending from the horizontal portion in a third direction perpendicular to the substrate and facing in the first direction, and The vertical portions are each connected to a different landing pad that is spaced apart in the first direction.

10. The semiconductor device according to claim 9, wherein: The word lines include a first word line and a second word line, the first word line and the second word line are located above the horizontal portion, between the vertical portions, and are spaced apart in the first direction.

11. The semiconductor device according to claim 1, wherein The channel pattern includes indium gallium zinc oxide.

12. A semiconductor device comprising: substrate; a lower insulating layer located on the substrate; a bit line located above the lower insulating layer and extending in a first direction parallel to the substrate; a first insulating pattern located above the bit line and extending in a second direction intersecting the first direction; a channel pattern electrically connected to the bit line and covering a side of the first insulating pattern; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern located between the channel pattern and the word line; a second insulating pattern located on the word line, the gate insulating pattern and the first insulating pattern; as well as a landing pad which is electrically connected to the channel pattern, wherein the word line comprises a protruding portion, the protruding portion protruding toward the upper surface of the lower insulating layer in a third direction perpendicular to the substrate, and Each of the protruding portions of the word line is located between adjacent bit lines in the second direction.

13. The semiconductor device according to claim 12, wherein: Each of the protruding portions of the word line overlaps the bit line adjacent in the second direction.

14. The semiconductor device according to claim 12, wherein: Three sides of the bit line are surrounded by the channel pattern.

15. The semiconductor device according to claim 14, wherein: A bottom surface of the bit line and lower portions of both side surfaces of the bit line extending from the bottom surface of the bit line are surrounded by the lower insulating layer, and An upper surface of the bit line and upper portions of both side surfaces of the bit line extending from the upper surface of the bit line are surrounded by the channel pattern.

16. The semiconductor device according to claim 14, wherein: An upper surface of the bit line and two side surfaces of the bit line are surrounded by the channel pattern, and A bottom surface of the bit line contacts an upper surface of the lower insulating layer.

17. The semiconductor device according to claim 12, wherein: The first insulating patterns and the channel patterns are alternately and repeatedly arranged along the first direction, The channel pattern includes a horizontal portion covering an upper surface of the bit line and a vertical portion covering opposite sides of the first insulating pattern adjacent in the first direction, and A word line is located between the vertical portions.

18. The semiconductor device according to claim 12, wherein: The first insulating patterns and the channel patterns are alternately and repeatedly arranged along the first direction, The channel pattern includes a horizontal portion covering an upper surface of the bit line and a vertical portion covering opposite sides of the first insulating pattern adjacent in the first direction, and Two word lines spaced apart in the first direction are located between the vertical portions.

19. A semiconductor device comprising: substrate; a lower insulating layer located on the substrate; a bit line located above the lower insulating layer and extending in a first direction parallel to the substrate; a first insulating pattern located above the bit line and extending in a second direction intersecting the first direction; a channel pattern electrically connected to the bit line and covering a side of the first insulating pattern; a word line extending in the second direction and spaced apart from the channel pattern; a gate insulating pattern located between the channel pattern and the word line; a second insulating pattern located on the word line, the gate insulating pattern, and the first insulating pattern; and a landing pad which is electrically connected to the channel pattern, wherein the bit line has an upper surface located at a higher vertical level than an upper surface of the lower insulating layer, and wherein a portion of the bit line located at a higher vertical level than an upper surface of the lower insulating layer overlaps the word line in the second direction and in a third direction perpendicular to the substrate.

20. The semiconductor device according to claim 19, wherein: The channel pattern includes a first surface in contact with an upper surface of the bit line and a second surface in contact with both side surfaces of the bit line, and Each of the second surfaces is in contact with the side surface of the bit line located at a higher vertical level than the upper surface of the lower insulating layer.

Images