Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device may include: a bit line extending in a first horizontal direction on a substrate; a channel layer on the bit line and penetrating in a portion of the bit line, including an oxide semiconductor material including indium (In), the channel layer having an inner wall and an outer wall; a gate insulating layer on one side of the inner wall of the channel layer, the gate insulating layer having an inner wall and an outer wall; an intermediate insulating layer between an inner wall of the channel layer and an outer wall of the gate insulating layer and including an insulating material different from an insulating material of the gate insulating layer; a word line on an inner wall of the gate insulating layer and extending in a second horizontal direction intersecting the first horizontal direction; and a contact layer on a top surface of the channel layer and a top surface of the gate insulating layer, in which an intermediate insulating layer is formed only on a portion of an outer wall of the gate insulating layer.

Description

Technical Field

[0001] Various example embodiments of the inventive concept relate to semiconductor devices, and more particularly, to semiconductor devices including vertical channel transistors. Background Art

[0002] To meet excellent performance and improved economic efficiency, it may be necessary to increase the integration degree of semiconductor devices. Specifically, the integration degree of memory devices is an important factor determining the economic feasibility of products. Since the integration degree of two-dimensional memory devices is mainly determined by the area occupied by a unit memory cell, the technical level for forming fine patterns is a decisive factor. However, since forming fine patterns may require more expensive equipment, the area of chip dies is still limited. Therefore, the integration degree of two-dimensional memory devices is still increasing to overcome the limitation of the area of chip dies. Accordingly, the demand for semiconductor devices including vertical channel transistors (VCTs) is increasing. Summary of the Invention

[0003] Various example embodiments of the inventive concept provide a semiconductor device having improved electrical characteristics and improved product reliability.

[0004] The objects solved by various example embodiments of the inventive concept are not limited to the above objects, and other objects not mentioned will be clearly understood by those skilled in the art from the following description.

[0005] According to various example embodiments of the inventive concept, there is provided a semiconductor device including: a bit line extending in a first horizontal direction on a substrate; a channel layer on the bit line and penetrating into a part of the bit line, the channel layer including an oxide semiconductor material containing indium (In), the channel layer having an inner wall and an outer wall; a gate insulating layer on one side of the inner wall of the channel layer, the gate insulating layer having an inner wall and an outer wall; an intermediate insulating layer between the inner wall of the channel layer and the outer wall of the gate insulating layer and including an insulating material different from the insulating material of the gate insulating layer; a word line on the inner wall of the gate insulating layer and extending in a second horizontal direction intersecting the first horizontal direction; and a contact layer on the top surface of the channel layer and the top surface of the gate insulating layer. The intermediate insulating layer is formed only on a part of the outer wall of the gate insulating layer.

[0006] According to some other example embodiments of the inventive concept, there is provided a semiconductor device including: a bit line extending in a first horizontal direction on a substrate; a channel layer having a U shape and penetrating into a part of the bit line, including InGaZnO x(IGZO), and having an inner wall and an outer wall; a gate insulating layer on one side of the inner wall of the channel layer, including a high-k dielectric material, the gate insulating layer having an inner wall and an outer wall; an intermediate insulating layer between the inner wall of the channel layer and the outer wall of the gate insulating layer, the intermediate insulating layer including at least one of silicon oxide and silicon oxynitride; a word line on the inner wall of the gate insulating layer and extending in a second horizontal direction intersecting the first horizontal direction; and a contact layer on the top surface of the channel layer and the top surface of the gate insulating layer.

[0007] According to still other exemplary embodiments of the inventive concept, there is provided a semiconductor device including: a bit line extending in a first horizontal direction on a substrate; a mold layer covering the bit line on the substrate, the mold layer having a mold opening; a channel layer on the inner wall of the mold opening, having a bottom penetrating into the bit line and a sidewall portion extending in a vertical direction on the inner wall of the mold opening, the channel layer including InGaZnO x (IGZO); a gate insulating layer within the mold opening and on the channel layer, the gate insulating layer including a high-k dielectric material; an intermediate insulating layer within the mold opening and between the channel layer and the gate insulating layer, the intermediate insulating layer including at least one of silicon oxide and silicon oxynitride; a word line within the mold opening, on the gate insulating layer, and extending in a second horizontal direction intersecting the first horizontal direction; a contact layer on the top surface of the channel layer and the top surface of the gate insulating layer; and a capacitor structure on the contact layer. The intermediate insulating layer is formed only in a portion between the channel layer and the gate insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] From the following detailed description in conjunction with the accompanying drawings, various exemplary embodiments will be more clearly understood, in which:

[0009] Figure 1 show a layout of a semiconductor device according to various exemplary embodiments;

[0010] Figure 2 show Figure 1 an enlarged layout of a part of a cell array region of

[0011] Figure 3 is a cross-sectional view taken along line A1 - A1' in Figure 2 ;

[0012] Figure 4 and Figure 5 are cross-sectional views showing a semiconductor device according to still other exemplary embodiments;

[0013] Figures 6 to 16 is a cross-sectional view showing a method of manufacturing a semiconductor device according to various exemplary embodiments in a process sequence; and

[0014] Figure 17 is a structural diagram showing a system including a semiconductor device according to various example embodiments. Detailed Embodiments

[0015] Hereinafter, various example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0016] Figure 1 shows a layout of a semiconductor device according to various example embodiments. Figure 2 shows Figure 1 an enlarged layout of a part of the cell array region. Figure 3 is a cross-sectional view taken along line A1 - A1' in Figure 2 .

[0017] Referring together to Figures 1 to 3 , the semiconductor device 100 may include a substrate 110, and the substrate 110 includes a cell array region MCA and a peripheral circuit region PCA.

[0018] In some example embodiments, the cell array region MCA may be a storage cell region of a dynamic random access memory (DRAM) device, and the peripheral circuit region PCA may be a core region or a peripheral circuit region of the DRAM device. For example, the peripheral circuit region PCA may include peripheral circuit transistors (not shown) that transmit signals and / or power to a storage cell array included in the cell array region MCA.

[0019] In some example embodiments, the peripheral circuit transistors (not shown) may form various circuits, such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.

[0020] In the cell array region MCA of the substrate 110, a plurality of bit lines BL extending in a first horizontal direction X and a plurality of word lines WL extending in a second horizontal direction Y intersecting the first horizontal direction X may be arranged. A plurality of cell transistors CTR may be provided at intersections between the plurality of bit lines BL and the plurality of word lines WL. A plurality of cell capacitors CAP may be respectively provided on the plurality of cell transistors CTR.

[0021] The plurality of word lines WL may include a first word line WL1 and a second word line WL2 alternately arranged in the first horizontal direction X, and the plurality of cell transistors CTR may include a first cell transistor CTR1 and a second cell transistor CTR2 alternately arranged in the first horizontal direction X. That is, the first cell transistor CTR1 may be provided at the first word line WL1, and the second cell transistor CTR2 may be provided at the second word line WL2.

[0022] The first unit transistor CTR1 and the second unit transistor CTR2 may have a mirror-symmetric structure with respect to each other. For example, the first unit transistor CTR1 and the second unit transistor CTR2 may have a mirror-symmetric structure with respect to a center line extending in the second horizontal direction Y.

[0023] In some example embodiments, the width of each of the plurality of bit lines BL may be 1F, and the pitch (i.e., the sum of the width and the spacing) of the plurality of bit lines BL may be 2F. In addition, the width of each of the plurality of word lines WL may be 1F, and the pitch of the plurality of word lines WL may be 2F. Therefore, the unit area for forming one unit transistor CTR may be 4F. 2 Therefore, the unit transistor CTR may be of a cross-point type, which may require a relatively small unit area, which may be beneficial to improving the integration degree of the semiconductor device 100.

[0024] The lower insulating layer 112 may be disposed on the substrate 110. In some example embodiments, the substrate 110 may include silicon, such as single-crystalline silicon, polycrystalline silicon, or amorphous silicon. In some other example embodiments, the substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. However, the example embodiments are not limited thereto. In some example embodiments, the substrate 110 may include a conductive region, such as an impurity-doped well or an impurity-doped structure. In addition, the lower insulating layer 112 may include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0025] The bit line BL extending in the first horizontal direction X may be disposed on the lower insulating layer 112. In some example embodiments, the bit line BL may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polycrystalline silicon, or a combination thereof. However, the example embodiments are not limited thereto. For example, the bit line BL may include a conductive layer 122, a lower conduction resistance barrier layer 124L disposed on the lower surface of the conductive layer 122, and an upper conduction resistance barrier layer 124U disposed on the top surface of the conductive layer 122. A bit line insulating layer (not shown) extending in the first horizontal direction X may be disposed on the sidewalls of the bit line BL. For example, the bit line insulating layer may fill the space between two adjacent bit lines BL and may be formed at the same height as the bit line BL.

[0026] The mold layer 130 can be disposed on the bit line BL and the bit line insulating layer. The mold layer 130 can include a plurality of mold openings 130H. Here, each mold opening 130H can have a first sidewall 130H1 and a second sidewall 130H2 facing each other. In addition, each mold opening 130H can have a rounded lower wall 130H3 that exposes the conductive layer 122 of the bit line BL. Through the rounded lower wall 130H3 of each mold opening 130H, a recessed area can be formed in the bit line BL. In addition, the mold layer 130 can be disposed to cover a flat area surrounding the recessed area of the bit line BL. For example, the mold layer 130 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride. However, the exemplary embodiments are not limited thereto.

[0027] A plurality of channel layers 140 can be disposed on the inner walls of the plurality of mold openings 130H. Each of the plurality of channel layers 140 can include a first portion 140P1 extending in a first horizontal direction X along the rounded lower wall 130H3 of the plurality of mold openings 130H and a second portion 140P2 connected to the first portion 140P1 and disposed on the first sidewall 130H1 and the second sidewall 130H2 of the plurality of mold openings 130H.

[0028] In some exemplary embodiments, each of the plurality of channel layers 140 can have a U-shaped vertical cross-section. The first portion 140P1 of each of the plurality of channel layers 140 can have a rounded corner. The second portion 140P2 of each of the plurality of channel layers 140 can include a first sidewall 140S1 and a second sidewall 140S2 opposite to each other, and the second sidewall 140S2 can be in contact with the mold layer 130.

[0029] In addition, the first portion 140P1 and the second portion 140P2 of each of the plurality of channel layers 140 can be in contact with the bit line BL. The first portion 140P1 of each of the plurality of channel layers 140 can be in contact with the conductive layer 122, and the second portion 140P2 of each of the plurality of channel layers 140 can be in contact with the sidewall of the upper conduction blocking layer 124U. However, the plurality of channel layers 140 may not be in contact with the lower conduction blocking layer 124L.

[0030] In some exemplary embodiments, the plurality of channel layers 140 can include an oxide semiconductor material. In some exemplary embodiments, the oxide semiconductor material can include indium (In), such as InGaZnO x (IGZO), Sn-doped InGaZnO x (IGZO), W-doped InGaZnO x (IGZO) and IZO (InZnO x ). However, the exemplary embodiments are not limited thereto.

[0031] The intermediate insulating layer 142, the gate insulating layer 150, and the word line WL may be sequentially disposed on the first sidewall 140S1 of the channel layer 140. For example, the gate insulating layer 150 may cover the intermediate insulating layer 142 and be conformally disposed on the top surface of the first portion 140P1 of the channel layer 140 and the first sidewall 140S1 of the second portion 140P2.

[0032] The word line WL may be disposed on the top surface of the first portion 140P1 of the channel layer 140 and the first sidewall 140S1 of the second portion 140P2, and the gate insulating layer 150 may be disposed between the word line WL and the channel layer 140. Here, the gate insulating layer 150 may include an outer wall facing the first sidewall 140S1 of the channel layer 140 and an inner wall facing the word line WL.

[0033] In the semiconductor device 100 according to various exemplary embodiments, the intermediate insulating layer 142 may be disposed between the first sidewall 140S1 of the channel layer 140 and the outer wall of the gate insulating layer 150. The intermediate insulating layer 142 may include an insulating material of a different type from the insulating material of the gate insulating layer 150. For example, the intermediate insulating layer 142 may include at least one of silicon oxide and silicon oxynitride, but the exemplary embodiments are not limited thereto. In some exemplary embodiments, the intermediate insulating layer 142 may include a bilayer of silicon oxide and silicon oxynitride.

[0034] In some exemplary embodiments, the intermediate insulating layer 142 may be formed only on a part of the outer wall of the gate insulating layer 150. Accordingly, the outer wall of the gate insulating layer 150 may include a portion in contact with the intermediate insulating layer 142 and a remaining portion in contact with the first sidewall 140S1 of the channel layer 140. In some exemplary embodiments, the length of the intermediate insulating layer 142 along the vertical direction Z may be substantially equal to the length of the word line WL along the vertical direction Z.

[0035] In some exemplary embodiments, the vertical level of the uppermost surface of the intermediate insulating layer 142 may be lower than the vertical level of the lowermost surface of the contact layer 170 described below, and the vertical level of the lowermost surface of the intermediate insulating layer 142 may be higher than the vertical level of the lowermost surface of the first sidewall 140S1 of the channel layer 140. That is, the intermediate insulating layer 142 may be disposed so as not to contact the contact layer 170.

[0036] In some example embodiments, the vertical level of the uppermost surface of the intermediate insulating layer 142 may be lower than the vertical level of the uppermost surface of the second portion 140P2 of the channel layer 140, and the vertical level of the lowermost surface of the intermediate insulating layer 142 may be higher than the vertical level of the uppermost surface of the first portion 140P1 of the channel layer 140. That is, the intermediate insulating layer 142 may be arranged to contact only a part of the first sidewall 140S1 of the channel layer 140.

[0037] The channel layer 140 having a U-shaped vertical cross-section may be disposed within a mold opening 130H, and two word lines WL may be arranged on the channel layer 140 within the mold opening 130H with a space therebetween. Here, one word line WL may be arranged to face a second portion 140P2 of the channel layer 140, and the other word line WL may be arranged to face another second portion 140P2 of the channel layer 140. One word line WL, a second portion 140P2 of the channel layer 140, the intermediate insulating layer 142 therebetween, and the gate insulating layer 150 may constitute a first unit transistor CTR1. In addition, the other word line WL, another second portion 140P2 of the channel layer 140, the intermediate insulating layer 142 therebetween, and the gate insulating layer 150 may constitute a second unit transistor CTR2. Therefore, the first unit transistor CTR1 and the second unit transistor CTR2 may be arranged mirror-symmetrically with respect to each other within the mold opening 130H.

[0038] In some example embodiments, the gate insulating layer 150 may include a high-k dielectric material having a dielectric constant higher than that of silicon oxide. In some example embodiments, the gate insulating layer 150 may have a dielectric constant of about 10 to about 25. For example, the gate insulating layer 150 may include HfO2, Al2O3, HfAlO3, Ta2O3, TiO2, or a combination thereof, but the example embodiments are not limited thereto.

[0039] In some example embodiments, the word line WL may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. However, the example embodiments are not limited thereto.

[0040] The contact layer 170 may be disposed on the top surface of the channel layer 140 and the top surface of the gate insulating layer 150. The contact layer 170 may cover the channel layer 140 and the gate insulating layer 150 and may extend onto the mold layer 130. The contact layer 170 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. However, the example embodiments are not limited thereto.

[0041] The insulating spacer 182A and the first insulating layer 182B can be disposed between two word lines WL in each of the plurality of mold openings 130H, and the second insulating layer 184 can be disposed on the two word lines WL. In addition, the third insulating layer 186 can be disposed on two sidewalls of the contact layer 170. For example, the insulating spacer 182A can include silicon nitride, and the first insulating layer 182B can include silicon oxide. In addition, the second insulating layer 184 and the third insulating layer 186 can include silicon nitride. However, the exemplary embodiments are not limited thereto.

[0042] The etch stop layer 188 can be disposed on the contact layer 170 and the third insulating layer 186. The etch stop layer 188 can include an opening 188H, and the top surface of the contact layer 170 can be exposed through the opening 188H.

[0043] The capacitor structure 190 can be disposed on the etch stop layer 188. The capacitor structure 190 can include a lower electrode 192, a capacitor dielectric layer 194, and an upper electrode 196. The sidewalls at the bottom of the lower electrode 192 can be disposed within the opening 188H of the etch stop layer 188, and the lower electrode 192 can extend in the vertical direction Z. The capacitor dielectric layer 194 can be disposed on the sidewalls of the lower electrode 192, and the upper electrode 196 can cover the lower electrode 192 on the capacitor dielectric layer 194.

[0044] To achieve excellent performance and improved economic efficiency, it may be necessary to increase the integration degree of semiconductor devices. Specifically, the integration degree of storage devices is an important factor determining the economic feasibility of products. Since the integration degree of two-dimensional storage devices is mainly determined by the area occupied by a unit storage cell, the technical level for forming fine patterns is the determining factor. However, since forming fine patterns may require more expensive equipment, the area of chip dice is still limited. Therefore, the integration degree of two-dimensional storage devices is still continuously increasing to overcome the limitation of the area of chip dice. Accordingly, the demand for semiconductor devices including vertical channel transistors (VCTs) is increasing.

[0045] Generally, in semiconductor devices using an oxide semiconductor material containing indium (In) as a channel layer constituting a vertical channel transistor, the gate insulating layer includes a high-k dielectric material to improve electrical characteristics. In this way, when the high-k dielectric material is used as the gate insulating layer, electrical characteristics such as on-current are improved, but electron trapping at the interface between the channel layer (oxide semiconductor material) and the gate insulating layer (high-k dielectric material) increases. Therefore, problems such as reduced thermal stability and / or product reliability may occur in semiconductor devices.

[0046] To solve this problem, in the semiconductor device 100 according to various exemplary embodiments of the present inventive concept, by inserting an intermediate insulating layer 142 including silicon oxide and / or silicon oxynitride between the first sidewall 140S1 of the channel layer 140 and the outer wall of the gate insulating layer 150, the problem of reduced thermal stability and product reliability of the semiconductor device 100 can be more effectively controlled.

[0047] Ultimately, silicon oxide and / or silicon oxynitride (i.e., the intermediate insulating layer 142), which has a relatively small electron trapping effect with respect to the oxide semiconductor material compared to the high-k dielectric material, is disposed on a part of the channel layer 140. Therefore, a semiconductor device 100 having improved electrical characteristics and at the same time improved product reliability can be provided.

[0048] Figure 4 and Figure 5 is a cross-sectional view showing a semiconductor device according to other exemplary embodiments.

[0049] Most of the components constituting the semiconductor devices 100A and 100B described below and the materials forming these components are substantially the same as or similar to those previously referred to Figures 1 to 3 described. Therefore, for ease of description, the description will focus on the differences from the above-described semiconductor device 100.

[0050] Referring to Figure 4 , the semiconductor device 100A may include a bit line BL, a word line WL, a channel layer 140, an intermediate insulating layer 142A, a gate insulating layer 150, a contact layer 170, and a capacitor structure 190.

[0051] In the semiconductor device 100A according to various exemplary embodiments, the intermediate insulating layer 142A may be disposed between the first sidewall 140S1 of the channel layer 140 and the outer wall of the gate insulating layer 150. The intermediate insulating layer 142A may include an insulating material of a different type from the gate insulating layer 150. For example, the intermediate insulating layer 142A may include at least one of silicon oxide and silicon oxynitride, but the exemplary embodiments are not limited thereto. In some exemplary embodiments, the intermediate insulating layer 142A may include a bilayer of silicon oxide and silicon oxynitride.

[0052] In some exemplary embodiments, the intermediate insulating layer 142A may be formed only on a part of the outer wall of the gate insulating layer 150. Therefore, the outer wall of the gate insulating layer 150 may include a part in contact with the intermediate insulating layer 142A and a remaining part in contact with the first sidewall 140S1 of the channel layer 140. In some exemplary embodiments, the length of the intermediate insulating layer 142A in the vertical direction Z may be greater than the length of the word line WL in the vertical direction Z.

[0053] In some example embodiments, the vertical level of the uppermost surface of the intermediate insulating layer 142A may be equal to the vertical level of the lowermost surface of the contact layer 170, and the vertical level of the lowermost surface of the intermediate insulating layer 142A may be higher than the vertical level of the lowermost surface of the first sidewall 140S1 of the channel layer 140. That is, the intermediate insulating layer 142A may be arranged to contact the contact layer 170.

[0054] In some example embodiments, the vertical level of the uppermost surface of the intermediate insulating layer 142A may be equal to the vertical level of the uppermost surface of the second portion 140P2 of the channel layer 140, and the vertical level of the lowermost surface of the intermediate insulating layer 142A may be higher than the vertical level of the uppermost surface of the first portion 140P1 of the channel layer 140. That is, the intermediate insulating layer 142A may be arranged to contact most of the first sidewall 140S1 of the channel layer 140.

[0055] Referring to Figure 5 , the semiconductor device 100B may include a bit line BL, a word line WL, a channel layer 140, an intermediate insulating layer 142B, a gate insulating layer 150, a contact layer 170, and a capacitor structure 190.

[0056] In the semiconductor device 100B according to various example embodiments, the intermediate insulating layer 142B may be disposed between the first sidewall 140S1 of the channel layer 140 and the outer wall of the gate insulating layer 150. The intermediate insulating layer 142B may include an insulating material of a different type from the insulating material of the gate insulating layer 150. For example, the intermediate insulating layer 142B may include at least one of silicon oxide and silicon oxynitride, but the example embodiments are not limited thereto. In some example embodiments, the intermediate insulating layer 142B may include a bilayer of silicon oxide and silicon oxynitride.

[0057] In some example embodiments, the intermediate insulating layer 142B may be formed only on a part of the outer wall of the gate insulating layer 150. Thus, the outer wall of the gate insulating layer 150 may include a portion in contact with the intermediate insulating layer 142B and a remaining portion in contact with the first sidewall 140S1 of the channel layer 140. In some example embodiments, the length of the intermediate insulating layer 142B in the vertical direction Z may be greater than the length of the word line WL in the vertical direction Z.

[0058] In some example embodiments, the vertical level of the uppermost surface of the intermediate insulating layer 142B may be lower than the vertical level of the lowermost surface of the contact layer 170, and the vertical level of the lowermost surface of the intermediate insulating layer 142B may be equal to the vertical level of the uppermost surface of the first portion 140P1 of the channel layer 140. That is, the intermediate insulating layer 142B may be arranged not to contact the contact layer 170.

[0059] In some example embodiments, the vertical level of the uppermost surface of the intermediate insulating layer 142B may be lower than the vertical level of the uppermost surface of the second portion 140P2 of the channel layer 140, and the lower surface of the intermediate insulating layer 142B may be disposed in a first horizontal direction X to contact the top surface of the first portion 140P1 of the channel layer 140. That is, the intermediate insulating layer 142B may be disposed to face both a sidewall and a lower surface of the word line WL.

[0060] Figures 6 to 16 is a cross-sectional view showing a method of manufacturing a semiconductor device in a process sequence according to various example embodiments.

[0061] Referring to Figure 6 , a lower insulating layer 112 may be formed on the substrate 110.

[0062] Next, a plurality of bit lines BL extending in a first horizontal direction X and a bit line insulating layer (not shown) filling a space between the plurality of bit lines BL may be formed on the lower insulating layer 112.

[0063] In some example embodiments, each of the plurality of bit lines BL may include a lower conduction blocking layer 124L, a conductive layer 122, and an upper conduction blocking layer 124U arranged in sequence. For example, a bit line formation space (not shown) may be formed by forming a bit line insulating layer on the lower insulating layer 112 and patterning the bit line insulating layer using a mask pattern (not shown), and the lower conduction blocking layer 124L, the conductive layer 122, and the upper conduction blocking layer 124U may be sequentially formed in the bit line formation space.

[0064] Next, the plurality of bit lines BL may be formed by removing portions of the lower conduction blocking layer 124L, the conductive layer 122, and the upper conduction blocking layer 124U formed above the top surface of the bit line insulating layer such that the top surface of the bit line insulating layer is exposed.

[0065] Referring to Figure 7 , a mold layer 130 may be formed on the plurality of bit lines BL and the bit line insulating layer.

[0066] The mold layer 130 may be formed using at least one of silicon oxide, silicon nitride, and silicon oxynitride. However, the example embodiments are not limited thereto, and the mold layer 130 may have a relatively large height in a vertical direction Z.

[0067] Next, a mask pattern (not shown) can be formed on the mold layer 130, and the mask pattern can be used as an etching mask to form a plurality of mold openings 130H. Each mold opening 130H can have a first sidewall 130H1 and a second sidewall 130H2 facing each other. In addition, each mold opening 130H can have a rounded lower wall 130H3 exposing the conductive layer 122 of the bit line BL. Through the rounded lower wall 130H3 of each mold opening 130H, a recessed area can be formed in the bit line BL.

[0068] Referring to Figure 8 , an initial channel layer 140L can be formed on the mold layer 130 to conformally cover the inner walls of the mold openings 130H.

[0069] In some example embodiments, the initial channel layer 140L can be formed using an oxide semiconductor material. The oxide semiconductor material can include indium (In), such as InGaZnO x (IGZO), Sn-doped InGaZnO x (IGZO), W-doped InGaZnO x (IGZO), and InZnO x (IZO). However, the example embodiments are not limited thereto.

[0070] In some example embodiments, the initial channel layer 140L can be formed using at least one of a chemical vapor deposition (CVD) process, a low-pressure CVD process, a plasma-enhanced CVD process, a metalorganic CVD (MOCVD) process, and an atomic layer deposition process. However, the example embodiments are not limited thereto.

[0071] Next, an initial intermediate insulating layer 142L can be conformally formed on the initial channel layer 140L. In some example embodiments, the initial intermediate insulating layer 142L can be formed using silicon oxide and / or silicon oxynitride.

[0072] Referring to Figure 9 , a portion of the initial intermediate insulating layer 142L (see Figure 8 ) can be etched to form an intermediate insulating layer 142 on the sidewalls of the initial channel layer 140L.

[0073] By patterning the initial intermediate insulating layer 142L using a mask pattern (not shown), the intermediate insulating layer 142 can be left only on the desired regions of the initial channel layer 140L.

[0074] In some example embodiments, the vertical level of the uppermost surface of the intermediate insulating layer 142 may be lower than the vertical level of the uppermost surface of the mold opening 130H, and the vertical level of the lowermost surface of the intermediate insulating layer 142 may be higher than the vertical level of the top surface of the bottom of the initial channel layer 140L. That is, the intermediate insulating layer 142 may be formed to contact only a part of the sidewalls of the initial channel layer 140L.

[0075] Referring to Figure 10 , a gate insulating layer 150 and a gate electrode layer 160L may be sequentially formed on the initial channel layer 140L to cover the intermediate insulating layer 142.

[0076] The gate insulating layer 150 may include a high-k dielectric material having a dielectric constant higher than that of silicon oxide. That is, the intermediate insulating layer 142 may include an insulating material of a different type from the insulating material of the gate insulating layer 150.

[0077] In some example embodiments, the gate electrode layer 160L may be formed using Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. However, the example embodiments are not limited thereto.

[0078] Referring to Figure 11 , an anisotropic etching process may be performed on the gate electrode layer 160L to remove the portion of the gate electrode layer 160L disposed on the bottom of the mold opening 130H, and the gate electrode layer 160L may remain on the first sidewall 130H1 and the second sidewall 130H2 of the mold opening 130H.

[0079] In addition, the portion of the gate electrode layer 160L disposed on the top surface of the mold layer 130 may be removed by an anisotropic etching process.

[0080] For example, the gate electrode layer 160L may be divided into two word lines WL, which are respectively disposed on the first sidewall 130H1 and the second sidewall 130H2 of the plurality of mold openings 130H.

[0081] In addition, the portion of the gate insulating layer 150 disposed on the bottom of the mold opening 130H may be removed by an anisotropic etching process. As a result, the top surface of the initial channel layer 140L may be exposed at the bottom of the mold opening 130H. In addition, by the anisotropic etching process, the portion of the gate insulating layer 150 disposed on the top surface of the mold layer 130 may be removed, and the top surface of the initial channel layer 140L may be exposed.

[0082] Referring to Figure 12 , an insulating liner 182A and a first insulating layer 182B may be formed inside the mold opening 130H.

[0083] The insulating spacer 182A and the first insulating layer 182B may be disposed between two adjacent word lines WL, and the insulating spacer 182A may be disposed on the top surface of the initial channel layer 140L.

[0084] Referring Figure 13 , the portion of the insulating spacer 182A disposed on the top surface of the mold layer 130 and the portion of the initial channel layer 140L disposed on the top surface of the mold layer 130 may be removed by an etch-back process or a planarization process to form the channel layer 140 within the mold opening 130H.

[0085] The channel layer 140 having a U-shaped vertical cross-section may be formed within the mold opening 130H by an etch-back process or a planarization process. In addition, since the portion of the initial channel layer 140L disposed on the top surface of the mold layer 130 is removed, the top surface of the mold layer 130 may be exposed.

[0086] In some example embodiments, the channel layer 140 may include a first portion 140P1 extending in a first horizontal direction X and second portions 140P2 connected to both ends of the first portion 140P1 and extending in a vertical direction Z. The first sidewall 140S1 of the second portion 140P2 may be surrounded by the intermediate insulating layer 142 and the gate insulating layer 150, and the second sidewall 140S2 of the second portion 140P2 may be surrounded by the mold layer 130. In addition, the top surface of the channel layer 140 may be at the same vertical level as the top surface of the mold layer 130.

[0087] Next, the upper portion of the word line WL disposed within the mold opening 130H may be removed by an etch-back process. In the etch-back process, the upper portion of the insulating spacer 182A and the upper portion of the first insulating layer 182B may be removed together.

[0088] Next, a second insulating layer 184 may be formed to fill the entrance of the mold opening 130H. The second insulating layer 184 may be disposed with a flat bottom surface on the top surface of the word line WL, the top surface of the insulating spacer 182A, and the top surface of the first insulating layer 182B.

[0089] Thus, a first unit transistor CTR1 and a second unit transistor CTR2 may be formed within the mold opening 130H. The first unit transistor CTR1 and the second unit transistor CTR2 may be arranged mirror-symmetrically with respect to each other.

[0090] Referring Figure 14 , a contact conductive layer 170L may be formed on the mold layer 130 and the second insulating layer 184.

[0091] In some example embodiments, the contact conductive layer 170L may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. However, the example embodiments are not limited thereto.

[0092] Referring to Figure 15 , a mask pattern (not shown) may be formed on the contact conductive layer 170L (see Figure 14 ), and a portion of the contact conductive layer 170L may be removed by using the mask pattern to form the contact layer 170, and the third insulating layer 186 may be formed in the region from which the contact conductive layer 170L has been removed.

[0093] In some example embodiments, the third insulating layer 186 may be formed of silicon nitride. However, the example embodiments are not limited thereto. In addition, sidewalls of the contact layer 170 may be surrounded by the third insulating layer 186, and a bottom surface of the contact layer 170 may cover a top surface of the channel layer 140 and a top surface of the gate insulating layer 150 to extend onto the mold layer 130.

[0094] Referring to Figure 16 , an etch stop layer 188 may be formed on the contact layer 170 and the third insulating layer 186. The etch stop layer 188 may include an opening 188H, and a top surface of the contact layer 170 may be exposed through the opening 188H.

[0095] Subsequently, a lower electrode 192, a capacitor dielectric layer 194, and an upper electrode 196 may be sequentially formed on the etch stop layer 188.

[0096] By performing the above manufacturing process, a semiconductor device 100 according to various example embodiments of the present inventive concept may be manufactured.

[0097] Referring to Figure 4 The semiconductor device 100A described may be manufactured by: setting a vertical level of a top surface of the intermediate insulating layer 142 to be substantially the same as a vertical level of a top surface of the initial channel layer 140L and setting a vertical level of a bottom surface of the intermediate insulating layer 142 to be higher than a vertical level of a top surface of a bottom of the initial channel layer 140L in Figure 9 .

[0098] Optionally, the semiconductor device 100B described with reference to Figure 5 may be manufactured by: setting a vertical level of a top surface of the intermediate insulating layer 142 to be lower than a vertical level of a top surface of the mold opening 130H and forming a bottom surface of the intermediate insulating layer 142 along a top surface of a bottom of the initial channel layer 140L in Figure 9 .

[0099] Figure 17is a structural diagram showing a system including a semiconductor device according to various example embodiments.

[0100] Referring Figure 17 , system 1000 includes a controller 1010, an input / output device 1020, a storage device 1030, an interface 1040, and a bus 1050.

[0101] System 1000 can be a mobile system or a system that transmits or receives information. In some example embodiments, the mobile system can be a portable computer, a network tablet, a mobile phone, a digital music player, or a memory card.

[0102] The controller 1010 is used to control the execution of programs in the system 1000 and can include a microprocessor, a digital signal processor, a microcontroller, or a similar device.

[0103] The input / output device 1020 can be used to input or output data of the system 1000. The system 1000 can use the input / output device 1020 to connect to an external device, such as a personal computer or a network, and can exchange data with the external device. The input / output device 1020 can be, for example, a touch screen, a touch pad, a keyboard, or a display.

[0104] The storage device 1030 can store data for the operation of the controller 1010 or store data processed by the controller 1010. The storage device 1030 can include any one of the semiconductor devices 100, 100A, and 100B according to various example embodiments of the present inventive concept described above.

[0105] The interface 1040 can be a data transmission path between the system 1000 and an external device. The controller 1010, the input / output device 1020, the storage device 1030, and the interface 1040 can communicate with each other via the bus 1050.

[0106] One or more of the elements disclosed above can include or be implemented in the following: a processing circuit, such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit can more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0107] When the terms "about" or "substantially" are used in combination with a numerical value in this specification, it is intended that the associated numerical value include manufacturing or operational tolerances (e.g., ±10%) near the stated numerical value. Further, when the words "generally" and "substantially" are used in combination with a geometric shape, it is intended that precision of the geometric shape is not required, but rather that the shape is within a free range within the scope of the present disclosure. Further, whether a numerical value or a shape is modified by "about" or "substantially", it will be understood that these values and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near the stated numerical value or shape. When a range is specified, the range includes all values therebetween, such as increments of 0.1%.

[0108] A statement such as "at least one of...", when following a list of elements, modifies the entire list of elements, rather than individual elements in the list. For example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C") can be interpreted to mean only A, only B, only C, or any combination of two or more of A, B, and C (such as, for example, ABC, AB, BC, and AC).

[0109] It should be understood that the various example embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. Descriptions of features or aspects within each embodiment are generally to be considered available for other similar features or aspects in other example embodiments; example embodiments are not necessarily mutually exclusive. Although one or more example embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

[0110] Although various example embodiments of the inventive concept have been specifically shown and described with reference thereto, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims. Accordingly, example embodiments should be considered only in a descriptive sense and not for purposes of limitation.

[0111] This application is based on and claims priority to Korean Patent Application No. 10-2023-0187515, filed with the Korean Intellectual Property Office on December 20, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A bit line extending in a first horizontal direction on the substrate; a channel layer on the bit line and penetrating into a portion of the bit line, comprising an oxide semiconductor material including indium, the channel layer having an inner wall and an outer wall; a gate insulating layer, on one side of the inner wall of the channel layer, the gate insulating layer having an inner wall and an outer wall; an intermediate insulating layer, between the inner wall of the channel layer and the outer wall of the gate insulating layer and comprising an insulating material different from an insulating material of the gate insulating layer; a word line extending on the inner wall of the gate insulating layer and in a second horizontal direction intersecting the first horizontal direction; as well as a contact layer on a top surface of the channel layer and a top surface of the gate insulating layer, The intermediate insulating layer is formed only on a portion of the outer wall of the gate insulating layer.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor material comprises InGaZnO x and InZnO x At least one of The gate insulating layer includes a high-k dielectric material, and The intermediate insulating layer includes at least one of silicon oxide and silicon oxynitride.

3. The semiconductor device according to claim 1 , wherein a vertical level of an uppermost surface of the intermediate insulating layer is lower than a vertical level of a lowermost surface of the contact layer, and A vertical level of a lowermost surface of the intermediate insulating layer is higher than a vertical level of a lowermost surface of the inner wall of the channel layer. 4 . The semiconductor device according to claim 3 , wherein a length of the intermediate insulating layer in a vertical direction is equal to a length of the word line in the vertical direction.

5. The semiconductor device according to claim 1, wherein the uppermost surface of the intermediate insulating layer contacts the lowermost surface of the contact layer, and A vertical level of a lowermost surface of the intermediate insulating layer is higher than a vertical level of a lowermost surface of the inner wall of the channel layer. 6 . The semiconductor device according to claim 5 , wherein a length of the intermediate insulating layer in a vertical direction is greater than a length of the word line in the vertical direction.

7. The semiconductor device according to claim 1, wherein a vertical level of an uppermost surface of the intermediate insulating layer is lower than a vertical level of a lowermost surface of the contact layer, and A lowermost surface of the intermediate insulating layer contacts a lowermost surface of the inner wall of the channel layer. 8 . The semiconductor device according to claim 7 , wherein the intermediate insulating layer faces both one sidewall and a lower surface of the word line.

9. The semiconductor device according to claim 1, wherein the bit line comprises a lower conductive barrier layer, a conductive layer, and an upper conductive barrier layer arranged in sequence, and The outer wall of the channel layer contacts the sidewall of the upper conductive barrier layer and the conductive layer, but does not contact the lower conductive barrier layer. 10 . The semiconductor device according to claim 9 , wherein a portion of the outer wall of the channel layer in contact with the conductive layer has a rounded corner.

11. A semiconductor device comprising: A bit line extending in a first horizontal direction on the substrate; The channel layer has a U-shape and penetrates into a portion of the bit line, including InGaZnO x , and having an inner wall and an outer wall; a gate insulating layer, on one side of the inner wall of the channel layer, comprising a high-k dielectric material, the gate insulating layer having an inner wall and an outer wall; an intermediate insulating layer, between the inner wall of the channel layer and the outer wall of the gate insulating layer, the intermediate insulating layer comprising at least one of silicon oxide and silicon oxynitride; a word line extending on the inner wall of the gate insulating layer and in a second horizontal direction intersecting the first horizontal direction; as well as A contact layer is on a top surface of the channel layer and a top surface of the gate insulating layer.

12. The semiconductor device according to claim 11, wherein the intermediate insulating layer is formed only on a portion of the outer wall of the gate insulating layer, and The outer wall of the gate insulating layer includes a portion contacting the intermediate insulating layer and a remaining portion contacting the inner wall of the channel layer. 13 . The semiconductor device according to claim 12 , wherein a length of the intermediate insulating layer in a vertical direction is equal to a length of the word line in the vertical direction. 14 . The semiconductor device according to claim 12 , wherein a length of the intermediate insulating layer in a vertical direction is greater than a length of the word line in the vertical direction.

15. The semiconductor device according to claim 11, wherein the bit line includes a recessed area and a flat area surrounding the recessed area, The semiconductor device further includes a mold layer covering the planar region of the bit line, and The outer wall of the channel layer contacts a sidewall of the mold layer and the recessed region of the bit line.

16. A semiconductor device comprising: A bit line extending in a first horizontal direction on the substrate; A mold layer covering the bit line on the substrate, the mold layer having a mold opening; A channel layer having a bottom portion penetrating into the bit line and a sidewall portion extending in a vertical direction on the inner wall of the mold opening, the channel layer comprising InGaZnO x ; a gate insulating layer, within the mold opening and on the channel layer, the gate insulating layer comprising a high-k dielectric material; an intermediate insulating layer, within the mold opening and between the channel layer and the gate insulating layer, the intermediate insulating layer comprising at least one of silicon oxide and silicon oxynitride; a word line within the mold opening, on the gate insulating layer, and extending in a second horizontal direction intersecting the first horizontal direction; a contact layer on a top surface of the channel layer and a top surface of the gate insulating layer; as well as A capacitor structure, on the contact layer, The intermediate insulating layer is formed only in a portion between the channel layer and the gate insulating layer.

17. The semiconductor device according to claim 16, wherein a vertical level of an uppermost surface of the intermediate insulating layer is lower than a vertical level of an uppermost surface of the sidewall portion of the channel layer, and A vertical level of a lowermost surface of the intermediate insulating layer is higher than a vertical level of an uppermost surface of the bottom portion of the channel layer.

18. The semiconductor device according to claim 16, wherein a vertical level of an uppermost surface of the intermediate insulating layer is equal to a vertical level of an uppermost surface of the sidewall portion of the channel layer, and A vertical level of a lowermost surface of the intermediate insulating layer is higher than a vertical level of an uppermost surface of the bottom portion of the channel layer.

19. The semiconductor device according to claim 16, wherein a vertical level of an uppermost surface of the intermediate insulating layer is lower than a vertical level of an uppermost surface of the sidewall portion of the channel layer, and A vertical level of a lowermost surface of the intermediate insulating layer is equal to a vertical level of an uppermost surface of the bottom portion of the channel layer.

20. The semiconductor device according to claim 16, wherein the bit line includes a recessed region, and The bottom of the channel layer fills the recessed region of the bit line.

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