Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and the method comprises the steps: respectively forming a first anti-reflection layer laminated layer, a second anti-reflection layer laminated layer and a third anti-reflection layer laminated layer in a unit region, a middle transition region and a peripheral region, wherein the first anti-reflection layer laminated layer, the second anti-reflection layer laminated layer and the third anti-reflection layer laminated layer have different transverse sizes; side wall layers are formed on the side walls of the first anti-reflection layer stacking layer, the second anti-reflection layer stacking layer and the third anti-reflection layer stacking layer, and then the floating gate layer is etched by taking the side wall layers, the second anti-reflection layer stacking layer and the third anti-reflection layer stacking layer as masks to form a control gate, a first peripheral circuit and a second peripheral circuit with different key sizes; by optimizing the SADP process steps, the patterning operation of the unit region, the middle transition region and the peripheral circuit region in the substrate can be completed by only using one layer of mask, so that the production cost and the process complexity are reduced, and as only one layer of mask is used, the multi-step photoetching, alignment and etching steps are reduced, the process deviation is reduced, and the production efficiency is improved. And the production yield of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and particularly relates to a semiconductor structure and a preparation method thereof. Background Art

[0002] At present, flash memory, also known as flash storage, has become the mainstream of non-volatile memory (NVM). In the manufacturing process of non-volatile memory, as the semiconductor process node continues to shrink to below 40 nm, the traditional optical lithography technology is limited by the physical diffraction limit and can no longer directly achieve the precise transfer of high-density patterns. Therefore, the industry widely adopts the self-aligned double patterning (SADP) technology to decompose a single lithography pattern into a high-density double pattern through the deposition of spacer layers and etching processes, thereby breaking through the limitation of lithography resolution. However, the SADP process technology faces challenges in the manufacturing of non-volatile memory.

[0003] The cell area of non-volatile memory usually consists of a high-density memory cell array. To meet the storage density requirements, the feature size of the memory cells generally needs to be controlled below 40 nm, while the feature size of the peripheral circuit area is usually greater than 90 nm to ensure sufficient electrical performance and reliability. When using the traditional SADP process technology to prepare non-volatile memory, due to the large size difference between the cell area and the peripheral circuit area, two sets of independent lithography masks are required to define the patterns of the cell area and the peripheral circuit area respectively. However, the preparation cost of the masks is high, and multiple lithography, alignment, and etching steps will prolong the manufacturing cycle and introduce more process deviations (such as overlay errors). The dual-lithography mask strategy significantly increases the production cost and process complexity. In addition, the separation of the patterning processes for the cell area and the peripheral circuit area may also increase the integration difficulty of the interface region, thereby affecting the yield of the prepared semiconductor structure. Summary of the Invention

[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor structure and a preparation method thereof, which are used to solve the problems of increased production cost and process complexity caused by using two sets of masks due to the large size difference between the cell area and the peripheral circuit area when using the SADP process technology to prepare non-volatile memory, and the process deviations caused thereby.

[0005] To achieve the above purpose and other related purposes, the present invention provides a preparation method of a semiconductor structure, and the preparation method includes the following steps:

[0006] Provide a substrate, which includes a cell region, an intermediate transition region, and a peripheral region. A floating gate layer, a blocking layer, an etch stop structure, a first anti-reflection layer, and a second anti-reflection layer are sequentially formed on the substrate;

[0007] Form a patterned first photoresist layer on the second anti-reflection layer. Etch the first anti-reflection layer and the second anti-reflection layer based on the first photoresist layer to form a first anti-reflection layer stack, a second anti-reflection layer stack, and a third anti-reflection layer stack in the cell region, the intermediate transition region, and the peripheral region respectively. Then remove the first photoresist layer;

[0008] Continue to etch part of the etch stop structure based on the first anti-reflection layer stack, the second anti-reflection layer stack, and the third anti-reflection layer stack to form a first stack, a second stack, and a third stack in the cell region, the intermediate transition region, and the peripheral region respectively. The lateral dimensions of the first stack, the second stack, and the third stack increase in sequence. Then remove the second anti-reflection layer and retain a certain thickness of the first anti-reflection layer;

[0009] Form a sidewall layer on the sidewalls of the first stack, the second stack, and the third stack. The top of the sidewall layer is higher than the top of the first anti-reflection layer and covers the first anti-reflection layer in the intermediate transition region and the peripheral region;

[0010] Use the sidewall layer, the second stack, and the third stack in the cell region as masks to etch the floating gate layer, the blocking layer, and the remaining etch stop structure to form a control gate in the cell region, a first peripheral circuit in the intermediate transition region, and a second peripheral circuit in the peripheral region.

[0011] Optionally, the lateral dimension of the first stack is 16 - 32 nm, the lateral dimension of the second stack is 90 - 180 nm, and the lateral dimension of the third stack is at least 0.6 μm.

[0012] Optionally, the etch stop structure includes, from bottom to top, a stacked first etch stop layer, a first hard mask layer, a second etch stop layer, and a second hard mask layer, where the first etch stop layer and the second etch stop layer have different etch selectivity ratios.

[0013] Optionally, the thickness of the first etch stop layer is greater than the thickness of the second etch stop layer, and the thickness of the second etch stop layer is

[0014] Optionally, the method for forming the dielectric layer includes a chemical vapor deposition process or an atomic layer deposition process.

[0015] Optionally, when etching the floating gate layer, the blocking layer, and the remaining etching stop structure, the etching distance of the unit region is greater than that of the intermediate transition region and the peripheral region.

[0016] Optionally, the critical dimension of the control gate located in the unit region is The critical dimension of the first peripheral circuit located in the intermediate transition region is The critical dimension of the second peripheral circuit in the peripheral region is

[0017] Optionally, the step of forming the sidewall layer includes: forming a dielectric layer on the sidewalls and the top of the first stack, the second stack, and the third stack, removing the dielectric layer on the top of the first anti-reflection layer, the dielectric layer on the etching stop structure, and the first anti-reflection layer in the unit region, and using the remaining dielectric layer on the sidewalls of the first stack, the second stack, and the third stack as the sidewall layer.

[0018] Optionally, an anisotropic etching process is used to remove the dielectric layer on the top of the first anti-reflection layer, the dielectric layer on the etching stop structure, and the first anti-reflection layer in the unit region.

[0019] The present invention also provides a semiconductor structure obtained by the preparation method of the semiconductor structure described above.

[0020] As described above, the semiconductor structure and its preparation method of the present invention have the following beneficial effects: By forming a first anti-reflection layer stack, a second anti-reflection layer stack, and a third anti-reflection layer stack with different lateral dimensions in the unit region, the intermediate transition region, and the peripheral region respectively, and forming a sidewall layer on the sidewalls of the first anti-reflection layer stack, the second anti-reflection layer stack, and the third anti-reflection layer stack, and then etching the floating gate layer using the sidewall layer, the second anti-reflection layer stack, and the third anti-reflection layer stack as masks to form a first control gate, a first peripheral circuit, and a second peripheral circuit with different critical dimensions. Through the optimization of the SADP process steps, the patterning operation of the unit region, the intermediate transition region, and the peripheral circuit region in the substrate can be completed using only one mask, thereby reducing the production cost and process complexity. And since only one mask is used, multiple photolithography, alignment, and etching steps are reduced, thus reducing process deviations and being beneficial to improving the production yield of the semiconductor structure. Description of the Drawings

[0021] Figure 1 It shows a schematic flow chart of the preparation method of the semiconductor structure of the present invention.

[0022] Figures 2 to 11 It shows schematic structural diagrams corresponding to each step in the preparation method of the semiconductor structure of the embodiment of the present invention.

[0023] Description of Component Labels

[0024] 10. Substrate; 11. Floating gate layer; 12. Insulating layer; 13. Barrier layer; 14. Etch stop structure; 141. First etch stop layer; 142. First hard mask layer; 143. Second etch stop layer; 144. Second hard mask layer; 151. First anti-reflection layer; 152. Second anti-reflection layer; 16. First photoresist layer; 171. First anti-reflection layer stack; 172. Second anti-reflection layer stack; 173. Third anti-reflection layer stack; 181. First stack; 182. Second stack; 183. Third stack; 191. Dielectric layer; 192. Sidewall layer; 201. Control gate; 202. First peripheral circuit; 203. Second peripheral circuit; S1 to S5: Steps. Detailed Implementation Modes

[0025] The following uses specific specific examples to illustrate the implementation modes of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] When detailing the embodiments of the present invention, for ease of explanation, the schematic diagrams showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0027] For the convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" etc. may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to encompass other directions of the device in use or operation, in addition to the directions depicted in the drawings.

[0028] In the context of this application, the structure where the first feature is "above" the second feature described may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0029] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0030] As Figure 1 shown, this embodiment provides a method for fabricating a semiconductor structure, and the fabrication method includes the following steps:

[0031] S1: Provide a substrate 10, the substrate 10 includes a unit region, an intermediate transition region, and a peripheral region. A floating gate layer 11, a blocking layer 13, an etch stop structure 14, a first anti-reflection layer 151, and a second anti-reflection layer 152 are sequentially formed on the substrate 10;

[0032] S2: Form a patterned first photoresist layer 16 on the second anti-reflection layer 152. Etch the first anti-reflection layer 151 and the second anti-reflection layer 152 based on the first photoresist layer 16 to form a first anti-reflection layer stack 171, a second anti-reflection layer stack 172, and a third anti-reflection layer stack 173 in the unit region, the intermediate transition region, and the peripheral region respectively. Then remove the first photoresist layer 16;

[0033] S3: Continue to etch part of the etch stop structure 14 based on the first anti-reflection layer stack 171, the second anti-reflection layer stack 172, and the third anti-reflection layer stack 173 to form a first stack 181, a second stack 182, and a third stack 183 in the unit region, the intermediate transition region, and the peripheral region respectively. The lateral dimensions of the first stack 181, the second stack 182, and the third stack 183 increase in sequence. Then remove the second anti-reflection layer 152 and retain a certain thickness of the first anti-reflection layer 151;

[0034] S4: Form a sidewall layer 192 on the sidewalls of the first stack 181, the second stack 182, and the third stack 183. The top of the sidewall layer 192 is higher than the top of the first anti-reflection layer 151 and covers the first anti-reflection layer 151 in the intermediate transition region and the peripheral region;

[0035] S5: Use the sidewall layer 192 in the unit region, the second stack 182, and the third stack 183 as masks to etch the floating gate layer 11, the blocking layer 13, and the remaining etch stop structure 14 to form a control gate 201 in the unit region, a first peripheral circuit 202 in the intermediate transition region, and a second peripheral circuit 203 in the peripheral region.

[0036] It should be noted that the above order does not strictly represent the order of the preparation method of the semiconductor structure protected by the present invention. Those skilled in the art can make changes according to the actual preparation steps. The following further introduces the preparation method of the semiconductor structure with reference to the accompanying drawings, specifically as follows:

[0037] In step S1, please refer to Figure 1 , Figure 2 and Figure 3 , a substrate 10 is provided. The substrate 10 includes a cell region, an intermediate transition region, and a peripheral region. A floating gate layer 11, a blocking layer 13, an etch stop structure 14, a first anti-reflection layer 151, and a second anti-reflection layer 152 are sequentially formed on the substrate 10.

[0038] In this embodiment, as Figure 2 shown, the substrate 10 is a common silicon substrate 10. The substrate 10 includes a cell region, an intermediate transition region, and a peripheral region. The substrate 10 provides a process platform for the subsequent formation of flash memories. In other embodiments, the material of the substrate 10 can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, etc. The substrate 10 can also be other types of substrates 10 such as a silicon-on-insulator substrate 10 or a germanium-on-insulator substrate 10.

[0039] In this embodiment, as Figure 3 shown, a deposition process can be used, such as physical vapor deposition process, chemical vapor deposition process, atomic layer deposition process, or plasma-enhanced chemical vapor deposition process, etc., to sequentially form a floating gate layer 11, a blocking layer 13, an etch stop structure 14, a first anti-reflection layer 151, and a second anti-reflection layer 152 above the substrate 10. The floating gate layer 11 prepares for the subsequent formation of the floating gate level. Specifically, the material of the floating gate layer 11 can include polysilicon. The blocking layer 13 can prevent the diffusion of the floating gate layer 11. An insulating layer 12 can also be formed between the blocking layer 13 and the floating gate layer 11 to further improve the anti-diffusion effect. Specifically, the materials of the blocking layer 13 and the insulating layer 12 include silicon oxide. In addition, an etch stop structure 14 is formed between the blocking layer 13 and the first anti-reflection layer 151. Specifically, the etch stop structure 14 includes a stacked first etch stop layer 141, a first hard mask layer 142, a second etch stop layer 143, and a second hard mask layer 144 from bottom to top. Among them, the first etch stop layer 141 and the second etch stop layer 143 have different etch selectivity ratios, so that in the subsequent process of forming the control gate 201 and the peripheral circuit mask, the etch stop structure 14 can protect the control gate 201, the blocking layer 13, and the floating gate layer 11 from damage.

[0040] As an example, the thickness of the first etch stop layer 141 is greater than the thickness of the second etch stop layer 143, and the thickness of the second etch stop layer 143 is For example: the thickness of the second etch stop layer 143 is or Details are not described one by one herein.

[0041] As an example, the materials of the first hard mask layer 142 and the second hard mask layer 144 include one or more of silicon nitride, DRAC material, BARC material, and APF material. Specifically, in this embodiment, the materials of the first etch stop layer 141 and the second etch stop layer 143 include plasma enhanced oxide (PEOX); the materials of the first hard mask layer 142 and the second hard mask layer 144 include APF (Advanced Patterning Film).

[0042] A first anti-reflection layer 151 and a second anti-reflection layer 152 are further formed on the etch stop structure 14, and the first anti-reflection layer 151 and the second anti-reflection layer 152 are prepared for forming an anti-reflection layer stack subsequently. Specifically, the materials of the first anti-reflection layer 151 and the second anti-reflection layer 152 may include bottom anti-reflective coatings (BARC), silicon nitride, or silicon oxynitride. The first anti-reflection layer 151 and the second anti-reflection layer 152 can absorb the light passing through the photoresist layer during the subsequent patterning process of the etch stop structure 14, reduce the influence of the standing wave effect. After forming the first anti-reflection layer 151 and the second anti-reflection layer 152, a planarization process needs to be performed to make the formed second anti-reflection layer 152 have a relatively flat surface. The planarization can be achieved by chemical mechanical polishing process.

[0043] In step S2, please refer to Figure 1 、 Figure 4 and Figure 5 , a patterned first photoresist layer 16 is formed on the second anti-reflection layer 152, and the first anti-reflection layer 151 and the second anti-reflection layer 152 are etched based on the first photoresist layer 16, and a first anti-reflection layer stack 171, a second anti-reflection layer stack 172, and a third anti-reflection layer stack 173 are respectively formed in the cell region, the intermediate transition region, and the peripheral region, and then the first photoresist layer 16 is removed.

[0044] In this embodiment, as Figure 4As shown, a first photoresist layer 16 is formed on the second anti-reflection layer 152, and the first photoresist layer 16 is exposed and developed to form a patterned first photoresist layer 16. Among them, the width of the patterned first photoresist layer 16 determines the widths of the subsequently formed first anti-reflection layer stack 171, second anti-reflection layer stack 172, and third anti-reflection layer stack 173.

[0045] As Figure 5 shown, using the patterned first photoresist layer 16 as a mask, the first anti-reflection layer 151 and the second anti-reflection layer 152 are synchronously etched. Etching the two layers of the first anti-reflection layer 151 and the second anti-reflection layer 152 simultaneously in one step is beneficial to ensuring the stability of the process, thereby transferring the pattern on the first photoresist layer 16 to the first anti-reflection layer 151 and the second anti-reflection layer 152. Above the etching stop structure 14, first anti-reflection layer stacks 171, second anti-reflection layer stacks 172, and third anti-reflection layer stacks 173 with different lateral widths are respectively formed in the cell region, the intermediate transition region, and the peripheral region. Among them, the first anti-reflection layer stacks 171, the second anti-reflection layer stacks 172, and the third anti-reflection layer stacks 173 are arranged in parallel, and the lateral dimensions between each of the first anti-reflection layer stacks 171 in the cell region can be the same or different, and can be set according to actual needs. Preferably, in this embodiment, each of the first anti-reflection layer stacks 171 in the cell region is set to have the same lateral dimension.

[0046] The patterned first photoresist layer 16 can be removed by ashing.

[0047] In step S3, please refer to Figure 1 and Figure 6 , based on the first anti-reflection layer stack 171, the second anti-reflection layer stack 172, and the third anti-reflection layer stack 173, part of the etching stop structure 14 is continuously etched to respectively form a first stack 181, a second stack 182, and a third stack 183 in the cell region, the intermediate transition region, and the peripheral region. The lateral dimensions of the first stack 181, the second stack 182, and the third stack 183 increase in sequence. Then, the second anti-reflection layer 152 is removed, and a certain thickness of the first anti-reflection layer 151 is retained.

[0048] In this embodiment, as Figure 6As shown, using the first antireflection stack 171, the second antireflection stack 172, and the third antireflection stack 173 as masks, the widths of the first antireflection stack 171, the second antireflection stack 172, and the third antireflection stack 173 determine the widths of the subsequently formed first antireflection stack 171, second antireflection stack 172, and third antireflection stack 173. The dry etching process is continued to etch the second hard mask layer 144 in the etch stop structure 14. The dry etching process has anisotropic etching characteristics and good etching profile controllability, which is beneficial for the morphologies of the first stack 181, the second stack 182, and the third stack 183 to better meet the process requirements. Finally, the end point of the etching stops in the second etch stop layer 143, reducing the damage to other film layer structures, so as to form the first stack 181, the second stack 182, and the third stack 183 in the cell region, the intermediate transition region, and the peripheral region. Among them, the first stack 181, the second stack 182, and the third stack 183 have different lateral dimensions and the lateral dimensions increase in sequence. Specifically, the lateral dimension of the first stack 181 is 16 - 32 nm, the lateral dimension of the second stack 182 is 90 - 180 nm, and the lateral dimension of the third stack 183 is at least 0.6 μm.

[0049] It should be noted that after the first stack 181, the second stack 182, and the third stack 183 are formed, the second antireflection layer 152 and part of the first antireflection layer 151 need to be removed, and a part of the first antireflection layer 151 is reserved above the first stack 181, the second stack 182, and the third stack 183, so as to reduce the damage to other film layers in the subsequent etching process.

[0050] In step S4, please refer to Figure 1 、 Figures 7 to 9 , a spacer layer 192 is formed on the sidewalls of the first stack 181, the second stack 182, and the third stack 183. The top of the spacer layer 192 is higher than the top of the first antireflection layer 151 and covers the first antireflection layer 151 in the intermediate transition region and the peripheral region.

[0051] As an example, the step of forming the spacer layer 192 covering the sidewalls of the first stack 181, the second stack 182, and the third stack 183 includes: first forming a dielectric layer 191 on the sidewalls and the top of the first stack 181, the second stack 182, and the third stack 183, removing the dielectric layer 191 on the top of the first antireflection layer 151, the dielectric layer 191 on the etch stop structure 14, and the first antireflection layer 151 in the cell region, and the remaining dielectric layer 191 on the sidewalls of the first stack 181, the second stack 182, and the third stack 183 serves as the spacer layer 192.

[0052] As Figure 7 shown, a deposition process, such as chemical vapor deposition or atomic layer deposition, can be used to form a dielectric layer 191 on the sidewalls and top of the first stack 181, the second stack 182, and the third stack 183. The material of the dielectric layer 191 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride. Specifically, in this embodiment, the material of the dielectric layer 191 is silicon oxide, which can be formed by atomic layer deposition.

[0053] As Figure 8 shown, the dielectric layer 191 on the top of the first anti-reflection layer 151, the dielectric layer 191 on the etch stop structure 14, and the first anti-reflection layer 151 in the cell region are removed. The remaining dielectric layer 191 on the sidewalls of the first stack 181, the second stack 182, and the third stack 183 serves as the sidewall layer 192. Specifically, a photoresist mask layer is first formed on the dielectric layer 191, and the photoresist mask layer is exposed and developed to form a patterned photoresist mask layer. In this process, the photoresist mask layer on the tops of the first stack 181, the second stack 182, and the third stack 183 is completely removed, and the dielectric layer 191 on the tops of the first stack 181, the second stack 182, and the third stack 183 is etched away, so that a part of the dielectric layer 191 is retained on the sidewalls of the first stack 181, the second stack 182, and the third stack 183 as the sidewall layer 192. Specifically, a reactive ion etching process using an etching gas including a fluorine-containing gas can be used to etch the dielectric layer 191, and then the first anti-reflection layer 151, the second hard mask layer 144, and the second etch stop layer 143 in the first stack 181 are continuously etched. Finally, the patterned photoresist mask layer is removed by ashing to form a semiconductor structure as Figure 9 shown.

[0054] In step S5, please refer to Figure 1 、 Figure 10 and Figure 11 , using the sidewall layer 192 in the cell region, the second stack 182, and the third stack 183 as masks to etch the floating gate layer 11, the blocking layer 13, and the remaining etch stop structure 14, forming a control gate 201 in the cell region and a first peripheral circuit 202 in the intermediate transition region and a second peripheral circuit 203 in the peripheral region.

[0055] In this embodiment, as Figure 10As shown, using the sidewall layer 192, the second stack 182, the third stack 183, and the sidewall layer 192 in the cell region as masks, the remaining etch stop structure 14, the floating gate layer 11, and the blocking layer 13 are continuously etched using a dry etching process. The dry etching process has anisotropic etching characteristics and good etching profile controllability, which is beneficial to making the morphologies of the formed control gate 201, the first peripheral circuit 202, and the second peripheral circuit 203 meet the process requirements. During the dry etching process, the top of the substrate 10 can be used as the etch stop position, reducing damage to other film layer structures. Moreover, by replacing the etching gas, the floating gate layer 11 and the blocking layer 13 can be etched in the same etching equipment, thus simplifying the process steps. As Figure 11 shown, after forming the control gate 201 in the cell region, the first peripheral circuit 202 in the intermediate transition region, and the second peripheral circuit 203 in the peripheral region, it is also necessary to remove the etch stop structure 14.

[0056] As an example, when etching the floating gate layer 11, the blocking layer 13, and the remaining etch stop structure 14, the etching distance for the cell region is greater than the etching distances for the intermediate transition region and the peripheral region.

[0057] Specifically, as Figure 11 shown, the etching distance for the cell region is greater than the etching distances for the intermediate transition region and the peripheral region, so that the control gate 201 in the cell region, the first peripheral circuit 202 in the intermediate transition region, and the second peripheral circuit 203 in the peripheral region have different heights, that is, the critical dimension of the control gate 201 located in the cell region is The critical dimension of the first peripheral circuit 202 located in the intermediate transition region is The critical dimension of the second peripheral circuit 203 in the peripheral region is so that the control gate 201, the first peripheral circuit 202, and the second peripheral circuit 203 have different operating voltages.

[0058] A method for manufacturing a semiconductor structure proposed in this embodiment forms first anti-reflection layer stacks 171, second anti-reflection layer stacks 172, and third anti-reflection layer stacks 173 with different lateral dimensions in a cell region, an intermediate transition region, and a peripheral region respectively. And a spacer layer 192 is formed on the sidewalls of the first anti-reflection layer stacks 171, the second anti-reflection layer stacks 172, and the third anti-reflection layer stacks 173. Then, using the spacer layer 192, the second anti-reflection layer stacks 172, and the third anti-reflection layer stacks 173 as masks, the floating gate layer 11 is etched to form a control gate 201, a first peripheral circuit 202, and a second peripheral circuit 203 with different critical dimensions. By optimizing the process steps of SADP, the patterning operation of the cell region, the intermediate transition region, and the peripheral circuit region in the substrate 10 can be completed using only one mask, thereby reducing the production cost and process complexity. And since only one mask is used, multiple photolithography, alignment, and etching steps are reduced, thus reducing process deviations and being beneficial to improving the production yield of the semiconductor structure.

[0059] In another embodiment of the present invention, a semiconductor structure is further proposed, and the semiconductor structure is obtained by using the manufacturing method of any one of the above-mentioned semiconductor structures.

[0060] In summary, for the semiconductor structure and its manufacturing method proposed in the present invention, first anti-reflection layer stacks, second anti-reflection layer stacks, and third anti-reflection layer stacks with different lateral dimensions are formed in a cell region, an intermediate transition region, and a peripheral region respectively. And a spacer layer is formed on the sidewalls of the first anti-reflection layer stacks, the second anti-reflection layer stacks, and the third anti-reflection layer stacks. Then, using the spacer layer, the second anti-reflection layer stacks, and the third anti-reflection layer stacks as masks, the floating gate layer is etched to form a control gate, a first peripheral circuit, and a second peripheral circuit with different critical dimensions. By optimizing the process steps of SADP, the patterning operation of the cell region, the intermediate transition region, and the peripheral circuit region in the substrate can be completed using only one mask, thereby reducing the production cost and process complexity. And since only one mask is used, multiple photolithography, alignment, and etching steps are reduced, thus reducing process deviations and being beneficial to improving the production yield of the semiconductor structure. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0061] The above embodiments merely illustrate the principles and effects of the present invention and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises the following steps: Providing a substrate, the substrate comprising a cell region, an intermediate transition region and a peripheral region, and sequentially forming a floating gate layer, a barrier layer, an etch stop structure, a first anti-reflection layer and a second anti-reflection layer on the substrate; forming a patterned first photoresist layer on the second anti-reflection layer, etching the first anti-reflection layer and the second anti-reflection layer based on the first photoresist layer, forming a first anti-reflection layer stack, a second anti-reflection layer stack and a third anti-reflection layer stack in the cell area, the intermediate transition area and the peripheral area respectively, and then removing the first photoresist layer; Continue etching part of the etching stop structure based on the first anti-reflection layer stack, the second anti-reflection layer stack and the third anti-reflection layer stack, and form a first stack, a second stack and a third stack in the unit area, the middle transition area and the peripheral area respectively, the lateral sizes of the first stack, the second stack and the third stack are increased in sequence, and then remove the second anti-reflection layer, and retain a certain thickness of the first anti-reflection layer; Forming a sidewall layer on the sidewalls of the first stack, the second stack and the third stack, wherein the top of the sidewall layer is higher than the top of the first anti-reflection layer and covers the first anti-reflection layer in the intermediate transition area and the peripheral area; The floating gate layer, the barrier layer and the remaining etching stop structure are etched using the sidewall layer, the second stack and the third stack in the cell area as masks to form a control gate located in the cell area, a first peripheral circuit located in the intermediate transition area and a second peripheral circuit in the peripheral area.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The lateral dimension of the first stack is 16-32 nm, the lateral dimension of the second stack is 90-180 nm, and the lateral dimension of the third stack is at least 0.6 μm.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The etch stop structure includes, from bottom to top, a stacked first etch stop layer, a first hard mask layer, a second etch stop layer, and a second hard mask layer, wherein the first etch stop layer and the second etch stop layer have different etch selectivities.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The thickness of the first etch stop layer is greater than the thickness of the second etch stop layer, and the thickness of the second etch stop layer is 5. The method for preparing a semiconductor structure according to claim 1, wherein: The method of forming the dielectric layer includes a chemical vapor deposition process or an atomic layer deposition process.

6. The method for preparing a semiconductor structure according to claim 1, wherein: When etching the floating gate layer, the barrier layer and the remaining etching stop structure, the etching distance of the cell region is greater than the etching distance of the intermediate transition region and the peripheral region.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The critical dimension of the control gate located in the cell region is The critical dimension of the first peripheral circuit located in the intermediate transition region is The critical dimension of the second peripheral circuit in the peripheral area is 8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of forming the sidewall layer includes: forming a dielectric layer on the sidewalls and top of the first stack, the second stack and the third stack before, removing the dielectric layer on the top of the first anti-reflection layer, the dielectric layer on the etch stop structure and the first anti-reflection layer in the unit area, and the remaining dielectric layer on the sidewalls of the first stack, the second stack and the third stack is used as a sidewall layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: An anisotropic etching process is used to remove the dielectric layer on the top of the first anti-reflection layer, the dielectric layer on the etch stop structure, and the first anti-reflection layer in the cell area.

10. A semiconductor structure, characterized in that: The semiconductor structure is obtained by the method for preparing a semiconductor structure according to any one of claims 1 to 9.

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