Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a memory system and a manufacturing method of the semiconductor device. The semiconductor device includes: a first peripheral circuit structure; a second peripheral circuit structure; the first storage structure comprises a plurality of first storage units arranged in the first direction and the second direction; wherein the first peripheral circuit structure and the second peripheral circuit structure are located on the two sides of the first storage structure in the third direction and connected with the first storage structure, and the first direction, the second direction and the third direction intersect with one another.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a memory system, and a method for manufacturing a semiconductor device. Background Art

[0002] In recent years, as the difficulty of breaking through semiconductor manufacturing processes has gradually increased, Moore's Law has gradually reached its bottleneck, and people expect to seek other ways to improve the integration of semiconductor devices. Summary of the Invention

[0003] The present application provides a semiconductor device, a memory system, and a method for manufacturing a semiconductor device that can at least partially solve the above problems or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: a first peripheral circuit structure; a second peripheral circuit structure; and a first memory structure including a plurality of first memory cells arranged along a first direction and a second direction; wherein, the first peripheral circuit structure and the second peripheral circuit structure are located on both sides of the first memory structure in a third direction and are connected to the first memory structure, and the first direction, the second direction, and the third direction intersect each other.

[0005] In an exemplary embodiment, the first memory cell includes a first transistor, a plurality of capacitors, and a second transistor arranged along the third direction.

[0006] In an exemplary embodiment, the first poles of each of the plurality of capacitors are connected to each other, one of the source or drain of the first transistor is connected to the first pole, and the gate of the second transistor is connected to the first pole.

[0007] In an exemplary embodiment, the capacitor is a ferroelectric capacitor.

[0008] In an exemplary embodiment, the first peripheral circuit structure includes a first substrate and a first peripheral circuit, and the first peripheral circuit is located between the first memory structure and the first substrate; and the second peripheral circuit structure includes a second substrate and a second peripheral circuit, and the second peripheral circuit is located between the first memory structure and the second substrate.

[0009] In an exemplary embodiment, the semiconductor device further includes: a wiring layer located on the side of the first substrate and / or the second substrate away from the first memory structure respectively and including a pad structure therein.

[0010] In an exemplary embodiment, the first peripheral circuit structure includes a first substrate and a first peripheral circuit, and the first peripheral circuit is located between the first storage structure and the first substrate; the second peripheral circuit structure includes a second substrate and a first circuit portion and a second circuit portion of the second peripheral circuit respectively located on two sides of the second substrate in a third direction; the semiconductor device further includes: at least one second storage structure, located on a side of the second peripheral circuit structure away from the first storage structure in the third direction and connected to the second peripheral circuit structure.

[0011] In an exemplary embodiment, the second storage structure includes a plurality of second storage units, and the second storage units include at least one of a NAND storage unit, a DRAM storage unit, and a ferroelectric storage unit.

[0012] In an exemplary embodiment, the second storage unit is a NAND storage unit, the second peripheral circuit includes a sense amplifier, and the first storage unit and the second storage unit share the sense amplifier.

[0013] In an exemplary embodiment, the semiconductor device further includes: a third peripheral circuit structure, located on a side of at least one second storage structure away from the second peripheral circuit structure in the third direction and connected to at least one second storage structure.

[0014] In an exemplary embodiment, the third peripheral circuit structure includes a third substrate and a third peripheral circuit, and the third peripheral circuit is located between the third substrate and at least one second storage structure; wherein, the semiconductor device further includes: a wiring layer, located on a side of the first substrate and / or the third substrate away from the second peripheral circuit structure respectively and including a pad structure located therein.

[0015] In a second aspect, some embodiments of the present application provide a memory system. The memory system includes: a memory including a semiconductor device as mentioned in any of the above embodiments; and a controller coupled to the memory for controlling the memory to store data.

[0016] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The manufacturing method includes: forming a first storage structure, the first storage structure including a plurality of first storage units arranged along a first direction and a second direction; connecting the first peripheral circuit structure to one side of the first storage structure in a third direction; and connecting the second peripheral circuit structure to the other side of the first storage structure in the third direction; wherein, the first direction, the second direction, and the third direction intersect with each other.

[0017] In an exemplary embodiment, the first storage unit includes a first transistor, a plurality of capacitors, and a second transistor arranged along a third direction. Wherein, forming the first storage structure includes: sequentially forming a plurality of capacitors and the first transistor on one side of a sacrificial substrate; removing the sacrificial substrate; and forming the second transistor on a side of the plurality of capacitors away from the first transistor; wherein, after forming the second transistor, connecting a first peripheral circuit structure to one side of the first storage structure in the third direction.

[0018] In an exemplary embodiment, after sequentially forming a plurality of capacitors and the first transistor on one side of a sacrificial substrate, the manufacturing method further includes: connecting a first carrier structure to a side of the first transistor away from the plurality of capacitors in the third direction; and after forming the second transistor, connecting a first peripheral circuit structure to one side of the first storage structure in the third direction includes: connecting the first peripheral circuit structure to a side of the first storage structure close to the second transistor; wherein, the manufacturing method further includes: removing the first carrier structure.

[0019] In an exemplary embodiment, the first storage unit includes a first transistor, a plurality of capacitors, and a second transistor arranged along a third direction. Wherein, forming the first storage structure includes: sequentially forming a plurality of capacitors and the first transistor on one side of a sacrificial substrate; and forming the second transistor on a side of the plurality of capacitors away from the first transistor; wherein, after sequentially forming a plurality of capacitors and the first transistor on one side of the sacrificial substrate, and before forming the second transistor on a side of the plurality of capacitors away from the first transistor, connecting a first peripheral circuit structure to one side of the first storage structure in the third direction includes: connecting the first peripheral circuit structure to a side of the first storage structure close to the first transistor.

[0020] In an exemplary embodiment, the manufacturing method further includes: forming a first circuit portion of a second peripheral circuit on a first side of a second substrate; and forming a second circuit portion of the second peripheral circuit on a second side of the second substrate opposite to the first side to form a second peripheral circuit structure.

[0021] In an exemplary embodiment, after forming a first circuit portion of a second peripheral circuit on a first side of a second substrate, the manufacturing method further includes: connecting a second carrier structure to a side of the first circuit portion away from the second substrate in the third direction.

[0022] In an exemplary embodiment, after connecting the second peripheral circuit structure to the other side of the first storage structure in the third direction, the manufacturing method further includes: connecting at least one second storage structure to a side of the second peripheral circuit structure away from the first storage structure in the third direction. Description of the Drawings

[0023] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments read in conjunction with the accompanying drawings. Among them:

[0024] Figure 1A is a cross-sectional schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0025] Figure 1B is a circuit schematic diagram of a first memory cell in a semiconductor device provided by an embodiment of the present application;

[0026] Figure 1C is a cross-sectional schematic diagram of a semiconductor device provided by an embodiment of the present application that includes a first memory cell;

[0027] Figure 2 is a cross-sectional schematic diagram of a semiconductor device provided by another embodiment of the present application;

[0028] Figure 3 is a cross-sectional schematic diagram of a semiconductor device provided by yet another embodiment of the present application;

[0029] Figure 4 is a block diagram of a system having a memory system provided by an embodiment of the present application;

[0030] Figure 5 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0031] Figures 6A to 6G is a schematic diagram of a semiconductor device during the manufacturing process provided by an embodiment of the present application;

[0032] Figures 7A to 7D is a cross-sectional schematic diagram of a semiconductor device during the manufacturing process provided by another embodiment of the present application; and

[0033] Figures 8A to 8E is a cross-sectional schematic diagram of a semiconductor device during the manufacturing process provided by yet another embodiment of the present application. Detailed Description of Specific Embodiments

[0034] To better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to distinguish one feature from another, and do not represent any limitation on the features, especially do not represent any order. Therefore, without departing from the teachings of the present application, the first peripheral circuit structure discussed in the present application can also be referred to as the second peripheral circuit structure, and vice versa.

[0036] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used as terms indicating approximation, rather than terms indicating degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0037] It should also be understood that expressions such as "comprising", "including", "having", "containing", and / or "including having" are open-ended rather than closed-ended expressions in this specification, which means that the stated features, elements, and / or components exist, but do not exclude the existence of one or more other features, elements, components, and / or their combinations. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, rather than just individual elements in the list. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0038] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this application belongs. It should also be understood that unless there is a clear statement in the present application, words defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0039] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. In addition, unless clearly defined or in contradiction with the context, the specific steps included in the methods described in the present application do not have to be limited to the recorded order, but can be executed in any order or executed in parallel.

[0040] In addition, in the present application, when using "connected" or "coupled", it can mean that there is direct contact or indirect contact between the corresponding components, unless there are clear other limitations or can be deduced from the context.

[0041] The present application will be described in detail below with reference to the drawings and in conjunction with embodiments.

[0042] An embodiment of the present application provides a semiconductor device. Figure 1A It is a cross-sectional schematic diagram of the semiconductor device provided by the embodiment of the present application. It should be noted that hereinafter, the D1 direction, D2 direction, and D3 direction in each drawing show the spatial relationship of each component in the semiconductor device. For example, the D3 direction is Figure 1A the stacking direction of the first storage structure 111, the first peripheral circuit structure 113, and the second peripheral circuit structure 114 shown, and the D1 direction and D2 direction are two directions that intersect (for example, are perpendicular) to each other in a plane intersecting (for example, perpendicular) to the stacking direction. The same concept will be adopted throughout this application to describe the spatial relationship of each component in the semiconductor device.

[0043] As Figure 1A shown, the semiconductor device 100 includes a first storage structure 111, a first peripheral circuit structure 113, and a second peripheral circuit structure 114. The first storage structure 111 includes a plurality of first storage units 112 arranged along a first direction and a second direction. The first peripheral circuit structure 113 and the second peripheral circuit structure 114 are located on both sides of the first storage structure 111 in the D3 direction and are connected to the first storage structure 111. In other words, the first peripheral circuit structure 113, the first storage structure 111, and the second peripheral circuit structure 114 can be stacked vertically. In this embodiment, the first peripheral circuit structure 113 and the second peripheral circuit structure 114 are respectively located on both sides of the first storage structure 111 in the D3 direction and are both connected to the first storage structure 111, which can break through the limitations of the semiconductor manufacturing process and effectively improve the integration degree of the semiconductor device 100. In addition, it can also reduce the transmission path between the peripheral circuits in the first peripheral circuit structure 113 and the second peripheral circuit structure 114 and the first storage structure 111, which is beneficial to improving the transmission efficiency and reducing the resistance-capacitance delay (i.e., RC delay), and better adapting to the development trend of high bandwidth.

[0044] In some embodiments, between the first peripheral circuit structure 113 and the first memory structure 111, and / or between the second peripheral circuit structure 114 and the first memory structure 111, they can be connected through "bonding technology". The "bonding technology" referred to in this application may include, but is not limited to, hybrid bonding, anodic bonding, fusion bonding, adhesive bonding, eutectic bonding, and transfer bonding, etc. In one implementation, both the first memory structure 111 and the first peripheral circuit structure 113 and the second peripheral circuit structure 114 are connected by hybrid bonding. For example, at the bonding interface 115 between the first memory structure 111 and the second peripheral circuit structure 114, the bonding contacts (for example, bonding contact 116) and the surrounding dielectric structures located in the first memory structure 111 and the second peripheral circuit structure 114 are in direct contact respectively. For example, the material of the bonding contact 116 may include copper (Cu), and the material of the dielectric structure may include silicon dioxide (SiO2). In this embodiment, by bonding (for example, hybrid bonding) the first memory structure 111 to the first peripheral circuit structure 113 and the second peripheral circuit structure 114 respectively, compared with connecting by means of leads or through silicon vias (TSV), a shorter interconnection distance can be achieved, further improving the transmission efficiency and reducing the RC delay. In addition, compared with TSV, the bonding contact 116 can have a smaller contact area, enabling a higher interconnection density.

[0045] In some embodiments, the first peripheral circuit structure 113 may include a first substrate 1131 and a first peripheral circuit 1132. The second peripheral circuit structure 114 includes a second substrate 1141 and a second peripheral circuit 1142. For example, the first peripheral circuit 1132 may be located on one side of the first substrate 1131. The first peripheral circuit 1132 may include a plurality of peripheral devices formed on the first substrate 1131. For example, the peripheral devices may include any suitable semiconductor devices such as metal oxide semiconductor field effect transistors, fin field effect transistors, bipolar transistors, diodes, resistors, inductors, and capacitors. These peripheral devices can form digital, analog, and / or digital-analog hybrid circuit modules for implementing various functions through an interconnection structure (for example, interconnecting lines and via structures). For example, similar to the first peripheral circuit structure 113, the second peripheral circuit 1142 may be located on one side of the second substrate 1141, and the second peripheral circuit 1142 may include a circuit module composed of peripheral devices. In the semiconductor device 100, the first peripheral circuit 1132 is located between the first memory structure 111 and the first substrate 1131, and the second peripheral circuit 1142 is located between the first memory structure 111 and the second substrate 1141.

[0046] In some embodiments, the first peripheral circuit 1132 in the first peripheral circuit structure 113 and the second peripheral circuit 1142 in the second peripheral circuit structure 114 may jointly form a peripheral circuit for controlling data transmission (such as writing, reading, and erasing, etc.) of multiple first memory cells 112 in the first memory structure 111. For example, as described above, the peripheral circuit may include multiple circuit modules, and these circuit modules may include sense amplifiers, word line drivers, bit line drivers, row decoders, column decoders, I / O circuits, charge pumps, voltage sources or generators, current or voltage references, etc. Among them, the layout of some circuit modules will be described in detail below.

[0047] In some embodiments, in the first memory structure 111, multiple first memory cells 112 are arranged along the D1 direction and the D2 direction (for example, in an array arrangement). For example, the first memory cell 112 may include multiple capacitors and at least one transistor. Among them, the transistor can be used to access or select the data stored in the capacitor. For example, the first memory cell 112 may include multiple capacitors and one transistor, or the first memory cell 112 may include multiple capacitors and two transistors.

[0048] Figure 1B is a circuit schematic diagram of the first memory cell in the semiconductor device provided by the embodiments of the present application. As Figure 1B shown, the first memory cell 112 may include a first transistor T1 arranged along the D3 direction, multiple (for example, two) capacitors C, and a second transistor T2. For example, the first poles of each of the multiple capacitors C are connected to each other, one of the source or drain of the first transistor T1 is connected to the first pole, and the gate of the second transistor T2 is connected to the first pole. In this embodiment, one memory cell 112 can include two transistors (i.e., the first transistor T1 and the second transistor T2) and multiple capacitors C, so that one memory cell 112 can be used to store multi-bit data, which helps to improve the storage capacity of the unit memory cell 112. From another perspective, multiple capacitors C share two transistors T1 and T2, which can reduce the number of transistors configured in the unit memory cell 112, thereby helping to improve the storage density.

[0049] Figure 1C is a schematic cross-sectional structure of the semiconductor device provided by the embodiments of the present application including the first memory cell. For example, Figure 1C may be Figure 1A a partial enlarged schematic diagram of the dotted area shown. The physical structure of the first memory cell 112 will be described by way of example below in conjunction with Figure 1A and Figure 1C to illustrate.

[0050] As Figure 1A and Figure 1CAs shown, the first storage structure 111 may include a first electrode layer 117, a first stacked structure 118, a storage column 119, a first channel layer 120, a second electrode 121, a second stacked structure 122, and a channel structure 123.

[0051] In some embodiments, the first electrode layer 117 may extend laterally in a plane perpendicular to the D3 direction. The material of the first electrode layer 117 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0052] In some embodiments, the first stacked structure 118 may be located on one side (e.g., the surface) of the first electrode layer 117. The first stacked structure 118 may include alternately stacked first dielectric layers 1181 and plate line layers 1182. Both the first dielectric layer 1181 and the plate line layer 1182 may extend laterally in a plane perpendicular to the D3 direction. The material of the first dielectric layer 1181 may include one or more of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The material of the plate line layer 1182 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. Figure 1C The shown first stacked structure 118 including two plate line layers 1182 is only an example. In other implementations, the first stacked structure 118 may also include three plate line layers 1182, or more plate line layers 1182, and the present application does not make specific limitations thereto.

[0053] In some embodiments, the storage column 119 may penetrate through the first stacked structure 118 and the first electrode layer 117 and protrude from the first electrode layer 117. The storage column 119 may include a storage function layer 1191 and an inner electrode 1192 sequentially arranged from outside to inside. For example, the storage function layer 1191 may be generally a tubular structure with one end closed, and the end of the storage function layer 1191 extending from the first electrode layer 117 is the closed end. The inner electrode 1192 may be embedded inside the storage function layer 1191 and in contact with the storage function layer 1191.

[0054] In some embodiments, the material of the storage functional layer 1191 may include ferroelectric materials. Ferroelectric materials may include zirconia (ZrO2), hafnium oxide (HfO2), aluminum (Al)-doped HfO2, silicon (Si)-doped HfO2, zirconium (Zr)-doped HfO2, lanthanum (La)-doped HfO2, yttrium (Y)-doped HfO2, and one or more of other element-doped ferroelectric materials. When an electric field is applied to the ferroelectric material layer, the central atoms stop at the low-energy state along the direction of the electric field. Conversely, when the reversed electric field is applied to the ferroelectric material layer, the central atoms move along the direction of the electric field in the crystal and stop at another low-energy state. A large number of central atoms moving and coupling in the crystal unit cell form ferroelectric domains, and the ferroelectric domains form polarization charges under the action of the electric field. The polarization charges formed by the reversal of the ferroelectric domains under the electric field are higher, and the polarization charges formed by the non-reversal of the ferroelectric domains under the electric field are lower. This binary stable state of the ferroelectric material enables it to be used as the storage functional layer 1191 to store logic information. In some other embodiments, the material of the storage functional layer 1191 may include antiferroelectric materials. Antiferroelectric materials may include lead zirconate (PbZrO3), lead hafnate (PbHfO3), sodium niobate (NaNbO3), ammonium dihydrogen phosphate (NH4H2PO4), ammonium iodate (NH4IO3), tungsten trioxide (WO3), etc. Antiferroelectric materials have better stability, and their application in memories will bring better data retention characteristics. For example, when the material of the storage functional layer 1191 is a ferroelectric material or an antiferroelectric material, the semiconductor device 100 can be used as a ferroelectric random access memory (FeRAM) or a part thereof. The first storage unit 112 (refer to Figure 1B ) can be used as a ferroelectric storage unit.

[0055] In some embodiments, the material of the internal electrode 1192 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. In some other embodiments, the internal electrode 1192 may be a composite layer structure (not shown). For example, the internal electrode 1192 may be composed of a conductive layer in contact with the storage functional layer 1191 and insulating columns located inside the conductive layer (not shown), and the present application does not make specific limitations thereon.

[0056] In some embodiments, the first channel layer 120 may cover the portion of the storage functional layer 1191 protruding from the first electrode layer 117 and the first electrode layer 117. The material of the first channel layer 120 may include one or more of polysilicon (poly-Si), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or any other suitable semiconductor material.

[0057] In some embodiments, the second electrode 121 may be located on a side of the first channel layer 120 away from the first electrode layer 117 and connected (e.g., in contact) with the first channel layer 120. For example, the second electrode 121 may be generally a columnar structure and be disposed generally coaxially with the first channel layer 120. The material of the second electrode 121 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0058] In some embodiments, the second stack structure 122 may be located on a side of the first stack structure 118 away from the first electrode layer 117 and includes a gate layer 1222 and two second dielectric layers 1221 located on opposite sides of the gate layer 1222. The material of the second dielectric layer 1221 may include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The material of the gate layer 1222 may include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. When the materials of the second dielectric layer 1221 and the first dielectric layer 1181 are the same, there may be no obvious interface between them.

[0059] In some embodiments, the channel structure 123 may penetrate the second stacked structure 122 to the storage column 119. The channel structure 123 may include a gate dielectric layer 1231 and a second channel layer 1232 arranged in sequence from outside to inside. Among them, the second channel layer 1232 is connected (e.g., in contact) to the inner electrode 1192. For example, the gate dielectric layer 1231 may be generally a tubular structure with both ends open, and the second channel layer 1232 may be located inside the gate dielectric layer 1231. In other words, the gate dielectric layer 1231 surrounds the second channel layer 1232. In some examples, the second channel layer 1232 may be generally a columnar structure. In other examples, the second channel layer 1232 may be generally a tubular structure, and an insulating column (not shown) may be provided inside it. Exemplarily, the material of the gate dielectric layer 1231 may include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. Exemplarily, the material of the second channel layer 1232 may include one or more of semiconductor materials such as polysilicon (Poly-Si), amorphous silicon (α-Si), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium tin oxide (ITO), etc. Optionally, a dopant may be incorporated into the material of the second channel layer 1232. For example, the conduction type of the dopant may be N-type or P-type, so that the second channel layer 1232 has N-type conduction or P-type conduction.

[0060] According to the above description, as Figures 1A to 1C shown, the portion of the first electrode layer 117, the first channel layer 120, the second electrode 121, and the storage column 119 protruding from the first electrode layer 117 may form the second transistor T2. For example, a part of the first electrode layer 117 in contact with the first channel layer 120 may serve as one pole (e.g., one of the source and drain) of the second transistor T2, and other parts of the first electrode layer 117 may serve as the second word line WL2. The portion of the inner electrode 1192 in the storage column 119 protruding from the first electrode layer 117 may serve as the control pole (e.g., the gate) of the second transistor T2. The portion of the storage function layer 1191 in the storage column 119 protruding from the first electrode layer 117 may serve as the gate dielectric of the second transistor T2. The second electrode 121 may serve as one pole (e.g., the other of the source and drain) of the second transistor T2. In the second transistor T2, the first channel layer 120 surrounds the portion of the inner electrode 1192 protruding from the first electrode layer 117, which can increase the gate length and gate control ability. The second transistor T2 may be referred to as a Channel-All-Around Field-Effect Transistor (CAA FET).

[0061] The portions of the storage function layer 1191 and the internal electrode 1192 respectively surrounded by a plate line layer 1182, and a portion of the plate line layer 1182 in contact with the storage function layer 1191 can form a capacitor C. For example, the portion of the internal electrode 1192 surrounded by the plate line layer 1182 can serve as the first pole of the capacitor C, a portion of the plate line layer 1182 in contact with the storage function layer 1191 can serve as the second pole of the capacitor C, and other portions of the plate line layer 1182 can serve as the plate line PL. A plurality of (e.g., two) capacitors C are arranged in the D3 direction. The first poles of these capacitors C share the internal electrode 1192 to achieve connection between them, and the first poles of these capacitors C are also connected to the control pole of the second transistor T2 (i.e., share the internal electrode 1192), so as to be able to achieve connection to the control pole of the second transistor T2.

[0062] The second channel layer 1232, the gate dielectric layer 1231, and a portion of the gate layer 1222 in contact with the gate dielectric layer 1231 can form a first transistor T1. The first transistor T1 can be referred to as a vertical channel type transistor. For example, the end of the second channel layer 1232 far from the internal electrode 1192 can serve as one pole of the first transistor T1 (e.g., one of the source and drain), and can be used to connect to the first bit line BL1. The end of the second channel layer 1232 close to the internal electrode 1192 can serve as the other pole of the first transistor T1 (e.g., the other of the source and drain), and can be connected to the first poles of a plurality of capacitors C (i.e., the internal electrode 1192). A portion of the gate layer 1222 in contact with the gate dielectric layer 1231 can serve as the control pole (e.g., the gate) of the first transistor T1, and other portions of the gate layer 1222 serve as the first word line WL1.

[0063] The first transistor T1, a plurality of capacitors C, and the second transistor T2 can form a storage cell 112. For example, the first word line WL1 can be a write word line, and the first bit line BL1 can be a write bit line. The second word line WL2 can be a read word line, and the second bit line BL2 can be a read bit line. As Figure 1A shown, in the semiconductor device 100, the first transistor T1 is closer to the second peripheral circuit structure 114, and the second transistor T2 is closer to the first peripheral circuit structure 113.

[0064] It should be noted that Figure 1CThe first memory cell 112 shown, which is composed of a first electrode layer 117, a first stacked structure 118, a memory pillar 119, a first channel layer 120, a second electrode 121, a second stacked structure 122, and a channel structure 123, can form a memory cell array when arranged in an array. The circuit structures and physical structures of the respective first memory cells 112 can be substantially the same. Those skilled in the art can design the arrangement pattern and the number of the first memory cells 112 in the memory cell array according to the memory storage capacity requirements of the memory in the memory system described below.

[0065] Referring again to Figure 1A , in some embodiments, the semiconductor device 100 may further include a wiring layer 124. For example, the wiring layer 124 may be located on a side of the second substrate 1141 away from the first memory structure 111. The wiring layer 124 may include pad structures (not shown) therein, which can be used to realize the coupling of the semiconductor device 100 with external devices. For example, in the wiring layer 124, the pad structures may be surrounded by surrounding dielectric materials. The materials of the pad structures may include one or more of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), or any other suitable conductive materials.

[0066] Figure 2 FIG. is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of the present application. For the purpose of concise description, the content identical to that in the previous embodiment will not be described again in the following text of the present application.

[0067] As Figure 2 shown, in the semiconductor device 200, the first memory structure 211 may include a plurality of first memory cells 212 arranged along the D1 direction and the D2 direction. The first peripheral circuit structure 213 and the second peripheral circuit structure 214 may be located on both sides of the first memory structure 211 in the D3 direction and connected to the first memory structure 211. The first transistor T1 is closer to the first peripheral circuit structure 213, and the second transistor T2 is closer to the second peripheral circuit structure 214. For the semiconductor device 200 having the above structure, its integration degree can be effectively improved, the transmission efficiency can be increased, and the RC delay can be reduced, better adapting to the development trend of high bandwidth.

[0068] In some embodiments, the wiring layer 224 may be located on a side of the second substrate 2141 away from the first memory structure 211 and include pad structures (not shown) therein.

[0069] It should be noted that Figure 1A and Figure 2The shown wiring layers 124 and 224 being located on the sides of the second substrates 1141 and 2141 away from the first storage structures 111 and 211 are merely examples. In other embodiments, the wiring layer including the pad structure may also be located on the side of the first substrate away from the first storage structure, or the wiring layer may be disposed on the sides of the first substrate and the second substrate respectively away from the first storage structure, which can improve the arrangement density of the pad structure and adapt to semiconductor devices having a relatively large number of pad structures.

[0070] Figure 3 is a schematic cross-sectional view of a semiconductor device provided by another embodiment of the present application. As Figure 3 shown, in the semiconductor device 300, the first peripheral circuit structure 313 may include a first substrate 3131 and a first peripheral circuit 3132. For example, the first peripheral circuit 3132 may be located on one side of the first substrate 3131 and may be located between the first storage structure 311 and the first substrate 3131. The second peripheral circuit structure 314 may include a second substrate 3141 and a second peripheral circuit 3142. Among them, the second peripheral circuit 3142 may include a first circuit portion 3142-1 and a second circuit portion 3142-2. The first circuit portion 3142-1 and the second circuit portion 3142-2 are respectively located on two sides of the second substrate 3141 in the D3 direction. For example, the second circuit portion 3142-2 may be located between the first storage structure 311 and the second substrate 3141.

[0071] In some embodiments, the semiconductor device 300 may further include a second storage structure 325. The second storage structure 325 may be located on the side of the second peripheral circuit structure 314 away from the first storage structure 311 in the D3 direction and is connected to the second peripheral circuit structure 314. For example, the second storage structure 325 and the second peripheral circuit structure 314 may be connected through a "bonding technology". In this embodiment, the first circuit portion 3142-1 and the second circuit portion 3142-2 are respectively disposed on two opposite sides of the second substrate 3141 in the second peripheral circuit structure 314, and the first storage structure 311 and the second storage structure 325 are respectively connected to two opposite sides of the second peripheral circuit structure 314, which can further improve the integration degree of the semiconductor device 300 and increase the storage density. At the same time, when the second storage structure 325 and the second peripheral circuit structure 314 are bonded, a shorter interconnect distance can also be achieved, further improving the transmission efficiency and reducing the RC delay, and further achieving a higher interconnect density.

[0072] In some embodiments, the second storage structure 325 may include a plurality of second storage units 326. For example, the plurality of second storage units 326 may be arranged in an array along the D1 direction and the D2 direction. The second storage unit 326 may include a NAND storage unit, a DRAM storage unit, and a ferroelectric storage unit. For example, one NAND storage unit may include a plurality of floating gate type or charge trapping type transistors. Also for example, one DRAM storage unit includes at least one capacitor and a transistor connected to at least one end of the at least one capacitor. When the first storage unit 312 in the first storage structure 311 and the second storage unit 326 in the second storage structure 325 are different types of storage units, heterogeneous stacking of different storage structures in the semiconductor device 300 can be achieved, which is beneficial to improving the transfer efficiency between different types of storage units.

[0073] In one implementation, the second storage unit 326 may be a NAND storage unit (not shown), and the first storage unit 312 is a ferroelectric storage unit having two transistors and a plurality of capacitors. The first circuit portion 3142-1 and / or the second circuit portion 3142-2 of the second peripheral circuit may include sense amplifiers, and the first storage unit 312 and the second storage unit 326 share the sense amplifiers. Among them, during a read operation, the sense amplifier may be configured to sense the storage unit to obtain stored data. For a read operation, both the NAND storage unit and the ferroelectric storage unit having two transistors and a plurality of capacitors are current-driven types. By sharing the sense amplifiers provided in the second peripheral circuit for these two types of storage units, the utilization rate of the sense amplifier can be improved, and the occupied area of the peripheral circuit can be saved.

[0074] In another implementation, as Figure 3 shown, the second storage unit 326 may be a ferroelectric storage unit as described in detail above. For example, one storage unit 326 may include a first transistor T1, a plurality of capacitors C, and a second transistor T2 arranged along the D3 direction. Among them, the capacitor C may be a ferroelectric capacitor. For example, the first storage structure 311 and the second storage structure 325 may be substantially symmetric with respect to the second peripheral circuit structure 314. When the first storage unit 312 in the first storage structure 311 and the second storage unit 326 in the second storage structure 325 are the same type of storage units, the first storage structure 311 and the second storage structure 325 can be formed using the same process method, which is beneficial to saving process costs. It should be noted that Figure 3The arrangement of the first transistor T1, the plurality of capacitors C, and the second transistor T2 in the first storage unit 312 and the second storage unit 326 shown is only an example. In other embodiments, the first transistor T1, the plurality of capacitors C, and the second transistor T2 in the first storage unit 312 and the second storage unit 326 may have other arrangements. For example, the first transistor T1 in the first storage unit 312 and the first transistor T1 in the second storage unit 326 may both be arranged closer to the second substrate 3141. The present application does not make specific limitations on this.

[0075] In some embodiments, the semiconductor device 300 may further include a third peripheral circuit structure 327. The third peripheral circuit structure 327 may be located on a side of the second storage structure 325 away from the second peripheral circuit structure 314 in the D3 direction and connected to the second storage structure 325 (e.g., bonded connection). The third peripheral circuit structure 327 may include a third substrate 3271 and a third peripheral circuit 3272. For example, the third peripheral circuit 3272 may be located on one side of the third substrate 3271 and may be located between the third substrate 3271 and the second storage structure 325. For example, the first peripheral circuit 3132, the first circuit portion 3142-1 and the second circuit portion 3142-2 of the second peripheral circuit, and the third peripheral circuit 3272 may jointly form a peripheral circuit for controlling data transmission (e.g., writing, reading, and erasing, etc.) of the plurality of first storage units 312 and the plurality of second storage units 326.

[0076] In some embodiments, in the semiconductor device 300, the wiring layer 324 may be located on a side of the first substrate 3131 and / or the third substrate 3271 away from the second peripheral circuit structure 314 respectively, and includes pad structures (not shown) therein.

[0077] It should be noted that Figure 3 The number of the second storage structures 325 shown is only an example. The number of the second storage structures 325 may be multiple, and the multiple second storage structures 325 are stacked and connected to each other in the D3 direction. In addition, a second peripheral circuit structure 314 as shown may be provided between adjacent second storage structures 325. The present application does not make limitations on this. Figure 3

[0078] Figure 4 The embodiment of the present application also provides a memory system. is a block diagram of a system with a memory system provided by the embodiment of the present application.

[0079] Figure 4 As Figure 4As shown, the system 400 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (which has a memory system 410 located therein). As Figure 4 shown, the system 400 can include a host 420 and a memory system 410. The memory system 410 can have one or more memories 411 and a controller 412. Among them, the memory 411 can include semiconductor devices described in any of the above embodiments (for example, Figures 1A to 1C the semiconductor device 100 shown, Figure 2 the semiconductor device 200 shown, and Figure 3 the semiconductor device 300 shown). The host 420 can be a processor of the electronic device, such as a central processing unit (CPU), or can be a system-on-chip (SoC), such as an application processor (AP). The host 420 can be configured to send or receive data to and from the memory 411.

[0080] In some embodiments, the controller 412 can be coupled to the memory 411 and the host 420, and is configured to control the memory 411. For example, the controller 412 can be configured to control the memory 411 to perform operations such as reading, erasing, and programming (for example, writing). The controller 412 can also manage the data stored in the memory 411 and communicate with the host 420. For example, the controller 412 can communicate with an external device (for example, the host 420) according to a specific communication protocol.

[0081] The embodiment of the present application also provides a manufacturing method of a semiconductor device. Figure 5 is a schematic flowchart of the manufacturing method of the semiconductor device provided by the embodiment of the present application. As Figure 5 shown, the manufacturing method 500 of the semiconductor device (hereinafter simply referred to as the manufacturing method 500) can include the following steps.

[0082] S510, form a first storage structure, where the first storage structure includes a plurality of first storage units arranged along a first direction and a second direction.

[0083] S520, connect a first peripheral circuit structure to one side of the first storage structure in a third direction.

[0084] S530, connect a second peripheral circuit structure to the other side of the first storage structure in the third direction.

[0085] According to the manufacturing method of the semiconductor device provided by this embodiment, by connecting a first peripheral circuit structure and a second peripheral circuit structure to the relative two sides of the first storage structure in the third direction respectively, the limitation of the semiconductor manufacturing process can be broken through, and the integration degree of the semiconductor device can be effectively improved. In addition, the transmission path between the peripheral circuits in the first peripheral circuit structure and the second peripheral circuit structure and the first storage structure can also be reduced, which is beneficial to improving the transmission efficiency and reducing the RC delay, and better adapting to the development trend of high bandwidth.

[0086] Figures 6A to 6G It is a schematic diagram of the semiconductor device provided by the embodiment of the present application during the manufacturing process. For example, Figures 6A to 6G can be used to form Figures 1A to 1C the semiconductor device 100 shown. The following will exemplarily illustrate the manufacturing method 500 including the above steps S510 to S530 in conjunction with Figure 6A and Figure 6G .

[0087] S510

[0088] Figure 6A It shows the intermediate structure 600a after forming a plurality of capacitors C and the first transistor T1 in the first storage structure 611. Figure 6B It shows the intermediate structure 600b after forming the second transistor T2 in the first storage structure 611.

[0089] As Figure 6A shown, in some embodiments, forming the first storage structure 611 may include: sequentially forming a plurality of capacitors C and the first transistor T1 on one side of the sacrificial substrate 630. Among them, the sacrificial substrate 630 will be removed in subsequent processes and play a supporting role in this step. For example, the sacrificial substrate 630 may include a silicon (Si) substrate, a germanium (Ge) substrate, a gallium arsenide (GaAs) substrate, or an indium phosphide (InP) substrate. Another example is that the sacrificial substrate 630 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate, etc.

[0090] The following will exemplarily illustrate the process method of sequentially forming a plurality of capacitors C and the first transistor T1 on one side of the sacrificial substrate 630.

[0091] In some embodiments, first, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof may be used to sequentially form a first electrode layer 617 and a first stacked structure 618 on one side of a sacrificial substrate 630. Among them, the first dielectric layer 6181 and the plate line layer 6182 in the first stacked structure 618 may be alternately formed by the above thin film deposition process.

[0092] Next, an etching process (e.g., dry etching and / or wet etching) may be used to form a storage hole (corresponding to the outer contour of the storage column 619) that sequentially penetrates the first stacked structure 618, the first electrode layer 617, and extends into the sacrificial substrate 630. Then, a storage functional layer 6191 may be formed on the inner wall of the storage hole by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and an inner electrode 6192 may be formed inside the storage functional layer 6191. In this step, both the storage functional layer 6191 and the inner electrode 6192 in the storage column 619 protrude from the first electrode layer 617.

[0093] Further, a second stacked structure 622 may be formed on the side of the first stacked structure 618 away from the sacrificial substrate 630 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The second stacked structure 622 may include a gate layer 6222 and second dielectric layers 6221 located on opposite sides of the gate layer 6222 in the D3 direction. Then, an etching process (e.g., dry etching and / or wet etching) may be used to form a channel hole (corresponding to the outer contour of the channel structure 623) that penetrates the second stacked structure 622 to the storage column 619. Next, a gate dielectric layer 6231 may be formed on the sidewall of the channel hole by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and a second channel layer 6232 may be formed inside the gate dielectric layer 6231. As an option, a second channel layer may be formed on the sidewall of the gate dielectric layer 6231, and an insulating column (not shown) may be formed inside the second channel layer.

[0094] As described in detail above, the portions of the storage functional layer 6191 and the inner electrode 6192 respectively surrounded by a plate line layer 6182, and a part of the plate line layer 6182 in contact with the storage functional layer 6191 may constitute a capacitor C. The second channel layer 6232, the gate dielectric layer 6231, and a part of the gate layer 6222 in contact with the gate dielectric layer 6231 may constitute a first transistor T1.

[0095] In some embodiments, after forming a plurality of capacitors C and a first transistor T1 in sequence on one side of a sacrificial substrate 630, a first carrier structure 631 may be connected to the side of the first transistor T1 away from the plurality of capacitors C in the D3 direction. For example, the first carrier structure 631 may be a semiconductor substrate.

[0096] In some embodiments, after forming a plurality of capacitors C and a first transistor T1 in sequence on one side of a sacrificial substrate 630, Figure 6A the shown intermediate structure 600a may be flipped 180°. In the case where the first carrier structure 631 is formed, the first carrier structure 631 may be used to carry components such as the first stacked structure 618 and the second stacked structure 622 located on its top side, so as to form a second transistor T2 on the other side of the sacrificial substrate 630.

[0097] The following is an example to illustrate the process method of forming a second transistor T2 on the side of the plurality of capacitors C away from the first transistor T1. First, as Figure 6A and Figure 6B shown, chemical mechanical polish (CMP) and etching (e.g., wet etching and / or dry etching) processes may be used to remove the sacrificial substrate 630 and expose the portion of the storage functional layer 6191 in the storage column 619 protruding from the first electrode layer 617. Then, a first channel layer 620 covering the storage functional layer 6191 protruding from the first electrode layer 617 may be formed by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, the first channel layer 620 also covers the surface of the first electrode layer 617. Next, an etching process and a thin film deposition process may be used to form a second electrode 621 connected (e.g., in contact) with the first channel layer 620.

[0098] As described in detail above, the first electrode layer 617, the first channel layer 620, the second electrode 621, and the portion of the storage column 619 protruding from the first electrode layer 617 may constitute the second transistor T2.

[0099] S520

[0100] Figure 6C The intermediate structure 600c after connecting the first peripheral circuit structure 613 to one side of the first storage structure 611 in the D3 direction is shown. As Figure 6CAs shown, in some embodiments, any known "bonding technique" in the art can be used to connect the first peripheral circuit structure 613 to the first storage structure 611. For example, the first peripheral circuit structure 613 is connected to the side of the first storage structure 611 close to the second transistor T2. In one implementation, first, the first peripheral circuit structure 613 can be placed on the side of the first storage structure 611 away from the first carrier structure 631, and the first peripheral circuit 6132 and the second transistor T2 are brought close to each other until the first peripheral circuit structure 613 and the first storage structure 611 are in contact (for example, the bonding contact 616 and the dielectric structure around it are in contact), thereby obtaining the first peripheral circuit structure 613 and the first storage structure 611 that are connected to each other.

[0101] In this embodiment, forming the second transistor T2 first and then connecting the first peripheral circuit structure 613 and the first storage structure 611 can cope with the adverse effects of the high-temperature process conditions during the formation of the second transistor T2 on the connection relationship between the first peripheral circuit structure 613 and the first storage structure 611. For example, when the first peripheral circuit structure 613 and the first storage structure 611 are connected through the bonding contact 616 (for example, the material of the bonding contact 616 is copper (Gu)), the high-temperature process conditions will cause the connection of the bonding contact 616 to fail, thereby affecting the connection reliability.

[0102] Figure 6D Shows the Figure 6C Intermediate structure 600d after flipping the shown intermediate structure 600c by 180°. Figure 6E Shows the intermediate structure 600e during the removal of the first carrier structure 631. In some embodiments, the intermediate structure 600c including the first carrier structure 631 can be flipped 180° so that the first carrier structure 631 is on the top side, as Figure 6D shown. The flipped intermediate structure 600d can facilitate performing subsequent processes on the other side of the first storage structure 611. Further, as Figure 6E shown, the first carrier structure 631 can be removed.

[0103] S530

[0104] Figure 6F Shows the intermediate structure 600f after connecting the second peripheral circuit structure 614 to the other side of the first storage structure 611 in the D3 direction. Figure 6G Shows the semiconductor device 600 after forming the wiring layer 624.

[0105] As Figure 6FAs shown, in some embodiments, any known "bonding technique" in the art can be used to connect the second peripheral circuit structure 614 to the first storage structure 611. For example, the second peripheral circuit structure 614 is connected to the side of the first storage structure 611 close to the first transistor T1. Optionally, a CMP process can be used to planarize the second substrate 6141 to reduce the size of the finally formed semiconductor device 700 (reference Figure 6G ) in the D3 direction.

[0106] In some embodiments, as Figure 6G shown, a wiring layer 624 can be formed on the side of the second substrate 6141 away from the first storage structure 611 by using a thin film deposition process and an etching process. Among them, the wiring layer 624 can include a pad structure (not shown) located therein.

[0107] Figures 7A to 7D is a schematic diagram during the manufacturing process of a semiconductor device provided by another embodiment of the present application. For example, Figures 7A to 7D can be used to form Figure 2 the shown semiconductor device 200. The following will exemplarily describe the manufacturing method 500 including the above steps S510 to S530 in conjunction with Figures 7A to 7D . For the purpose of concise description, the content that is the same as that in the previous embodiment in the following text will not be repeated in this application.

[0108] S510

[0109] Figure 7A shows an intermediate structure 700a after forming a plurality of capacitors C and the first transistor T1 in the first storage structure 711. Figure 7B shows an intermediate structure 700b after forming the second transistor T2. As Figure 7A shown, in some embodiments, forming the first storage structure 711 may include: sequentially forming a plurality of capacitors C and the first transistor T1 on one side of the sacrificial substrate 730. As Figure 7B shown, after sequentially forming a plurality of capacitors C and the first transistor T1 on one side of the sacrificial substrate 730, the Figure 7A shown intermediate structure 700a can be flipped 180°, and the second transistor T2 is formed on the side of the plurality of capacitors C away from the first transistor T1.

[0110] S520

[0111] Continue to refer to Figure 7A and Figure 7B, after forming a plurality of capacitors C and a first transistor T1 in sequence on one side of the sacrificial substrate 730, and before forming a second transistor T2 on the side of the plurality of capacitors C away from the first transistor T1, the first peripheral circuit structure 713 can be connected to one side of the first storage structure 711 in the D3 direction. In some embodiments, any known "bonding technique" in the art can be used to connect the first peripheral circuit structure 713 to the first storage structure 711. For example, the first peripheral circuit structure 713 is connected to the side of the first storage structure 711 close to the first transistor T1.

[0112] In this embodiment, connecting the first peripheral circuit structure 713 and the first storage structure 711 first and then forming the second transistor T2 can be applied to the case of forming the second transistor T2 under low-temperature process conditions, which is beneficial to simplifying the process flow, reducing the number of flips of the intermediate structure, and omitting the step of connecting the carrier structure, thereby improving production efficiency and reducing manufacturing costs.

[0113] S530

[0114] Figure 7C The intermediate structure 700c after connecting the second peripheral circuit structure 714 to the other side of the first storage structure 711 in the D3 direction is shown. Figure 7D The semiconductor device 700 after forming the wiring layer 724 is shown.

[0115] As Figure 7C shown, in some embodiments, any known "bonding technique" in the art can be used to connect the second peripheral circuit structure 714 to the first storage structure 711. For example, the second peripheral circuit structure 714 is connected to the side of the first storage structure 711 close to the second transistor T2. Optionally, a CMP process can be used to planarize the second substrate 7141.

[0116] In some embodiments, as Figure 7D shown, a wiring layer 724 can be formed on the side of the second substrate 7141 away from the first storage structure 711 by using a thin film deposition process and an etching process. Among them, the wiring layer 724 can include a pad structure (not shown) located therein.

[0117] Figures 8A to 8E is a cross-sectional schematic diagram of a semiconductor device provided by another embodiment of the present application during manufacturing. For example, Figures 8A to 8E can be used to form Figure 3 the semiconductor device 300 shown. In this embodiment, steps S510 and S520 can be executed by the process methods described in the above embodiments, and the present application will not elaborate here. The following will be combined with Figures 8A to 8E exemplarily illustrate the manufacturing method 500 including the above step S530.

[0118] In some embodiments, before performing step S530, a second peripheral circuit structure may be formed first. Figure 8A is a cross-sectional schematic view of a semiconductor structure including a second substrate 8141, a first circuit portion 8142-1 of a second peripheral circuit, and a second carrier structure 832. Figure 8B is to Figure 8A a cross-sectional schematic view after the semiconductor structure shown is flipped 180°. Figure 8C is at Figure 8B a cross-sectional schematic view further including a second circuit portion 8142-2 of a second peripheral circuit on the basis of.

[0119] In some embodiments, first, as Figure 8A shown, a first circuit portion 8142-1 of a second peripheral circuit may be formed on a first side of a second substrate 8141. For example, the second substrate 8141 may include a silicon (Si) substrate, a germanium (Ge) substrate, a gallium arsenide (GaAs) substrate, or an indium phosphide (InP) substrate. Further, for example, the second substrate 8141 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate, etc. Optionally, after forming the first circuit portion 8142-1 of the second peripheral circuit on the first side of the second substrate 8141, the second carrier structure 832 may be connected to a side of the first circuit portion 8142-1 away from the second substrate 8141 in the D3 direction. For example, the second carrier structure 832 may be a semiconductor substrate. Then, as Figure 8B shown, Figure 8A the semiconductor structure shown may be flipped 180° so as to perform subsequent process methods on a second side of the second substrate 8141 opposite to the first side. For example, the second carrier structure 832 may be used to carry components such as the first circuit portion 8142-1 of the second peripheral circuit and the second substrate 8141 located on its top side. Then, as Figure 8C shown, a second circuit portion 8142-2 of a second peripheral circuit may be formed on the second side of the second substrate 8141, thereby forming a second peripheral circuit structure 814. For example, the second carrier structure 832 may further be used to carry the second circuit portion 8142-2. Thus, a second peripheral circuit structure 814 having the first circuit portion 8142-1 and the second circuit portion 8142-2 on opposite sides of the second substrate 8141 respectively may be formed.

[0120] S730

[0121] Figure 8D shows an intermediate structure 800a after connecting the second peripheral circuit structure 814 to the other side of the first storage structure 811 in the D3 direction. As Figure 8DAs shown, in some embodiments, any known "bonding technique" in the art can be used to connect the second peripheral circuit structure 814 to the first storage structure 811. For example, the second circuit portion 8142-2 of the second peripheral circuit structure 814 and the first storage structure 811 are brought close to each other. Further, the second carrier structure 832 can be removed from the second peripheral circuit structure 814.

[0122] In some embodiments, after connecting the second peripheral circuit structure 814 to the other side of the first storage structure 811 in the D3 direction, the manufacturing method 500 may further include: a step of connecting at least one second storage structure to the side of the second peripheral circuit structure away from the first storage structure in the D3 direction. Among them, Figure 8E The semiconductor device 800 after connecting the second storage structure 825 is shown.

[0123] As Figure 8E shown, in some embodiments, any known "bonding technique" in the art can be used to connect the second storage structure 825 connected with the third peripheral circuit structure 827 to the second peripheral circuit structure 814. For example, the third peripheral circuit structure 827 and the second storage structure 825 can be formed by the methods of steps S510 and S520 described in the above embodiments. It should be noted that, in some implementation manners, at least one third storage structure 825 can be directly connected to the side of the second peripheral circuit structure 814 away from the first storage structure 811, and the step of forming the third peripheral circuit structure 827 on the side of at least one third storage structure 825 away from the second peripheral circuit structure 814 can be omitted.

[0124] In some embodiments, a wiring layer 824 can be formed on the side of the third substrate 8271 in the third peripheral circuit structure 827 away from the first storage structure 811 by using a thin film deposition process and an etching process. Among them, the wiring layer 824 can include a pad structure (not shown) located therein.

[0125] The above description is only for the embodiments of the present application and the explanation of the applied technical principles. Those skilled in the art should understand that the protection scope involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A semiconductor device, characterized in that, Comprising: A first peripheral circuit structure; A second peripheral circuit structure; And A first memory structure, including a plurality of first memory cells arranged along a first direction and a second direction; Wherein, the first peripheral circuit structure and the second peripheral circuit structure are located on both sides of the first memory structure in a third direction, and are connected to the first memory structure, and the first direction, the second direction, and the third direction intersect with each other.

2. The semiconductor device according to claim 1, wherein, The first memory cell includes a first transistor arranged along the third direction, a plurality of capacitors, and a second transistor.

3. The semiconductor device according to claim 2, wherein, The first poles of each of the plurality of capacitors are connected to each other, one of the source or drain of the first transistor is connected to the first pole, and the gate of the second transistor is connected to the first pole.

4. The semiconductor device according to claim 2 or 3, wherein, The capacitor is a ferroelectric capacitor.

5. The semiconductor device according to claim 1, wherein, The first peripheral circuit structure includes a first substrate and a first peripheral circuit, and the first peripheral circuit is located between the first memory structure and the first substrate; and The second peripheral circuit structure includes a second substrate and a second peripheral circuit, and the second peripheral circuit is located between the first memory structure and the second substrate.

6. The semiconductor device according to claim 5, wherein, Further comprising: A wiring layer, located on the side of the first substrate and / or the second substrate away from the first memory structure respectively, and including a pad structure therein.

7. The semiconductor device according to claim 1, wherein, The first peripheral circuit structure includes a first substrate and a first peripheral circuit, and the first peripheral circuit is located between the first memory structure and the first substrate; The second peripheral circuit structure includes a second substrate and a first circuit portion and a second circuit portion of the second peripheral circuit respectively located on both sides of the second substrate in the third direction; The semiconductor device further includes: At least one second memory structure, located on the side of the second peripheral circuit structure away from the first memory structure in the third direction, and connected to the second peripheral circuit structure.

8. The semiconductor device according to claim 7, wherein, The second memory structure includes a plurality of second memory cells, and the second memory cell includes at least one of a NAND memory cell, a DRAM memory cell, and a ferroelectric memory cell.

9. The semiconductor device according to claim 8, wherein, The second memory cell is a NAND memory cell, the second peripheral circuit includes a sense amplifier, and the first memory cell and the second memory cell share the sense amplifier.

10. The semiconductor device according to claim 7, wherein, Further comprising: A third peripheral circuit structure, located on the side of the at least one second memory structure away from the second peripheral circuit structure in the third direction, and connected to the at least one second memory structure.

11. The semiconductor device according to claim 10, wherein, The third peripheral circuit structure includes a third substrate and a third peripheral circuit, and the third peripheral circuit is located between the third substrate and the at least one second memory structure; Wherein, the semiconductor device further includes: A wiring layer, located on the side of the first substrate and / or the third substrate away from the second peripheral circuit structure respectively, and including a pad structure therein.

12. A memory system, characterized in that, Comprising: A memory, including the semiconductor device according to any one of claims 1 to 11; And A controller, coupled to the memory, for controlling the memory to store data.

13. A method for manufacturing a semiconductor device, characterized in that,Comprising: Form a first storage structure, the first storage structure including a plurality of first storage units arranged along a first direction and a second direction; Connect a first peripheral circuit structure to one side of the first storage structure in a third direction; And Connect a second peripheral circuit structure to the other side of the first storage structure in the third direction; Wherein, the first direction, the second direction, and the third direction intersect with each other.

14. The manufacturing method according to claim 13, wherein, The first storage unit includes a first transistor, a plurality of capacitors, and a second transistor arranged along the third direction, wherein forming the first storage structure includes: Sequentially form the plurality of capacitors and the first transistor on one side of a sacrificial substrate; Remove the sacrificial substrate; and Form the second transistor on a side of the plurality of capacitors away from the first transistor; Wherein, after forming the second transistor, connect the first peripheral circuit structure to one side of the first storage structure in the third direction.

15. The manufacturing method according to claim 14, wherein, After sequentially forming the plurality of capacitors and the first transistor on one side of a sacrificial substrate, the method further includes: Connect a first carrier structure to a side of the first transistor away from the plurality of capacitors in the third direction; and After forming the second transistor, connecting the first peripheral circuit structure to one side of the first storage structure in the third direction includes: Connect the first peripheral circuit structure to a side of the first storage structure close to the second transistor; Wherein, the method further includes: Remove the first carrier structure.

16. The manufacturing method according to claim 13, wherein, The first storage unit includes a first transistor, a plurality of capacitors, and a second transistor arranged along the third direction, wherein forming the first storage structure includes: Sequentially form the plurality of capacitors and the first transistor on one side of a sacrificial substrate; and Form the second transistor on a side of the plurality of capacitors away from the first transistor; Wherein, after sequentially forming the plurality of capacitors and the first transistor on one side of a sacrificial substrate, and before forming the second transistor on a side of the plurality of capacitors away from the first transistor, connecting the first peripheral circuit structure to one side of the first storage structure in the third direction includes: Connect the first peripheral circuit structure to a side of the first storage structure close to the first transistor.

17. The manufacturing method according to any one of claims 13 to 16, wherein, Further includes: Form a first circuit portion of a second peripheral circuit on a first side of a second substrate; And Form a second circuit portion of the second peripheral circuit on a second side of the second substrate opposite to the first side to form the second peripheral circuit structure.

18. The manufacturing method according to claim 17, wherein, After forming the first circuit portion of the second peripheral circuit on a first side of a second substrate, the method further includes: Connect a second carrier structure to a side of the first circuit portion away from the second substrate in the third direction.

19. The manufacturing method according to claim 17, wherein, After connecting the second peripheral circuit structure to the other side of the first storage structure in the third direction, the method further includes: Connect at least one second storage structure to a side of the second peripheral circuit structure away from the first storage structure in the third direction.

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