Three-dimensional stacked chip and manufacturing method thereof

Abstract

The invention discloses a three-dimensional stacked chip and a manufacturing method thereof. The three-dimensional stacked chip comprises a substrate, a first storage module and a logic module, the first storage module and the logic module are sequentially stacked on the substrate, and the first storage module is arranged between the logic module and the substrate; the first storage module is used for providing and storing data required by the logic module and supporting the logic module to complete corresponding work; and the logic module performs signal interaction with the outside through the first storage module and the substrate. The influence of heat generated by the logic module on the storage module is avoided, the power consumption tolerance of the logic module is remarkably improved, and the number of conductive paths needing to be arranged in the storage module stacking structure can be effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and more specifically, relates to a three-dimensional stacked chip and a manufacturing method thereof. Background Art

[0002] With the explosion of large language models in AI applications, artificial intelligence software has put forward higher requirements for the chip design industry. Traditional chip architectures and supporting memories far cannot meet the requirements of large language models for large bandwidth and high capacity. To meet the needs of the explosive development of AI, it is necessary to accelerate the research and development of new chip architectures and new storage technologies. Summary of the Invention

[0003] Aiming at the above defects or improvement requirements of the prior art, the present invention provides a three-dimensional stacked chip and a manufacturing method thereof, which avoid the influence of heat generated by logic modules on storage modules, significantly improve the power consumption tolerance of logic modules, and can effectively reduce the number of conductive vias required in the storage module stacking structure.

[0004] To achieve the above object, according to one aspect of the present invention, there is provided a three-dimensional stacked chip, including a substrate, a first storage module, and a logic module; the first storage module and the logic module are sequentially stacked on the substrate, and the first storage module is disposed between the logic module and the substrate; the first storage module is used to provide and store data required by the logic module, and support the logic module to complete corresponding work; the logic module exchanges signals with the outside through the first storage module and the substrate.

[0005] In some embodiments, the three-dimensional stacked chip further includes one or more stacked second storage modules, and the one or more stacked second storage modules are disposed between the first storage module and the logic module to form a storage module stacking structure with the first storage module; the one or more stacked second storage modules are used to provide and store data required by the logic module, and support the logic module to complete corresponding work; the logic module exchanges signals with the outside through the storage module stacking structure and the substrate.

[0006] In some embodiments, the logic module is connected to the power supply through the storage module stacking structure and is grounded through the side opposite to the storage module stacking structure.

[0007] In some embodiments, the logic module is grounded through the storage module stacking structure and is connected to the power supply through the side opposite to the storage module stacking structure.

[0008] In some embodiments, the logic module includes a plurality of stacked sub-logic modules, and the first storage module and the one or more stacked second storage modules are used to provide and store data required by the plurality of stacked sub-logic modules, and support the plurality of stacked sub-logic modules to complete corresponding work.

[0009] In some embodiments, the sub-logic modules closer to the memory module stack structure have lower power, and the sub-logic modules farther from the memory module stack structure have higher power.

[0010] In some embodiments, the first memory module is directly or indirectly disposed on the substrate, and one or more stacked second memory modules are directly or indirectly disposed on the first memory module as a whole, and the logic module is directly or indirectly disposed on the one or more stacked second memory modules.

[0011] In some embodiments, the above three-dimensional stacked chip further includes an external circuit disposed on the substrate; the logic module obtains working instructions from the external circuit through the substrate and via the memory module stack structure, completes corresponding work, and transmits the processing result via the memory module stack structure and through the substrate.

[0012] In some embodiments, the above three-dimensional stacked chip further includes a silicon interposer and an external circuit, the silicon interposer is disposed between the first memory module and the substrate, and the external circuit is disposed on the silicon interposer; the logic module obtains working instructions from the external circuit through the silicon interposer and via the memory module stack structure, completes corresponding work, and transmits the processing result via the memory module stack structure and through the silicon interposer.

[0013] In some embodiments, the above three-dimensional stacked chip further includes a silicon interposer and an external circuit, the silicon interposer is disposed between the first memory module and the substrate, and the external circuit is disposed on the silicon interposer; the logic module obtains working instructions from the external circuit through the silicon interposer and the substrate and via the memory module stack structure, completes corresponding work, and transmits the processing result via the memory module stack structure and through the silicon interposer and the substrate.

[0014] In some embodiments, the above three-dimensional stacked chip further includes a heat dissipation module, and the heat dissipation module is directly or indirectly disposed on the logic module.

[0015] In some embodiments, the heat dissipation module forms an electrical connection with the logic module, and the logic module uses the heat dissipation module to connect to the power supply or ground.

[0016] In some embodiments, the logic module is connected to the heat dissipation module through a conductive spacer layer.

[0017] According to another aspect of the present invention, there is provided a method for manufacturing a three-dimensional stacked chip, including:

[0018] Forming a first stack structure; the first stack structure includes a logic structure and one or more second memory modules sequentially stacked on the logic structure;

[0019] Form a second stacked structure using a first storage structure and a first stacked structure; the second stacked structure includes a first storage module and one or more second storage modules and logic modules stacked in sequence on the first storage module, the first storage module is obtained by processing the first storage structure, and the logic module is obtained by processing a logic structure;

[0020] Connect the first storage module to the substrate.

[0021] In some embodiments, the first storage structure includes a first substrate and a first storage device and a first interconnect layer formed on the first substrate; obtaining the first storage module by processing the first storage structure includes: forming a through-silicon via penetrating the first substrate of the first storage structure.

[0022] In some embodiments, the first storage structure includes a first substrate and a first storage device and a first interconnect layer formed on the first substrate; obtaining the first storage module by processing the first storage structure includes: thinning the first substrate of the first storage structure and forming a through-silicon via penetrating the thinned first substrate.

[0023] In some embodiments, the logic structure includes a second substrate and logic devices and a second interconnect layer formed on the second substrate; obtaining the logic module by processing the logic structure includes: thinning the second substrate of the logic structure and forming a through-silicon via penetrating the thinned second substrate.

[0024] In some embodiments, the second storage module includes: a thinned third substrate, a second storage device and a third interconnect layer formed on the third substrate, and a fourth interconnect layer formed on the back surface of the thinned third substrate.

[0025] In some embodiments, the method for fabricating the above three-dimensional stacked chip further includes: disposing a heat dissipation module on the logic module.

[0026] In some embodiments, a conductive spacer layer and a heat dissipation module are sequentially disposed on the logic module, and the logic module is connected to the heat dissipation module through the conductive spacer layer, so that the logic module can connect to a power supply or ground using the heat dissipation module.

[0027] Generally speaking, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects: The stacked structure of the storage module is arranged between the logic module and the substrate, so that the logic module is arranged on the stacked structure of the storage module, which provides great convenience for the heat dissipation of the logic module. The logic module is closer to the heat dissipation module than the stacked structure of the storage module, avoiding the influence of the heat generated by the logic module on the storage module, and significantly improving the power consumption tolerance of the logic module. In addition, the logic module is connected to the power supply or ground through the side opposite to the stacked structure of the storage module, avoiding the need to borrow the stacked structure of the storage module for both power supply and ground connection. Therefore, the number of conductive vias (such as through-silicon vias) that need to be arranged in the stacked structure of the storage module can be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a three-dimensional stacked chip;

[0029] Figure 2 is a schematic structural diagram of a three-dimensional stacked chip according to an embodiment of the present invention;

[0030] Figure 3 is a schematic structural diagram of a three-dimensional stacked chip according to another embodiment of the present invention;

[0031] Figure 4 is a schematic structural diagram of a three-dimensional stacked chip according to another embodiment of the present invention;

[0032] Figures 5A - 5J is a schematic diagram of a manufacturing method of a three-dimensional stacked chip according to an embodiment of the present invention;

[0033] Figure 6 is a schematic diagram of a manufacturing process of a three-dimensional stacked chip according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary in nature rather than restrictive.

[0035] Stacking the storage module and the logic module in multiple layers can multiply the system bandwidth and capacity, and thus can fully meet the requirements of large language models. Figure 1 A solution for a three-dimensional stacked chip is given.

[0036] As Figure 1As shown in the figure, a logic module 103 and multiple memory modules 105 are sequentially stacked on a substrate 101. The memory modules 105 are arranged above the logic module 103, and the logic module 103 is arranged between the memory modules 105 and the substrate 101. On the one hand, it is convenient to provide appropriate power and ground for the logic module 103. On the other hand, it is convenient for the logic module 103 to transfer data with the outside world. At the same time, since a large amount of heat is generated when the logic module 103 operates, this part of the heat is mainly dissipated upward through the side where the memory modules 105 are located. However, the memory modules 105 are very sensitive to heat, and the multi-layer stacked memory modules 105 further limit the heat dissipation. Especially when the logic module 103 operates at high power, this stacking method will cause a serious heat accumulation effect, greatly reducing the power consumption tolerance of the logic module 103. Therefore, Figure 1 the three-dimensional stacked chip shown in the figure cannot meet the requirements of large language models for the power consumption and computing power of the logic module.

[0037] In order to improve the power consumption tolerance of the logic module and reduce the adverse effects of heat accumulation on the memory module, it is necessary to Figure 1 further improve the three-dimensional stacked chip shown in the figure.

[0038] As Figure 2 shown in the figure, the three-dimensional stacked chip according to the embodiment of the present invention includes a substrate 201, a first memory module 203, one or more second memory modules 207, and a logic module 205. The first memory module 203, one or more second memory modules 207, and the logic module 205 are sequentially stacked on the substrate 201. The first memory module 203 and one or more second memory modules 207 form a memory module stacking structure. The logic module 205 is arranged on the memory module stacking structure, and the memory module stacking structure is arranged between the substrate 201 and the logic module 205.

[0039] One side of the first memory module 203 forms an electrical connection with the adjacent second memory module 207, and the other side of the first memory module 203 forms an electrical connection with the substrate 201. One side of the logic module 205 forms an electrical connection with the adjacent second memory module 207. When one side of the second memory module 207 is adjacent to other second memory modules 207, one side of the second memory module 207 forms an electrical connection with the adjacent second memory module 207; when both sides of the second memory module 207 are adjacent to other second memory modules 207, both sides of the second memory module 207 form electrical connections with other second memory modules 207.

[0040] Further, the logic module 205 forms a conductive connection with the first storage module 203 and one or more second storage modules 207, enabling the logic module 205 to interact with the first storage module 203 and one or more second storage modules 207 for data. Specifically, the first storage module 203 and one or more second storage modules 207 are used to provide and store the data required by the logic module 205, supporting the logic module 205 to complete corresponding tasks. In some embodiments, at least part of the first storage module 203 and one or more second storage modules 207 can also implement a small amount of logic control functions, that is, at least part of these storage modules are a combination of storage media and logic media, and this combination may be a one-dimensional structure, a two-dimensional structure or a three-dimensional structure. In some embodiments, the functions that the logic module 205 can implement include one or more of arithmetic, control, interface, and data processing.

[0041] The logic module 205 forms a conductive connection with the first storage module 203 and one or more second storage modules 207, thereby forming a conductive path in the storage module stack structure, enabling the logic module 205 to interact with the outside world through the storage module stack structure. In some embodiments, the logic module 205 is connected to the power supply through the storage module stack structure and is grounded through the side opposite to the storage module stack structure. In some other embodiments, the logic module 205 is grounded through the storage module stack structure and is connected to the power supply through the side opposite to the storage module stack structure.

[0042] In some embodiments, the logic module 205 includes a plurality of stacked sub-logic modules, and the adjacent surfaces of the plurality of stacked sub-logic modules form a conductive connection. In some embodiments, the sub-logic module closer to the storage module stack structure has lower power, and the sub-logic module farther from the storage module stack structure has higher power, which helps to dissipate the heat of the sub-logic module with higher power and reduce the impact of heat on the storage module.

[0043] In some embodiments, one or more second storage modules 207 can be omitted, and the storage module stack structure is replaced by the first storage module 203. That is, one side of the first storage module 203 forms a conductive connection with the logic module 205, and the other side of the first storage module 203 forms a conductive connection with the substrate 201. The above solution of placing the logic module on top of the storage module still applies to the case of only one storage module.

[0044] In some embodiments, the above-described manner of forming the conductive connection includes one or more of hybrid bonding connection and conductive bump connection. In some embodiments, the first storage module 203 may be directly or indirectly disposed on the substrate 201, and one or more second storage modules 207 as a whole may also be directly or indirectly disposed on the first storage module 203, and the logic module 205 may also be directly or indirectly disposed on one or more second storage modules 207. In some embodiments, adjacent means closest proximity, which may be either directly adjacent or indirectly adjacent. For example, when there are no other second storage modules 207 or other structures between two adjacent second storage modules 207, they are directly adjacent; when there are no other second storage modules 207 between two adjacent second storage modules 207 but there are other structures, they are indirectly adjacent; the second storage module 207 adjacent to the first storage module 203 refers to the second storage module 207 closest to the first storage module 203; the second storage module 207 adjacent to the logic module 205 refers to the second storage module 207 closest to the logic module 205.

[0045] In some embodiments, an external circuit (such as a GPU / CPU) is further disposed on the substrate 201. The external circuit and the first storage module 203 are connected through an external interface and the substrate 201, and the substrate 201 is then connected to a circuit board through an external pin (not shown in the figure). At this time, the logic module 205 is connected to power or ground through the storage module stack structure and the substrate 201. Further, the logic module 205 obtains a work instruction from the outside (external circuit) through the substrate 201 and via the storage module stack structure, completes the corresponding work, and transmits the processing result via the storage module stack structure and through the substrate 201 (transmitted to the external circuit).

[0046] In some embodiments, a silicon interposer is disposed between the first storage module 203 and the substrate 201 to provide high-density electrical connections using the silicon interposer. An external circuit (such as a GPU / CPU) is further disposed on the silicon interposer. The external circuit and the first storage module 203 are connected through an external interface and the silicon interposer, and the silicon interposer is then connected to an external pin through the external interface and the substrate 201, and finally connected to a circuit board through the external pin (not shown in the figure). At this time, the logic module 205 is connected to power and ground through the storage module stack structure and the silicon interposer. Further, the logic module 205 obtains a work instruction from the outside (external circuit) through the silicon interposer (or through the silicon interposer and the substrate 201) and via the storage module stack structure, completes the corresponding work, and transmits the processing result via the storage module stack structure and through the silicon interposer (or through the silicon interposer and the substrate 201) (transmitted to the external circuit).

[0047] In some embodiments, the substrate 201 is made of one or more of silicon, silicon germanium, germanium, silicon-on-insulator (SOI) film, and organic materials. In some embodiments, the first storage module 203 is Flash, RRAM, DRAM, MRAM, or SRAM, and the second storage module 207 is Flash, RRAM, DRAM, MRAM, or SRAM.

[0048] Figure 2 The structure shown provides convenience for the logic module 205 to dissipate heat through the side opposite to the storage module stack structure by arranging the logic module 205 on top of the storage module stack structure, avoiding heat accumulation caused by the obstruction of heat conduction in both the upper and lower directions of the logic module when the logic module is between the storage module stack structure and the substrate, and significantly reducing the impact of the heat generated by the logic module on the storage module.

[0049] As Figure 3 shown, a heat dissipation module 301 is arranged on the logic module 205. The heat dissipation module 301 can ensure that a large amount of heat generated by the logic module 205 during high-power operation is dissipated in time, so the power consumption tolerance of the logic module can be significantly improved. In some embodiments, the heat dissipation module 301 can be directly or indirectly arranged on the logic module 205. Generally speaking, the positional relationship among the storage module stack structure, the logic module 205, and the heat dissipation module 301 only needs to satisfy that the high-power logic module 205 is closer to the top heat dissipation module 301 than the storage module stack structure. In some embodiments, the heat dissipation module 301 forms an electrical connection with the logic module 205, and the logic module 205 uses the heat dissipation module 301 to connect to the power supply or ground. In some embodiments, the logic module 205 is directly connected to the heat dissipation module 301. In some embodiments, the logic module 205 is connected to the heat dissipation module 301 through a conductive spacer layer.

[0050] Furthermore, as Figure 4 shown, the three-dimensional stacked chip includes three second storage modules 207. The first storage module 203 includes a first substrate and a first interconnect layer 401 disposed on one side of the first substrate. The logic module 205 includes a second substrate and a second interconnect layer 402 disposed on one side of the second substrate. Each second storage module 207 includes a third substrate and a third interconnect layer 403 and a fourth interconnect layer 404 disposed on both sides of the third substrate. The first interconnect layer 401 of the first storage module 203 is bonded to the fourth interconnect layer 404 of the adjacent second storage module 207, and the second interconnect layer 402 of the logic module 205 is bonded to the third interconnect layer 403 of the adjacent second storage module 207.

[0051] When one side of the second storage module 207 is adjacent to other second storage modules 207, the third interconnection layer 403 of the second storage module 207 is bonded to the fourth interconnection layer 404 of the adjacent other second storage modules 207, or the fourth interconnection layer 401 of the second storage module 207 is bonded to the third interconnection layer 403 of the adjacent other second storage modules 207. When both sides of the second storage module 207 are adjacent to other second storage modules 207, the third interconnection layer 403 of the second storage module 207 is bonded to the fourth interconnection layer 404 of the other second storage modules 207 adjacent to one side, and the fourth interconnection layer 404 of the second storage module 207 is bonded to the third interconnection layer 403 of the other second storage modules 207 adjacent to the other side.

[0052] In some embodiments, when one or more second storage modules 207 are removed and only the first storage module 203 remains, the first interconnection layer 401 of the first storage module 203 is bonded to the second interconnection layer 402 of the logic module 205.

[0053] In some embodiments, the first interconnection layer 401 includes an insulating layer and a conductive structure formed in the insulating layer; the second interconnection layer 402 includes an insulating layer and a conductive structure formed in the insulating layer; the third interconnection layer 403 includes an insulating layer and a conductive structure formed in the insulating layer; the fourth interconnection layer 404 includes an insulating layer and a conductive structure formed in the insulating layer. In some embodiments, the bonding connection means that the insulating layers at the interface of the two interconnection layers form a chemical bond, and the conductive structures at the interface of the two interconnection layers undergo physical interdiffusion, thereby forming a bonding interface between the interconnection layers.

[0054] The storage module stack structure further includes a plurality of Through Silicon Vias (TSVs). Specifically, the first storage module 203 includes a plurality of first silicon vias 405 penetrating the first substrate, each second storage module 207 includes a plurality of second silicon vias 407 penetrating the third substrate, and the logic module 205 includes a plurality of third silicon vias 409 penetrating the second substrate. In some embodiments, forming the first silicon via includes forming a hole structure penetrating the first substrate and filling the hole structure with an insulating material and a conductive material; forming the second silicon via includes forming a hole structure penetrating the third substrate and filling the hole structure with an insulating material and a conductive material; forming the third silicon via includes forming a hole structure penetrating the second substrate and filling the hole structure with an insulating material and a conductive material.

[0055] Through the conductive structures in the first to fourth interconnect layers and the first and second through-silicon vias, the logic module 205 forms a conductive connection with the first memory module 203 and one or more second memory modules 207, and forms a conductive path in the memory module stack structure, enabling the logic module 205 to interact with the first memory module 203 and one or more second memory modules 207 for data, and to interact with the outside world through the memory module stack structure for signals. In some embodiments, the logic module 205 is connected to the power supply through the conductive structures in the first to fourth interconnect layers and the first and second through-silicon vias, and is connected to the ground through the third through-silicon via and the heat dissipation module. In some embodiments, the logic module 205 is connected to the ground through the conductive structures in the first to fourth interconnect layers and the first and second through-silicon vias, and is connected to the power supply through the third through-silicon via and the heat dissipation module.

[0056] Figures 5A - 5J is a schematic diagram of a method for manufacturing a three-dimensional stacked chip according to an embodiment of the present invention, Figure 6 is a flowchart of an example method 600 for manufacturing a three-dimensional stacked chip. First, in combination with Figures 5A - 5C the formation processes of the first memory structure, the logic structure, and the second memory structure required for manufacturing a three-dimensional stacked chip will be described.

[0057] Forming the first memory structure includes: forming a first memory device and a first interconnect layer on a first substrate. As Figure 5A shown, a first memory device is formed on the first substrate 501, and then a first interconnect layer 503 is formed on the first memory device. The first interconnect layer 503 includes an insulating layer 505 and a plurality of conductive structures 507 formed in the insulating layer 505. Obviously, the plane where the first interconnect layer 503 is located is the front face of the first memory structure, and the plane opposite to the first interconnect layer 503 is the back face of the first memory structure. In some embodiments, in addition to the storage function, the first memory device can also implement a small amount of logic control functions. In some embodiments, forming the first memory structure further includes: forming a conductive structure inserted into the first substrate according to a preset thinning amount of the first substrate.

[0058] Forming the logic structure includes: forming a logic device and a second interconnect layer on a second substrate. As Figure 5BAs shown, a logic device is formed on the second substrate 509, and then a second interconnect layer 511 is formed on the logic device. The second interconnect layer 511 includes an insulating layer 513 and a plurality of conductive structures 515 formed in the insulating layer 513. Obviously, the surface where the second interconnect layer 511 is located is the front face of the logic structure, and the face opposite to the second interconnect layer 511 is the back face of the logic structure. In some embodiments, the functions that the logic device can implement include one or more of arithmetic operation, control, interface, and data processing. In some embodiments, forming the logic structure further includes: forming a conductive structure inserted into the second substrate according to a preset thinning amount of the second substrate.

[0059] In a manner similar to forming the first storage structure, one or more (e.g., 3) second storage structures are formed. Specifically, a second storage device and a third interconnect layer are formed on the third substrate to form the second storage structure. As Figure 5C shown, a second storage device is formed on the third substrate 519, and then a third interconnect layer 521 is formed on the second storage device. The third interconnect layer 521 includes an insulating layer 523 and a plurality of conductive structures 525 formed in the insulating layer 523. Obviously, the surface where the third interconnect layer 521 is located is the front face of the second storage structure, and the face opposite to the third interconnect layer 521 is the back face of the second storage structure. In some embodiments, at least part of the second storage device can also implement a small amount of logic control functions in addition to the storage function. In some embodiments, forming the second storage structure further includes: forming a conductive structure inserted into the third substrate according to a preset thinning amount of the third substrate.

[0060] The exemplary method 600 begins at operation 601. As Figure 6 shown, the second storage structure is inverted, the third interconnect layer and the second interconnect layer are aligned, and the second storage structure and the logic structure are combined so that the second storage structure and the logic structure form a conductive connection through the third interconnect layer and the second interconnect layer. As Figure 5D shown, the second storage structure 526 and the logic structure 527 are combined in a face-to-face manner to form a bonding interface 528. Specifically, forming the bonding interface 528 includes: making the insulating layer 523 in the third interconnect layer 521 form a chemical bond at the interface with the insulating layer 513 in the second interconnect layer 511, and making the conductive structure 525 in the third interconnect layer 521 physically diffuse with the conductive structure 515 in the second interconnect layer 511 at the interface.

[0061] The exemplary method 600 continues at operation 603. As Figure 6 shown, the third substrate of the second storage structure is thinned, through-silicon vias penetrating the thinned third substrate are formed, and a fourth interconnect layer is formed on the thinned third substrate to form a second storage module.Figure 5E As shown, the third substrate 519 of the second storage structure 526 is thinned to obtain a thinned substrate 529, through-silicon vias 531 penetrating the substrate 529 are formed, a fourth interconnect layer 533 is further formed on the substrate 529, and then a second storage module 534 is formed. The fourth interconnect layer 533 includes an insulating layer 535 and a plurality of conductive structures 537 formed in the insulating layer 535. Obviously, the plane where the fourth interconnect layer 533 is located is the back of the second storage module 534. In some embodiments, the third substrate is thinned until the conductive structures inserted into the third substrate before are exposed, and the conductive structures form through-silicon vias penetrating the thinned third substrate.

[0062] In some embodiments, the insulating layer in the first to fourth interconnect layers is one or more insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the formation process of the conductive structures in the first to fourth interconnect layers includes: first forming openings in the insulating layer, and then filling the required openings with a conductor material. In some embodiments, the conductor materials for manufacturing the conductive structures include, but are not limited to, tungsten, cobalt, copper, aluminum, doped silicon, silicide, or a combination of the above materials. In some embodiments, filling the openings with a conductor material can be performed by ALD, CVD, PVD, and / or other suitable methods.

[0063] The exemplary method 600 continues with operation 605, as Figure 6 shown, in a manner similar to operations 601 and 603, more second storage modules are sequentially stacked on the second storage module to obtain a first stacked structure including a logic structure and a plurality of second storage modules. As Figure 5F shown, a second storage module 536 and a second storage module 538 are sequentially stacked on the second storage module 534. The second storage module 536 and the second storage module 534 are combined in a face-to-back manner to form a bonding interface 540. Specifically, the third interconnect layer 542 of the second storage module 536 is bonded to the fourth interconnect layer 533 of the second storage module 534. The second storage module 538 and the second storage module 536 are combined in a face-to-back manner to form a bonding interface 544. Specifically, the third interconnect layer 548 of the second storage module 538 is bonded to the fourth interconnect layer 546 of the second storage module 536. Similar to the second storage module 534, through-silicon vias 552 penetrating the substrate 550 are formed in the second storage module 536, and through-silicon vias 556 penetrating the substrate 554 are formed in the second storage module 538.

[0064] The exemplary method 600 continues with operation 607, as Figure 6As shown, invert the first storage structure, align the first interconnect layer and the fourth interconnect layer, and combine the first storage structure and the second storage module so that the first storage structure and the second storage module form a conductive connection through the first interconnect layer and the fourth interconnect layer. As Figure 5G As shown, the first storage structure 558 and the second storage module 538 are combined in a face-to-back manner to form a bonding interface 560. Specifically, the first interconnect layer 503 of the first storage structure 558 is bonded to the fourth interconnect layer 562 of the second storage module 538.

[0065] In some embodiments, the exemplary method 600 continues with operation 609, as Figure 6 As shown, thin the first substrate of the first storage structure to form a through-silicon via penetrating the thinned first substrate, thereby forming a first storage module; thin the second substrate of the logic structure to form a through-silicon via penetrating the thinned second substrate, thereby forming a logic module; the logic module, the plurality of second storage modules, and the first storage module form a second stacked structure. That is, when forming the through-silicon vias of the first storage module and the logic module, the substrates are both thinned. After connecting the power supply or ground through the side opposite to the storage module stacked structure, the number of through-silicon vias that need to be provided in the storage module stacked structure is significantly reduced. Therefore, by reasonably controlling the thinning amounts of the substrates of the first storage module and the logic module and the thinning amounts of the substrates of the previous plurality of second storage modules, the thickness of each substrate can not only meet the process and design requirements of the through-silicon vias for the corresponding structures, but also meet the need to provide sufficient support strength for the second stacked structure.

[0066] As Figure 5H As shown, thin the first substrate 501 of the first storage structure 558 to obtain the thinned substrate 560, form a through-silicon via 562 penetrating the substrate 560, thereby forming a first storage module 564; thin the second substrate 509 of the logic structure to obtain the thinned substrate 566, form a through-silicon via 568 penetrating the substrate 566, thereby forming a logic module 570.

[0067] In some embodiments, thin the first substrate until the conductive structure inserted into the first substrate is exposed, and this conductive structure forms a through-silicon via penetrating the thinned first substrate. In some embodiments, thin the second substrate until the conductive structure inserted into the second substrate is exposed, and this conductive structure forms a through-silicon via penetrating the thinned second substrate.

[0068] In some embodiments, the exemplary method 600 continues with operation 611, as Figure 6As shown, through-silicon vias are formed that penetrate the first substrate of the first memory structure, thereby forming a first memory module; the second substrate of the logic structure is thinned, through-silicon vias are formed that penetrate the thinned second substrate, thereby forming a logic module; the logic module, a plurality of second memory modules, and the first memory module form a second stacked structure. That is to say, when forming the through-silicon vias of the first memory module, the substrate is not thinned, and only when forming the through-silicon vias of the logic module, the substrate is thinned. This is because the memory module can tolerate a larger through-silicon via structure than the logic module. Especially after connecting the power supply or ground through the side opposite to the memory module stacked structure, the number of through-silicon vias that need to be provided in the memory module stacked structure including the first memory module is significantly reduced. Thus, the substrate of the first memory module is allowed to have a greater thickness, thereby providing sufficient support strength for the second stacked structure. Correspondingly, the substrate of the logic module can reach a sufficient thinning level to meet the process and design requirements of the through-silicon vias in the logic module.

[0069] As Figure 5I shown, through-silicon vias 572 are formed that penetrate the first substrate 501, thereby forming a first memory module 574; the second substrate 509 of the logic structure is thinned to obtain a thinned substrate 576, through-silicon vias 578 are formed that penetrate the substrate 576, thereby forming a logic module 580.

[0070] In some embodiments, the second substrate is thinned until the conductive structure previously inserted into the second substrate is exposed, and the conductive structure forms through-silicon vias that penetrate the thinned second substrate.

[0071] Example method 600 continues with operation 613, as Figure 6 shown, the back surface of the first memory module is conductively connected to the substrate. Taking the example where the substrate is thinned when forming the through-silicon vias of both the first memory module and the logic module, as Figure 5J shown, the back surface of the first memory module 564 is conductively connected to the substrate 582 through a conductive bump 584, and the other side of the substrate 582 is then conductively connected to the circuit board through a conductive bump.

[0072] In some embodiments, the first memory module further includes an interconnect layer formed on its back surface, and the first memory module forms a conductive connection with the substrate by means of the interconnect layer.

[0073] In some embodiments, an external circuit is further provided on the substrate, and the external circuit forms a conductive connection with the first memory module through the conductive structure in the substrate.

[0074] In some embodiments, a silicon interposer is introduced. The back surface of the first memory module forms a conductive connection with the silicon interposer, and the silicon interposer and the substrate form a conductive connection through conductive bumps. The other side of the substrate is then connected to the circuit board through conductive bumps. In some embodiments, an external circuit is also provided on the silicon interposer, and the external circuit forms a conductive connection with the first memory module through conductive structures in the silicon interposer and the substrate.

[0075] In some embodiments, a heat dissipation module is provided on the back surface of the logic module, and the back surface of the logic module forms a conductive connection with the heat dissipation module. On the one hand, the heat dissipation module is used to connect to the power supply or ground, and on the other hand, the heat dissipation module is used to dissipate a large amount of heat generated by the logic module during high-power operation. In some embodiments, the logic module further includes an interconnect layer formed on its back surface, and the logic module forms a conductive connection with the heat dissipation module by means of this interconnect layer. In some embodiments, the logic module is directly connected to the heat dissipation module. In some embodiments, the logic module and the heat dissipation module are connected through a conductive spacer layer.

[0076] In the above method, the step of forming one or more second storage structures can be omitted. Correspondingly, the first storage structure is inverted, and the first storage structure and the logic module are combined so that the first storage structure and the logic module form a conductive connection through the first interconnect layer and the second interconnect layer.

[0077] It should be noted that the above method for manufacturing a three-dimensional stacked chip is merely exemplary and should not be used to limit the present invention. The step content and / or sequence in the above method can be adjusted according to actual needs to obtain the same or similar technical effects. For example, the processes of forming the first storage structure and the logic module are independent of each other and there is no order between them. In addition, the step of combining the second storage structure and the logic module can be carried out after the manufacture of the first storage structure is completed, or can be carried out before the manufacture of the first storage structure is completed.

[0078] The present invention arranges the memory module stack structure between the logic module and the substrate, so that the logic module is arranged above the memory module stack structure, which provides great convenience for the heat dissipation of the logic module. The logic module is closer to the heat dissipation module than the memory module stack structure, avoiding the influence of the heat generated by the logic module on the memory module, and significantly improving the power consumption tolerance of the logic module. In addition, the logic module is connected to the power supply or ground through the side opposite to the memory module stack structure, avoiding the need for both the power supply and the ground to pass through the memory module stack structure. Therefore, the number of conductive vias (through-silicon vias) that need to be provided in the memory module stack structure can be effectively reduced.

[0079] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0080] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0081] Any process or method description represented in a flowchart or described in other ways herein can be understood to represent a module, segment, or portion of code including one or more (two or more) executable instructions for implementing a specific logical function or process. And the scope of the preferred embodiments of the present application includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed.

[0082] The logic and / or steps represented in a flowchart or described in other ways herein, for example, can be considered as a sequenced list of executable instructions for implementing a logical function, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in combination with these instruction execution systems, apparatus, or devices.

[0083] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the method in the above embodiments can be completed by a program instructing relevant hardware, and this program can be stored in a computer-readable storage medium. When this program is executed, it includes one or a combination of the steps of the method embodiment.

[0084] In addition, each functional unit in various embodiments of the present application may be integrated into one processing module, or each unit may exist physically alone, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the above-mentioned integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a magnetic disk, an optical disc, or the like.

[0085] As described above, the foregoing are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various changes or substitutions thereof, and these should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A three-dimensional stacked chip, characterized in that: It includes a substrate, a first storage module and a logic module; the first storage module and the logic module are stacked on the substrate in sequence, and the first storage module is arranged between the logic module and the substrate; the first storage module is used to provide and store data required by the logic module to support the logic module to complete corresponding work; the logic module exchanges signals with the outside world through the first storage module and the substrate.

2. The three-dimensional stacked chip according to claim 1, characterized in that: It also includes one or more stacked second storage modules, which are arranged between the first storage module and the logic module to form a storage module stacking structure with the first storage module; the one or more stacked second storage modules are used to provide and store data required by the logic module to support the logic module to complete corresponding tasks; the logic module exchanges signals with the outside world via the storage module stacking structure and the substrate.

3. The three-dimensional stacked chip according to claim 2, characterized in that: The logic module is connected to a power source via the memory module stacking structure, and is connected to a ground via a side opposite to the memory module stacking structure.

4. The three-dimensional stacked chip according to claim 2, characterized in that: The logic module is connected to the ground via the memory module stacking structure, and is connected to a power source via a side opposite to the memory module stacking structure.

5. The three-dimensional stacked chip according to claim 2, characterized in that: The logic module includes multiple stacked sub-logic modules, and the first storage module and the one or more stacked second storage modules are used to provide and store data required by the multiple stacked sub-logic modules, supporting the multiple stacked sub-logic modules to complete corresponding tasks.

6. The three-dimensional stacked chip according to claim 5, characterized in that: The sub-logic modules closer to the storage module stacking structure have lower power, and the sub-logic modules farther from the storage module stacking structure have higher power.

7. The three-dimensional stacked chip according to claim 2, characterized in that: The first storage module is directly or indirectly disposed on the substrate, the one or more stacked second storage modules are directly or indirectly disposed on the first storage module as a whole, and the logic module is directly or indirectly disposed on the one or more stacked second storage modules.

8. The three-dimensional stacked chip according to any one of claims 2 to 7, characterized in that: It also includes an external circuit, which is arranged on the substrate; the logic module obtains work instructions from the external circuit through the substrate and the storage module stacking structure, completes the corresponding work, and transmits the processing results through the storage module stacking structure and the substrate.

9. The three-dimensional stacked chip according to any one of claims 2 to 7, characterized in that: It also includes a silicon interposer and an external circuit, wherein the silicon interposer is arranged between the first storage module and the substrate, and the external circuit is arranged on the silicon interposer; the logic module obtains work instructions from the external circuit through the silicon interposer and the storage module stacking structure, completes corresponding work, and transmits the processing results through the storage module stacking structure and the silicon interposer.

10. The three-dimensional stacked chip according to any one of claims 2 to 7, characterized in that: It also includes a silicon interposer and an external circuit, wherein the silicon interposer is arranged between the first storage module and the substrate, and the external circuit is arranged on the silicon interposer; the logic module obtains work instructions from the external circuit through the silicon interposer and the substrate and via the storage module stacking structure, completes corresponding work, and transmits the processing results through the storage module stacking structure, through the silicon interposer and the substrate.

11. The three-dimensional stacked chip according to any one of claims 2 to 7, characterized in that: It also includes a heat dissipation module, which is directly or indirectly arranged on the logic module.

12. The three-dimensional stacked chip according to claim 11, characterized in that: The heat dissipation module forms a conductive connection with the logic module, and the logic module is connected to a power source or a ground via the heat dissipation module.

13. The three-dimensional stacked chip according to claim 12, characterized in that: The logic module is connected to the heat dissipation module through a conductive spacer layer.

14. A method for manufacturing a three-dimensional stacked chip, characterized in that: include: forming a first stacking structure; The first stacking structure includes a logic structure and one or more second storage modules sequentially stacked on the logic structure; The second stacking structure is formed by using the first storage structure and the first stacking structure; the second stacking structure includes a first storage module and one or more second storage modules and a logic module sequentially stacked on the first storage module, the first storage module is obtained by processing the first storage structure, and the logic module is obtained by processing the logic structure; A first memory module is connected to the substrate.

15. The method for manufacturing a three-dimensional stacked chip according to claim 14, characterized in that: The first memory structure includes a first substrate and a first memory device and a first interconnect layer formed on the first substrate; Processing the first storage structure to obtain the first storage module includes: forming a through silicon via penetrating the first substrate of the first storage structure.

16. The method for manufacturing a three-dimensional stacked chip according to claim 14, wherein: The first memory structure includes a first substrate and a first memory device and a first interconnect layer formed on the first substrate; Processing the first storage structure to obtain the first storage module includes: thinning the first substrate of the first storage structure to form a through silicon via penetrating the thinned first substrate.

17. The method for manufacturing a three-dimensional stacked chip according to claim 14, wherein: The logic structure includes a second substrate and a logic device and a second interconnect layer formed on the second substrate; Processing the logic structure to obtain the logic module includes: thinning the second substrate of the logic structure to form a through silicon via that penetrates the thinned second substrate.

18. The method for manufacturing a three-dimensional stacked chip according to any one of claims 14 to 17, characterized in that: The second memory module includes: a thinned third substrate, a second memory device and a third interconnection layer formed on the third substrate, and a fourth interconnection layer formed on the back side of the thinned third substrate.

19. The method for manufacturing a three-dimensional stacked chip according to any one of claims 14 to 17, characterized in that: Also includes: A heat dissipation module is provided on the logic module.

20. The method for manufacturing a three-dimensional stacked chip according to claim 19, characterized in that: A conductive spacer layer and a heat dissipation module are sequentially arranged on the logic module, and the logic module is connected to the heat dissipation module through the conductive spacer layer, so that the logic module can be connected to a power source or a ground via the heat dissipation module.

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