Silicon-on-insulator lateral insulated gate bipolar transistor device and preparation method thereof
By designing hole and electron extraction channels in SOI-LIGBT devices, the problem of large on-resistance and high shutdown loss is solved, and the rapid shutdown and conductance modulation effects are achieved.
Patent Information
- Application Number
- CN202510532033.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-25
- Publication Date
- 2025-06-20
AI Technical Summary
SOI-LIGBT devices have problems such as large on-resistance and high shutdown loss in high temperature, high voltage and high power environments.
A silicon-on-insulated gate bipolar transistor device is designed to form an electron extraction channel by setting a hole extraction channel between the two gates and a third trench and a fourth trench between the collector region and the N-type doped region.
It realizes rapid shutdown, reduces the device's turn-off loss, while maintaining the concentration of carriers in the N-type drift region, increasing the device's conductivity adjustment effect, and reducing on-resistance.
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Figure CN120187050A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of power semiconductors, and particularly relates to a silicon-on-insulator lateral insulated gate bipolar transistor device and a preparation method thereof. Background Art
[0002] The silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT, Silicon-On-Insulator Lateral Insulated Gate Bipolar Transistor) integrates the advantages of silicon-on-insulator (SOI, Silicon-On-Insulator) and insulated gate bipolar transistor (IGBT), and at the same time can be well compatible with the complementary metal oxide semiconductor (CMOS, Complementary Metal Oxide Semiconductor) process, making the SOI-LIGBT the core component of a monolithic power integration chip and playing a great role in many fields such as smart grids, smart home appliances, industry, medicine, aerospace, etc.
[0003] However, since SOI-LIGBT devices usually operate in high-temperature, high-voltage, and high-power environments, they face serious hot carrier effects and the problem of hot carrier degradation with an aggravated specific hole current component, resulting in a large on-resistance and high turn-off loss of SOI-LIGBT devices. Summary of the Invention
[0004] The embodiments of this application provide a silicon-on-insulator lateral insulated gate bipolar transistor device and a preparation method thereof, which can solve the problems of large on-resistance and high turn-off loss of SOI-LIGBT devices.
[0005] In a first aspect, the embodiments of this application provide a silicon-on-insulator lateral insulated gate bipolar transistor device, including a P-type substrate, a buried oxide layer, and an N-type drift region stacked in sequence, an emitter region and a collector region located on top of the N-type drift region, a P top layer provided on one side of the top of the N-type drift region close to the emitter region, a first trench and a second trench spaced between the emitter region and the P top layer, an N-type doped region provided on one side of the top of the N-type drift region close to the collector region, a third trench and a fourth trench spaced between the collector region and the N-type doped region, and the collector region is located between the P top layer and the third trench;
[0006] The middle part of one side of the P top layer close to the emitter region is in contact with the emitter region, both the first trench and the second trench are in contact with the emitter region, the upper surface of the first trench forms a first gate, the upper surface of the second trench forms a second gate, and a hole extraction channel is formed between the first trench and the second trench;
[0007] The third trench is filled with a first polysilicon layer, and the fourth trench is filled with a second polysilicon layer. A first oxide layer is formed between the third trench and the first polysilicon layer, and a second oxide layer is formed between the fourth trench and the second polysilicon layer. Both the third trench and the fourth trench are in contact with the collector region, the N-type drift region, and the N-type doping region. The bottom surfaces of both the third trench and the fourth trench are in contact with the top surface of the buried oxide layer. An electron extraction channel is formed between the third trench and the fourth trench.
[0008] Optionally, the depths of both the third trench and the fourth trench are greater than the depth of the N-type doping region.
[0009] Optionally, the widths of the first trench and the second trench are the same.
[0010] Optionally, P-type doping ions are deposited in the P top layer.
[0011] Optionally, the emitter region includes a P-well region, a P+ body contact region, and an N+ cathode region.
[0012] The P-well region is located at the top of the N-type drift region. Both the P+ body contact region and the N+ cathode region are located at the top of the P-well region. The P+ body contact region and the N+ cathode region are in contact with each other to form an emitter. Both the N+ cathode region and the P-well region are in contact with the first trench and the second trench.
[0013] Optionally, the depths of the P+ body contact region and the N+ cathode region are the same.
[0014] In a second aspect, an embodiment of the present application provides a method for manufacturing an SOI lateral insulated gate bipolar transistor device, which is applied to the above SOI lateral insulated gate bipolar transistor device. The manufacturing method includes:
[0015] Form a buried oxide layer on a P-type substrate, and form an N-type drift region on the buried oxide layer.
[0016] Etch trenches on the N-type drift region to form a first trench, a second trench, a third trench, a fourth trench, and a fifth trench on the N-type drift region.
[0017] After preheating and oxidizing to grow 500 angstroms of sacrificial oxygen in both the first trench and the second trench, perform dry oxygen treatment to form a gate oxide structure, and form a first gate on the upper surface of the gate oxide structure in the first trench and a second gate on the upper surface of the gate oxide structure in the second trench.
[0018] Form a first oxide layer on the inner wall of the third trench and a second oxide layer on the inner wall of the fourth trench.
[0019] Deposit and grow polysilicon in the third trench formed with the first oxide layer and the fourth trench formed with the second oxide layer respectively, so that the third trench is filled with a first polysilicon layer and the fourth trench is filled with a second polysilicon layer.
[0020] Deposit and grow P-type doped ions in the fifth trench by low-pressure chemical vapor deposition to form a P top layer;
[0021] Form a P-well region of the emitter region on one side of the N-type drift region near the first trench, and form an N-type buffer layer of the collector region at a position near the third trench on the top of the N-type drift region;
[0022] Through ion implantation, form a P+ body contact region and an N+ cathode region of the emitter region on the top of the P-well region; the P+ body contact region and the N+ cathode region are arranged in parallel and in contact with each other to form an emitter;
[0023] Through ion implantation, form a P+ collector on the N-type buffer layer, and through ion implantation, form an N-type doped region on one side of the N-type drift region near the third trench;
[0024] Wherein, the first gate and the second gate are both located between the emitter region and the P top layer, the collector region is located between the P top layer and the third trench, and the third trench and the fourth communication are both located between the collector region and the N-type doped region;
[0025] The middle part of one side of the P top layer near the emitter region is in contact with the emitter region, and the first trench and the second trench are both in contact with the emitter region; the third trench and the fourth trench are both in contact with the collector region, the N-type drift region, and the N-type doped region, and the bottom surfaces of the third trench and the fourth trench are both in contact with the top surface of the buried oxide layer.
[0026] Optionally, the preparation method further includes:
[0027] Perform planarization treatment on the polysilicon in the third trench and the fourth trench.
[0028] The above solution of the present application has the following beneficial effects:
[0029] In the embodiment of the present application, there is a hole extraction channel between the two gates of the device, a third trench and a fourth communication structure are arranged between the collector region and the N-type doped region, and an electron extraction channel is formed between the third trench and the fourth communication. Since the hole extraction channel is connected to the emitter region, when a voltage is applied to the gates of the silicon-on-insulator lateral insulated gate bipolar transistor device, a hole barrier is formed between the two gates, thereby blocking the hole extraction channel to achieve fast turn-off, reducing the turn-off loss of the device, and at the same time maintaining the carrier concentration in the N-type drift region, increasing the conductivity modulation effect of the device, reducing the on-resistance of the device, and further reducing the loss when the device is turned on.
[0030] In addition, when the carrier concentration in the N-type drift region of the silicon-on-insulator lateral insulated gate bipolar transistor device decreases, the electron extraction channel between the third trench and the fourth trench can extract electrons from the N-type doping region into the N-type drift region, maintaining the carrier concentration in the N-type drift region while ensuring performance, achieving rapid extraction of electrons, enhancing the conductivity modulation effect of the silicon-on-insulator lateral insulated gate bipolar transistor device, greatly reducing the on-resistance, achieving rapid turn-off, and further reducing the turn-off loss.
[0031] Other beneficial effects of this application will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0033] Figure 1 Schematic structural diagram of a silicon-on-insulator lateral insulated gate bipolar transistor device provided by an embodiment of this application;
[0034] Figure 2a is Figure 1 Forward conduction mechanism diagram of the cross-section along A-A';
[0035] Figure 2b is Figure 1 Forward turn-off mechanism diagram of the cross-section along A-A';
[0036] Figure 3a is Figure 1 Forward conduction mechanism diagram of the cross-section along C-C';
[0037] Figure 3b is Figure 1 Forward turn-off mechanism diagram of the cross-section along C-C';
[0038] Figure 4 Flowchart of the manufacturing method of a silicon-on-insulator lateral insulated gate bipolar transistor device provided by an embodiment of this application.
[0039]
DESCRIPTION OF THE REFERENCE NUMERALS
[0040] 100, P-type substrate; 200, buried oxide layer; 300, N-type drift region; 400, emitter region; 500, collector region; 600, P top layer; 701, first gate; 702, second gate. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0041] In the following description, for purposes of illustration and not limitation, specific details such as particular system architectures, technologies, etc. are set forth in order to provide a thorough understanding of embodiments of the present application. However, those skilled in the art should understand that the present application may be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary details.
[0042] It should be understood that when used in the specification and claims of the present application, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or their combinations.
[0043] It should also be understood that the term "and / or" as used in the specification and claims of the present application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0044] As used in the specification and claims of the present application, the term "if" may be construed, depending on the context, as "when" or "once" or "in response to determining" or "in response to detecting". Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be construed, depending on the context, as meaning "once determined" or "in response to determining" or "once detected [the described condition or event]" or "in response to detecting [the described condition or event]".
[0045] In addition, in the description of the specification and claims of the present application, the terms "first", "second", "third", etc. are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.
[0046] Reference to "an embodiment" or "some embodiments" or the like described in the specification of the present application means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, statements such as "in an embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "comprising", "including", "having", and their variants all mean "including but not limited to", unless otherwise specifically emphasized in another way.
[0047] In view of the problems of large on-resistance and high turn-off loss of current SOI-LIGBT devices, an embodiment of the present application provides a silicon-on-insulator lateral insulated-gate bipolar transistor device. A hole extraction channel is provided between two gates of the device, a third trench and a fourth communication structure are provided between the collector region and the N-type doped region, and an electron extraction channel is formed between the third trench and the fourth communication. Since the hole extraction channel is connected to the emitter region, when the silicon-on-insulator lateral insulated-gate bipolar transistor device is gated, a hole barrier is formed between the two gates, thereby blocking the hole extraction channel to achieve fast turn-off, reducing the turn-off loss of the device, and at the same time maintaining the carrier concentration in the N-type drift region, increasing the conductivity modulation effect of the device, reducing the on-resistance of the device, and further reducing the loss when the device is turned on.
[0048] In addition, when the carrier concentration in the N-type drift region of the silicon-on-insulator lateral insulated-gate bipolar transistor device decreases, the electron extraction channel between the third trench and the fourth trench can extract electrons from the N-type doped region into the N-type drift region, maintaining the carrier concentration in the N-type drift region while ensuring performance, achieving fast extraction of electrons, enhancing the conductivity modulation effect of the silicon-on-insulator lateral insulated-gate bipolar transistor device, greatly reducing the on-resistance, achieving fast turn-off, and further reducing the turn-off loss.
[0049] The silicon-on-insulator lateral insulated-gate bipolar transistor device provided by the present application will be exemplarily described below in conjunction with specific embodiments.
[0050] As Figure 1 shown, the silicon-on-insulator lateral insulated-gate bipolar transistor device provided by the embodiment of the present application includes a P-type substrate 100, a buried oxide layer 200, and an N-type drift region 300 stacked in sequence, an emitter region 400 and a collector region 500 located on the top of the N-type drift region 300, a P top layer 600 (i.e., P-top layer) is provided on one side of the top of the N-type drift region 300 close to the emitter region 400, a first trench and a second trench are provided at intervals between the emitter region 400 and the P top layer 600, an N-type doped region (i.e., C2 in the figure) is provided on one side of the top of the N-type drift region 300 close to the collector region 500, a third trench and a fourth trench (i.e., C1 in the figure) are provided at intervals between the collector region 500 and the N-type doped region, and the collector region 500 is located between the P top layer 600 and the third trench.
[0051] The middle part of one side of the P top layer 600 close to the emitter region 400 is in contact with the emitter region 400. Both the first trench and the second trench are in contact with the emitter region 400. The upper surface of the first trench forms the first gate 701, and the upper surface of the second trench forms the second gate 702. A hole extraction channel is formed between the first trench and the second trench. When the device is in the on state, the first gate 701 and the second gate 702 are pressurized, and hole barriers are formed inside the first gate 701 and inside the second gate 702, thereby blocking the path of the hole extraction channel (Adaptive Hole Channel, AHC). At the same time, the carrier concentration in the N-type drift region 300 is maintained, and the conductance modulation effect of the device is increased, thereby greatly reducing the on-resistance of the device to reduce the loss during conduction.
[0052] The third trench is filled with a first polysilicon layer, and the fourth trench is filled with a second polysilicon layer. A first oxide layer is formed between the third trench and the first polysilicon layer, and a second oxide layer is formed between the fourth trench and the second polysilicon layer. Both the third trench and the fourth trench are in contact with the collector region 500, the N-type drift region 300, and the N-type doped region. The bottom surfaces of the third trench and the fourth trench are both in contact with the top surface of the buried oxide layer 200. An electron extraction channel is formed between the third trench and the fourth trench. Specifically, the gap between the third trench and the fourth trench filled with the polysilicon layer constitutes the electron extraction channel. Compared with the prior art, the electron extraction channel is voltage-controlled by the third trench and the fourth trench filled with the polysilicon layer. Electrons are connected to the collector through the electron extraction channel. When the device is turned on, an electron barrier is formed between the third trench and the fourth trench filled with the polysilicon layer, thereby closing the electron extraction channel connecting the N-type doped region and the collector region 500 between the third trench and the fourth trench. Conversely, when the device is turned off, the electron extraction channel is opened to achieve fast turn-off and reduce the turn-off loss of the device.
[0053] The depths of the above-mentioned third trench and fourth trench are both greater than the depth of the N-type doped region. The widths of the above-mentioned first trench and second trench are the same, and the depths of the above-mentioned first trench and second trench are both greater than the depth of the P top layer 600. P-type doped ions are deposited in the P top layer 600, specifically, P-type doped ions of 3×10 15 cm -3 can be used.
[0054] In some embodiments of the present application, 500 Å of sacrificial oxygen can be pre-oxidized and grown in the first trench and the second trench, and then a gate oxide structure is formed by dry oxygen treatment. Then, the first gate 701 is formed on the upper surface of the gate oxide structure in the first trench, and the second gate 702 is formed on the upper surface of the gate oxide structure in the second trench. It can be understood that the materials of the first gate 701 and the second gate 702 can both be metal or polysilicon.
[0055] In some embodiments of the present application, the above-mentioned emitter region 400 includes a P-well region, a P+ body contact region, and an N+ cathode region.
[0056] The P-well region is located on top of the N-type drift region 300. Both the P+ body contact region and the N+ cathode region are located on top of the P-well region. The P+ body contact region and the N+ cathode region are in contact with each other to form the emitter. Both the N+ cathode region and the P-well region are in contact with the first trench and the second trench. The middle part of the side of the P top layer 600 close to the emitter region 400 is in contact with the P+ body contact region. The depths of the P+ body contact region and the N+ cathode region are the same. In the on state, the emitter region 400 is depleted by the first gate 701 and the second gate 702, and the hole extraction channel is pinched off to maintain a high injection efficiency. The P top layer 600 is higher than the N-type drift region 300, which results in a reduced on-state voltage. During the turn-off transient process, the P-well region only adaptively returns to the neutral region, and then the hole extraction channel is opened.
[0057] In some embodiments of the present application, the above-mentioned collector region 500 includes an N-type buffer layer located on top of the N-type drift region 300, and a P+ collector is formed on the N-type buffer layer. Wherein, the N-type buffer layer is in contact with the third trench and the fourth trench.
[0058] In some embodiments of the present application, as Figure 1 、 Figure 2a and Figure 2b shown, a hole barrier is formed inside the first gate and inside the second gate. In the on state, the emitter region (i.e., the depletion region in the figure) is depleted by the trench gate, and the hole path is pinched off to maintain a high injection efficiency. The P top layer region is higher than the N-type drift region, which results in a low on-state voltage (VON). During the turn-off transient process, the P-well region adaptively returns to the neutral region, and then the hole channel is opened. As Figure 1 、 Figure 3a and Figure 3b shown, an electron barrier is formed between the third trench and the fourth trench. When the device is in forward conduction and the collector (i.e., the P+ collector) voltage increases, the P+ in the collector region injects holes into the N-type drift region. The third trench and the fourth trench (i.e., C1 in the figure) are under reverse voltage. The N-type doped region (i.e., C2 in the figure) is connected to the collector. The mutual depletion between the third trench and the fourth trench increases the channel distribution resistance of the C2 and C1 regions, blocking the channel between the C2 region and the N-type drift region. When the device is in reverse cut-off, due to the conductance modulation effect, the collector and the emitter jointly inject electrons and holes into the N-type drift region. As the gate voltage decreases, C1 is under forward voltage, the depletion region becomes narrower, the electron channel is opened, and a large number of electron-hole pairs are accumulated in the body and extracted through this path. The extracted electrons recombine with the holes in the P-type heavily doped region (i.e., the P top layer) at the collector, accelerating the turn-off of the device and reducing the tail current, and reducing the turn-off loss.
[0059] In summary, the silicon-on-insulator lateral insulated gate bipolar transistor device provided by the present application is provided with an adaptive hole extraction channel between two gates. The adaptive hole extraction channel is controlled by a polysilicon gate electrode, and holes pass through the adaptive hole extraction channel and are connected to the emitter. Since the hole extraction channel is connected to the emitter region, when a voltage is applied to the gates of the silicon-on-insulator lateral insulated gate bipolar transistor device, a hole barrier is formed between the two gates, thereby blocking the hole extraction channel to achieve fast turn-off, reducing the turn-off loss of the device. At the same time, the concentration of carriers in the N-type drift region is maintained, the conductivity modulation effect of the device is increased, the on-resistance of the device is reduced, and thus the loss during device conduction is reduced.
[0060] In addition, a third trench and a fourth communication structure are provided between the collector region and the N-type doped region, and an adaptive electron extraction channel is formed between the third trench and the fourth communication. Electrons pass through the adaptive electron extraction channel and are connected to the collector. When the carrier concentration in the N-type drift region of the silicon-on-insulator lateral insulated gate bipolar transistor device decreases, the electron extraction channel between the third trench and the fourth trench can extract electrons from the N-type doped region into the N-type drift region, maintaining the carrier concentration in the N-type drift region while ensuring performance, achieving fast extraction of electrons, enhancing the conductivity modulation effect of the silicon-on-insulator lateral insulated gate bipolar transistor device, greatly reducing the on-resistance, achieving fast turn-off, and further reducing the turn-off loss.
[0061] The design of the adaptive hole extraction channel and the adaptive electron extraction channel enables holes and electrons to quickly enter the emitter / collector terminal and be injected into the semiconductor layer, thereby effectively improving the device efficiency and power density while reducing the leakage current.
[0062] Through TCAD simulation software, structural simulation and electrical characteristic simulation studies are carried out. Compared with the traditional SOI-LIGBT device, the turn-off loss of the silicon-on-insulator lateral insulated gate bipolar transistor device of the present application is reduced by 46.3% under the condition that the same on-state voltage drop is 1.05V. The on-resistance of the device is reduced, and the turn-off loss is reduced.
[0063] The following is an exemplary description of the preparation method of the silicon-on-insulator lateral insulated gate bipolar transistor device provided by the present application in combination with specific embodiments.
[0064] In some embodiments of the present application, the preparation method provided by the embodiments of the present application is mainly only used for the above-mentioned silicon-on-insulator lateral insulated gate bipolar transistor device.
[0065] As Figure 4 shown, the preparation method of the above-mentioned silicon-on-insulator lateral insulated gate bipolar transistor device includes the following steps:
[0066] Step 41: Form a buried oxide layer on the P-type substrate and form an N-type drift region on the buried oxide layer.
[0067] Step 42: Etch trenches on the N-type drift region to form a first trench, a second trench, a third trench, a fourth trench, and a fifth trench on the N-type drift region.
[0068] The above-mentioned first trench, second trench, third trench, fourth trench, and fifth trench can all be rectangular trenches. Specifically, rectangular trenches can be formed by etching through a mask.
[0069] Step 43: After preheating and oxidizing to grow 500 Å of sacrificial oxygen in both the first trench and the second trench, perform dry oxidation to form a gate oxide structure, form a first gate on the upper surface of the gate oxide structure in the first trench, and form a second gate on the upper surface of the gate oxide structure in the second trench.
[0070] Step 44: Form a first oxide layer on the inner wall of the third trench and form a second oxide layer on the inner wall of the fourth trench.
[0071] The thicknesses of the above-mentioned first oxide layer and second oxide layer can both be 500 Å.
[0072] Specifically, sacrificial oxygen can be preheated and oxidized and then dry oxidized on the inner wall of the third trench to form the first oxide layer, and sacrificial oxygen can be preheated and oxidized and then dry oxidized on the inner wall of the fourth trench to form the second oxide layer.
[0073] Step 45: Deposit and grow polysilicon in the third trench formed with the first oxide layer and the fourth trench formed with the second oxide layer respectively, so that the third trench is filled with a first polysilicon layer and the fourth trench is filled with a second polysilicon layer.
[0074] Specifically, low-pressure chemical vapor deposition can be used to deposit and grow polysilicon in the third trench and the fourth trench respectively, so that the third trench is filled with a first polysilicon layer and the fourth trench is filled with a second polysilicon layer.
[0075] It can be understood that after forming polysilicon layers in the third trench and the fourth trench, the polysilicon in the third trench and the fourth trench can also be planarized to flatten the excess silicon on the surface, so that the 、 top surfaces of the first polysilicon layer, the second polysilicon layer, and the N-type drift region are in the same horizontal plane.
[0076] Step 46: Deposit and grow P-type doped ions in the fifth trench by low-pressure chemical vapor deposition to form a P top layer.
[0077] Step 47, form a P-well region of the emitter region on one side of the top of the N-type drift region near the first trench, and form an N-type buffer layer of the collector region at a position on the top of the N-type drift region near the third trench.
[0078] Specifically, an ion implanter can be used to implant ions under the action of a mask plate to form a P-well region of the emitter region on one side of the top of the N-type drift region near the first trench, and form an N-type buffer layer of the collector region at a position on the top of the N-type drift region near the third trench.
[0079] Step 48, through ion implantation, form a P+ body contact region and an N+ cathode region of the emitter region on the top of the P-well region.
[0080] The P+ body contact region and the N+ cathode region are arranged in parallel and in contact with each other to form the emitter.
[0081] Specifically, through ion implantation, a P+ body contact region and an N+ cathode region of the emitter region can be formed on the top of the P-well region.
[0082] It should be noted that when performing ion implantation, the ions implanted in the P-well region are boron ions, the ions implanted in the P+ body contact region are boron ions, and the ions implanted in the N+ cathode region are phosphorus ions.
[0083] Step 49, through ion implantation, form a P+ collector on the N-type buffer layer, and through ion implantation, form an N-type doped region on one side of the top of the N-type drift region near the third trench.
[0084] Specifically, through ion implantation, a P+ collector can be formed on the N-type buffer layer, and through ion implantation, an N-type doped region can be formed on one side of the top of the N-type drift region near the third trench, to obtain a silicon-on-insulator lateral insulated-gate bipolar transistor device as shown in Figure 1 It should be noted that when performing ion implantation, the ions implanted in the N-type buffer layer are phosphorus ions, the ions implanted in the P+ collector are boron ions, and the ions implanted in the N-type doped region are phosphorus ions.
[0085] Among them, both the first gate and the second gate are located between the emitter region and the P top layer, the collector region is located between the P top layer and the third trench, and both the third trench and the fourth communication are located between the collector region and the N-type doped region.
[0086] The middle part of one side of the P top layer close to the emitter region is in contact with the emitter region, and both the first trench and the second trench are in contact with the emitter region and the P top layer; both the third trench and the fourth trench are in contact with the collector region, the N-type drift region, and the N-type doped region, and the bottom surfaces of both the third trench and the fourth trench are in contact with the top surface of the buried oxide layer.
[0087] It can be understood that during the preparation process of the silicon-on-insulator lateral insulated gate bipolar transistor device, after completing step 49, dry etching can also be used to form contact holes and form a passivation layer.
[0088] It is worth mentioning that the silicon-on-insulator lateral insulated gate bipolar transistor device prepared by the above preparation method has an adaptive hole extraction channel and an adaptive electron extraction channel. These two channels enable holes and electrons to quickly enter the emitter / collector terminal and be injected into the semiconductor layer, thereby effectively improving the device efficiency and power density while reducing the leakage current.
[0089] The above are the preferred embodiments of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle described in the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.
Claims
1. A silicon-on-insulator lateral insulated gate bipolar transistor device, comprising a P-type substrate, a buried oxide layer and an N-type drift region stacked in sequence, an emitter region and a collector region located on top of the N-type drift region, characterized in that: A P top layer is provided on a side of the top of the N-type drift region close to the emitter region, a first trench and a second trench are provided between the emitter region and the P top layer, an N-type doping region is provided on a side of the top of the N-type drift region close to the collector region, a third trench and a fourth trench are provided between the collector region and the N-type doping region, and the collector region is located between the P top layer and the third trench; The middle part of the P top layer close to the emitter region is in contact with the emitter region, the first trench and the second trench are both in contact with the emitter region, a first gate is formed on the upper surface of the first trench, a second gate is formed on the upper surface of the second trench, and a hole extraction channel is formed between the first trench and the second trench; The third trench is filled with a first polysilicon layer, the fourth trench is filled with a second polysilicon layer, a first oxide layer is formed between the third trench and the first polysilicon layer, and a second oxide layer is formed between the fourth trench and the second polysilicon layer; the third trench and the fourth trench are both in contact with the collector region, the N-type drift region, and the N-type doped region, the bottom surface of the third trench and the bottom surface of the fourth trench are both in contact with the top surface of the buried oxide layer, and an electron extraction channel is formed between the third trench and the fourth trench.
2. The silicon-on-insulator lateral insulated gate bipolar transistor device according to claim 1, characterized in that: The depths of the third trench and the fourth trench are both greater than the depth of the N-type doping region.
3. The silicon-on-insulator lateral insulated gate bipolar transistor device according to claim 1, characterized in that: The first trench and the second trench have the same width.
4. The silicon-on-insulator lateral insulated gate bipolar transistor device according to claim 1, characterized in that: P-type doping ions are deposited in the P top layer.
5. The silicon-on-insulator lateral insulated gate bipolar transistor device according to claim 1, characterized in that: The emitter region includes a P well region, a P+ body contact region and an N+ cathode region; The P-well region is located at the top of the N-type drift region, the P+ body contact region and the N+ cathode region are both located at the top of the P-well region, the P+ body contact region and the N+ cathode region are in contact with each other to form an emitter, and the N+ cathode region and the P-well region are both in contact with the first trench and the second trench.
6. The silicon-on-insulator lateral insulated gate bipolar transistor device according to claim 5, characterized in that: The P+ body contact region and the N+ cathode region have the same depth.
7. A method for preparing a silicon-on-insulator lateral insulated gate bipolar transistor device, characterized in that: Applicable to the silicon-on-insulator lateral insulated gate bipolar transistor device according to any one of claims 1 to 6, the preparation method comprising: Forming a buried oxide layer on a P-type substrate, and forming an N-type drift region on the buried oxide layer; Etching trenches on the N-type drift region to form a first trench, a second trench, a third trench, a fourth trench and a fifth trench on the N-type drift region; After preheating and oxidizing to grow 500 angstroms of sacrificial oxygen in both the first trench and the second trench, dry oxygen treatment is performed to form a gate oxide structure, and a first gate is formed on the upper surface of the gate oxide structure in the first trench, and a second gate is formed on the upper surface of the gate oxide structure in the second trench; forming a first oxide layer on an inner wall of the third trench, and forming a second oxide layer on an inner wall of the fourth trench; Depositing and growing polysilicon in the third trench where the first oxide layer is formed and in the fourth trench where the second oxide layer is formed, respectively, so that the third trench is filled with the first polysilicon layer and the fourth trench is filled with the second polysilicon layer; Depositing and growing P-type doping ions in the fifth trench by low pressure chemical vapor deposition to form a P top layer; Forming a P-well region of an emitter region on one side of the top of the N-type drift region close to the first trench, and forming an N-type buffer layer of a collector region at a position of the top of the N-type drift region close to the third trench; By ion implantation, a P+ body contact region and an N+ cathode region of the emitter region are formed on the top of the P well region; the P+ body contact region and the N+ cathode region are arranged in parallel and contact each other to form an emitter; Forming a P+ collector on the N-type buffer layer by ion implantation, and forming an N-type doping region on a side of the top of the N-type drift region close to the third trench by ion implantation; Wherein, the first gate and the second gate are both located between the emitter region and the P top layer, the collector region is located between the P top layer and the third trench, and the third trench and the fourth channel are both located between the collector region and the N-type doped region; The middle part of the P top layer close to the emitter region is in contact with the emitter region, and the first groove and the second groove are both in contact with the emitter region; the third groove and the fourth groove are both in contact with the collector region, the N-type drift region, and the N-type doped region, and the bottom surface of the third groove and the bottom surface of the fourth groove are both in contact with the top surface of the buried oxide layer.
8. The preparation method according to claim 7, characterized in that: The preparation method further comprises: The polysilicon in the third trench and the fourth trench is planarized.