LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and preparation method

Abstract

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate on which a gate structure is formed; the drift regions are symmetrically arranged in the substrate on two sides of the gate structure; the source region and the drain region are symmetrically arranged on the drift region on the two sides of the gate structure, and the source region and the drain region are interchangeable; the isolation layer is located on the drift region between the source region and the drain region; and the floating field plates are positioned at the top of the isolation layer and are uniformly and symmetrically distributed on two sides of the gate structure. The floating field plate is not connected with the gate structure, the source region or the drain region, leakage current is avoided, the electric field distribution of the drift region is more uniform by forming the floating field plate, the surface electric field peak value of the device is reduced, and the voltage resistance of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to an LDMOS device and a manufacturing method thereof. Background Art

[0002] In semiconductor processes, a laterally diffused metal oxide semiconductor (LDMOS) device is a semiconductor device applied to radio frequency circuits and is commonly used in radio frequency power circuits. High-voltage LDMOS is often used in high-voltage power integrated circuits to meet requirements such as high voltage resistance and power control, and has characteristics such as high reliability, high integration, and fast switching speed. However, in LDMOS devices, electric field lines are prone to concentrating in the channel region, the electric field distribution is concentrated in the edge region, and the electric field distribution is uneven in each region, which affects the device performance. The field plate structure can redistribute the surface electric field to reduce the local strong electric field region and improve the breakdown voltage of the device. However, the electrical performance of current LDMOS devices still needs to be improved. Therefore, an LDMOS device and a manufacturing method thereof are needed to solve the above problems. Summary of the Invention

[0003] The present invention provides an LDMOS device and a manufacturing method thereof to solve all or part of the above-mentioned problems of the prior art. By means of a floating field plate, the electric field distribution in the drift region is made more uniform, the peak value of the surface electric field of the device is reduced, and the breakdown voltage of the device is increased. When a high voltage is applied to the device, the potential of the drift region rises, and the potential of the floating field plate is adjusted accordingly to help redistribute the electric field and relieve the electric field concentration; the potential is dynamically adjusted according to the working state of the device, and the electric field distribution can be effectively controlled even when the device is in a high-voltage state.

[0004] The present invention provides an LDMOS device, including a substrate, on which a gate structure is formed; a drift region symmetrically disposed on the source region and the drain region of the substrate on both sides of the gate structure, and symmetrically disposed on the drift region on both sides of the gate structure, and the source region and the drain region are interchangeable; an isolation layer located on the drift region between the source region and the drain region; a floating field plate located on the top of the isolation layer and uniformly and symmetrically distributed on both sides of the gate structure. The floating field plate is not connected to the gate structure or the drain region to avoid the generation of leakage current. By forming the floating field plate, the electric field distribution in the drift region is made more uniform, the peak value of the surface electric field of the device is reduced, and the breakdown voltage of the device is increased.

[0005] The floating field plate is in a "convex" shape structure, including a large rectangular part and a small rectangular part connected to one side of the large rectangular part, so as to make the current distribution more uniform.

[0006] A plurality of the floating field plates are regularly spaced in the vertical and horizontal directions; the orientation directions of the small rectangular parts of two adjacent columns are opposite to make the electric field distribution more uniform.

[0007] Sidewall structures are formed on both sides of the gate structure and the floating field plate, and silicide layers are formed on the tops. The sidewall structures protect the sidewalls of the gate structure and the floating field plate; the silicide layers are formed by self-alignment technology.

[0008] It further includes a dielectric layer, which covers the gate structure, the floating field plate, and the substrate. The dielectric layer is used to achieve electrical isolation between conductive structures and between adjacent devices.

[0009] It further includes plug structures, namely a source region plug structure, a drain region plug structure, and a gate plug structure; the drain region plug structure is located on the top of the drain region and penetrates the dielectric layer; the source region plug structure is located on the top of the source region and penetrates the dielectric layer; the gate plug structure is located on the top of the gate structure and penetrates the dielectric layer. It is used to realize the connection with the external circuit.

[0010] The isolation layer is a shallow trench isolation structure; it provides electrical isolation between different active regions; the gate structure material is polysilicon; the floating field plate material is polysilicon.

[0011] It also provides a method for manufacturing an LDMOS device, manufacturing the LDMOS device described in any one of the above, including the following steps: S1: Provide a substrate, in which a drift region, a source region, a drain region, and an isolation layer are formed; S2: Deposit undoped polysilicon on the substrate to form a polysilicon layer; S3: Perform ion implantation on the polysilicon layer; S4: Etch the polysilicon layer to form a polysilicon gate structure and a polysilicon floating field plate, and form the floating field plate, which can improve the uniformity of the electric field distribution.

[0012] It further includes S5: Form sidewall structures on both sides of the polysilicon gate structure and the polysilicon floating field plate, and then form silicide layers on the tops of the polysilicon gate structure and the polysilicon floating field plate; S6: Deposit a dielectric layer; S7: Form a source region plug structure, a drain region plug structure, and a gate plug structure. The method is used for platforms below 40nm in advanced processes. By means of the floating field plate, the uniformity of the electric field distribution is improved. The device can effectively control the electric field distribution under high voltage conditions, the electric field peak value is reduced, and the breakdown voltage is increased.

[0013] Compared with the prior art, the beneficial effects of the present invention mainly include the following: The floating field plate is not connected to the gate structure or the drain region, avoiding the generation of leakage current; through the floating field plate, the electric field distribution in the drift region is more uniform. When a high voltage is applied to the device, the potential of the drift region rises, and the potential of the floating field plate is adjusted accordingly, redistributing the electric field and alleviating the electric field concentration; The potential is dynamically adjusted according to the working state of the device. The device can effectively control the electric field distribution under high voltage conditions, the electric field peak value is reduced, and the breakdown voltage of the device is increased. Description of the Drawings

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0015] Figure 1 It is a schematic cross-sectional structure diagram of an LDMOS device provided by the present invention.

[0016] Figure 2 It is a schematic partial cross-sectional structure diagram of an LDMOS device provided by the present invention.

[0017] Figure 3 It is a top view structure diagram of an LDMOS device provided by the present invention.

[0018] Figure 4 It is a flowchart of a manufacturing method of an LDMOS device provided by the present invention. Detailed implementation manners

[0019] The following description and drawings fully disclose the specific implementation manners of the present invention, enabling those skilled in the art to practice them. Other implementation manners may include structural, logical, electrical, process, and other changes. The embodiments only represent possible variations. Unless explicitly required, the individual components and functions are optional, and the order of operations can be changed. Some parts and features of some embodiments may be included in or replace parts and features of other embodiments.

[0020] Embodiment 1

[0021] This embodiment provides an LDMOS device, the structure is as Figure 1 shown, including a substrate 110. In this embodiment, the substrate 110 includes a substrate 111 and a P-type well 112 located on the substrate 111. A gate structure 120 is formed on the substrate 110; a drift region 130, symmetrically disposed in the substrate 110 on both sides of the gate structure 120; a source region 140 and a drain region 150, symmetrically disposed on the drift region 130 on both sides of the gate structure 120, and the source region 140 and the drain region 150 can be interchanged; an isolation layer 160, located on the drift region 130 between the source region 140 and the drain region 150. The isolation layer 160 is a shallow trench isolation structure, providing electrical isolation, and the material used is silicon oxide; a floating field plate 170, located on the top of the isolation layer 160, evenly and symmetrically distributed on both sides of the gate structure 120. The LDMOS device is a symmetric structure, and the high voltage can be connected to either end. By forming the floating field plate, the electric field distribution in the drift region is made more uniform, reducing the peak value of the surface electric field of the device and improving the breakdown voltage performance of the device.

[0022] As shown Figure 2 in Figure 2 , the floating field plate 170 has a "convex" shape structure, including a large rectangular portion 171 and a small rectangular portion 172 connected to one side of the large rectangular portion 171. A plurality of floating field plates 170 are regularly spaced in the vertical and horizontal directions. The vertical direction is along the length direction of the gate structure 120, as shown Figure 2 in the Y direction in Figure 2 , and the horizontal direction is along the width direction of the gate structure 120, as shown Figure 2 in the X direction in Figure 2 . The orientation directions of the small rectangular portions 172 of two adjacent columns are opposite to each other, making the current distribution more uniform.

[0023] The material of the gate structure 120 is polysilicon; the material of the floating field plate 170 is polysilicon. As shown Figure 3 in Figure 3 , sidewall structures 190 are formed on both sides of the gate structure 120 and the floating field plate 170. In this embodiment, the sidewall structure 190 is composed of alternating oxides and nitrides, which protects the sidewalls of the gate structure 120 and the floating field plate 170. Silicide layers 200 are formed on the tops of the gate structure 120 and the floating field plate 170, and the silicide layers 200 are formed by self-alignment technology.

[0024] It further includes a dielectric layer 210, which covers the gate structure 120, the floating field plate 170, and the substrate 110, and is used to achieve electrical isolation between conductive structures and between adjacent devices.

[0025] It further includes plug structures (CT), namely a source region plug structure 181, a drain region plug structure 182, and a gate plug structure 183. The source region plug structure 181 is located on the top of the source region 140 and penetrates the dielectric layer 210. The drain region plug structure 182 is located on the top of the drain region 150 and penetrates the dielectric layer 210. The gate plug structure 183 is located on the top of the gate structure 120 and penetrates the dielectric layer 210. The plug structures are used to achieve connection with the metal interconnect structure. The plug structures include an adhesion layer and a filling layer. In this embodiment, the material used for the adhesion layer is titanium / titanium nitride, and the material used for the filling layer is tungsten.

[0026] Embodiment 2

[0027] This embodiment provides a method for manufacturing an LDMOS device. An opening position for the floating field plate 170 is designed and added on the photomask used in the polysilicon etching step, and the floating field plate 170 is etched. Moreover, the floating field plate 170 is not connected to the gate structure 120, the source region 140, or the drain region 150, avoiding the generation of leakage current. As shown Figure 4As shown, it includes the following steps: S1: Provide a substrate 110, in which a drift region 130, a source region 140, a drain region 150, and an isolation layer 160 are formed; S2: Deposit undoped polysilicon on the substrate 110 to form a polysilicon layer; S3: Perform ion implantation on the polysilicon layer; S4: Etch the polysilicon layer to form a polysilicon gate structure 120 and a polysilicon floating field plate 170. In this embodiment, amorphous carbon film (APF) is used as the hard mask for polysilicon etching; S5: Form sidewall structures 190 on both sides of the polysilicon gate structure 120 and the polysilicon floating field plate 170, and form a self-aligned silicide layer 200 on the top; S6: Deposit a dielectric layer 210; S7: Form a source region plug structure 181, a drain region plug structure 182, and a gate plug structure 183. The floating field plate 170 is obtained through photomask design in combination with polysilicon deposition and polysilicon etching; the floating field plate 170 is not connected to the gate structure 120, the source region 140, and the drain region 150, avoiding the generation of leakage current. This method is applied to platforms below the advanced process of 40 nm. The floating field plate 170 improves the uniformity of the electric field distribution, reduces the electric field peak value, and increases the device breakdown voltage.

[0028] It should be understood that some commonly used English nouns or letters used in this application for the convenience of clear description are only for exemplary reference rather than limiting interpretation or specific usage, and the protection scope of this application should not be limited by their possible Chinese translations or specific letters. It should also be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. An LDMOS device, characterized in that: include: A substrate having a gate structure formed thereon; A drift region, symmetrically arranged in the substrate on both sides of the gate structure; A source region and a drain region, symmetrically arranged on the drift region on both sides of the gate structure; an isolation layer, located on the drift region between the source region and the drain region; A plurality of floating field plates are located on the top of the isolation layer and are evenly and symmetrically distributed on both sides of the gate structure.

2. The LDMOS device according to claim 1, characterized in that: The floating field plate is a "convex" shaped structure, including a large rectangular part and a small rectangular part connected to one side of the large rectangular part.

3. The LDMOS device according to claim 2, characterized in that: The plurality of floating field plates are arranged at regular intervals in the vertical and horizontal directions; the small rectangular parts in two adjacent columns are oriented in opposite directions.

4. The LDMOS device according to claim 1, characterized in that: Sidewall structures are formed on both sides of the gate structure and the floating field plate, and silicide layers are formed on the tops of both structures.

5. The LDMOS device according to claim 1, characterized in that: It also includes a dielectric layer, which covers the gate structure, the floating field plate and the substrate.

6. The LDMOS device according to claim 5, characterized in that: It also includes plug structures, namely a source plug structure, a drain plug structure and a gate plug structure; the drain plug structure is located at the top of the drain region and penetrates the dielectric layer; the source plug structure is located at the top of the source region and penetrates the dielectric layer; the gate plug structure is located at the top of the gate structure and penetrates the dielectric layer.

7. The LDMOS device according to claim 1, characterized in that: The isolation layer is a shallow trench isolation structure.

8. The LDMOS device according to claim 1, characterized in that: The gate structure material is polysilicon; the floating field plate material is polysilicon.

9. A method for preparing an LDMOS device, characterized in that: The method for preparing the LDMOS device according to any one of claims 1 to 8 comprises the following steps: S1: providing a substrate, wherein a drift region, a source region, a drain region and an isolation layer are formed in the substrate; S2: depositing non-doped polysilicon on the substrate to form a polysilicon layer; S3: performing ion implantation on the polysilicon layer; S4: etching the polysilicon layer to form a polysilicon gate structure and a polysilicon floating field plate.

10. The preparation method according to claim 9, characterized in that: After step S4, the following steps are also included: S5: forming a sidewall structure on both sides of the polysilicon gate structure and the polysilicon floating field plate, and then forming a silicide layer on top of the polysilicon gate structure and the polysilicon floating field plate; S6: depositing a dielectric layer; S7: forming a source plug structure, a drain plug structure and a gate plug structure.

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