Thin film transistor, thin film transistor substrate, method of manufacturing thin film transistor, and display device including thin film transistor

Abstract

A thin film transistor, a thin film transistor substrate, a method of manufacturing the thin film transistor, and a display device including the thin film transistor are provided. The thin film transistor includes: a base substrate; an active material layer on the base substrate; and a gate electrode spaced apart from the active material layer and overlapping at least a portion of the active material layer, wherein the active material layer includes a channel portion overlapping the gate electrode, a source connection portion in contact with one side of the channel portion, a drain connection portion in contact with the other side of the channel portion, and an insulating portion in contact with at least one of the source connection portion and the drain connection portion, and wherein the channel portion, the source connection portion, the drain connection portion, and the insulating portion are disposed on the same layer. Therefore, the thin film transistor can be manufactured without patterning the active material layer, so that defects that may occur during patterning of the active material layer can be avoided. As a result, the stability of the thin film transistor is improved.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10 - 2023 - 0185835, filed on December 19, 2023. For all purposes, the entire disclosure of the Korean patent application is incorporated herein by reference as if fully set forth herein. Technical field

[0003] The present disclosure relates to a thin - film transistor, a thin - film transistor substrate, a method of manufacturing a thin - film transistor, and a display device including the thin - film transistor. Background art

[0004] Transistors are widely used as switching devices or driving devices in the electronic field. In particular, since thin - film transistors can be fabricated on a glass substrate or a plastic substrate, they are used as switching devices for display devices such as liquid - crystal display devices or organic light - emitting devices.

[0005] Based on the material constituting the active material layer, thin - film transistors can be classified into amorphous silicon thin - film transistors using amorphous silicon as the active material layer, polycrystalline silicon thin - film transistors using polycrystalline silicon as the active material layer, and oxide semiconductor thin - film transistors using an oxide semiconductor as the active material layer.

[0006] Among them, oxide semiconductor thin - film transistors (oxide semiconductor TFTs) having a high mobility and a large resistance change depending on the oxygen content have the advantage of being able to easily obtain desired characteristics. In addition, the manufacturing cost of oxide semiconductor thin - film transistors is relatively low because, during the manufacturing process of oxide semiconductor thin - film transistors, the oxide constituting the active layer can be formed at a relatively low temperature. Due to the nature of the oxide, the oxide semiconductor is transparent, so oxide semiconductor thin - film transistors are advantageous for realizing transparent display devices.

[0007] In order to apply an oxide semiconductor to a thin - film transistor, it is necessary to pattern the oxide semiconductor layer and make a part of the patterned oxide semiconductor layer conductive. However, during the patterning process and subsequent processes, loss or deterioration may occur at the edge of the oxide semiconductor pattern or at the insulating layer. In the case of such loss or deterioration, the stability of the thin - film transistor may deteriorate.

[0008] Recently, in order to maximize the advantages of oxide semiconductor thin - film transistors, research is being conducted to improve the stability and electrical characteristics of oxide thin - film transistors and reduce the manufacturing cost of oxide semiconductor thin - film transistors. Summary of the invention

[0009] One aspect of the present disclosure is to provide a thin film transistor that can be manufactured without patterning an active material layer and a thin film transistor substrate including the thin film transistor.

[0010] Another aspect of the present disclosure is to provide a thin film transistor and a thin film transistor substrate having an insulating portion formed by doping a dopant instead of patterning an active material layer, and realizing a channel portion, a source connection portion, and a drain connection portion through the insulating portion.

[0011] Another aspect of the present disclosure is to provide a method of manufacturing a thin film transistor and a method of manufacturing a thin film transistor substrate in which an insulating portion is formed by doping a dopant without patterning an active material layer to achieve the same effect as patterning.

[0012] Another aspect of the present disclosure is to provide a display device including the thin film transistor as described above and thus having excellent reliability.

[0013] According to one aspect of the present disclosure, the above and other objects can be achieved by providing a thin film transistor including: an active material layer on a base substrate; and a gate electrode separated from the active material layer and overlapping at least a part of the active material layer, wherein the active material layer includes: a channel portion overlapping the gate electrode; a source connection portion contacting one side of the channel portion; a drain connection portion contacting the other side of the channel portion; and an insulating portion contacting at least one of the source connection portion and the drain connection portion, and wherein the channel portion, the source connection portion, the drain connection portion, and the insulating portion are provided in the same layer.

[0014] The active material layer may include an oxide semiconductor material, and the insulating portion may include a first dopant.

[0015] The first dopant may include at least one of nitrogen (N), sulfur (S), chlorine (Cl), gallium (Ga), tungsten (W), iron (Fe), and tin (Sn).

[0016] The first dopant may include nitrogen (N), and based on the total number of atoms of the insulating portion, the insulating portion may include 40 to 60 atomic percent (at%) of oxygen and 4 to 10 atomic percent (at%) of nitrogen.

[0017] Each of the source connection portion and the drain connection portion may include a second dopant different from the first dopant.

[0018] The second dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H).

[0019] The insulating portion may further include the second dopant.

[0020] The oxide semiconductor material may include at least one of IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, ITZO (InSnZnO)-based, InO-based, ZnO-based, and FIZO (FeInZnO)-based oxide semiconductor materials.

[0021] The active material layer may not be patterned.

[0022] The channel portion, the source connection portion, the drain connection portion, and the insulating portion are integrally formed.

[0023] The thin film transistor may further include a light-shielding layer disposed between the substrate and the active material layer and overlapping the channel portion.

[0024] The thin film transistor may further include a first capacitor electrode integrally formed with the light-shielding layer and not overlapping the channel portion.

[0025] The active material layer may include a second capacitor electrode separated from the channel portion, and the second capacitor electrode is insulated from at least one of the source connection portion and the drain connection portion through the insulating portion, and wherein the first capacitor electrode and the second capacitor electrode overlap each other to form a first capacitor. In addition, the oxide semiconductor material may include gallium (Ga), and the first dopant may include gallium (Ga). In addition, the concentration of gallium (Ga) included in the insulating portion may be higher than the concentration of gallium (Ga) included in the channel portion, the source connection portion, or the drain connection portion. In addition, the active material layer may include a first oxide semiconductor material layer and a second oxide semiconductor material layer on the first oxide semiconductor material layer.

[0026] Another embodiment of the present disclosure provides a thin film transistor substrate, the thin film transistor substrate including a first thin film transistor and a second thin film transistor on a base substrate, wherein the first thin film transistor and the second thin film transistor include an active material layer, wherein the first thin film transistor includes: a first channel portion on the base substrate; a first source connection portion in contact with one side of the first channel portion; a first drain connection portion in contact with the other side of the first channel portion; and a first gate electrode separated from the active material layer and overlapping the first channel portion, wherein the second thin film transistor includes: a second channel portion on the base substrate; a second source connection portion in contact with one side of the second channel portion; a second drain connection portion in contact with the other side of the second channel portion; and a second gate electrode separated from the active material layer and overlapping the second channel portion, wherein the first thin film transistor and the second thin film transistor are separated from each other with an insulating portion therebetween, the active material layer including the first channel portion, the first source connection portion, the first drain connection portion, the second channel portion, the second source connection portion, the second drain connection portion, and the insulating portion, and the first channel portion, the first source connection portion, the first drain connection portion, the second channel portion, the second source connection portion, the second drain connection portion, and the insulating portion are provided in the same layer.

[0027] The first channel portion, the first source connection portion, the first drain connection portion, the second channel portion, the second source connection portion, the second drain connection portion, and the insulating portion may be integrally formed.

[0028] The first channel portion, the first source connection portion, the first drain connection portion, the second channel portion, the second source connection portion, the second drain connection portion, and the insulating portion include an oxide semiconductor material, and wherein the insulating portion may further include a first dopant.

[0029] The first dopant may include at least one of nitrogen (N), sulfur (S), chlorine (Cl), gallium (Ga), tungsten (W), iron (Fe), and tin (Sn).

[0030] The first source connection portion, the first drain connection portion, the second source connection portion, and the second drain connection portion may include a second dopant different from the first dopant.

[0031] Another embodiment of the present disclosure provides a display device, the display device including the thin film transistor substrate and the light emitting element.

[0032] Another embodiment of the present disclosure provides a display device, the display device including a plurality of pixels disposed on a substrate, wherein each of the plurality of pixels includes: a display element; and a pixel driving circuit for driving the display element, wherein the pixel driving circuit includes the above thin film transistor.

[0033] The active material layer may be integrally formed over the plurality of pixels.

[0034] Another embodiment of the present disclosure provides a method of manufacturing a thin film transistor, the method including: forming an active material layer on a substrate; forming a mask on the active material layer; forming an insulating portion by doping a first dopant into a portion of the active material layer that does not overlap with the mask; forming a gate electrode spaced apart from the active material layer on the active material layer; and forming a source connection portion and a drain connection portion by rendering conductive a portion of the active material layer that does not overlap with the gate electrode, wherein a portion of the active material layer that overlaps with the gate electrode forms a channel portion, wherein the source connection portion is disposed between the channel portion and the insulating portion, and the drain connection portion is spaced apart from the source connection portion and is disposed between the channel portion and the insulating portion.

[0035] The first dopant may include at least one of nitrogen (N), sulfur (S), chlorine (Cl), gallium (Ga), tungsten (W), iron (Fe), and tin (Sn).

[0036] The rendering conductive is performed by plasma treatment or doping with a second dopant.

[0037] According to an embodiment of the present disclosure, since a thin film transistor can be manufactured without patterning the active material layer, defects that may occur during patterning of the active material layer can be avoided. As a result, the stability of the thin film transistor is improved.

[0038] In addition, since the channel portion, the source connection portion, the drain connection portion, and the insulating portion can be implemented with one active material layer, the channel portion, the source connection portion, the drain connection portion, and the insulating portion can be integrally implemented with one material.

[0039] According to an embodiment of the present disclosure, an active region of a thin film transistor can be defined by an insulating portion formed by doping a dopant, without patterning an active material layer. Since the patterning process of the active material layer can be omitted, the process efficiency is improved, and the use of harmful substances in the etching process can be reduced. Therefore, the process of manufacturing the thin film transistor is environmentally friendly.

[0040] Since the thin film transistor according to the embodiment of the present disclosure can be manufactured without patterning, defects are reduced and the thin film transistor can have excellent reliability. In addition, a display device including the thin film transistor according to another embodiment of the present disclosure has excellent reliability and can have excellent display performance.

[0041] In addition to the effects mentioned above, other features and advantages of the present disclosure are described below. From the description and explanation, those skilled in the art will clearly understand the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings included to provide a further understanding of the present disclosure and incorporated into this application and constituting a part of this application illustrate embodiments of the present disclosure and are used to explain the principles of the present disclosure together with the specification. From the following detailed description in conjunction with the drawings, the above and other objects, features, and other advantages of the present disclosure will be more clearly understood.

[0043] Figure 1 is a plan view of a thin film transistor according to an embodiment of the present disclosure.

[0044] Figure 2 is along Figure 1 a cross-sectional view taken along IA-IA' of

[0045] Figure 3 is along Figure 1 a cross-sectional view taken along IB-IB' of

[0046] Figure 4A and Figure 4B are diagrams respectively illustrating the bonding states of nitrogen (N) doped in an oxide semiconductor material.

[0047] Figure 5 is a schematic diagram illustrating oxygen vacancies.

[0048] Figure 6 is a schematic diagram illustrating the mechanism of removing oxygen vacancies by nitrogen (N) doping.

[0049] Figure 7 is a schematic diagram illustrating the change in bandgap state caused by nitrogen-oxygen bonding (N-O bonding).

[0050] Figure 8AIt is a diagram showing the change in the carrier density of an oxide semiconductor material according to the nitrogen concentration. Figure 8B It is a diagram showing the change in the mobility and surface resistance of an oxide semiconductor material according to the nitrogen concentration. Figure 8C It illustrates the resistance of an oxide semiconductor material according to the concentrations of oxygen and nitrogen.

[0051] Figure 9 It is a cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0052] Figure 10 It is a cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0053] Figure 11 It is a cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0054] Figure 12 It is a cross-sectional view of a thin-film transistor according to another embodiment of the present disclosure.

[0055] Figure 13A It is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present disclosure.

[0056] Figure 13B It is Figure 13A a plan view of the active material layer of

[0057] Figure 14 It is a cross-sectional view of a thin-film transistor substrate according to another embodiment of the present disclosure.

[0058] Figures 15A to 15F It is a cross-sectional view illustrating the manufacturing process of a thin-film transistor substrate according to another embodiment of the present disclosure.

[0059] Figure 16 It is a schematic diagram of a display device according to another embodiment of the present disclosure.

[0060] Figure 17 It is Figure 16 the circuit diagram of the pixel of

[0061] Figure 18 It is Figure 17 the plan view of the pixel of

[0062] Figure 19 It is a cross-sectional view along Figure 18 II-II” of

[0063] Figure 20 It is the circuit diagram of the pixel of a display device according to another embodiment of the present disclosure. Detailed Embodiments

[0064] The advantages, features, and methods for implementing the present disclosure will be clarified by the following embodiments described with reference to the accompanying drawings. However, the present disclosure may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosure to those skilled in the art.

[0065] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings for describing the embodiments of the present disclosure are merely examples, and thus the present disclosure is not limited to the details shown in the drawings. The same reference numerals denote the same elements throughout. In the following description, when it is determined that a detailed description of related known functions or configurations unnecessarily obscures the focus of the present disclosure, the detailed description will be omitted.

[0066] In cases where "comprising", "having", and "including" described in this application are used, additional parts may be added, unless "only" is used. Terms in the singular form may include the plural form, unless there is a contrary indication.

[0067] When interpreting an element, although not explicitly stated, the element should be interpreted as including an error range.

[0068] When describing positional relationships, for example, when the positional relationship is described as "on", "above", "below", and "next to", one or more other parts may be provided between the two parts, unless "exactly" or "directly" is used.

[0069] Spatial relative terms such as "below", "beneath", "lower", "above", and "upper" may be used herein to easily describe the relationship of one or more elements shown in the drawings to one or more other elements. It will be understood that these terms are intended to cover different orientations of the device in addition to the orientation depicted in the drawings. For example, if the device shown in the drawings is inverted, the device described as being "below" or "beneath" another device may be disposed "above" the other device. Thus, the exemplary term "below or beneath" may include both the "below or beneath" and "above" orientations. Similarly, the exemplary term "above" or "on" may include both the "above" and "below or beneath" orientations.

[0070] When describing temporal relationships, for example, when the temporal order is described as "after", "behind", "next", and "before", discontinuous cases may be included, unless "exactly" or "directly" is used.

[0071] It will be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0072] The term "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of "at least one of the first item, the second item, and the third item" represents all combinations of two or more of the first item, the second item, and the third item, as well as the first item, the second item, or the third item.

[0073] As can be fully understood by those skilled in the art, the features of various embodiments of the present disclosure may be combined or combined with each other in part or in whole, and may interoperate with each other and be technically driven. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0074] Hereinafter, a thin film transistor and a display device including the thin film transistor according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar elements are denoted by the same reference numerals, even if they are shown in different drawings.

[0075] In an embodiment of the present disclosure, for ease of description, the source electrode and the drain electrode are distinguished from each other. However, the source electrode and the drain electrode may be used interchangeably. The source electrode may be the drain electrode, and the drain electrode may be the source electrode. In addition, the source electrode in any one embodiment of the present disclosure may be the drain electrode in other embodiments of the present disclosure, and the drain electrode in any one embodiment of the present disclosure may be the source electrode in other embodiments of the present disclosure.

[0076] In some embodiments of the present disclosure, for ease of explanation, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode, but the embodiments of the present disclosure are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. In addition, the source region may be the drain electrode, and the drain region may be the source electrode.

[0077] Figure 1 is a plan view of a thin film transistor 100 according to an embodiment of the present disclosure, Figure 2 is along Figure 1 a cross-sectional view taken along IA-IA' of Figure 3 is along Figure 1 a cross-sectional view taken along IB-IB' of

[0078] Reference Figure 1 、 Figure 2 and Figure 3 , according to one embodiment of the present disclosure, the thin film transistor 100 includes: an active material layer 130 on a substrate 110; and a gate electrode 150 separated from and at least partially overlapping the active material layer 130. In addition, the thin film transistor 100 may include a source electrode 160 and a drain electrode 170 separated from each other and respectively connected to the active material layer 130.

[0079] The active material layer 130 includes a channel portion 130n overlapping the gate electrode 150, a source connection portion 130a in contact with one side of the channel portion 130n, a drain connection portion 130b in contact with the other side of the channel portion 130n, and an insulating portion 130i in contact with at least one of the source connection portion 130a and the drain connection portion 130b.

[0080] According to an embodiment of the present disclosure, the thin film transistor TFT may be composed of a channel portion 130n, a source connection portion 130a, a drain connection portion 130b, a gate electrode 150, a source electrode 160, and a drain electrode 170. The thin film transistor 100 may be disposed on the substrate 110.

[0081] The substrate 110 is a component that supports the thin film transistor 100. Anything that supports the thin film transistor TFT may be non - restrictively referred to as the substrate 110.

[0082] Glass or plastic may be used as the substrate 110. For example, a transparent plastic having flexible properties such as polyimide may be used as the plastic. When polyimide is used as the substrate 110, a heat - resistant polyimide capable of withstanding high temperatures may be used in consideration of performing a high - temperature deposition process on the substrate 110.

[0083] A light - shielding layer 111 may be provided on the substrate 110 (see Figure 11 ). The light - shielding layer may be omitted.

[0084] Reference Figure 2 and Figure 3 , a buffer layer 120 is provided on the substrate 110. The buffer layer 120 may be made of an insulating material. For example, the buffer layer 120 may include at least one of insulating materials selected from silicon oxide, silicon nitride, and metal - based oxides. The buffer layer 120 may have a single - layer structure or a multi - layer structure.

[0085] The buffer layer 120 blocks air and moisture and thus can protect the channel portion 130n. In addition, the surface above the substrate 110 may be made uniform by the buffer layer 120.

[0086] The active material layer 130 is disposed on the base substrate 110. Referring to Figure 2 and Figure 3 , the active material layer 130 may be disposed on the buffer layer 120, and the buffer layer 120 is disposed on the base substrate 110.

[0087] According to an embodiment of the present disclosure, the channel portion 130n, the source connection portion 130a, the drain connection portion 130b, and the insulating portion 130i included in the active material layer 130 may all be disposed in the same layer. The channel portion 130n, the source connection portion 130a, the drain connection portion 130b, and the insulating portion 130i may be integrally formed. Each region of the active material layer 130 may be distinguished by doping.

[0088] According to an embodiment of the present disclosure, the active material layer 130 may include an oxide semiconductor material. Specifically, the channel portion 130n, the source connection portion 130a, the drain connection portion 130b, and the insulating portion 130i may include an oxide semiconductor material.

[0089] The oxide semiconductor material may include, for example, at least one of IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, ITZO (InSnZnO)-based, InO-based, ZnO-based, and FIZO (FeInZnO)-based oxide semiconductor materials. However, the embodiments of the present disclosure are not limited thereto, and the active material layer 130 may include other oxide semiconductor materials known in the art.

[0090] The channel portion 130n overlaps with the gate electrode 150. The channel portion 130n has semiconductor characteristics. According to the voltage applied to the gate electrode 150, the channel portion 130n may have electrical characteristics similar to those of a conductor or characteristics similar to those of an insulator. For example, when the thin film transistor TFT is in the off state, the channel portion 130n may have a resistivity in the range of 10 -4 Ω·cm to 10 4 Ω·cm.

[0091] According to an embodiment of the present disclosure, each of the source connection portion 130a and the drain connection portion 130b may have electrical characteristics similar to those of a conductor. For example, each of the source connection portion 130a and the drain connection portion 130b may have a resistivity of 10 -4 Ω·cm or less. Regardless of whether the thin film transistor TFT is on or off, the source connection portion 130a and the drain connection portion 130b may each have a substantially constant resistivity.

[0092] According to an embodiment of the present disclosure, the source connection part 130a and the drain connection part 130b may be referred to as conductor regions.

[0093] According to an embodiment of the present disclosure, the insulating part 130i may have insulating properties. The insulating part 130i may have, for example, a resistivity of 10 7 Ω·cm or greater. Specifically, the insulating part 130i may have a resistivity of 10 8 Ω·cm or greater. More specifically, the insulating part 130i may have a resistivity of 10 7 to 10 20 Ω·cm or 10 8 to 10 18 Ω·cm. Regardless of whether the thin film transistor TFT is on or off, the insulating part 130i may have a substantially constant resistivity.

[0094] According to an embodiment of the present disclosure, the insulating part 130i may be referred to as an insulating region.

[0095] According to an embodiment of the present disclosure, the insulating part 130i may include a first dopant. The active material layer 130 may be selectively doped with the first dopant to form the insulating part 130i. Specifically, the insulating part 130i may be formed by selectively doping the oxide semiconductor material constituting the active material layer 130 with the first dopant. According to an embodiment of the present disclosure, the region of the active material layer 130 doped with the first dopant may be referred to as the insulating part 130i.

[0096] The first dopant is used to increase the resistance of the oxide semiconductor material. For example, the first dopant may be used to remove oxygen vacancies that appear in the oxide semiconductor material. By removing oxygen vacancies with the first dopant, the carrier density of the oxide semiconductor material can be reduced, and the mobility and conductivity of the oxide semiconductor material can be reduced. As a result, the region of the oxide semiconductor material doped with the first dopant may have insulating properties. According to an embodiment of the present disclosure, the carrier density is also referred to as the carrier concentration and represents the number of charge carriers per volume.

[0097] The insulating part 130i is a region where the active material layer 130 is selectively doped with the first dopant, and may be defined as a part having a very low carrier density and resulting insulating properties. The insulating part 130i has a low carrier density and has a low mobility and a high resistance compared to other regions of the active material layer 130.

[0098] According to an embodiment of the present disclosure, the first dopant may include at least one of nitrogen (N), sulfur (S), chlorine (Cl), gallium (Ga), tungsten (W), iron (Fe), and tin (Sn).

[0099] For example, nitrogen (N) used as a first dopant can be doped into the oxide semiconductor material constituting the active material layer 130 and can be disposed at positions where oxygen vacancies appear. Thus, carriers generated by the oxygen vacancies can be captured by nitrogen (N). By capturing carriers, the carrier density and mobility in the doped region are reduced, and the resistance of the doped region is increased. Consequently, the portion doped with nitrogen (N) can have insulating characteristics. In this case, the carriers generated by the oxygen vacancies are electrons (e-).

[0100] In addition, at least one of the first dopants which are non-metal elements sulfur (S) and chlorine (Cl) can be doped into the oxide semiconductor material and disposed at positions where oxygen vacancies appear. Thus, the carriers generated by the oxygen vacancies are captured by sulfur (S) or chlorine (Cl), such that the portion doped with the first dopant can have insulating characteristics. Therefore, a part of the active material layer 130 doped with at least one of sulfur (S) and chlorine (Cl) can become an insulating portion 130i.

[0101] When at least one of the first dopants which are metal elements gallium (Ga), tungsten (W), iron (Fe), and tin (Sn) is doped into the oxide semiconductor material, the metal-oxygen bond in the doped region can be increased. Therefore, the region of the oxide semiconductor material doped with at least one of gallium (Ga), tungsten (W), iron (Fe), and tin (Sn) becomes an oxide in an oxygen (O)-saturated state and can thus have insulating characteristics.

[0102] For example, in an oxygen atmosphere in an O2 gas state, when an indium (In)-based oxide semiconductor material containing indium (In) is doped with a metal element such as gallium (Ga), tungsten (W), iron (Fe), and tin (Sn), the doped metal element replaces indium (In), and at the same time, the doped metal element can combine with oxygen (O). As a result, indium (In) can be removed from the doped region of the oxide semiconductor material, thereby reducing the carrier density. In addition, because the doped metal element can form a strong bond with oxygen, the region of the oxide semiconductor material doped with a metal element such as gallium (Ga), tungsten (W), iron (Fe), and tin (Sn) becomes an oxygen-rich oxide, and the insulation of the doped region can be increased. Therefore, a part of the active material layer 130 doped with at least one of gallium (Ga), tungsten (W), iron (Fe), and tin (Sn) can become an insulating portion 130i.

[0103] A detailed description of the changes in the electrical characteristics of the active material layer 130 and the oxide semiconductor material due to the doping of the first dopant will be described later.

[0104] According to an embodiment of the present invention, the channel portion 130n, the source connection portion 130a, and the drain connection portion 130b are regions not doped with the first dopant. The channel portion 130n, the source connection portion 130a, and the drain connection portion 130b are protected from the influence of the first dopant.

[0105] According to an embodiment of the present disclosure, a region having an electrical function among the active material layers 130 may be referred to as an active region ACT. In Figure 1 , Figure 2 and Figure 3 's thin film transistor 100, the active material layer 130 includes a channel portion 130n, a source connection portion 130a, a drain connection portion 130b, and an insulating portion 130i. In addition, in Figure 1 , Figure 2 and Figure 3 's thin film transistor 100, the channel portion 130n, the source connection portion 130a, and the drain connection portion 130b may be referred to as the active region ACT.

[0106] The channel portion 130n has semiconductor characteristics of the oxide semiconductor material constituting the active material layer 130. On the other hand, the source connection portion 130a and the drain connection portion 130b are conductive regions formed by selective conductivity.

[0107] The source connection portion 130a and the drain connection portion 130b may be formed by selectively conducting the active material layer 130. Specifically, the source connection portion 130a and the drain connection portion 130b may be formed by selectively conducting the oxide semiconductor material constituting the active material layer 130. According to an embodiment of the present disclosure, selective conductivity is performed after forming the insulating portion 130i by selectively doping the first dopant.

[0108] The selectively conductive portion of the active material layer 130 has excellent conductivity and can be used as a wiring portion.

[0109] According to an embodiment of the present disclosure, selective conductivity means improving the conductivity of a selected portion of the active material layer 130 or providing conductivity to a selected portion of the active material layer 130. According to an embodiment of the present disclosure, selective conductivity can be achieved by doping a second dopant into a selected region of the active material layer 130. The source connection portion 130a and the drain connection portion 130b may contain the second dopant.

[0110] According to an embodiment of the present disclosure, doping may be performed by implanting dopant ions. Specifically, the source connection portion 130a and the drain connection portion 130b may include a second dopant doped by ion implantation.

[0111] According to an embodiment of the present disclosure, the second dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H).

[0112] According to an embodiment of the present disclosure, the active material layer 130 is formed of an oxide semiconductor material, and the second dopant is injected into selected portions of the active material layer 130 to form a source connection portion 130a and a drain connection portion 130b by doping.

[0113] However, embodiments of the present disclosure are not limited thereto, and conductivity may be provided to the source connection portion 130a and the drain connection portion 130b by other methods. According to an embodiment of the present disclosure, conductivity may be provided to the source connection portion 130a and the drain connection portion 130b via plasma treatment. For example, in the patterning process of the gate insulating layer 140 or the gate electrode 150, the source connection portion 130a and the drain connection portion 130b may be formed by selective conductivity via plasma treatment.

[0114] When the source connection portion 130a and the drain connection portion 130b are doped with the first dopant, the conductivity of the source connection portion 130a and the drain connection portion 130b may be reduced. Therefore, in order to prevent the source connection portion 130a and the drain connection portion 130b from being doped with the first dopant during the manufacturing process of the thin film transistor 100, the source connection portion 130a and the drain connection portion 130b may be protected by a mask or the like.

[0115] The channel portion 130n is also protected from being doped with the first dopant. In addition, the channel portion 130n is protected from being doped with the second dopant.

[0116] According to an embodiment of the present disclosure, a region of the active material layer 130 that is not doped with the first dopant and the second dopant and is not electrically conductive may become the channel portion 130n.

[0117] The channel portion 130n of the active material layer 130 is a region overlapping with the gate electrode 150. The doping process of the second dopant may be performed using the gate electrode 150 as a mask. As a result, the portion of the active material layer 130 overlapping with the gate electrode 150 is not doped with the second dopant and thus becomes the channel portion 130n.

[0118] On the other hand, by doping the first dopant, the insulating portion 130i has stable insulating characteristics. Therefore, even after doping the first dopant and then doping the insulating portion 130i with the second dopant, the insulating portion 130i can maintain its insulating characteristics. Even during the process of forming the source connection portion 130a and the drain connection portion 130b, when the insulating portion 130i is doped with the second dopant, the insulating characteristics of the insulating portion 130i can be maintained.

[0119] According to an embodiment of the present disclosure, the insulating portion 130i may further include a second dopant.

[0120] According to an embodiment of the present disclosure, the channel portion 130n, the source connection portion 130a, the drain connection portion 130b, and the insulating portion 130i are distinguished from each other by doping with dopants without patterning the active material layer 130. Alternatively, the channel portion 130n, the source connection portion 130a, the drain connection portion 130b, and the insulating portion 130i may be distinguished from each other by doping with dopants and plasma treatment without patterning the active material layer 130.

[0121] Therefore, according to an embodiment of the present disclosure, the active material layer 130 may not be patterned. In addition, the channel portion 130n, the source connection portion 130a, the drain connection portion 130b, and the insulating portion 130i may be integrally formed.

[0122] Refer to Figure 2 and Figure 3 , a gate insulating layer 140 is provided on the active material layer 130. The gate insulating layer 140 may include at least one of silicon oxide, silicon nitride, and metal-based oxides. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure. The gate insulating layer 140 protects the channel portion 130n.

[0123] Refer to Figure 1 and Figure 2 , the gate insulating layer 140 may be formed over the entire upper surface of the substrate 110. For example, the gate insulating layer 140 may cover all of the channel portion 130n, the source connection portion 130a, and the drain connection portion 130b except for the contact regions.

[0124] However, the embodiment of the present disclosure is not limited thereto, and the gate insulating layer 140 may be patterned. For example, the gate insulating layer 140 may be patterned into a shape corresponding to the gate electrode 150.

[0125] The gate electrode 150 is provided on the gate insulating layer 140. The gate electrode 150 is formed to overlap the channel portion 130n of the active material layer 130.

[0126] The gate electrode 150 may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloy, silver-based metals such as silver (Ag) or silver alloy, copper-based metals such as copper (Cu) or copper alloy, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 150 may have a multilayer structure including at least two conductive layers having different physical properties.

[0127] Referring Figure 2 and Figure 3 , an interlayer insulating film 145 may be provided on the gate insulating layer 140 and the gate electrode 150. The interlayer insulating film 145 is an insulating layer made of an insulating material. The interlayer insulating film 145 may be made of an organic material, an inorganic material, or a laminate of an organic material layer and an inorganic material layer.

[0128] A source electrode 160 and a drain electrode 170 may be provided on the interlayer insulating film 145.

[0129] Each of the source electrode 160 and the drain electrode 170 may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and their alloys. Each of the source electrode 160 and the drain electrode 170 may be configured as a single layer made of a metal or a metal alloy, or a multilayer made of two or more layers.

[0130] According to an embodiment of the present disclosure, the source electrode 160 may be connected to the source connection portion 130a. Specifically, the source electrode 160 may be electrically connected to the source connection portion 130a through a contact hole and may transmit an electrical signal to the channel portion 130n.

[0131] The drain electrode 175 is separated from the source electrode 160 and may be connected to the drain connection portion 130b. Specifically, the drain electrode 175 may be electrically connected to the drain connection portion 130b through a contact hole and may transmit an electrical signal to the channel portion 130n.

[0132] According to an embodiment of the present disclosure, the source connection portion 130a may be used as a source electrode, and the drain connection portion 130b may be used as a drain electrode. In addition, the source connection portion 130a and the drain connection portion 130b may be interchanged with each other.

[0133] The source electrode 160 and the drain electrode 170 may be omitted. When the source electrode 160 and the drain electrode 170 are omitted, the source connection portion 130a may be used as a source electrode, and the drain connection portion 130b may be used as a drain electrode.

[0134] In the following text, the changes in the electrical characteristics of the active material layer 130 and the oxide semiconductor material due to doping with the first dopant will be described in detail.

[0135] Figure 4A and Figure 4B are diagrams respectively illustrating the bonding states of nitrogen (N) doped in the oxide semiconductor material constituting the active material layer 130.

[0136] In the oxide semiconductor material, when an oxygen atom bonded to a metal atom is removed, oxygen vacancies occur. When oxygen vacancies occur, free electrons bound by oxygen are released, and carrier electrons (e-) are generated. When nitrogen is doped into the oxide semiconductor material, the oxygen vacancies caused by the removal of oxygen atoms are filled with nitrogen (N). Specifically, the sites of oxygen vacancies generated by removing oxygen atoms are filled with doped nitrogen. When the sites where oxygen vacancies occur are filled with nitrogen (N), the carrier electrons (e-) bind to nitrogen (N), and the carrier density and mobility of the oxide semiconductor material decrease. Therefore, the resistance of the oxide semiconductor material can increase.

[0137] Referring to Figure 4A , nitrogen (N) can be placed at the sites where oxygen vacancies occur, and the nitrogen (N) placed at the sites can bind to other oxygen (O) present in the oxide semiconductor material and can also bind to other metal elements M1, M2.

[0138] Referring to Figure 4B , nitrogen (N) doped into the oxide semiconductor material can bind to two oxygen atoms to form an O-N-O bond. As a result, the escape of oxygen from the oxide semiconductor material is prevented, and the resistance of the oxide semiconductor material can be further increased.

[0139] Figure 5 is a schematic diagram illustrating the oxygen vacancy Vo.

[0140] Referring to Figure 5 's (A), due to the oxygen vacancy Vo, two electrons (-) can be generated. The valence of oxygen (O) is divalent (2+). Therefore, when oxygen is removed from the oxide semiconductor material, as Figure 5 's (B) shows, the effect is to remove a divalent oxygen atom (O 2+ ), thereby generating two electrons (-).

[0141] On the other hand, hydrogen has a monovalent (1+) atom. Therefore, as Figure 5 's (C) shows, when the oxygen vacancy (Vo) site is replaced by a hydrogen (H) atom, the effect is to place the hydrogen atom (H+) in a monovalent state, thereby generating one electron (-).

[0142] Figure 6It is a schematic diagram illustrating the mechanism of removing oxygen vacancies by nitrogen (N) doping.

[0143] Referring to Figure 6 (A) of, two electrons (-) can be generated through the oxygen vacancy Vo.

[0144] Nitrogen has a trivalent valence (3+). Therefore, as shown in Figure 6 (B) of, when nitrogen (N) is doped into the oxide semiconductor material, nitrogen (N) replaces the oxygen vacancy Vo site and can capture all two electrons (-) generated by the oxygen vacancy Vo. Referring to Figure 6 (B) of, even after the nitrogen (N) doped into the oxide semiconductor material has captured all two electrons (-) generated by the oxygen vacancy Vo, nitrogen can still have another site (marked with "+") capable of capturing additional atoms or electrons.

[0145] Referring to Figure 6 (C) of, the nitrogen (N) doped into the oxide semiconductor material not only replaces the oxygen vacancy Vo site but also binds to hydrogen (H) atoms.

[0146] When hydrogen flows into the oxide semiconductor material, hydrogen can combine with oxygen in the oxide semiconductor material and can remove oxygen from the oxide semiconductor material. As a result, hydrogen can cause oxygen vacancies Vo in the oxide semiconductor material.

[0147] However, when nitrogen (N) is doped into the oxide semiconductor material, nitrogen (N) not only replaces the oxygen vacancy Vo site but also binds to hydrogen (H) atoms [see Figure 6 (C) of]. As a result, the appearance of oxygen vacancies Vo caused by hydrogen is prevented, and the insulating property of the oxide semiconductor material can be stably maintained at the nitrogen doping site.

[0148] Therefore, the insulating portion 130i formed by nitrogen doping according to the embodiments of the present disclosure has excellent insulating properties and can stably maintain the insulating properties.

[0149] Figure 7 It is a schematic diagram illustrating the change in the bandgap state caused by nitrogen-oxygen bonding (N-O bonding). Specifically, Figure 7 shows the valence band tail (VBT).

[0150] The oxide semiconductor material, for example, Figure 7The IGZO-based oxide semiconductor material shown in [description] may have a valence band tail (VBT) due to the p orbitals of oxygen atoms. When a nitrogen-oxygen (N-O) bond is formed through nitrogen doping (N-doping), unfilled energy gap states in the band gap are formed by nitrogen with p orbitals (N-p) and oxygen with p orbitals (O-p), enabling electron capture. In this way, the Fermi level Ef can be controlled through nitrogen doping, and the band gap can be increased to insulate the oxide semiconductor material.

[0151] Figure 8A is a graph illustrating the change in the carrier density of the oxide semiconductor material according to the nitrogen (N) concentration. Figure 8B is a graph illustrating the change in the mobility and surface resistance of the oxide semiconductor material according to the nitrogen (N) concentration. According to an embodiment of the present disclosure, the carrier density may be referred to as the carrier concentration and represents the number of charge carriers per volume. For example, in an embodiment of the present disclosure, the carrier density is measured as the number of charge carriers per cm -3 unit.

[0152] Referring to Figure 8A it is noted that as the concentration of nitrogen (N) contained in the oxide semiconductor material increases, the carrier density of the oxide semiconductor material decreases.

[0153] Referring to Figure 8B it is noted that as the concentration of nitrogen (N) contained in the oxide semiconductor material increases, the mobility of the oxide semiconductor material decreases and the surface resistance (R) increases. According to an embodiment of the present disclosure, the surface resistance (R) may be referred to as the sheet resistance and is expressed as "ohms per square" or "Ω / □".

[0154] Figure 8C illustrates the resistance of the oxide semiconductor material according to the concentrations of oxygen and nitrogen. Specifically, Figure 8C illustrates the surface resistance of the oxide semiconductor layer as a function of the partial pressure of oxygen (O2) and the amount of nitrogen (N2) during the manufacture of the IGZO oxide semiconductor layer.

[0155] According to an embodiment of the present disclosure, in order for the insulating portion 130i to have a sufficiently high resistivity and insulating properties, the oxygen content may be designed to be in the range of 40 atomic percent (at%) to 60 atomic percent (at%) and the nitrogen content may be designed to be in the range of 4 atomic percent (at%) to 10 atomic percent (at%) with respect to the total number of atoms in the insulating portion 130i. Accordingly, the insulating portion 130i may include 40 to 60 atomic percent (at%) of oxygen (O) and 4 to 10 atomic percent (at%) of nitrogen (N) with respect to the total number of atoms contained therein.

[0156] More specifically, in the insulating portion 130i, the oxygen content can be 50 atomic percent (at%) or more, and the nitrogen content can be 4 atomic percent (at%) or more, relative to the total number of atoms included in the insulating portion 130i. In this case, relative to the total number of atoms contained in the oxide semiconductor material, the insulating portion 130i can contain more than 50 at% of oxygen (O) and more than 4 at% of nitrogen (N).

[0157] Similar to nitrogen (N), at least one of sulfur (S) and chlorine (Cl), which are non-metal elements among the first dopants, can also be doped into the oxide semiconductor material and placed at positions where oxygen vacancies occur. Since the carriers generated by the oxygen vacancies can be captured by sulfur (S) or chlorine (Cl), the portion doped with the first dopant can have insulating properties. As a result, a part of the active material layer 130 doped with at least one of sulfur (S) and chlorine (Cl) can become the insulating portion 130i.

[0158] When at least one of the first dopants, which are metal elements such as gallium (Ga), tungsten (W), iron (Fe), and tin (Sn), is doped into a part of the oxide semiconductor material, the metal-oxygen bond in the doped portion can be increased. For example, in an oxygen atmosphere in the O2 gas state, when an indium (In)-based oxide semiconductor material containing indium (In) is doped with a metal element such as gallium (Ga), tungsten (W), iron (Fe), or tin (Sn), the doped metal element replaces indium (In), and at the same time, the doped metal element can combine with oxygen (O). Through this doping, indium (In) is removed from the doped region of the oxide semiconductor material, thereby reducing the carrier density, and the doped metal element can form a strong bond with oxygen. As a result, the portion of the oxide semiconductor material doped with a metal element such as gallium (Ga), tungsten (W), iron (Fe), or tin (Sn) becomes an oxide, and the insulation of the doped portion can be increased. Therefore, the portion of the active material layer 130 doped with at least one of gallium (Ga), tungsten (W), iron (Fe), and tin (Sn) can be the insulating portion 130i.

[0159] A metal element that is the same as the metal element included in the active region ACT of the active material layer 130 can be used as the first dopant. For example, the oxide semiconductor material constituting the active material layer 130 includes gallium (Ga), and gallium (Ga) can be used as the first dopant for forming the insulating portion 130i. In this case, the concentration of gallium (Ga) in the insulating portion 130i is higher than the concentration of gallium (Ga) in the active region ACT. Therefore, according to an embodiment of the present disclosure, when the active region ACT includes the same element as the first dopant (hereinafter referred to as "dopant element"), the concentration of the dopant element included in the insulating portion 130i is higher than the concentration of the dopant element included in the active region ACT.

[0160] Figure 9 FIG. 4 is a cross-sectional view of a thin film transistor 200 according to another embodiment of the present disclosure. Hereinafter, in order to avoid redundancy, components that have been described will be briefly described, or descriptions of components that have been described will be omitted.

[0161] Refer to Figure 9 , the gate insulating layer 140 can be patterned. As Figure 9 shown in FIG. 5, the gate insulating layer 140 can be patterned into a shape corresponding to the gate electrode 150.

[0162] The gate insulating layer 140 and the gate electrode 150 can be patterned in one process. During the patterning process of the gate insulating layer 140 and the gate electrode 150, selective conductivity can be performed to form the source connection portion 130a and the drain connection portion 130b. Specifically, during the patterning process of the gate insulating layer 140 and the gate electrode 150, selective conductivity can be performed in a plasma treatment process. As a result, the source connection portion 130a and the drain connection portion 130b can be formed.

[0163] According to an embodiment of the present disclosure, a plasma treatment process is performed after forming the insulating portion 130i by selectively doping with the first dopant. Since the insulating portion 130i has stable insulating characteristics ensured by doping with the first dopant, the insulating portion 130i is not electrically conductive and can maintain its insulating characteristics even when exposed to the plasma treatment process.

[0164] Figure 10 FIG. 6 is a cross-sectional view of a thin film transistor 300 according to another embodiment of the present disclosure.

[0165] Refer to Figure 10 , the active material layer 130 can have a multilayer structure.

[0166] According to another embodiment of the present disclosure, the active material layer 130 may include a first oxide semiconductor material layer MO1 and a second oxide semiconductor material layer MO2 on the first oxide semiconductor material layer MO1. The first oxide semiconductor material layer MO1 and the second oxide semiconductor material layer MO2 may include the same semiconductor material or different semiconductor materials.

[0167] The first oxide semiconductor material layer MO1 supports the second oxide semiconductor material layer MO2. Accordingly, the first oxide semiconductor material layer MO1 may be referred to as a support layer. A main channel portion may be formed in the second oxide semiconductor material layer MO2. However, embodiments of the present disclosure are not limited thereto, and a main channel portion may be formed in the first oxide semiconductor material layer MO1.

[0168] Figure 11 is a cross-sectional view of a thin film transistor 400 according to another embodiment of the present disclosure.

[0169] The thin film transistor 400 according to another embodiment of the present disclosure may further include a light-shielding layer 111 overlapping with the channel portion 130n.

[0170] The light-shielding layer 111 is disposed between the substrate 110 and the active material layer 130. Specifically, the light-shielding layer 111 may be disposed between the substrate 110 and the buffer layer 120.

[0171] The light-shielding layer 111 blocks light incident from the outside and protects the channel portion 130n. The light-shielding layer 111 may be made of a material having a light-blocking property. The light-shielding layer 111 may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloy, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe).

[0172] According to an embodiment of the present disclosure, the light-shielding layer 111 may have conductivity. The light-shielding layer 111 may be electrically connected to either the source electrode 160 or the drain electrode 170.

[0173] Refer to Figure 11 , the light-shielding layer 111 is connected to the source connection portion 130a. The light-shielding layer 111 may be electrically connected to the source electrode 160 through the source connection portion 130a. However, embodiments of the present disclosure are not limited thereto, and the light-shielding layer 111 may be connected to the drain connection portion 130b. The light-shielding layer 111 may be electrically connected to the drain electrode 175 through the drain connection portion 130b.

[0174] Figure 12 is a cross-sectional view of a thin film transistor 500 according to another embodiment of the present disclosure.

[0175] According to another embodiment of the present disclosure, the light-shielding layer 111 of the thin-film transistor 500 can be used as a capacitor electrode. Specifically, the thin-film transistor 500 according to another embodiment of the present disclosure may further include a first capacitor electrode CE1 that is integral with the light-shielding layer 111 and does not overlap with the channel portion 130n. The first capacitor electrode CE1 can be connected to the light-shielding layer 111. Referring to Figure 12 , a portion of the light-shielding layer 111 that does not overlap with the channel portion 130n can be used as the first capacitor electrode CE1.

[0176] Figure 12 FIG. shows a structure in which the light-shielding layer 111 is electrically connected to the source electrode 160 through the source connection portion 130a. In Figure 12 , the source connection portion 130a is the source electrode 160. Through this connection, the first capacitor electrode CE1 can be connected to the source electrode 160 through the source connection portion 130a. Referring to Figure 12 , the first capacitor electrode CE1 is connected to the light-shielding layer 111, so the first capacitor electrode CE1 can be applied with the same voltage as the voltage applied to the source electrode 160.

[0177] In Figure 12 , in the thin-film transistor 500 shown, the source connection portion 130a serves as the source electrode 160.

[0178] According to another embodiment of the present disclosure, the thin-film transistor 500 may include a second capacitor electrode CE2. Referring to Figure 12 , the second capacitor electrode CE2 can be formed in the active material layer 130. For example, a portion of the active material layer 130 can be made conductive to become the second capacitor electrode CE2.

[0179] Specifically, the active material layer 130 may include a second capacitor electrode CE2 that is separated from the channel portion 130n. The second capacitor electrode CE2 can be insulated from at least one of the source connection portion 130a and the drain connection portion 130b through the insulating portion 130i. Referring to Figure 12 , the second capacitor electrode CE2 is separated and insulated from the source connection portion 130a with the insulating portion 130i therebetween. In addition, the second capacitor electrode CE2 is separated and insulated from the drain connection portion 130b.

[0180] According to another embodiment of the present disclosure, the first capacitor electrode CE1 and the second capacitor electrode CE2 can overlap each other to form a first capacitor C1.

[0181] Referring to Figure 12 , the thin-film transistor 500 may include a third capacitor electrode CE3. The third capacitor electrode CE3 can be disposed on the interlayer insulating film 145.

[0182] The third capacitor electrode CE3 may overlap with the second capacitor electrode CE2. The second capacitor electrode CE2 and the third capacitor electrode CE3 may overlap with each other to form a second capacitor C2. A total capacitor Ct may be formed by the first capacitor C1 and the second capacitor C2.

[0183] Referring to Figure 12 , a passivation layer 180 may be provided on the drain electrode 175 and the third capacitor electrode CE3. Bridging electrodes BR1, BR2 may be provided on the passivation layer 180.

[0184] Referring to Figure 12 , the third capacitor electrode CE3 may be connected to the first capacitor electrode CE1 through the bridging electrode BR1. Through this connection, the same voltage may be applied to the first capacitor electrode CE1 and the third capacitor electrode CE3. In the thin film transistor 500 shown in Figure 12 , the third capacitor electrode CE3 may be subjected to the same voltage as the voltage applied to the source electrode 160.

[0185] The second capacitor electrode CE2 may be connected to the gate electrode 150 through another bridging electrode BR2. This connection causes the same voltage as the gate electrode 150 to be applied to the second capacitor electrode CE2.

[0186] Figure 13A is a cross-sectional view of a thin film transistor substrate 600 according to another embodiment of the present disclosure.

[0187] Figure 13A shows a structure in which two thin film transistors TFT1, TFT2 are formed of one active material layer 130.

[0188] Referring to Figure 13A , a thin film transistor substrate 600 according to another embodiment of the present disclosure includes a first thin film transistor TFT1 and a second thin film transistor TFT2 on a base substrate 110, and the first thin film transistor TFT1 and the second thin film transistor TFT2 include an active material layer 130.

[0189] Specifically, referring to Figure 13A , the first thin film transistor TFT1 includes a first channel portion 131n on the base substrate 110, a first source connection portion 131a connected to one side of the first channel portion 131n, a first drain connection portion 131b connected to the other side of the first channel portion 131n, and a first gate electrode 151 separated from the active material layer 130 and overlapping with the first channel portion 131n. According to another embodiment of the present disclosure, the first channel portion 131n, the first source connection portion 131a, and the first drain connection portion 131b may be referred to as a first active region ACT1. Referring to Figure 13A, the first thin film transistor TFT1 may include a first source electrode 161 and a first drain electrode 171 disposed on the interlayer insulating film 145.

[0190] The second thin film transistor TFT2 includes a second channel portion 132n on the base substrate 110, a second source connection portion 132a connected to one side of the second channel portion 132n, a second drain connection portion 132b connected to the other side of the second channel portion 132n, and a second gate electrode 152 separated from the active material layer 130 and overlapping the second channel portion 132n. According to another embodiment of the present disclosure, the second channel portion 132n, the second source connection portion 132a, and the second drain connection portion 132b may be referred to as the second active region ACT2. Refer to Figure 13A , the second thin film transistor TFT2 may include a second source electrode 162 and a second drain electrode 172 disposed on the interlayer insulating film 145.

[0191] The active material layer 130 includes a first channel portion 131n, a first source connection portion 131a, a first drain connection portion 131b, a second channel portion 132n, a second source connection portion 132a, a second drain connection portion 132b, and an insulating portion 130i. The first channel portion 131n, the first source connection portion 131a, the first drain connection portion 131b, the second channel portion 132n, the second source connection portion 132a, the second drain connection portion 132b, and the insulating portion 130i may be disposed in the same layer.

[0192] According to another embodiment of the present disclosure, the first channel portion 131n, the first source connection portion 131a, the first drain connection portion 131b, the second channel portion 132n, the second source connection portion 132a, the second drain connection portion 132b, and the insulating portion 130i included in the active material layer 130 may all be disposed on the buffer layer 120.

[0193] According to another embodiment of the present disclosure, the active material layer 130 may be configured to have a single structure that is not patterned. Therefore, the first channel portion 131n, the first source connection portion 131a, the first drain connection portion 131b, the second channel portion 132n, the second source connection portion 132a, the second drain connection portion 132b, and the insulating portion 130i may be integrally formed.

[0194] Figure 13B is Figure 13A a plan view of the active material layer 130.

[0195] Refer to Figure 13B, the active material layer 130 may have an integrated structure including a first channel portion 131n, a first source connection portion 131a, a first drain connection portion 131b, a second channel portion 132n, a second source connection portion 132a, a second drain portion, and an insulating portion 130i.

[0196] In Figure 13B , the region outside the first active region ACT1 and the second active region ACT2 of the active material layer 130 may be the insulating portion 130i. In Figure 13B , an active material layer 130 is shown in which all regions other than the first channel portion 131n, the first source connection portion 131a, the first drain connection portion 131b, the second channel portion 132n, the second source connection portion 132a, and the second drain connection portion 132b are the insulating portion 130i. However, embodiments of the present disclosure are not limited thereto, and the active material layer 130 may further include a capacitor electrode, a wiring portion, and the like.

[0197] According to another embodiment of the present disclosure, the first thin film transistor TFT1 and the second thin film transistor TFT2 may be separated from each other with the insulating portion 130i therebetween. The insulating portion 130i may be used as an insulator for electrically separating components from each other.

[0198] In addition, at least one of the first source connection portion 131a and the first drain connection portion 131b is insulated from at least one of the second source connection portion 132a and the second drain connection portion 132b through the insulating portion 130i.

[0199] The active material layer 130 may include an oxide semiconductor material. Specifically, the first channel portion 131n, the first source connection portion 131a, the first drain connection portion 131b, the second channel portion 132n, the second source connection portion 132a, the second drain connection portion 132b, and the insulating portion 130i may include an oxide semiconductor material.

[0200] The insulating portion 130i further includes a first dopant. The first dopant may include at least one of nitrogen (N), sulfur (S), chlorine (Cl), gallium (Ga), tungsten (W), iron (Fe), and tin (Sn). By doping with the first dopant, a specific portion of the active material layer 130 including the oxide semiconductor material may selectively have insulating properties. Since the first dopant and dopant doping have been described, their detailed description will be omitted.

[0201] The first source connection portion 131a, the first drain connection portion 131b, the second source connection portion 132a, and the second drain connection portion 132b may include a second dopant. The second dopant is different from the first dopant. The second dopant may include at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H).

[0202] The second dopant may have a function opposite to that of the first dopant. By doping with the second dopant, a part of the active material layer 130 including the oxide semiconductor material can be selectively conductive. During the conductivity process using the second dopant, the insulating portion 130i can be doped with the second dopant. As a result, the insulating portion 130i may further include the second dopant. Since the second dopant and the conductivity have been described, their detailed descriptions will be omitted.

[0203] Figure 14 is a cross-sectional view of a thin film transistor substrate 700 according to another embodiment of the present disclosure. Referring to Figure 14 , the thin film transistors TFT1 and TFT2 can be connected to the capacitor Ct.

[0204] Figure 14 The thin film transistor substrate 700 shown in includes a light-shielding layer 111 and a bridging electrode BR13 provided on the base substrate 110. The light-shielding layer 111 overlaps with the second channel portion 132n of the second thin film transistor TFT2.

[0205] According to another embodiment of the present disclosure, the thin film transistor substrate 700 may include a first capacitor electrode CE1. The first capacitor electrode CE1 may be integrally formed with the light-shielding layer 111 and does not overlap with the second channel portion 132n. Referring to Figure 14 , the portion of the light-shielding layer 111 that does not overlap with the second channel portion 132n may be the first capacitor electrode CE1.

[0206] The light-shielding layer 111 can be connected to the second drain connection portion 132b of the second thin film transistor TFT2. Since the first capacitor electrode CE1 is connected to the light-shielding layer 111, the first capacitor electrode CE1 can be applied with the same voltage as the voltage applied to the second drain connection portion 132b.

[0207] In Figure 14 the thin film transistor substrate 700 shown, the second drain connection portion 132b can be used as the second drain electrode 1752, and the second source connection portion 132a can be used as the second source electrode 162.

[0208] According to another embodiment of the present disclosure, the thin film transistor substrate 700 may include a second capacitor electrode CE2. The second capacitor electrode CE2 may be formed in the active material layer 130. For example, a part of the active material layer 130 may be made conductive to become the second capacitor electrode CE2.

[0209] Referring Figure 14 , the active material layer 130 may include a second capacitor electrode CE2 separated from the second channel portion 132n. The second capacitor electrode CE2 may be insulated from the second drain connection portion 132b by an insulating portion 130i. The first capacitor electrode CE1 and the second capacitor electrode CE2 overlap to form a first capacitor C1.

[0210] Referring Figure 14 , the thin film transistor substrate 700 may further include a third capacitor electrode CE3. The third capacitor electrode CE3 may overlap with the second capacitor electrode CE2. The second capacitor electrode CE2 and the third capacitor electrode CE3 overlap to form a second capacitor C2. A capacitor Ct as a total capacitor may be formed by the first capacitor C1 and the second capacitor C2.

[0211] Referring Figure 14 , the third capacitor electrode CE3 may be connected to the first capacitor electrode CE1 through a bridging electrode BR12. Through this connection, the same voltage may be applied to the first capacitor electrode CE1 and the third capacitor electrode CE3. In Figure 14 the thin film transistor substrate 700 shown, the third capacitor electrode CE3 may be applied with the same voltage as the voltage of the second drain connection portion 132b.

[0212] The second capacitor electrode CE2 may be connected to the second gate electrode 152 of the second thin film transistor TFT2 through a bridging electrode BR11. Through this connection, the same voltage as the voltage applied to the second gate electrode 152 may be applied to the second capacitor electrode CE2.

[0213] In addition, the second gate electrode 152 of the second thin film transistor TFT2 may be connected to the first drain connection portion 131b of the first thin film transistor TFT1 through a bridging electrode BR13. As a result, the same voltage may be applied to the first drain connection portion 131b of the first thin film transistor TFT1, the second gate electrode 152 of the second thin film transistor TFT2, and the second capacitor electrode CE2. In addition, the signal transmitted to the first drain connection portion 131b through the first thin film transistor TFT1 may be applied to the second gate electrode 152 of the second thin film transistor TFT2.

[0214] Referring Figure 14, the gate insulating layers 141 and 142 can be patterned. The first gate electrode 151 is disposed on the first gate insulating film 141 of the first thin film transistor TFT1, and the second gate electrode 152 can be disposed on the second gate insulating film 142 of the second thin film transistor TFT2. In the thin film transistor substrate 700 shown in Figure 14 , in the thin film transistor substrate 700, the first drain connection portion 131b can be used as the first drain electrode 175, and the first source connection portion 131a can be used as the first source electrode 161.

[0215] Hereinafter, a method of manufacturing the thin film transistor substrate 600 according to another embodiment of the present disclosure will be described with reference to Figures 15A to 15F . The manufacturing method shown in Figures 15A to 15F can also be applied to the thin film transistors 100, 200, 300, 400, and 500 according to the embodiments of the present disclosure. Therefore, Figures 15A to 15F the manufacturing method of the thin film transistor substrate 600 shown in

[0216] Figures 15A to 15F can be referred to as a method of manufacturing a thin film transistor.

[0217] Referring to Figure 15A , to manufacture the thin film transistor substrate 600 or the thin film transistor, an active material layer 130 is formed on the base substrate 110. Specifically, as shown in Figure 15A , a buffer layer 120 can be formed on the base substrate 110, and an active material layer 130 can be formed on the buffer layer 120. A light-shielding layer 111 can be further formed between the base substrate 110 and the buffer layer 120.

[0218] Referring to Figure 15B , masks 410 and 420 are formed on the active material layer 130. According to another embodiment of the present disclosure, the masks 410 and 420 can be formed of a photoresist. The photoresist patterns formed by exposure and development of the photoresist can become the masks 410 and 420.

[0219] The masks 410 and 420 are formed in regions overlapping with the active regions ACT1 and ACT2. For example, the first mask 410 is formed on a region overlapping with the first active region ACT1 of the first thin film transistor TFT1, and the second mask 420 can be formed on a region overlapping with the second active region ACT2 of the second thin film transistor TFT2.

[0220] Referring to Figure 15C , doping is performed to form the insulating portion 130i. Specifically, the regions of the active material layer 130 that do not overlap with the masks 410 and 420 are doped with a first dopant to form the insulating portion 130i.

[0221] According to another embodiment of the present disclosure, the first dopant may include at least one of nitrogen (N), sulfur (S), chlorine (Cl), gallium (Ga), tungsten (W), iron (Fe), and tin (Sn). Refer to Figure 15C , for example, the insulating portion 130i may be formed by nitrogen doping. The regions of the active material layer 130 that overlap with the masks 410 and 420 are not doped with the first dopant.

[0222] The regions of the active material layer 130 that overlap with the masks 410 and 420 are not doped to form the first active region ACT1 of the first thin film transistor TFT1 and the second active region ACT2 of the second thin film transistor TFT2.

[0223] Refer to Figure 15D , and the masks 410 and 420 are removed. Accordingly, the active material layer 130 including the active regions ACT1 and ACT2 is formed.

[0224] Refer to Figure 15E , a gate insulating layer 140 is formed on the active material layer 130, and gate electrodes 151 and 152 are formed on the gate insulating layer 140. The gate electrodes 151 and 152 are formed on the active material layer 130 while being separated from the active material layer 130. Specifically, the first gate electrode 151 is formed to at least partially overlap with the first active region ACT1 of the first thin film transistor TFT1, and the second gate electrode 152 is formed to at least partially overlap with the second active region ACT2 of the second thin film transistor TFT2.

[0225] Next, a conductivity-imparting process is performed. The regions of the active material layer 130 that do not overlap with the gate electrodes 151 and 152 are made conductive through the conductivity-imparting process, thereby forming source connection portions 131a and 132a and drain connection portions 131b and 132b. In the active regions ACT1 and ACT2, the regions that overlap with the gate electrodes 151 and 152 are not made conductive and become channel portions 131n and 132n.

[0226] Specifically, through the conductivity-imparting process, the regions of the first active region ACT1 that do not overlap with the first gate electrode 151 are made conductive to form the first source connection portion 131a and the first drain connection portion 131b. In addition, the regions of the second active region ACT2 that do not overlap with the second gate electrode 152 are made conductive to form the second source connection portion 132a and the second drain connection portion 132b.

[0227] The portion of the first active region ACT1 that overlaps with the first gate electrode 151 becomes the first channel portion 131n. The portion of the second active region ACT2 that overlaps with the second gate electrode 152 becomes the second channel portion 132n.

[0228] The source connection portions 131a and 132a are disposed between the channel portions 131n and 132n and the insulating portion 130i. The drain connection portions 131b and 132b are separated from the source connection portions 131a and 132a and are disposed between the channel portions 131n and 132n and the insulating portion 130i.

[0229] Conductivization can be achieved by plasma treatment or doping with a second dopant. According to another embodiment of the present disclosure, the second dopant can be different from the first dopant.

[0230] When conductivization is achieved by doping with a second dopant, at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H) can be used as the second dopant.

[0231] Next, referring to Figure 15F , an interlayer insulating film 145 is formed on the gate electrodes 151 and 152 and the source electrodes 161 and 162, and drain electrodes 175 and 172 are formed on the interlayer insulating film 145 to complete the first thin film transistor TFT1 and the second thin film transistor TFT2. Accordingly, a thin film transistor according to an embodiment of the present disclosure can be manufactured, and a thin film transistor substrate 600 according to another embodiment of the present disclosure can be manufactured.

[0232] Hereinafter, a display device including the above-described thin film transistor or thin film transistor substrate will be described in detail.

[0233] Figure 16 is a schematic diagram of a display device 800 according to another embodiment of the present disclosure.

[0234] A display device 800 according to another embodiment of the present disclosure may include a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0235] Gate lines GL and data lines DL are disposed in the display panel 310, and pixels P are disposed at intersections of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P.

[0236] The controller 340 controls the gate driver 320 and the data driver 330.

[0237] For example, the controller 340 uses signals provided from an external system (not shown) to generate a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330. In addition, the controller 340 samples input image data input from the external system, realigns it, and provides the realigned digital image data RGB to the data driver 330.

[0238] The gate control signal GCS includes a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, and a gate clock GCLK. In addition, the gate control signal GCS may include a control signal for controlling the shift register 350.

[0239] The data control signal DCS includes a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

[0240] The data driver 330 provides a data voltage to the data lines DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into an analog data voltage and provides the data voltage to the data lines DL.

[0241] The gate driver 320 may include a shift register 350. The shift register 350 sequentially provides gate pulses to the gate lines GL in one frame using the start signal and the gate clock transmitted from the controller 340.

[0242] The gate driver 320 may sequentially provide a gate pulse GP to the gate line GL during one frame using the shift register 350. Here, one frame refers to a period during which one image is output through the display panel. In addition, the gate driver 320 provides a gate cut-off signal Goff capable of turning off the switching element to the gate line GL during the remaining period in one frame when the gate pulse GP is not provided. Hereinafter, the gate pulse GP and the gate cut-off signal Goff are collectively referred to as a scan signal SS.

[0243] According to an embodiment of the present disclosure, the gate driver 320 may be mounted in the display panel 310. In this way, a structure in which the gate driver 320 is directly mounted in the display panel 310 is referred to as an in-panel gate (GIP) structure.

[0244] As Figure 16 shown, the display panel 310 may include a plurality of pixels P. The plurality of pixels P may be disposed on a substrate 110. Each of the plurality of pixels P may include a pixel driving circuit PDC. The plurality of pixel driving circuits PDC corresponding to the plurality of pixels P may be disposed on the substrate 110.

[0245] Each of the plurality of pixel driving circuits PDC may include the above-described thin film transistor TFT. In addition, each of the plurality of pixel driving circuits PDC may include the above-described first thin film transistor TFT1 and second thin film transistor TFT2. Each of the thin film transistors TFT, TFT1, and TFT2 included in the pixel driving circuit PDC includes an active material layer 130, and the active material layer 130 may be integrally formed over all of the plurality of pixels P.

[0246] According to an embodiment of the present disclosure, the active material layer 130 may be integrally formed in each of the plurality of pixels P without patterning. In addition, the active material layer 130 may be integrally formed between the plurality of pixels P. Specifically, the active material layer 130 may be integrally formed between the plurality of pixels P without patterning.

[0247] Figure 17 is Figure 16 a circuit diagram of the pixel P, Figure 18 is Figure 17 a plan view of the pixel P, and Figure 19 is Figure 18 a cross-sectional view taken along II-II” of

[0248] Figure 17 The circuit diagram of

[0249] is an equivalent circuit diagram of the pixel P of the display device 800 including the organic light emitting diode OLED as the display element 710.

[0250] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by a scan signal SS provided via the gate line GL. The above-described thin film transistor TFT or the first thin film transistor TFT1 may be applied as Figure 17 the first thin film transistor TR1 of

[0251] The data line DL provides a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls the application of the data voltage Vdata.

[0252] The driving power supply line PL provides a driving voltage Vdd to the display element 710, and the second thin film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode OLED as the display element 710. The above-described thin film transistor TFT or the second thin film transistor TFT2 may be applied as Figure 17 the second thin film transistor TR2 of

[0253] When the first thin-film transistor TR1 is turned on by a scanning signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata provided from the data line DL is supplied to the gate electrode of the second thin-film transistor TR2 connected to the display element 710. The data voltage Vdata is charged into the capacitor Ct formed between the gate electrode and the source electrode of the second thin-film transistor TR2. Figure 17 The capacitor Ct is a storage capacitor.

[0254] The amount of current supplied to the organic light-emitting diode OLED serving as the display element 710 through the second thin-film transistor TR2 is controlled according to the data voltage Vdata, so that the gray level of the light emitted from the display element 710 can be controlled.

[0255] Refer to Figure 18 and Figure 19 The first thin-film transistor TR1 and the second thin-film transistor TR2 are provided on the substrate 110.

[0256] The substrate 110 can be made of glass or plastic. As the substrate 110, a plastic having flexible characteristics such as polyimide PI can be used.

[0257] A light-shielding layer 111 is provided on the substrate 110. The light-shielding layer 111 can have a light-blocking property. The light-shielding layer 111 can protect the active material layer and the channel portion A2 by blocking the light incident from the outside. A part of the light-shielding layer 111 can become the first capacitor electrode CE1. Refer to Figure 18 and Figure 19 The light-shielding layer 111 and the first capacitor electrode CE1 can be integrally formed.

[0258] In addition, the data line DL, the driving power line PL, and the first bridging electrode BR21 can be provided on the substrate 110.

[0259] A buffer layer 120 is provided on the light-shielding layer 111, the first capacitor electrode CE1, the data line DL, the driving power line PL, and the first bridging electrode BR21. The buffer layer 120 can be made of an insulating material and protect the channel portions A1 and A2 from moisture or oxygen entering from the outside.

[0260] An active material layer 130 is provided on the buffer layer 120. The active material layer 130 can include an oxide semiconductor material. The active material layer 130 can include an oxide semiconductor layer made of an oxide semiconductor material.

[0261] The active material layer 130 includes a first channel portion A1, a first source connection portion, a first drain connection portion, a second channel portion A2, a second source connection portion, a second drain connection portion, and an insulating portion 130i. Refer to Figure 18 andFigure 19 , the first source connection portion becomes the first source electrode S1, the first drain connection portion becomes the first drain electrode D1, the second source connection portion becomes the second source electrode S2, and the second drain connection portion becomes the second drain electrode D2.

[0262] In addition, a part of the active material layer 130 can be made conductive to become the second capacitor electrode CE2. In another embodiment of the present disclosure, the drain region of the first thin film transistor TR1 can be extended to become the second capacitor electrode CE2.

[0263] According to an embodiment of the present disclosure, the active material layer 130 can be integrally formed within each pixel P without patterning. In addition, multiple active material layers 130 can be integrally formed between pixels P without patterning.

[0264] The first source electrode S1 of the first thin film transistor TR1 is connected to the data line DL through a contact hole. The first drain electrode D1 of the first thin film transistor TR1 is connected to the first bridging electrode BR21 through a contact hole.

[0265] The second source electrode S2 of the second thin film transistor TR2 is connected to the light shielding layer 111 through a contact hole. Therefore, the first capacitor electrode CE1 can be applied with the same voltage as that of the second source electrode S2.

[0266] A gate insulating layer 140 is provided on the active material layer 130. The gate insulating layer 140 has insulating properties and separates the active material layer 130 from the gate electrodes G1, G2. The gate insulating layer 140 can cover the entire top surface of the active material layer 130.

[0267] The first gate electrode G1 of the first thin film transistor TR1 and the second gate electrode G2 of the second thin film transistor TR2 are provided on the gate insulating layer 140.

[0268] Refer to Figure 18 and Figure 19 , an interlayer insulating film 145 is provided on the gate electrodes G1, G2, and a third capacitor electrode CE3 is provided on the interlayer insulating film 145. The third capacitor electrode CE3 can be arranged to overlap with the first capacitor electrode CE1 and the second capacitor electrode CE2.

[0269] A passivation layer 180 can be provided on the third capacitor electrode CE3. The passivation layer 180 protects the thin film transistors TR1, TR2.

[0270] A gate line GL and bridging electrodes BR22, BR23, BR24 are provided on the passivation layer 180.

[0271] The gate line GL is connected to the first gate electrode G1 of the first thin film transistor TR1 through a contact hole. Accordingly, a scan signal SS can be applied to the first gate electrode G1 of the first thin film transistor TR1.

[0272] A second bridging electrode BR22 is disposed on the passivation layer 180, and the second bridging electrode BR22 connects the driving power line PL and the second drain electrode D2 of the second thin film transistor TR2. Specifically, referring to Figure 18 , a part of the second bridging electrode BR22 is connected to the driving power line PL through a contact hole, and another part of the second bridging electrode BR22 is connected to the second drain electrode D2 of the second thin film transistor TR2 through another contact hole. Accordingly, a driving voltage Vdd can be applied to the second drain electrode D2 of the second thin film transistor TR2.

[0273] A third bridging electrode BR23 is disposed on the passivation layer 180, and the third bridging electrode BR23 connects the first bridging electrode BR21, the second gate electrode G2 of the second thin film transistor TR2, and the second capacitor electrode CE2.

[0274] Since the first bridging electrode BR21 is connected to the first drain electrode D1 of the first thin film transistor TR1, a data voltage Vdata transmitted to the first drain electrode D1 through the first thin film transistor TR1 can be applied to the second gate electrode G2 of the second thin film transistor TT2 via the first bridging electrode BR21 and the third bridging electrode BR23.

[0275] In addition, a voltage identical to the voltage of the second gate electrode G2 can be applied to the second capacitor electrode CE2 through the third bridging electrode BR23.

[0276] Accordingly, the same voltage can be applied to the first drain electrode D1 of the first thin film transistor TR1, the second gate electrode G2 of the second thin film transistor TR2, and the second capacitor electrode CE2.

[0277] A fourth bridging electrode BR24 is disposed on the passivation layer 180, and the fourth bridging electrode BR24 connects the light shielding layer 111 and the third capacitor electrode CE3. Accordingly, a voltage identical to the voltage of the first capacitor electrode CE1 can be applied to the third capacitor electrode CE3. Referring to Figure 18 and Figure 19 , the third capacitor electrode CE3 can be subjected to the same voltage as the second source electrode S2 of the second thin film transistor TR2.

[0278] The first capacitor C1 can be formed by overlapping the first capacitor electrode CE1 and the second capacitor electrode CE2. The second capacitor C2 can be formed by overlapping the second capacitor electrode CE2 and the third capacitor electrode CE3. The total capacitor Ct is formed by the first capacitor C1 and the second capacitor C2.

[0279] A planarization layer 190 is provided on the gate line GL and the bridge electrodes BR22, BR23, BR24. The planarization layer 190 planarizes the upper portions of the first thin film transistor TR1 and the second thin film transistor TR2 and protects the first thin film transistor TR1 and the second thin film transistor TR2.

[0280] The first electrode 711 of the display element 710 is provided on the planarization layer 190. The first electrode 711 of the display element 710 can contact the fourth bridge electrode BR24 through a contact hole formed in the planarization layer 190. Accordingly, the first electrode 711 can be connected to the second source electrode S2 of the second thin film transistor TR2.

[0281] A bank layer 750 is provided at the edge of the first electrode 711. The bank layer 750 defines the light emitting region of the display element 710.

[0282] An organic light emitting layer 712 is provided on the first electrode 711, and a second electrode 713 is provided on the organic light emitting layer 712. Accordingly, the display element 710 can be completed. Figure 19 The display element 710 shown in is an organic light emitting diode OLED. Accordingly, the display device 800 according to an embodiment of the present disclosure can be referred to as an organic light emitting display device.

[0283] Figure 20 is a circuit diagram of a pixel P of a display device 900 according to another embodiment of the present disclosure.

[0284] Figure 20 The pixel P included in the display device 900 of includes an organic light emitting diode OLED as the display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0285] In the pixel P, signal lines DL, EL, GL, PL, SCL, and RL for providing signals to the pixel driving circuit PDC are provided.

[0286] A data voltage Vdata is provided to the data line DL, a scan signal SS is provided to the gate line GL, and a driving voltage Vdd for driving the pixel is provided to the driving power line PL. A reference voltage Vref is provided to the reference line RL, and a sense control signal SCS is provided to the sense control line SCL.

[0287] Refer to Figure 20, the gate line of the n-th pixel P is labeled as "GLn", and the gate line of the adjacent (n + 1)-th pixel P (i.e., "GLn+1") can be used as the sensing control line SCL of the n-th pixel P.

[0288] For example, the pixel driving circuit PDC includes a first thin film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, a second thin film transistor TR2 (driving transistor) for controlling the magnitude of the current output to the display element 710 according to the data voltage Vdata transmitted through the first thin film transistor TR1, and a third thin film transistor TR3 (sensing transistor) for sensing the characteristics of the first thin film transistor TR1.

[0289] The capacitor C1 is located between the gate electrode of the second thin film transistor TR2 and the display element 710. The capacitor C1 provided between the first node n1 and the second node n2 is also referred to as the storage capacitor Cst.

[0290] The first thin film transistor TR1 is turned on by the scan signal SS provided to the gate line GL, and transmits the data voltage Vdata provided to the data line DL to the gate electrode of the second thin film transistor TR2.

[0291] The third thin film transistor TR3 is connected to the first node n1 between the second thin film transistor TR2 and the display element 710, and is connected to the reference line RL. The third thin film transistor TR3 is turned on or off by the sensing control signal SCS, and senses the characteristics of the second thin film transistor TR2 as a driving transistor during the sensing period.

[0292] The second node n2 connected to the gate electrode of the second thin film transistor TR2 is connected to the first thin film transistor TR1.

[0293] When the first thin film transistor TR1 is turned on, the data voltage Vdata provided through the data line DL is provided to the gate electrode of the second thin film transistor TR2. The data voltage Vdata is charged into the capacitor C1 formed between the gate electrode and the source electrode of the second thin film transistor TR2.

[0294] The light emission control signal EM is provided to the light emission control line EL.

[0295] The fourth thin film transistor TR4 is a light emission control transistor for controlling the light emission timing by controlling the second thin film transistor TR2. The fourth thin film transistor TR4 transmits the driving voltage Vdd to the second thin film transistor TR2 or blocks the driving voltage Vdd according to the light emission control signal EM. When the fourth thin film transistor TR4 is turned on, a current is provided to the second thin film transistor TR2, so that light is emitted from the display element 710.

[0296] The pixel driving circuit PDC according to another embodiment of the present disclosure may be formed into various structures other than those described above. The pixel driving circuit PDC may include, for example, three thin film transistors or five thin film transistors or more thin film transistors. In addition, the pixel driving circuit PDC may include two or more capacitors.

[0297] The present disclosure described above is not limited to the above embodiments and drawings, and it is well known to those skilled in the art that various substitutions, modifications, and changes can be made within the scope of the technical details of the present disclosure.

Claims

1. A thin film transistor, comprising: an active material layer on a base substrate; as well as a gate electrode, the gate electrode being spaced apart from the active material layer and overlapping at least a portion of the active material layer, The active material layer comprises: a channel portion, the channel portion overlapping the gate electrode; a source connection portion, the source connection portion being in contact with one side of the channel portion; a drain connection portion contacting the other side of the channel portion; and an insulating portion contacting at least one of the source connecting portion and the drain connecting portion, and The channel portion, the source connecting portion, the drain connecting portion and the insulating portion are arranged in the same layer.

2. The thin film transistor according to claim 1, wherein the active material layer comprises an oxide semiconductor material, and The insulating portion includes a first dopant.

3. The thin film transistor according to claim 2, The first dopant includes at least one of nitrogen (N), sulfur (S), chlorine (Cl), gallium (Ga), tungsten (W), iron (Fe) and tin (Sn).

4. The thin film transistor according to claim 2, wherein each of the source connecting portion and the drain connecting portion includes a second dopant different from the first dopant.

5. The thin film transistor according to claim 4, The second dopant includes at least one of boron (B), phosphorus (P), fluorine (F) and hydrogen (H).

6. The thin film transistor according to claim 4, Wherein the insulating portion further includes the second dopant.

7. The thin film transistor according to claim 2, The oxide semiconductor material includes at least one of IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, ITZO (InSnZnO)-based, InO-based, ZnO-based and FIZO (FeInZnO)-based oxide semiconductor materials.

8. The thin film transistor according to claim 1, The channel portion, the source connecting portion, the drain connecting portion and the insulating portion are integrally formed.

9. The thin film transistor according to claim 1, A light shielding layer is further included, which is disposed between the base substrate and the active material layer and overlaps with the channel portion.

10. The thin film transistor according to claim 9, A first capacitor electrode is further included, the first capacitor electrode being integrally formed with the light shielding layer and not overlapping the channel portion.

11. The thin film transistor according to claim 10, wherein the active material layer includes a second capacitor electrode separated from the channel portion, and The second capacitor electrode is insulated from at least one of the source connection portion and the drain connection portion by the insulating portion, and The first capacitor electrode and the second capacitor electrode overlap each other to form a first capacitor.

12. The thin film transistor according to claim 3, wherein the first dopant comprises nitrogen (N), and The insulating portion includes 40 to 60 atomic % (at %) of oxygen and 4 to 10 atomic % (at %) of nitrogen based on the total number of atoms of the insulating portion.

13. The thin film transistor according to claim 3, The oxide semiconductor material includes gallium (Ga), and the first dopant includes gallium (Ga).

14. The thin film transistor according to claim 13, The concentration of gallium (Ga) included in the insulating portion is higher than the concentration of gallium (Ga) included in the channel portion, the source connecting portion, or the drain connecting portion.

15. The thin film transistor according to claim 2, The active material layer includes a first oxide semiconductor material layer and a second oxide semiconductor material layer on the first oxide semiconductor material layer.

16. A thin film transistor substrate, comprising a first thin film transistor and a second thin film transistor on a base substrate, wherein the first thin film transistor and the second thin film transistor include an active material layer, The first thin film transistor comprises: a first channel portion, the first channel portion being on the base substrate; a first source connection portion, the first source connection portion being in contact with one side of the first channel portion; a first drain connection portion, the first drain connection portion being in contact with the other side of the first channel portion; and a first gate electrode, the first gate electrode being separated from the active material layer and overlapping the first channel portion, The second thin film transistor comprises: a second channel portion, the second channel portion being on the base substrate; a second source connection portion, the second source connection portion being in contact with one side of the second channel portion; a second drain connection portion contacting the other side of the second channel portion; and a second gate electrode, the second gate electrode being spaced apart from the active material layer and overlapping the second channel portion, wherein the first thin film transistor and the second thin film transistor are separated from each other with an insulating portion therebetween, The active material layer includes the first channel portion, the first source connecting portion, the first drain connecting portion, the second channel portion, the second source connecting portion, the second drain connecting portion and the insulating portion, and The first channel portion, the first source connection portion, the first drain connection portion, the second channel portion, the second source connection portion, the second drain connection portion, and the insulating portion are disposed in the same layer.

17. The thin film transistor substrate according to claim 16, The first channel portion, the first source connecting portion, the first drain connecting portion, the second channel portion, the second source connecting portion, the second drain connecting portion and the insulating portion are integrally formed.

18. The thin film transistor substrate according to claim 16, wherein the first channel portion, the first source connection portion, the first drain connection portion, the second channel portion, the second source connection portion, the second drain connection portion and the insulating portion comprise an oxide semiconductor material, and Wherein the insulating portion further comprises a first dopant.

19. The thin film transistor substrate according to claim 18, The first dopant includes at least one of nitrogen (N), sulfur (S), chlorine (Cl), gallium (Ga), tungsten (W), iron (Fe) and tin (Sn).

20. The thin film transistor substrate according to claim 18, The first source connecting portion, the first drain connecting portion, the second source connecting portion, and the second drain connecting portion include a second dopant different from the first dopant.

21. A display device comprising a plurality of pixels arranged on a base substrate, wherein each of the plurality of pixels comprises: Display components; as well as a pixel driving circuit for driving the display element, The pixel driving circuit comprises a thin film transistor according to any one of claims 1 to 15.

22. The display device according to claim 21, The active material layer is integrally formed on the plurality of pixels.

23. A method for manufacturing a thin film transistor, the method comprising: forming an active material layer on a base substrate; forming a mask on the active material layer; forming an insulating portion by doping a first dopant into a portion of the active material layer that does not overlap the mask; forming a gate electrode on the active material layer and separated from the active material layer; as well as forming a source connection portion and a drain connection portion by making conductive a portion of the active material layer that does not overlap the gate electrode, wherein a portion of the active material layer overlapping with the gate electrode forms a channel portion, wherein the source connection portion is disposed between the channel portion and the insulating portion, and The drain connection portion is spaced apart from the source connection portion and is disposed between the channel portion and the insulating portion.

24. The method according to claim 23, The first dopant includes at least one of nitrogen (N), sulfur (S), chlorine (Cl), gallium (Ga), tungsten (W), iron (Fe) and tin (Sn).

25. The method according to claim 23, The conducting is performed by plasma treatment or doping with a second dopant.

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