Method for manufacturing electronic device and electronic device

Abstract

The present invention discloses a method for manufacturing an electronic device and an electronic device, generally relating to the field of semiconductor manufacturing technology. The method comprises: depositing a stress layer comprising a negative Poisson's ratio material in a manufacturing region of a wafer; annealing the wafer; and removing the stress layer from the manufacturing region of the wafer. The disclosed method for manufacturing an electronic device utilizes a negative Poisson's ratio material as a stress layer in a stress memory technique. This allows the stress layer crystals to maintain a stretched state in both the lateral and longitudinal directions due to thermal expansion of the gate electrode layer, thereby improving carrier mobility in the channel.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor manufacturing technology. More specifically, the present invention relates to a method for manufacturing an electronic device and the electronic device. Background Art

[0002] Stress Memorization Technique (SMT) is an important method to improve the carrier mobility in N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (N-MOSFET).

[0003] In existing technologies, stress memory technology typically uses silicon nitride (SiN) as the stress layer material. During the spike annealing process, the silicon nitride and the polysilicon in the gate electrode layer expand according to their own thermal expansion coefficients. Because the expansion coefficient of polysilicon is greater than that of silicon nitride, the gate electrode layer also expands to a greater extent, exerting outward tension on the material surrounding the gate electrode layer. The SiN layer is stretched and deformed by the tension of the gate electrode layer. The deformation of the SiN crystal introduces tensile stress into the semiconductor field-effect transistor. The transfer of tensile stress to the channel can significantly increase carrier mobility. However, as semiconductor product sizes decrease, the improvement in channel carrier mobility achieved by stress memory technology based on SiN stress layers is no longer sufficient to meet production requirements. Further improving the degree to which stress memory technology can enhance channel carrier mobility has become a technical challenge.

[0004] In view of this, there is an urgent need to provide a solution for manufacturing electronic devices so as to improve the mobility of carriers in the channel of the electronic devices. Summary of the Invention

[0005] In order to at least solve one or more technical problems described in the above background technology section, the present invention proposes the following technical solutions and multiple embodiments thereof.

[0006] In a first aspect, the present invention discloses a method for fabricating an electronic device, comprising: depositing a stress layer having a negative Poisson's ratio material in a fabrication region of a wafer; annealing the wafer; and removing the stress layer in the fabrication region of the wafer.

[0007] In a second aspect, the present invention further discloses an electronic device, which is manufactured according to the method described in the first aspect.

[0008] According to the method for manufacturing electronic devices disclosed in the present invention, by using a negative Poisson's ratio material as a stress layer in stress memory technology, the deformation of the stress layer crystal due to the thermal expansion of the gate electrode layer can be maintained in a stretched state in both the lateral and longitudinal directions, thereby improving the mobility of carriers in the channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an illustrative and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0010] Figure 1 An exemplary schematic diagram of producing an N-MOSFET based on stress memory technology in some embodiments of the present invention is shown.

[0011] Figure 2 FIG2 is an exemplary schematic diagram showing deformation of a SiN crystal due to tension in some embodiments of the present invention.

[0012] Figure 3 An exemplary schematic diagram of producing CMOS based on stress memory technology in some embodiments of the present invention is shown.

[0013] Figure 4 An exemplary flow chart of a method for manufacturing an electronic device in some embodiments of the present invention is shown.

[0014] Figure 5 An exemplary schematic diagram illustrating a method for manufacturing an electronic device in some embodiments of the present invention is shown.

[0015] Figure 6 Exemplary schematic diagrams showing deformation of positive and negative Poisson's ratio materials in some embodiments of the present invention are shown.

[0016] Figure 7 An exemplary schematic diagram of using SMT based on negative Poisson's ratio materials to produce CMOS in some embodiments of the present invention is shown. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work shall fall within the scope of protection of the present invention.

[0018] It should be understood that the terms "include" and "comprising" used in the description and claims of the present invention indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0019] It should also be understood that the terminology used in this specification is for the purpose of describing specific embodiments only and is not intended to limit the present invention. As used in the specification and claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should further be understood that the term "and / or" as used in the specification and claims refers to any and all possible combinations of one or more of the associated listed items, including and including these combinations.

[0020] As used in this specification and claims, the term “if” can be interpreted as “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [described condition or event] is detected” can be interpreted as meaning “upon determination” or “in response to determining” or “upon detection of [described condition or event]” or “in response to detecting [described condition or event],” depending on the context.

[0021] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Stress memory technology is an important method to improve the carrier mobility in N-channel metal oxide semiconductor field effect transistors. Figure 1 FIG. 4 shows an exemplary schematic diagram of producing an N-MOSFET based on stress memory technology in some embodiments of the present invention, as shown in FIG. Figure 1As shown, the production of N-MOSFETs based on stress memory technology involves multiple process steps. The gate stacking process involves stacking a gate dielectric layer and a gate electrode layer on a silicon substrate. The gate dielectric layer is typically made of silicon dioxide (SiO2) or a high-k material. Its primary function is to form an insulating barrier between the gate electrode and the silicon substrate, while also regulating the carrier concentration and movement within the channel through the electric field effect. The gate electrode layer, commonly made of polysilicon, is responsible for applying voltage to control the conduction and cutoff of the channel. The extension region implantation process primarily involves implanting N-type impurities such as phosphorus (P) and arsenic (As) into the areas near the source and drain electrodes to form extension regions near the source and drain, shortening the channel length. The spacer formation process primarily forms insulating spacer structures on both sides of the gate to enable precise control of the source and drain implantation regions. The source / drain implantation process primarily uses ion implantation to introduce N-type impurities into the source and drain regions. The silicon nitride deposition process primarily grows a thin film of silicon nitride on the surface of a semiconductor wafer. Spike annealing is a rapid thermal process that heats the wafer to a high temperature (e.g., 1035°C) in a very short time, followed by rapid cooling. The silicidation process forms metal silicide on the silicon surface through a chemical reaction between metal and silicon, thereby improving current conduction efficiency.

[0023] During the spike annealing process, the silicon nitride and polysilicon in the gate electrode layer expand according to their own coefficients of thermal expansion. Because the expansion coefficient of polysilicon is greater than that of silicon nitride, the gate electrode layer also expands more, exerting outward tension on the material surrounding the gate electrode layer. The tension from the gate electrode layer causes the SiN layer to stretch and deform. Figure 2 FIG2 shows an exemplary schematic diagram of SiN crystal deformation due to stretching in some embodiments of the present invention. Figure 2 As shown in the figure, due to the Poisson's ratio of SiN being 0.24, its 100 crystal orientation is stretched, while its 010 crystal orientation is compressed. The deformation of the SiN crystal introduces tensile stress to the N-MOSFET. The transfer of tensile stress to the channel significantly accelerates the electron mobility of the N-MOSFET, thereby increasing the drive current of the N-MOSFET.

[0024] A characteristic of SMT is that the tensile stress introduced by the cap-shaped stress layer can improve the performance of N-MOSFETs, but it can adversely affect the performance of P-channel Metal-Oxide-Semiconductor Field-Effect Transistors (P-MOSFETs). Complementary Metal-Oxide-Semiconductor (CMOS) is an integrated circuit electronic device composed of P-MOSFETs and N-MOSFETs connected in a complementary and symmetrical manner. It utilizes the complementary properties of the two field-effect transistors to achieve specific circuit functions and is widely used in digital and analog circuits. To introduce SMT into the CMOS production process and improve the performance of N-MOSFETs while preserving the performance of P-MOSFETs, the general practice is to deposit a silicon nitride film, then remove the silicon nitride film from the PMOS region through photolithography and etching, followed by a rapid annealing process.

[0025] Figure 3 FIG1 shows an exemplary schematic diagram of producing CMOS based on stress memory technology in some embodiments of the present invention. Figure 3 As shown, shallow trench isolation (STI) is a physical isolation structure created on the substrate to separate different MOSFETs from each other. Regarding the well implantation process, it can be understood that: using a silicon wafer as the substrate, N-type impurities can be doped into the substrate to form an N-type well (N Well), based on which a P-MOSFET can be fabricated; P-type impurities can also be doped into the substrate to form a P-type well (P Well), based on which an N-MOSFET can be fabricated. After depositing the SiN film layer, to remove the SiN material on the surface of the P-MOSFET, the N-MOSFET surface is covered with photoresist, and the SiN material on the top surface of the P-MOSFET is then etched. After the SiN material on the top surface of the P-MOSFET is removed, the entire device can be spike annealed to deform the SiN crystal covering the top surface of the N-MOSFET, thereby introducing tensile stress into the channel of the N-MOSFET to improve electron mobility. It is understandable that the process steps for producing N-MOSFET based on SMT, including gate stacking, extension region implantation, sidewall formation, source / drain implantation, SiN deposition, SiN removal, and silicidation, described above are also applicable to the method for producing CMOS based on SMT, and will not be repeated here.

[0026] Currently, stress memory technology based on SiN stress layers has become a standard technology for improving carrier mobility in processes of 90nm and below. However, as semiconductor product sizes decrease, the effect of stress memory technology based on SiN capping layers on improving carrier mobility in the channel has been unable to meet production needs. How to further improve the degree of improvement in carrier mobility in the channel by stress memory technology has become a technical problem. In view of this, the present invention proposes a method for manufacturing electronic devices to enhance the effect of stress memory technology on improving carrier mobility in the channel.

[0027] Figure 4 FIG. 1 shows an exemplary flow chart of a method for manufacturing an electronic device in some embodiments of the present invention. Figure 4 As shown, the method includes: step 401, depositing a stress layer having a negative Poisson's ratio material in a manufacturing area of ​​a wafer; step 402, annealing the wafer; and step 403, removing the stress layer in the manufacturing area of ​​the wafer.

[0028] It is understood that the method proposed in the present invention can be used to manufacture electronic devices, including but not limited to semiconductor field effect transistors, such as N-MOSFET, CMOS, and complex circuits obtained by combining N-MOSFET and / or CMOS, and the present invention does not impose any restrictions on this. Figure 5 An exemplary schematic diagram of a method for manufacturing an electronic device in some embodiments of the present invention is shown below. Figure 5 Let's explain steps 401-403.

[0029] As for step 401, it can be understood that semiconductor field effect transistors can be manufactured using a silicon wafer as a substrate, wherein the wafer includes an edge area and a manufacturing area, and the manufacturing area is an area used to produce and manufacture semiconductor field effect transistors or complex circuits. A prototype device of N-MOSFET or CMOS can be prepared in the manufacturing area through a process including gate stacking, extension area injection, sidewall formation, source / drain injection and other process steps. In some embodiments, after completing the source / drain injection process and forming the source and drain of the N-MOSFET or CMOS on the wafer, a stress layer having a negative Poisson's ratio material is deposited in the manufacturing area of ​​the wafer. Negative Poisson's ratio material is a material whose Poisson's ratio is a negative number, wherein the Poisson's ratio (υ) refers to the lateral positive strain ε of the material when it is subjected to unidirectional tension or compression. x and longitudinal normal strain ε y The ratio of υ=-ε x / ε y .

[0030] Regarding step 402, it is understandable that the wafer may be subjected to spike annealing. During the annealing process, the gate electrode layer of the semiconductor field effect transistor in the embryonic state will undergo thermal expansion, thereby causing the negative Poisson's ratio material in the stress layer to deform. The deformation of the stress layer will transfer stress to the channel within the semiconductor field effect transistor, thereby improving the mobility of carriers in the channel. Figure 6 Schematic diagrams showing the deformation of positive and negative Poisson's ratio materials in some embodiments of the present invention are shown. Figure 6 As shown in , for positive Poisson's ratio materials, the material will produce elongation deformation along the load direction and shortening deformation in the direction perpendicular to the load; for negative Poisson's ratio materials, the material will produce elongation deformation along the load direction and elongation deformation in the direction perpendicular to the load. Figure 6 As can be seen, because SiN is a material with a positive Poisson's ratio, in stress memory technology based on a SiN cap layer, when the SiN crystal is deformed by the thermal expansion of the gate electrode layer and stretched in the 100 crystal direction, it will generate tensile stress in the same direction on the channel. In other words, the channel maintains a tensile stress state in the 100 crystal direction, which helps to improve the carrier mobility in the 100 crystal direction. In the method disclosed in the present invention, the stress layer is made of a material with a negative Poisson's ratio. The deformation of the stress layer crystals caused by the thermal expansion of the gate electrode layer can maintain a tensile state in both the 100 and 010 crystal directions, thereby generating greater strain in the 110 crystal direction, further improving the carrier mobility in the channel.

[0031] Regarding step 403 , it is understood that the stress transferred from the stress layer to the channel will be memorized in the channel region. Even after the stress layer is removed, the channel will still maintain a certain tensile stress state, thereby improving carrier mobility.

[0032] It can be understood that according to the method for manufacturing electronic devices disclosed in the present invention, by using negative Poisson's ratio material as a stress layer in stress memory technology, the deformation of the stress layer crystal due to the thermal expansion of the gate electrode layer can be maintained in a stretched state in the horizontal and vertical directions at the same time, thereby improving the mobility of carriers in the channel.

[0033] In some embodiments, the negative Poisson's ratio material includes: SiS2.

[0034] It is understood that SiS2 has a Poisson's ratio of -0.13, which can be used in the stress memory technology based on negative Poisson's ratio materials disclosed in the present invention. Since pyrite crystals, α-cristobalite, and semi-fluorographene have negative Poisson's ratio properties, in some embodiments, pyrite, α-cristobalite, or semi-fluorographene can be selected as negative Poisson's ratio materials.

[0035] In some embodiments, the method for manufacturing an electronic device disclosed in the present invention further comprises: controlling silicon and sulfur to react under first reaction conditions in a sealed silica tube to prepare SiS2.

[0036] In some embodiments, the first reaction conditions include: a reaction temperature in the range of [773K, 1073K] and / or a reaction ratio of silicon to sulfur of 1:2.2.

[0037] As is well understood, silicon dioxide (SiO2) has excellent high-temperature resistance and chemical stability, and the sealed silica tube provides a relatively stable environment for the reaction between silicon and sulfur. High-purity silicon and sulfur react in a ratio of 1:2.2 at temperatures of 773-1073K in a sealed silica tube to produce NP phase SiS2.

[0038] In some embodiments, the method for manufacturing an electronic device disclosed in the present invention further comprises: controlling silicon and sulfur to react under second reaction conditions in a boron nitride dry pot to prepare SiS2.

[0039] In some embodiments, the second reaction condition includes: a reaction pressure of 2.8 GPa and / or a reaction temperature of 1473K.

[0040] In some embodiments, HP1 SiS2 can be obtained by controlling the reaction of silicon and sulfur in a boron nitride (BN) crucible in a cylindrical graphite heater at 2.8 GPa and 1473 K for 15 minutes, followed by quenching to room temperature and then decompression.

[0041] In some embodiments, when preparing a CMOS, after depositing a stress layer having a negative Poisson's ratio material in a manufacturing area of ​​a wafer, the method includes: forming a photoresist protection layer on the surface of an N-MOSFET; and etching the negative Poisson's ratio material on the upper surface of a P-MOSFET gate.

[0042] It is understandable that stress memory technology will degrade the performance of P-MOSFET. Since CMOS is a device composed of P-MOSFET and N-MOSFET, when preparing CMOS based on stress memory technology, it is necessary to protect P-MOSFET to prevent its performance from being damaged.

[0043] In some embodiments, forming a protective photoresist layer on the surface of the N-MOSFET includes: uniformly coating a positive photoresist on the surface of a wafer; exposing the wafer to light in areas other than the N-MOSFET; and developing the wafer with a developer. In these embodiments, after the development process, the photoresist covering the N-MOSFET remains unexposed, thereby forming a protective photoresist layer on the surface of the N-MOSFET. The areas other than the N-MOSFET are no longer covered by the photoresist due to exposure.

[0044] In some embodiments, etching the negative Poisson's ratio material on the upper surface of the P-MOSFET gate includes: etching the negative Poisson's ratio material on the upper surface of the P-MOSFET gate using a plasma etching technique.

[0045] In some embodiments, after etching the negative Poisson's ratio material on the upper surface of the P-MOSFET gate, the method further includes removing etching impurities on the surface of the P-MOSFET.

[0046] It is understandable that after etching the negative Poisson's ratio material on the upper surface of the P-MOSFET gate, impurities such as etching products will remain on the surface of the wafer manufacturing area and the surface of the wafer edge area. Chemical cleaning methods can be used to remove these impurities.

[0047] In some embodiments, after etching the negative Poisson's ratio material on the upper surface of the P-MOSFET gate, the method further includes: removing the photoresist protection layer on the surface of the N-MOSFET.

[0048] It is understandable that the photoresist protective layer on the surface of the N-MOSFET can be removed by using an alkaline solution or an organic solvent, or by using a reactive ion etching method.

[0049] Figure 7 FIG. 1 shows an exemplary schematic diagram of using SMT based on negative Poisson's ratio materials to produce CMOS in some embodiments of the present invention. Figure 7 As shown in sub-figure (a) of FIG, a buffer oxide layer is deposited on the surface of the P-MOSFET and the N-MOSFET, wherein the material of the buffer oxide layer can be SiO2. It can be understood that by depositing a buffer oxide layer between the stress layer and the wafer manufacturing area, it can play a role in buffering stress, reducing the adverse effects of the stress layer on the wafer substrate and the device structure in the manufacturing area, and protecting the integrity and performance stability of the device. Figure 7 As shown in sub-figure (b) in FIG, a stress layer having a negative Poisson's ratio material is deposited in the manufacturing area of ​​the wafer, wherein the negative Poisson's ratio material selected can be SiS2. Figure 7As shown in the sub-figure (c) in FIG, the negative Poisson's ratio material on the upper surface of the gate electrode layer of the P-MOSFET is removed by photolithography and etching processes, wherein the photolithography process is used to form a photoresist protection layer on the surface of the N-MOSFET, and then the negative Poisson's ratio material on the upper surface of the gate electrode layer of the P-MOSFET is etched. Figure 7 As shown in the sub-figure (d) in FIG, after the etching is completed, the etching impurities generated in the etching process are removed and the photoresist protection layer on the surface of the N-MOSFET is removed. Figure 7 As shown in sub-figure (e) in Figure 3, the wafer is annealed to introduce tensile stress to the N-MOSFET.

[0050] Furthermore, the present invention discloses an electronic device, which is manufactured according to the method described in the above embodiments of the present invention.

[0051] In summary, the specific functions implemented by the electronic device provided in the embodiments of this specification can be explained in comparison with the aforementioned embodiments in this specification, and can achieve the technical effects of the aforementioned embodiments, so they will not be repeated here.

[0052] It should be noted that, for the purpose of simplicity, the present invention describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will understand that the scheme of the present invention is not limited by the order of the described actions. Therefore, based on the disclosure or teachings of the present invention, those skilled in the art will understand that some of the steps therein can be performed in other orders or simultaneously. Further, those skilled in the art will understand that the embodiments described in the present invention can be regarded as optional embodiments, that is, the actions or modules involved therein are not necessarily necessary for the implementation of one or more schemes of the present invention. In addition, depending on the different schemes, the present invention also has different emphases on the description of some embodiments. In view of this, those skilled in the art will understand that the parts that are not described in detail in a certain embodiment of the present invention may also refer to the relevant descriptions of other embodiments.

Claims

1. A method for manufacturing an electronic device, characterized in that include: depositing a stress layer having a negative Poisson's ratio material in a fabrication area of ​​the wafer; annealing the wafer; as well as removing the stress layer in the manufacturing area of ​​the wafer; The negative Poisson's ratio material includes: SiS2; In a sealed silica tube, silicon and sulfur are controlled to react under first reaction conditions to prepare the SiS2; during the annealing process, the gate electrode layer of the semiconductor field effect transistor undergoes thermal expansion, causing the negative Poisson's ratio material in the stress layer to deform.

2. The method according to claim 1, characterized in that The first reaction conditions include: a reaction temperature in the range of [773K, 1073K] and / or a reaction ratio of silicon to sulfur of 1:2.

2.

3. The method according to claim 1, characterized in that Further including: In a boron nitride dry pot, silicon and sulfur are controlled to react under a second reaction condition to prepare the SiS2.

4. The method according to claim 3, characterized in that The second reaction conditions include: a reaction pressure of 2.8 GPa and / or a reaction temperature of 1473 K.

5. The method according to claim 1, wherein In the case of preparing CMOS, after depositing a stress layer having a negative Poisson's ratio material in a manufacturing area of ​​a wafer, the following steps are included: forming a photoresist protection layer on the surface of the N-MOSFET; Etch the negative Poisson's ratio material on the upper surface of the P-MOSFET gate.

6. The method according to claim 5, characterized in that After etching the negative Poisson's ratio material on the upper surface of the P-MOSFET gate, including: Etching impurities on the surface of the P-MOSFET are removed.

7. The method according to claim 5, characterized in that After etching the negative Poisson's ratio material on the upper surface of the P-MOSFET gate, including: The photoresist protection layer on the surface of the N-MOSFET is removed.

8. An electronic device, characterized in that: The electronic device is manufactured according to the method according to any one of claims 1 to 7.

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