Integrated circuit device

Abstract

An integrated circuit device may include a first transistor, comprising a first nanosheet having a first width in a first horizontal direction, a first gate structure surrounding the first nanosheet and extending on a first side of the first nanosheet in a second horizontal direction perpendicular to the first horizontal direction, and a first source / drain region on an opposite side of the first nanosheet in the first horizontal direction; and a second transistor over the first transistor, and a second nanosheet over the first nanosheet and having a second width in the first horizontal direction equal to the first width, a second gate structure surrounding the second nanosheet and on a second side of the second nanosheet in the second horizontal direction, and second source / drain regions on both sides of the second nanosheet in the first horizontal direction.

Description

Technical Field

[0001] The inventive concept relates to an integrated circuit device, and more particularly, to an integrated circuit device including a field effect transistor. Background Art

[0002] Recently, with the rapid development of the scaling down of integrated circuit devices, it may be necessary to ensure not only a fast operation speed in the integrated circuit device but also an operation accuracy in the integrated circuit device. As the integration degree of integrated circuit devices increases and their sizes decrease, field effect transistors with nanosheets are used. Accordingly, it may be necessary to develop an integrated circuit device having a new structure that can improve the performance and reliability of the nanosheet field effect transistor. Summary of the Invention

[0003] The inventive concept provides an integrated circuit device capable of providing high integration and improved reliability in a nanosheet field effect transistor.

[0004] Aspects of the inventive concept are not limited to those described above, and other aspects not described herein will be clearly understood by those skilled in the art from the following description.

[0005] According to an embodiment of the inventive concept, an integrated circuit device may include: a first transistor including a plurality of first nanosheets having a first width in a first horizontal direction, a first gate structure surrounding the plurality of first nanosheets and extending on a first side of the plurality of first nanosheets in a second horizontal direction, and a first source / drain region on an opposite side of the plurality of first nanosheets in the first horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction, a first side of the plurality of first nanosheets in the second horizontal direction being opposite to a second side of the plurality of first nanosheets in the second horizontal direction; and a second transistor above the first transistor, the second transistor including a plurality of second nanosheets above the plurality of first nanosheets and having a second width in the first horizontal direction, a second gate structure surrounding the plurality of second nanosheets and extending on a second side of the plurality of second nanosheets in the second horizontal direction, and a second source / drain region on an opposite side of the plurality of second nanosheets in the first horizontal direction, the second width being equal to the first width, a second side of the plurality of second nanosheets in the second horizontal direction being opposite to a first side of the plurality of second nanosheets in the second horizontal direction, and the second side of the plurality of second nanosheets in the second horizontal direction being above the second side of the plurality of first nanosheets in the second horizontal direction.

[0006] According to an embodiment of the inventive concept, an integrated circuit device may include: a lower transistor; and an upper transistor at a vertical level higher than the lower transistor. The lower transistor may include a lower source / drain region and a lower gate structure between the lower source / drain regions. The upper transistor may include an upper source / drain region and an upper gate structure between the upper source / drain regions. The lower gate structure and the upper gate structure may divide a plurality of nanosheets into an upper part and a lower part and share the plurality of nanosheets. The plurality of nanosheets may be stacked in a vertical direction and have aligned centers.

[0007] According to an embodiment of the inventive concept, an integrated circuit device may include: two first transistors spaced apart from each other in a first horizontal direction; two second transistors spaced apart from each other in the first horizontal direction, the second transistors being above the two first transistors; and two third transistors spaced apart from each other in the first horizontal direction, with the two first transistors and the two second transistors therebetween. Each of the two first transistors may include a plurality of first nanosheets having a first width in the first horizontal direction, a first gate structure surrounding the plurality of first nanosheets and extending on a first side of the plurality of first nanosheets in a second horizontal direction, and a first source / drain region on an opposite side of the plurality of first nanosheets in the first horizontal direction. The second horizontal direction may be perpendicular to the first horizontal direction. A first side of the plurality of first nanosheets in the second horizontal direction may be opposite to a second side of the plurality of first nanosheets in the second horizontal direction. Each of the two second transistors may include a plurality of second nanosheets, a second gate structure, and a second source / drain region, the plurality of second nanosheets being above a lower one of the plurality of first nanosheets and having a second width in the first horizontal direction, the second gate structure surrounding the plurality of second nanosheets and extending on a second side of the plurality of second nanosheets in the second horizontal direction, and the second source / drain region on an opposite side of the plurality of second nanosheets in the first horizontal direction. The second width may be equal to the first width. A second side of the plurality of second nanosheets in the second horizontal direction may be opposite to a first side of the plurality of second nanosheets in the second horizontal direction. A second side of the plurality of second nanosheets in the second horizontal direction may be above a second side of a lower one of the plurality of first nanosheets in the second horizontal direction. Each of the two third transistors may include a plurality of third nanosheets having a third width equal to the first width in the first horizontal direction, a third gate structure surrounding the plurality of third nanosheets and extending on one side of the plurality of third nanosheets in the second horizontal direction, and third source / drain regions on both sides of the plurality of third nanosheets. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1is a plan view schematically showing an integrated circuit device according to an embodiment;

[0010] Figure 2 is a cross-sectional view of the integrated circuit device taken along line A-A; Figure 1 of the integrated circuit device;

[0011] Figure 3 is a cross-sectional view of the integrated circuit device taken along line B-B; Figure 1 of the integrated circuit device;

[0012] Figure 4 is a cross-sectional view of the integrated circuit device taken along line C-C; Figure 1 of the integrated circuit device;

[0013] Figure 5 is a circuit diagram showing an integrated circuit device according to an embodiment;

[0014] Figure 6 is showing Figure 5 the front layout of the integrated circuit device;

[0015] Figure 7 is showing Figure 5 the backside layout of the integrated circuit device;

[0016] Figure 8 is a cross-sectional view of the integrated circuit device taken along lines X1-X2 and X3-X4; Figure 6 and 7 of the integrated circuit device;

[0017] Figure 9 is a cross-sectional view of the integrated circuit device taken along lines Y1-Y2 and Y3-Y4; Figure 6 and 7 of the integrated circuit device; and

[0018] Figures 10 to 30 is a cross-sectional view showing a method of manufacturing an integrated circuit device in a process sequence according to an embodiment. DETAILED DESCRIPTION

[0019] When the terms "about" or "substantially" are used in this specification in connection with a numerical value, it is intended that the associated numerical value include manufacturing or operating tolerances around the stated value (e.g., ±10%). Further, when the words "substantially" and "about" are used in connection with a geometry, it is intended that the precision of the geometry is not required, but rather the tolerance of the shape is within the scope of the present disclosure. Additionally, whether a numerical value or a shape is modified by "about" or "substantially", it should be understood that these values and shapes should be interpreted to include manufacturing or operating tolerances around the stated numerical value or shape (e.g., ±10%). When a range is specified, the range includes all values therebetween, such as increments of 0.1%.

[0020] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 is a plan view schematically showing an integrated circuit device according to an embodiment. Figure 2 is taken along line A-A Figure 1 of the integrated circuit device. Figure 3 is taken along line B-B Figure 1 of the integrated circuit device. Figure 4 is taken along line C-C Figure 1 of the integrated circuit device.

[0022] For ease of description and understanding, a plan view is shown as a representative. However, depending on the position in the integrated circuit device 10, as Figure 3 shown in the cross-sectional view taken along line B-B may show a split gate region SG or a common gate region CG.

[0023] In addition, although it would be correct to not show the first gate contact 171 and the second gate contact 173 in Figure 2 because the first gate contact 171 and the second gate contact 173 are not in the cross-section but in the diagonal direction, for ease of description and understanding, the first gate contact 171 and the second gate contact 173 are shown together.

[0024] Referring together to Figures 1 to 4 , the integrated circuit device 10 according to an embodiment may include a plurality of first to third transistors TR1, TR2, and TR3, and each of the plurality of first to third transistors TR1, TR2, and TR3 may constitute a logic unit including a multi-bridge-channel field-effect transistor (MBCFET).

[0025] The integrated circuit device 10 according to an embodiment may have a constant unit area in a first horizontal direction (X direction) and a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction). The integrated circuit device 10 may include a plurality of nanosheets NS, a gate structure GS, source / drain regions SD, and a gate dielectric film 141.

[0026] The plurality of nanosheets NS may include semiconductor patterns having a relatively large width in the first horizontal direction (X direction) and the second horizontal direction (Y direction) and a relatively small thickness in the vertical direction (Z direction). For example, the plurality of nanosheets NS may have a width in the range of about 5 nm to about 100 nm and a thickness in the range of about 1 nm to about 10 nm, but the embodiment is not limited thereto. Each of the plurality of nanosheets NS may be an active nanosheet and may be used as a channel region.

[0027] The gate structure GS can be formed to surround a plurality of nanosheets NS. In some embodiments, the gate structure GS can include doped polysilicon, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or a combination thereof. For example, the gate structure GS can include Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, or a combination thereof, but the embodiments are not limited thereto.

[0028] The source / drain regions SD can be connected to both ends of the plurality of nanosheets NS with respect to the gate structure GS. The source / drain regions SD can include an epitaxial layer doped with impurities such as boron (B), arsenic (As), or phosphorus (P). The source / drain regions SD can include a silicon (Si) epitaxial layer or a silicon germanium (SiGe) epitaxial layer.

[0029] The gate dielectric film 141 can be located between the gate structure GS and the plurality of nanosheets NS. In some embodiments, the gate dielectric film 141 can include silicon oxide, silicon oxynitride, a high-k dielectric material having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k dielectric material can include metal oxide or metal oxynitride. For example, the high-k dielectric materials that can be used as the gate dielectric film 141 can include HfO, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO, AlO, or a combination thereof, but the embodiments are not limited thereto.

[0030] An integrated circuit device 10 according to an embodiment can include a first transistor TR1 and a second transistor TR2 stacked in a split gate region SG in a vertical direction (Z direction), and a third transistor TR3 spaced apart from the first transistor TR1 and the second transistor TR2 in a first horizontal direction (X direction) and located in a common gate region CG.

[0031] First, the first transistor TR1 and the second transistor TR2 stacked and positioned in the split gate region SG of the integrated circuit device 10 are described.

[0032] In some embodiments, the first transistor TR1 and the second transistor TR2 can be different types of transistors. For example, the first transistor TR1 can include an n-channel metal oxide semiconductor (NMOS) transistor, and the second transistor TR2 can include a p-channel metal oxide semiconductor (PMOS) transistor. However, the embodiments are not limited thereto, the first transistor TR1 can include a PMOS transistor, and the second transistor TR2 can include an NMOS transistor.

[0033] In some embodiments, the plurality of nanosheets NS may include a plurality of first nanosheets NS1 and a plurality of second nanosheets NS2 spaced apart from each other in the vertical direction (Z direction). The dummy nanosheet 131 may be located between the plurality of first nanosheets NS1 and the plurality of second nanosheets NS2. Additionally, the dummy nanosheet 131 may also be located below the plurality of first nanosheets NS1. Here, the dummy nanosheet 131 may refer to a structure having a nanosheet shape but not operating. That is, the dummy nanosheet 131 may be understood as being opposite to the active nanosheet.

[0034] In some embodiments, the source / drain regions SD may include a first source / drain region SD1 and a second source / drain region SD2 spaced apart from each other in the vertical direction (Z direction). Additionally, the sidewall isolation layer 117 and the first isolation layer 121 may be located between the first source / drain region SD1 and the second source / drain region SD2. The sidewall isolation layer 117 and the first isolation layer 121 may include different insulating materials. Here, the first source / drain region SD1 may include a first source / drain contact 171SD in contact with its lower portion. Additionally, the second source / drain region SD2 may include a second source / drain contact 173SD in contact with its upper portion.

[0035] In some embodiments, the gate structure GS may include a first gate structure GS1 and a second gate structure GS2 spaced apart from each other in the vertical direction (Z direction).

[0036] In the first transistor TR1, the first gate structure GS1 may include a plurality of first sub-gates S1 surrounding the plurality of first nanosheets NS1 and a first main gate 155 in contact with the plurality of first sub-gates S1 and extending on one side (e.g., the +Y side) in the second horizontal direction (Y direction). Additionally, the first gate structure GS1 may include a first gate contact 171 in contact with the lower portion of the first main gate 155. Here, the plurality of first sub-gates S1 may include dual-conductive material films 151 and 153 containing different materials.

[0037] In Figure 3 In the cross-sectional view, at the side of the first gate structure GS1, the first insulating layer 161 may be positioned and have a thickness greater than the thickness of the first gate structure GS1 in the vertical direction (Z direction). Additionally, at the upper portion of the first gate structure GS1, the second insulating layer 163 may be positioned and have a thickness greater than the thickness of the second gate structure GS2 in the vertical direction (Z direction). In some embodiments, the dummy nanosheet 131 may be located below the lowermost first sub-gate S1 among the plurality of first sub-gates S1.

[0038] The spacer 115 may be located on two sidewalls of the first gate structure GS1. The spacer 115 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, or a combination thereof.

[0039] The first source / drain region SD1 may be located at both ends of the plurality of first nanosheets NS1, and the lower surface of the first source / drain contact 171SD in contact with the lower portion of the first source / drain region SD1 may be at the same vertical level as the lower surface of the first gate contact 171.

[0040] In the second transistor TR2, the second gate structure GS2 may include a plurality of second sub-gates S2 surrounding the plurality of second nanosheets NS2 and a second main gate 157 in contact with the plurality of second sub-gates S2 and extending on the other side (e.g., the -Y side) in the second horizontal direction (Y direction). Additionally, the second gate structure GS2 may include a second gate contact 173 in contact with the upper portion of the second main gate 157. Here, each of the plurality of second sub-gates S2 may include a single conductive material film 151 containing the same material.

[0041] In Figure 3 In a cross-sectional view, on the side of the second gate structure GS2, the second insulating layer 163 may be positioned and have a thickness greater than the thickness of the second gate structure GS2 in the vertical direction (Z direction). Additionally, below the second gate structure GS2, the first insulating layer 161 may be positioned and have a thickness greater than the thickness of the first gate structure GS1 in the vertical direction (Z direction). In some embodiments, an insulating pattern layer 143 including the same material as the gate dielectric film 141 may be positioned to extend from the upper surface of the uppermost second sub-gate S2 among the plurality of second sub-gates S2 into the second insulating layer 163. According to an embodiment, this may be a feature generated by the manufacturing method described below for the integrated circuit device 10.

[0042] The second source / drain region SD2 may be located at both ends of the plurality of second nanosheets NS2, and the upper surface of the second source / drain contact 173SD in contact with the upper portion of the second source / drain region SD2 may be at the same level as the upper surface of the second gate contact 173.

[0043] In Figure 3In the cross-sectional view, the first main gate 155 of the first gate structure GS1 constituting the first transistor TR1 can be in the diagonal direction of the second main gate 157 of the second gate structure GS2 constituting the second transistor TR2. Additionally, the first gate contact 171 can be in the diagonal direction of the second gate contact 173. That is, the first gate structure GS1 and the second gate structure GS2 can be located above and below the dummy nanosheet 131 with respect to the virtual nanosheet between the plurality of first nanosheets NS1 and the plurality of second nanosheets NS2, respectively.

[0044] Next, the third transistor TR3 located in the common gate region CG of the integrated circuit device 10 is described.

[0045] In some embodiments, the plurality of nanosheets NS can include a plurality of first nanosheets NS1 and a plurality of second nanosheets NS2 spaced apart from each other in the vertical direction (Z direction). The dummy nanosheet 131 can be located between the plurality of first nanosheets NS1 and the plurality of second nanosheets NS2. Additionally, the dummy nanosheet 131 can also be located below the plurality of first nanosheets NS1.

[0046] Here, the third transistor TR3 can use both the plurality of first nanosheets NS1 and the plurality of second nanosheets NS2 as the channel region. That is, when the channel region is referred to as the plurality of third nanosheets in the third transistor TR3, the vertical level of the uppermost surface of the plurality of third nanosheets can be the same as the vertical level of the uppermost surface of the plurality of second nanosheets NS2, and the vertical level of the lowermost surface of the plurality of third nanosheets can be the same as the vertical level of the lowermost surface of the plurality of first nanosheets NS1.

[0047] In some embodiments, the gate structure GS can include a third gate structure GS3 extending in the vertical direction (Z direction).

[0048] In the third transistor TR3, the third gate structure GS3 can include a plurality of third sub-gates S3 surrounding the plurality of nanosheets NS and a third main gate 159 that contacts the plurality of third sub-gates S3 and extends on one side (e.g., the +Y side) in the second horizontal direction (Y direction). Additionally, the third gate structure GS3 can include a third gate contact 175 that contacts the lower and upper portions of the third main gate 159. The third gate contact 175 can be located on a straight line in the vertical direction (Z direction). Here, some of the plurality of third sub-gates S3 can include dual-conductive material films 151 and 153 containing different materials.

[0049] In Figure 3In a cross-sectional view, at the side of the third gate structure GS3, the third insulating layer 165 may be positioned and have a thickness greater than the thickness of the third gate structure GS3 in the vertical direction (Z direction). In some embodiments, the dummy nanosheet 131 may be located below the lowermost third sub-gate S3 among the plurality of third sub-gates S3. In some embodiments, the insulating pattern layer 143 including the same material as the gate dielectric film 141 may be positioned to extend from the upper surface of the uppermost third sub-gate S3 among the plurality of third sub-gates S3 into the interior of the third insulating layer 165. According to an embodiment, this may be a feature resulting from the manufacturing method described below for the integrated circuit device 10.

[0050] In some embodiments, the vertical level of the uppermost surface of the third gate structure GS3 may be the same as the vertical level of the uppermost surface of the second gate structure GS2, and the vertical level of the lowermost surface of the third gate structure GS3 may be the same as the vertical level of the lowermost surface of the first gate structure GS1.

[0051] In the integrated circuit device 10 according to an embodiment, a three-dimensional vertical stacked structure in which the first transistor TR1 and the second transistor TR2 are stacked in the vertical direction (Z direction) may be used, and a single third transistor TR3 may be used in the vertical direction (Z direction). Accordingly, the integrated circuit device 10 may provide high integration due to a reduction in the unit area, may reduce the capacitance between the gate structure and the gate contact, and may thus have improved electrical performance.

[0052] Figure 5 is a circuit diagram showing an integrated circuit device according to an embodiment. Figure 6 is showing Figure 5 a front layout view of the integrated circuit device. Figure 7 is showing Figure 5 a backside layout view of the integrated circuit device. Figure 8 is a cross-sectional view of the integrated circuit device taken along lines X1-X2 and X3-X4 Figure 6 and 7 of the integrated circuit device. Figure 9 is a cross-sectional view of the integrated circuit device taken along lines Y1-Y2 and Y3-Y4 Figure 6 and 7 of the integrated circuit device.

[0053] Referring together to Figures 5 to 9 , the integrated circuit device 100 may have a flip-flop structure including six transistors for operation.

[0054] Most of the components of the integrated circuit device 100 described below and the materials forming the components are the same as those referred to above Figures 1 to 4The components and materials described are substantially the same or similar. Thus, for ease of description, the description focuses on the differences from the above-described integrated circuit device 10. The concept of "substantially the same" for an element can indicate that the element can be exactly the same, and can also indicate that the element can be determined to be the same considering the errors or deviations that occur during the process.

[0055] The integrated circuit device 100 may include two first transistors TR1, two second transistors TR2 stacked above the two first transistors TR1, and two third transistors TR3 having the two first transistors TR1 and the two second transistors TR2 therebetween (see Figure 3 ). Here, the two first transistors TR1 may include NMOS transistors, and the two second transistors TR2 may include PMOS transistors, but the embodiments are not limited thereto.

[0056] In some embodiments, in the integrated circuit device 100, one of the two first transistors TR1 may correspond to the first internal clock CLK1, and one of the two second transistors TR2 may correspond to the second internal clock CLK2. Additionally, the other of the two first transistors TR1 may correspond to the first internal inverted clock CLKB1, and the other of the two second transistors TR2 may correspond to the second internal inverted clock CLKB2. Additionally, any one of the two third transistors TR3 (see Figure 3 ) may correspond to the first signal D, and the other of the two third transistors TR3 ( Figure 3 ) may correspond to the second signal Q.

[0057] The integrated circuit device 100 according to the inventive concept may provide a flip-flop structure by using a three-dimensional vertical stacking structure in which NMOS transistors and PMOS transistors are stacked in the vertical direction (Z direction), and thus may have highly integrated and improved electrical performance.

[0058] Figures 10 to 30 is a cross-sectional view showing a method of manufacturing an integrated circuit device in a process sequence according to an embodiment.

[0059] For ease of description and understanding, Figures 10 to 15 is a cross-sectional view corresponding to a cross-section taken along line A-A of Figure 1 , and Figures 16 to 30 is a cross-sectional view corresponding to cross-sections taken along line A-A and line B-B of Figure 1 .

[0060] Referring to Figure 10 , the sacrificial layer 103 and the nanosheets NS may be alternately formed on the substrate 101.

[0061] In some embodiments, the sacrificial layer 103 and the nanosheets NS may be formed by an epitaxial process. Additionally, the sacrificial layer 103 and the nanosheets NS may include materials having an etching selectivity with respect to each other. For example, each of the sacrificial layer 103 and the nanosheets NS may include a single-crystalline layer of a Group-IV semiconductor, a Group-IV-IV compound semiconductor, or a Group-III-V compound semiconductor, and the sacrificial layer 103 and the nanosheets NS may include different materials. For example, the sacrificial layer 103 may include silicon germanium (SiGe), and the nanosheets NS may include single-crystalline silicon.

[0062] In some embodiments, the epitaxial process may include a chemical vapor deposition (CVD) process such as vapor phase epitaxy (VPE) and ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy, or a combination thereof. In the epitaxial process, a liquid or gas precursor may be used as a precursor for forming the sacrificial layer 103 and the nanosheets NS.

[0063] Here, dummy sacrificial layers 105 other than the nanosheets NS may be partially formed between the sacrificial layers 103. In some embodiments, the sacrificial layer 103 may include silicon germanium (SiGe) having a relatively low concentration of germanium (Ge), and each dummy sacrificial layer 105 may include silicon germanium (SiGe) having a relatively high concentration of germanium (Ge).

[0064] Reference Figure 11 , sacrificial mask patterns 111 and 113 may be formed on the uppermost sacrificial layer 103, and then the sacrificial layer 103 and the dummy sacrificial layer 105 may be patterned using the sacrificial mask patterns 111 and 113 as etching masks.

[0065] In some embodiments, the sacrificial mask patterns 111 and 113 may include a first sacrificial mask pattern 111 containing polysilicon and a second sacrificial mask pattern 113 containing silicon nitride.

[0066] Next, spacers 115 may be formed to conformally cover the sidewalls and upper surface of the sacrificial layer 103, the sidewalls of the dummy sacrificial layer 105, and the sidewalls and upper surface of the sacrificial mask patterns 111 and 113. For example, the spacers 115 may include at least one material selected from thermal oxide, silicon oxide, and silicon nitride.

[0067] Reference Figure 12 , the sacrificial layer 103, the dummy sacrificial layer 105, and the nanosheets NS may be patterned using the sidewalls of the sacrificial mask patterns 111 and 113 and the spacers 115 as etching masks.

[0068] Next, a sidewall isolation layer 117 can be formed to cover the sidewalls and the upper surface of the sacrificial layer 103, the sidewalls of the dummy sacrificial layer 105, and the sidewalls of the spacers 115. The sidewall isolation layer 117 can include an insulating material different from the material of the spacers 115.

[0069] Reference Figure 13 , the sidewalls of the sacrificial mask patterns 111 and 113, the sidewalls of the spacers 115, and the sidewalls of the sidewall isolation layer 117 can be used as an etch mask to pattern the sacrificial layer 103 and the nanosheets NS, so that the upper surface of the substrate 101 can be exposed.

[0070] Next, a second source / drain region SD2 can be formed on the exposed upper surface of the substrate 101 using an epitaxial process and using the two exposed sidewalls of the sacrificial layer 103 and the nanosheets NS as seed layers.

[0071] Referring Figure 14 , an etching process that leaves only the sidewall isolation layer 117 on the exposed sidewalls of the dummy sacrificial layer 105 can be performed, and a first isolation layer 121 can be formed on the upper portion of the second source / drain region SD2.

[0072] Although not shown, first, the vertical height of the uppermost surface of the first isolation layer 121 can be formed to be the same as the vertical height of the uppermost surface of the spacers 115. For example, the first isolation layer 121 can include any material selected from silicon oxide and silicon oxynitride.

[0073] Next, a portion of the first isolation layer 121 can be etched, and a recessed region (not shown) can be formed. Thus, both the sidewalls of the sacrificial layer 103 and the nanosheets NS can be exposed.

[0074] Next, a first source / drain region SD1 can be formed while filling the recessed region using an epitaxial process and using both the exposed sidewalls of the sacrificial layer 103 and the nanosheets NS as seed layers.

[0075] Reference Figure 15 , a second isolation layer 123 can be formed on the upper portion of the first source / drain region SD1.

[0076] The second isolation layer 123 can include substantially the same material as the first isolation layer 121. For example, the second isolation layer 123 can include any material selected from silicon oxide and silicon oxynitride.

[0077] Next, the uppermost surface of the spacers 115 can be etched, and the sacrificial mask patterns 111 and 113 (see Figure 14 ) exposed due to the etching can be removed. Thus, the uppermost surface of the nanosheets NS can be exposed.

[0078] Reference Figure 16 , the dummy sacrificial layer 105 can be completely removed between the sacrificial layers 103 (see Figure 15 ).

[0079] By using the etching selectivity between the sacrificial layer 103 and the dummy sacrificial layer 105, the dummy sacrificial layer 105 can be completely removed without removing the sacrificial layer 103. Therefore, empty spaces can be formed between some of the sacrificial layers 103.

[0080] Reference Figure 17 , a dummy nanosheet layer 131L can be formed to surround the sacrificial layer 103 and the nanosheet NS and conformally cover the spacer 115 and the second isolation layer 123.

[0081] The dummy nanosheet layer 131L can include an insulating material and, for example, can include at least one material selected from silicon oxide, silicon nitride, and silicon oxynitride.

[0082] Reference Figure 18 , the dummy nanosheet 131 can be formed at the position where the dummy sacrificial layer 105 is located (see Figure 15 ).

[0083] Specifically, the dummy nanosheet layer 131L can be patterned (see Figure 17 ), and the dummy nanosheet 131 can be formed between the sacrificial layers 103. That is, the dummy sacrificial layer 105 can be replaced with the dummy nanosheet 131 at the same position by a replacement process.

[0084] Reference Figure 19 , the sacrificial layer 103 (see Figure 18 ) can be completely removed from between the nanosheet NS and / or the dummy nanosheet 131.

[0085] By using the etching selectivity between the nanosheet NS and the sacrificial layer 103 and the etching selectivity between the dummy nanosheet 131 and the sacrificial layer 103, the sacrificial layer 103 can be completely removed without removing the nanosheet NS and the dummy nanosheet 131. Therefore, empty spaces can be formed between the nanosheet NS and / or the dummy nanosheet 131.

[0086] Reference Figure 20 , the gate dielectric film 141 can be formed to surround the exposed surfaces of the nanosheet NS and the dummy nanosheet 131.

[0087] Next, a conductive material film 151 can be formed on the gate dielectric film 141 to fill the space between the nanosheet NS and / or the dummy nanosheet 131.

[0088] The conductive material film 151 may be referred to as a buried conductive film. Each of the conductive material films 151 may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or a combination thereof.

[0089] Reference Figure 21 , a lower sacrificial layer 107 may be formed to cover a part of the intermediate dummy nanosheet 131 and its lower region.

[0090] Next, the exposed conductive material film 151 may be removed. Due to the lower sacrificial layer 107, the conductive material film 151 located in the lower region of the intermediate dummy nanosheet 131 can be protected, and the conductive material film 151 located in the upper region of the intermediate dummy nanosheet 131 can be completely removed.

[0091] Reference Figure 22 , the lower sacrificial layer 107 (see Figure 21 ) can be removed, and a dual conductive material film 151 and 153 can be formed at the position where the conductive material film 151 has been removed to surround the nanosheet NS and the dummy nanosheet 131.

[0092] The dual conductive material films 151 and 153 may include different conductive materials, such as doped polysilicon and conductive metal nitride.

[0093] Through the above process, with respect to the intermediate dummy nanosheet 131, the dual conductive material films 151 and 153 may be located in the upper region of the intermediate dummy nanosheet 131, and the single conductive material film 151 may be located in the lower region of the intermediate dummy nanosheet 131.

[0094] Reference Figure 23 , a first insulating layer 161 may be formed to surround the internal space of the spacer 115, the nanosheet NS, the dummy nanosheet 131, the conductive material film 151, and the dual conductive material films 151 and 153 from which the sacrificial mask patterns 111 and 113 (see Figure 14 ) have been removed.

[0095] The first insulating layer 161 may include silicon nitride, but the embodiment is not limited thereto. Then, the upper surface of the first insulating layer 161 may be polished, whereby the upper surface of the second separation layer 123 can be exposed. In the polishing process, the second separation layer 123 may be used as an etch stop film.

[0096] Reference Figure 24 , different etching may be performed on the split gate region SG and the common gate region CG.

[0097] Based on the drawings, in the split gate region SG, the first recessed region 161H can be formed by etching only the upper left portion of the first insulating layer 161, and in the common gate region CG, the first recessed region 161H can be formed by completely etching the left side region of the first insulating layer 161.

[0098] Accordingly, a part of the first insulating layer 161 can exist in the left side region of the split gate region SG, but the upper surface of the insulating pattern layer 143 including the same material as the gate dielectric film 141 can be exposed in the left side region of the common gate region CG.

[0099] Reference Figure 25 is made, and the first main gate 155 can be formed to completely fill each of the first recessed regions 161H in the split gate region SG and the common gate region CG.

[0100] The first main gate 155 can include substantially the same material as the conductive material film 151. In the left side region of the split gate region SG, the first main gate 155 can be formed on a part of the first insulating layer 161, and in the left side region of the common gate region CG, the first main gate 155 can be formed on the upper surface of the insulating pattern layer 143.

[0101] Reference Figure 26 is made, a part of the upper portion of the first main gate 155 can be etched, and the first insulating layer 161 can be formed in the region where that part has been etched.

[0102] Next, the first gate contact 171 that digs into a specific part of the upper portion of the first main gate 155 and contacts the first main gate 155 can be formed. The first gate contact 171 can pass through the first insulating layer 161 and can be connected to the first main gate 155. The first gate contact 171 can be formed in both the split gate region SG and the common gate region CG.

[0103] Reference Figure 27 is made, and the substrate 101 on which the first gate contact 171 is formed can be inverted.

[0104] Accordingly, based on the drawings, the resulting structure can be described as having a shape in which the substrate 101 is located at the top and the first gate contact 171 digs into a specific part of the lower portion of the first main gate 155 and contacts the first main gate 155.

[0105] Reference Figure 28 is made, the substrate 101 (see Figure 27 ) can be removed, and different second insulating layers 163 can be formed in the split gate region SG and the common gate region CG.

[0106] Based on the drawings, each second insulating layer 163 may be formed on the upper surface of the insulating pattern layer 143. In the split gate region SG, a second recessed region 163H may be formed by etching the left region of the second insulating layer 163, and in the common gate region CG, the second insulating layer 163 may be formed without being etched.

[0107] Referring Figure 29 , different etching may be performed on the split gate region SG and the common gate region CG.

[0108] Based on the drawings, in the split gate region SG, a third recessed region 163H2 may be formed by etching the upper left region of the first insulating layer 161 and the insulating pattern layer 143, and in the common gate region CG, a third recessed region 163H2 may be formed by etching the right region of the second insulating layer 163 and the insulating pattern layer 143.

[0109] Therefore, a part of the first insulating layer 161 may exist in the left region of the split gate region SG, and the first insulating layer 161 may completely exist in the left region of the common gate region CG.

[0110] Referring Figure 30 , a second main gate 157 may be formed to completely fill each of the third recessed regions 163H2 in the split gate region SG and the common gate region CG.

[0111] The second main gate 157 may include substantially the same material as the first main gate 155.

[0112] Based on the drawings, in the left region of the split gate region SG, the first main gate 155 may be formed on a part of the first insulating layer 161, and in the right region of the common gate region CG, the second main gate 157 may be formed on the upper surface of the first main gate 155.

[0113] Next, a part of the upper portion of the second main gate 157 may be etched, and the second insulating layer 163 may be formed in the region where the part has been etched.

[0114] Therefore, a third main gate 159 in which the first main gate 155 and the second main gate 157 are merged may be formed in the common gate region CG.

[0115] Returning to the reference Figure 3, the second gate contact 173 and the third gate contact 175 that are formed to dig into a specific portion of the upper part of the second main gate 157 and contact the second main gate 157 can be formed. The second gate contact 173 and the third gate contact 175 can penetrate the second insulating layer 163 and can be connected to the second main gate 157. The second gate contact 173 and the third gate contact 175 can be respectively formed in the split gate region SG and the common gate region CG.

[0116] Through the above manufacturing process, the integrated circuit device 10 according to the embodiment can be manufactured. The integrated circuit device 10 according to the inventive concept can use a three-dimensional vertical stacking structure in which NMOS transistors and PMOS transistors are stacked in the vertical direction, and thus can have highly integrated and improved electrical performance.

[0117] Although aspects of the inventive concept have been specifically shown and described with reference to embodiments of the inventive concept, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

[0118] Cross-reference to related applications

[0119] This application is based on and claims priority to Korean Patent Application No. 10-2023-0187520, filed with the Korean Intellectual Property Office on December 20, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: a first transistor including a plurality of first nanosheets having a first width in a first horizontal direction, a first gate structure surrounding the plurality of first nanosheets and extending on a first side of the plurality of first nanosheets in a second horizontal direction, and a first source / drain region on an opposite side of the plurality of first nanosheets in the first horizontal direction, The second horizontal direction is perpendicular to the first horizontal direction, The first side of the plurality of first nanosheets in the second horizontal direction is opposite to the second side of the plurality of first nanosheets in the second horizontal direction; as well as a second transistor above the first transistor, the second transistor comprising a plurality of second nanosheets above the plurality of first nanosheets and having a second width in the first horizontal direction, a second gate structure surrounding the plurality of second nanosheets and extending on a second side of the plurality of second nanosheets in the second horizontal direction, and a second source / drain region on an opposite side of the plurality of second nanosheets in the first horizontal direction, the second width is equal to the first width, The second side of the plurality of second nanosheets in the second horizontal direction is opposite to the first side of the plurality of second nanosheets in the second horizontal direction, and The second sides of the plurality of second nanosheets in the second horizontal direction are above the second sides of the plurality of first nanosheets in the second horizontal direction.

2. The integrated circuit device according to claim 1, further comprising: a first insulating layer below a lower portion of the second gate structure; as well as a second insulating layer on an upper portion of the first gate structure, wherein The first gate structure includes a plurality of first sub-gates and a first main gate, The plurality of first sub-gates surround the plurality of first nanosheets, The first main gate contacts the plurality of first sub-gates and extends along the second horizontal direction on the first side of the plurality of first nanosheets in the second horizontal direction, The second gate structure includes a plurality of second sub-gates and a second main gate, The plurality of second sub-gates surround the plurality of second nanosheets, The second main gate contacts the plurality of second sub-gates and extends on the second side of the plurality of second nanosheets in the second horizontal direction, The thickness of the second insulating layer in the vertical direction is greater than the thickness of the second gate structure above the first gate structure in the vertical direction, and The thickness of the first insulating layer in the vertical direction is greater than the thickness of the first gate structure in the vertical direction.

3. The integrated circuit device according to claim 2, wherein: In a cross-sectional view, the first main gate of the first gate structure is disposed in a diagonal direction relative to the second main gate of the second gate structure.

4. The integrated circuit device according to claim 2, further comprising: A plurality of gate dielectric films, wherein Each of the plurality of first sub-gates includes a double conductive material film, Each of the plurality of second sub-gates includes a single conductive material film, and The plurality of gate dielectric films are between the plurality of first nanosheets and the plurality of first sub-gates and between the plurality of second nanosheets and the plurality of second sub-gates.

5. The integrated circuit device according to claim 4, further comprising: Insulation pattern layer, wherein The insulating pattern layer is located on an upper surface of an uppermost second sub-gate among the plurality of second sub-gates, and A material of the insulating pattern layer is the same as a material of the plurality of gate dielectric films.

6. The integrated circuit device according to claim 1, further comprising: a third transistor spaced apart from the first transistor and the second transistor in the first horizontal direction, wherein the third transistor comprising a plurality of third nanosheets having a third width in the first horizontal direction, a third gate structure surrounding the plurality of third nanosheets and extending on one side of the plurality of third nanosheets in the second horizontal direction, and a third source / drain region on an opposite side of the plurality of third nanosheets in the first horizontal direction, The third width is equal to the first width, The level of the uppermost surfaces of the plurality of third nanosheets is equal to the level of the uppermost surfaces of the plurality of second nanosheets, and A level of lowermost surfaces of the plurality of third nanosheets is equal to a level of lowermost surfaces of the plurality of first nanosheets. 7 . The integrated circuit device of claim 6 , wherein a lowermost nanosheet among the plurality of first nanosheets and a lowermost nanosheet among the plurality of third nanosheets each comprise a dummy nanosheet.

8. The integrated circuit device according to claim 6, wherein The level of the uppermost surface of the third gate structure is the same as the level of the uppermost surface of the second gate structure, and The level of the lowermost surface of the third gate structure is the same as the level of the lowermost surface of the first gate structure.

9. The integrated circuit device according to claim 6, wherein The first transistor includes a first gate contact contacting a lower portion of the first gate structure, The second transistor includes a second gate contact contacting an upper portion of the second gate structure, and The third transistor includes a third gate contact contacting an upper portion and a lower portion of the third gate structure, respectively.

10. The integrated circuit device according to claim 9, wherein: In a cross-sectional view, the first gate contact is arranged in a diagonal direction relative to the second gate contact, and The third gate contact is located on a straight line in the vertical direction.

11. An integrated circuit device comprising: Lower transistor; as well as an upper transistor at a higher vertical level than the lower transistor, wherein The lower transistor includes a lower source / drain region and a lower gate structure between the lower source / drain region, The upper transistor includes an upper source / drain region and an upper gate structure between the upper source / drain region, The lower gate structure and the upper gate structure divide the plurality of nanosheets into an upper portion and a lower portion and share the plurality of nanosheets, and The plurality of nanosheets are stacked in a vertical direction and have aligned centers.

12. The integrated circuit device of claim 11, wherein the plurality of nanosheets comprises: The bottom dummy nanosheet and the middle dummy nanosheet; a plurality of lower active nanosheets between the lowermost dummy nanosheet and the middle dummy nanosheet; as well as A plurality of active nanosheets are disposed above the middle dummy nanosheet, The lower transistor includes the plurality of lower active nanosheets as a lower channel region, and The upper transistor includes the plurality of upper active nanosheets as an upper channel region.

13. The integrated circuit device according to claim 12, wherein The lower gate structure contacts both the lowermost dummy nanosheet and the middle dummy nanosheet, The upper gate structure contacts the middle dummy nanosheet, and The upper gate structure does not contact the lowermost dummy nanosheet.

14. The integrated circuit device according to claim 11, wherein: In cross-sectional view, the lower transistor includes a lower gate contact contacting a lower portion of the lower gate structure, The upper transistor includes an upper gate contact contacting an upper portion of the upper gate structure, and The lower gate contact is disposed in a diagonal direction relative to the upper gate contact.

15. The integrated circuit device according to claim 11, further comprising: an upper insulating layer, above the lower gate structure; as well as A lower insulating layer, below the upper gate structure, wherein In the cross-sectional view, the thickness of the upper insulating layer is greater than the thickness of the upper gate structure above the lower gate structure in the vertical direction, and In the vertical direction, the thickness of the lower insulating layer is greater than the thickness of the lower gate structure.

16. An integrated circuit device comprising: two first transistors spaced apart from each other in a first horizontal direction; two second transistors spaced apart from each other in the first horizontal direction, the second transistors being above the two first transistors; as well as two third transistors are spaced apart from each other in the first horizontal direction, and the two first transistors and the two second transistors are located between the two third transistors, Each of the two first transistors includes a plurality of first nanosheets having a first width in the first horizontal direction, a first gate structure surrounding the plurality of first nanosheets and extending on a first side of the plurality of first nanosheets in a second horizontal direction, and first source / drain regions on opposite sides of the plurality of first nanosheets in the first horizontal direction, The second horizontal direction is perpendicular to the first horizontal direction, The first side of the plurality of first nanosheets in the second horizontal direction is opposite to the second side of the plurality of first nanosheets in the second horizontal direction, Each of the two second transistors includes a plurality of second nanosheets above a lower one of the plurality of first nanosheets and having a second width in the first horizontal direction, a second gate structure surrounding the plurality of second nanosheets and extending on a second side of the plurality of second nanosheets in the second horizontal direction, and a second source / drain region on an opposite side of the plurality of second nanosheets in the first horizontal direction, the second width is equal to the first width, The second side of the plurality of second nanosheets in the second horizontal direction is opposite to the first side of the plurality of second nanosheets in the second horizontal direction, The second side of the plurality of second nanosheets in the second horizontal direction is located above the second side of the lower first nanosheet in the plurality of first nanosheets in the second horizontal direction, Each of the two third transistors includes a plurality of third nanosheets having a third width equal to the first width in the first horizontal direction, a third gate structure surrounding the plurality of third nanosheets and extending on one side of the plurality of third nanosheets in the second horizontal direction, and third source / drain regions on both sides of the plurality of third nanosheets.

17. The integrated circuit device of claim 16, wherein The level of the uppermost surfaces of the plurality of third nanosheets is the same as the level of the uppermost surfaces of the plurality of second nanosheets, and The level of the lowermost surfaces of the plurality of third nanosheets is the same as the level of the lowermost surfaces of the plurality of first nanosheets.

18. The integrated circuit device of claim 16, wherein The level of the uppermost surface of the third gate structure is the same level as the level of the uppermost surface of the second gate structure, and A level of a lowermost surface of the third gate structure is the same level as a level of a lowermost surface of the first gate structure.

19. The integrated circuit device of claim 16, wherein The number of active nanosheets in the third plurality of nanosheets is equal to the sum of the number of active nanosheets in the first plurality of nanosheets and the number of active nanosheets in the second plurality of nanosheets.

20. The integrated circuit device of claim 16, wherein The two first transistors include n-channel metal oxide semiconductor (NMOS) transistors, The two second transistors include p-channel metal oxide semiconductor (PMOS) transistors, and The two first transistors, the two second transistors, and the two third transistors form a flip-flop structure.

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