Display panel and display device

Abstract

The invention provides a display panel and a display device, the display panel is provided with a display area, the display panel comprises a first substrate, the first substrate of the display area comprises a first substrate, a first metal layer and a metal oxide semiconductor layer, the first metal layer is arranged on one side of the first substrate, and the first metal layer comprises a plurality of data lines which are sequentially arranged at intervals; the metal oxide semiconductor layer is arranged on the side, away from the first substrate, of the first metal layer, the metal oxide semiconductor layer comprises a plurality of transparent active layers, each transparent active layer comprises a channel, a source electrode region and a drain electrode region, the source electrode regions and the drain electrode regions are located on the two sides of the channel, and the source electrode regions are electrically connected with the data lines through via holes; wherein the orthographic projections of the channel, the source electrode region and the drain electrode region on the first substrate are overlapped with the orthographic projection of the data line on the first substrate, and the display panel provided by the invention can improve the product yield of the display panel while giving consideration to high pixel resolution.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the development of display technologies, consumer electronic products that rely on the display function of display panels, such as mobile phones, televisions, personal digital assistants, digital cameras, laptop computers, desktop computers, virtual reality (VR for short) display devices, and augmented reality (AR for short) display devices, emerge in an endless stream. The rise of the "metaverse" concept has also made VR / AR display devices widely concerned by consumers and has broad market application prospects.

[0003] VR / AR display devices are near-eye display devices and have high requirements for the resolution of the display panels therein. For example, it is necessary to increase the pixel density unit (Pixels Per Inch, PPI for short) of the display panels in VR / AR display devices to a level above 1500. However, when the PPI is increased, the distance between two adjacent active layers will be compressed, resulting in the minimum distance between two adjacent active layers not meeting the design requirements. Taking Figure 1 the 2000PPI display panel shown as an example, the horizontal distance a between two adjacent active layers is 4.2 micrometers, but the minimum distance b between two adjacent active layers is only 2.95 micrometers, which cannot meet the design requirements and greatly reduces the product yield.

[0004] Therefore, how to improve the product yield of the display panel while taking into account high pixel resolution is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] This application provides a display panel and a display device, which can effectively solve the problem that the display panels in existing VR / AR display devices cannot take into account both high resolution and product yield.

[0006] In a first aspect, the present application provides a display panel. The display panel has a display area and includes a first substrate. The first substrate of the display area includes: a first substrate; a first metal layer disposed on one side of the first substrate, the first metal layer including a plurality of data lines disposed at intervals in sequence; a metal oxide semiconductor layer disposed on the side of the first metal layer facing away from the first substrate, the metal oxide semiconductor layer including a plurality of transparent active layers, the transparent active layer including a channel and source and drain regions located on both sides of the channel, the source region being connected to the data line through a via; wherein, the orthographic projections of the channel, the source region, and the drain region on the first substrate all overlap with the orthographic projection of the data line on the first substrate.

[0007] Optionally, the first substrate of the display area further includes: at least one first insulating layer disposed between the first metal layer and the metal oxide semiconductor layer; wherein, the source region is connected to the data line through a first via penetrating through the at least one first insulating layer.

[0008] Optionally, the first substrate of the display area further includes: at least one first insulating layer disposed between the first metal layer and the metal oxide semiconductor layer; a second metal layer disposed on the side of the metal oxide semiconductor layer facing away from the first substrate; at least one second insulating layer disposed between the metal oxide semiconductor layer and the second metal layer; wherein, the second metal layer includes a plurality of bridging portions, the bridging portions are connected to the source region through a second via penetrating through the at least one second insulating layer, and the bridging portions are connected to the data line through a third via penetrating through the at least one second insulating layer and the at least one first insulating layer.

[0009] Optionally, the display panel further has a non-display area. The first substrate of the non-display area includes: a first gate metal layer including a plurality of first gates, the first gates being used as gates of low-temperature polysilicon thin-film transistors disposed in the non-display area; wherein, the first gate metal layer and the first metal layer are disposed in the same layer and have the same material.

[0010] Optionally, the first substrate of the display area further includes: a first transparent conductive layer disposed on a side of the metal oxide semiconductor layer facing away from the first substrate. The first transparent conductive layer includes a plurality of first transparent conductive portions. Each first transparent conductive portion includes a first part and a second part. The first part is connected to the drain region through a via hole. A second transparent conductive layer is disposed on a side of the first transparent conductive layer facing away from the first substrate. The second transparent conductive layer includes a plurality of second transparent conductive portions. The second transparent conductive portions are connected to the second parts through via holes. Wherein, the second part is located between two adjacent data lines, and the distances between the second part and the two adjacent data lines are different.

[0011] Optionally, the first transparent conductive portion further includes a connecting portion connecting the first part and the second part. The connecting portion is inclined with respect to the data line, and the included angle between the connecting portion and the data line is an acute angle, and the included angle is less than or equal to 20°.

[0012] Optionally, the first substrate of the display area further includes: a first light-shielding layer disposed between the first transparent conductive layer and the second transparent conductive layer. The first light-shielding layer includes a plurality of first light-shielding portions. Each first light-shielding portion includes a first sub-light-shielding portion, a second sub-light-shielding portion, and an avoidance portion. The first sub-light-shielding portion is disposed corresponding to the source region. The second sub-light-shielding portion is disposed corresponding to the drain region. The avoidance portion connects the first sub-light-shielding portion and the second sub-light-shielding portion. Wherein, the avoidance portion forms a notch on a side close to the second part.

[0013] Optionally, the display panel further includes a second substrate and a liquid crystal layer. The second substrate is disposed opposite to the first substrate. The liquid crystal layer is disposed between the first substrate and the second substrate. Wherein, the second substrate includes: a second substrate; a second light-shielding layer disposed on one side of the second substrate. Wherein, the second light-shielding organic layer includes a plurality of second light-shielding portions. The extending direction of the second light-shielding portions is different from the extending direction of the first light-shielding portions.

[0014] Optionally, the first substrate of the display area further includes: a color filter layer disposed between the first transparent conductive layer and the first light-shielding layer. The color filter layer includes a plurality of color filter units. Each color filter unit includes a first filter unit, a second filter unit, and a third filter unit. Wherein, two adjacent first filter units are spaced apart, two adjacent second filter units are spaced apart, and two adjacent third filter units are spaced apart.

[0015] In a second aspect, the present application provides a display device, which includes a housing and the display panel described in any one of the above. Wherein, the housing has an accommodation space, and the display panel is disposed in the accommodation space.

[0016] Embodiments of the present application provide a display panel and a display device. The display panel has a display area. The display panel includes a first substrate. The first substrate of the display area includes a first substrate, a first metal layer, and a metal oxide semiconductor layer. Wherein, the first metal layer is disposed on one side of the first substrate, and the first metal layer includes a plurality of data lines arranged at intervals; the metal oxide semiconductor layer is disposed on the side of the first metal layer away from the first substrate, and the metal oxide semiconductor layer includes a plurality of transparent active layers. The transparent active layer includes a channel and source regions and drain regions located on both sides of the channel. The source region is electrically connected to the data line through a via; wherein, the orthographic projections of the channel, the source region, and the drain region on the first substrate all overlap with the orthographic projection of the data line on the first substrate. In the display panel provided by the embodiments of the present application, since the orthographic projections of the channel, the source region, and the drain region in the transparent active layer on the first substrate all overlap with the orthographic projection of the data line on the first substrate, therefore, the overlapping area between the transparent active layer and the data line can be increased, so as to form the transparent active layer in the area above the data line as much as possible, and then reduce the area of the transparent active layer in the area between two adjacent data lines, reduce the width occupied by the transparent active layer in the arrangement direction of the data lines, and minimize or eliminate as much as possible the part of the transparent active layer that is inclined relative to the data line. Furthermore, when the pitch between two adjacent data lines is reduced and the resolution of the display panel is improved, the minimum pitch between two adjacent transparent active layers can be increased as much as possible, thereby improving the production yield of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0018] Figure 1 It is a schematic plan view of two adjacent transparent active layers in an array substrate of a display area in the related art.

[0019] Figure 2 It is a schematic plan view of a display panel provided by some embodiments of the present application.

[0020] Figure 3 It is a schematic diagram of the film layer structure of a display panel provided by some embodiments of the present application.

[0021] Figure 4A plan view of a plurality of adjacent transparent active layers in the first substrate of the display area provided by some embodiments of the present application.

[0022] Figure 5 A schematic diagram of the film layer structure of the first substrate and the second substrate provided by Embodiment 1 of the present application.

[0023] Figure 6a A plan view of the first transparent conductive portion provided by some embodiments of the present application.

[0024] Figure 6b A plan view of the first light-shielding portion provided by some embodiments of the present application.

[0025] Figure 6c A plan view of the second transparent conductive portion provided by some embodiments of the present application.

[0026] Figure 6d A plan view of the data line, transparent active layer, first transparent conductive portion, first light-shielding portion, and second transparent conductive portion provided by some embodiments of the present application and stacked.

[0027] Figure 7 A plan view of the color filter unit provided by Embodiment 1 of the present application.

[0028] Figure 8 A schematic diagram of the film layer structure of the first substrate and the second substrate provided by Embodiment 2 of the present application.

[0029] Figure 9 A schematic diagram of the film layer structure of the first substrate and the second substrate provided by Embodiment 3 of the present application.

[0030] Figure 10 A schematic diagram of the film layer structure of the first substrate and the second substrate provided by Embodiment 4 of the present application.

[0031] Explanation of reference numerals:

[0032] Active layer A; horizontal pitch a; minimum pitch b;

[0033] Display panel 01; display area AA; non-display area NAA; first substrate 10; first substrate 101; first metal layer 102; data line 1021; metal oxide semiconductor layer 103; transparent active layer 1031; channel 1032; source region 1033; drain region 1034; at least one first insulating layer 104; second metal layer 105; bridging portion 1051; at least one second insulating layer 106; first transparent conductive layer 107; first transparent conductive portion 1071; first portion 1072; second portion 1073; connecting portion 1074; second transparent conductive layer 108; second transparent conductive portion 1081; first light-shielding layer 109; first light-shielding portion 1091; first sub-light-shielding portion 1092; second sub-light-shielding portion 1093; avoidance portion 1094; notch 1095; color filter layer 110; color filter unit 1101; first filter unit 1102; second filter unit 1103; third filter unit 1104; second gate metal layer 111; third transparent conductive layer 112; fourth transparent conductive layer 113; third gate metal layer 114; composite functional layer M1; first gate insulating layer M2; first interlayer dielectric layer M3; second interlayer dielectric layer M4; second gate insulating layer M5; third gate insulating layer M6; third interlayer dielectric layer M7; first barrier insulating layer M8; second barrier insulating layer M9; first planarization layer M10; first passivation layer M11; second passivation layer M12; second planarization layer M13; third planarization layer M14; third passivation layer M15; first gate metal layer N11; first gate N111; first via hole H1; second via hole H2; third via hole H3; second substrate 20; second substrate 201; second light-shielding layer 202; second light-shielding portion 2021; liquid crystal layer 30; Detailed implementation manners

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. In addition, it should be understood that the specific implementation manners described herein are only for explaining and illustrating the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the orientation words such as "upper" and "lower" generally refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; and "inner" and "outer" refer to the outline of the device.

[0035] The following disclosure provides many different embodiments or examples for implementing different structures of the present application. To simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are only examples and are not intended to limit the present application. In addition, the present application may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials. The following will be described in detail respectively. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments.

[0036] Embodiment 1

[0037] Figure 2 It is a schematic plan view of a display panel provided in some embodiments of the present application; Figure 3 It is a schematic diagram of the film layer structure of a display panel provided in some embodiments of the present application; Figure 4 It is a schematic plan view of two adjacent transparent active layers in the first substrate of the display area provided in some embodiments of the present application; Figure 5 It is a schematic diagram of the film layer structure of the first substrate and the second substrate provided in Embodiment 1 of the present application. Combining Figures 2 - 5 As shown, in a first aspect, Embodiment 1 of the present application provides a display panel 01. The display panel 01 can be applied to a VR display device with high-resolution display requirements, and the type of the display panel 01 can be a liquid crystal display panel.

[0038] Specifically, the display panel 01 has a display area AA. The display panel 01 includes a first substrate 10. The first substrate 10 of the display area AA includes a first substrate 101, a first metal layer 102, and a metal oxide semiconductor layer 103. Among them, the first metal layer 102 is disposed on one side of the first substrate 101, and the first metal layer 102 includes a plurality of data lines 1021 arranged at intervals in sequence; the metal oxide semiconductor layer 103 is disposed on the side of the first metal layer 102 away from the first substrate 101. The metal oxide semiconductor layer 103 includes a plurality of transparent active layers 1031. The transparent active layer 1031 includes a channel 1032 and a source region 1033 and a drain region 1034 located on both sides of the channel 1032. The source region 1033 is electrically connected to the data line 1021 through a via hole; among them, the positive projections of the channel 1032, the source region 1033, and the drain region 1034 on the first substrate 101 all overlap with the positive projection of the data line 1021 on the first substrate 101.

[0039] In the display panel 01 provided by the embodiment of the present application, since the projections of the channel 1032, the source region 1033, and the drain region 1034 in the transparent active layer 1031 on the first substrate 101 all overlap with the projection of the data line 1021 on the first substrate 101, the overlapping area between the transparent active layer 1031 and the data line 1021 can be increased, so as to form the transparent active layer 1031 in the area above the data line 1021 as much as possible. Furthermore, the area of the transparent active layer 1031 in the region between two adjacent data lines 1021 is reduced, the width occupied by the transparent active layer 1031 in the arrangement direction of the data lines 1021 is reduced, and the portion of the transparent active layer 1031 that is inclined with respect to the data line 1021 is minimized or eliminated as much as possible. Therefore, when the pitch between two adjacent data lines 1021 is reduced and the resolution of the display panel 01 is improved, the minimum pitch between two adjacent transparent active layers 1031 can be increased as much as possible, thereby improving the production yield of the display panel 01.

[0040] In some embodiments of the present application, the extending direction of the transparent active layer 1031 is the same as the extending direction of the data line 1021. For example, both the transparent active layer 1031 and the data line 1021 are strip-shaped, and the extending directions of the transparent active layer 1031 and the data line 1021 are both perpendicular to the arrangement direction of the data lines 1021.

[0041] Refer to Figure 5 , in some embodiments of the present application, the first substrate 10 of the display area AA further includes at least one first insulating layer 104, and the at least one first insulating layer 104 is disposed between the first metal layer 102 and the metal oxide semiconductor layer 103; wherein, the source region 1033 is electrically connected to the data line 1021 through a first via hole H1 penetrating through the at least one first insulating layer 104.

[0042] In the display panel 01 provided by the embodiment of the present application, since the transparent active layer 1031 is disposed on the side of the data line 1021 away from the first substrate 101, and the projection of the source region 1033 of the transparent active layer 1031 on the first substrate 101 overlaps with the projection of the data line 1021 on the first substrate 101, the source region 1033 can be electrically connected to the data line 1021 through a first via hole H1 penetrating through the at least one first insulating layer 104 by directly disposing a via hole on the side of the source region 1033 facing the first substrate 101.

[0043] In some embodiments of the present application, the display panel 01 further has a non-display area NAA. The first substrate 10 of the non-display area NAA includes: a first gate metal layer N11, including a plurality of first gates N111, and the first gates N111 are used as the gates of the low-temperature polycrystalline silicon thin-film transistors disposed in the non-display area NAA; wherein, the first gate metal layer N11 and the first metal layer 102 are disposed on the same layer and have the same material.

[0044] In the display panel 01 provided by the embodiments of the present application, the first substrate 10 of the display area AA includes a plurality of metal oxide thin-film transistors, and the transparent active layer 1031 is used as the semiconductor layer of the metal oxide thin-film transistors disposed in the display area AA; the first substrate 10 of the non-display area NAA includes a plurality of low-temperature polycrystalline silicon thin-film transistors, and the first gates N111 in the first gate metal layer N11 are used as the gates of the low-temperature polycrystalline silicon thin-film transistors disposed in the non-display area NAA. That is to say, the first substrate 10 includes metal oxide thin-film transistors disposed in the display area AA and low-temperature polycrystalline silicon thin-film transistors disposed in the non-display area NAA. Furthermore, the display driving circuit in the first substrate 10 of the display area AA can make full use of the characteristics of the low off-state current of the metal oxide thin-film transistors and the non-reduction of the aperture ratio by the transparent active layer 1031, and the gate driving circuit in the first substrate 10 of the non-display area NAA can make full use of the strong stability of the low-temperature polycrystalline silicon thin-film transistors, greatly improving the display performance of the display panel 01. In addition, since the first gate metal layer N11 and the first metal layer 102 are disposed on the same layer and have the same material, the first gate metal layer N11 and the first metal layer 102 can be integrally formed, simplifying the film layer structure of the first substrate 10 and reducing the production and manufacturing costs.

[0045] Figure 6a A plan view of the first transparent conductive part provided by some embodiments of the present application; Figure 6b A plan view of the first light-shielding part provided by some embodiments of the present application; Figure 6c A plan view of the second transparent conductive part provided by some embodiments of the present application; Figure 6d A plan view of the data line, transparent active layer, first transparent conductive part, first light-shielding part, and second transparent conductive part stacked together provided by some embodiments of the present application. Combining Figure 5 and Figure 6a 、 6b, as shown in FIGS. 6c and 6d, in some embodiments of the present application, the first substrate 10 of the display area AA further includes a first transparent conductive layer 107 and a second transparent conductive layer 108. The first transparent conductive layer 107 is disposed on a side of the metal oxide semiconductor layer 103 away from the first substrate 101. The first transparent conductive layer 107 includes a plurality of first transparent conductive portions 1071. The first transparent conductive portion 1071 includes a first portion 1072 and a second portion 1073. The first portion 1072 is electrically connected to the drain region 1034 through a via hole; the second transparent conductive layer 108 is disposed on a side of the first transparent conductive layer 107 away from the first substrate 101. The second transparent conductive layer 108 includes a plurality of second transparent conductive portions 1081. The second transparent conductive portion 1081 is electrically connected to the second portion 1073 through a via hole; wherein, the second portion 1073 is located between two adjacent data lines 1021, and the distances between the second portion 1073 and the two adjacent data lines 1021 are different.

[0046] In the related art, the second portion 1073 in the first transparent conductive portion 1071 that is electrically connected to the second transparent conductive portion 1081 through a via hole is often disposed in the middle region between two adjacent data lines 1021, and the first portion 1072 in the first transparent conductive portion 1071 overlaps with the drain region 1034 and the data line 1021. This makes it necessary to form a connecting portion 1074 with a relatively large inclination angle with respect to the data line 1021 between the first portion 1072 and the second portion 1073, which will result in a relatively small spacing distance between two adjacent first transparent conductive portions 1071 at the connecting portion 1074 and less than the safety threshold, thereby causing a yield problem in the display panel 01.

[0047] In the present application, by making the distances between the second portion 1073 and the two adjacent data lines 1021 different, the second portion 1073 can be made not to be located in the middle region between two adjacent data lines 1021. For example, each second portion 1073 can be made closer to the data line 1021 on its left side, or each second portion 1073 can be made closer to the data line 1021 on its right side. Furthermore, the inclination angle between the connecting portion 1074 between the first portion 1072 and the second portion 1073 and the data line 1021 is reduced, and the spacing distance between two adjacent first transparent conductive portions 1071 at the connecting portion 1074 is increased, thereby improving the production yield of the display panel 01.

[0048] In some embodiments of the present application, the first transparent conductive portion 1071 further includes a connecting portion 1074 connecting the first portion 1072 and the second portion 1073. The connecting portion 1074 is inclined with respect to the data line 1021, and the included angle between the connecting portion 1074 and the data line 1021 is an acute angle, and the included angle is less than or equal to 20°.

[0049] In the display panel 01 provided by the embodiments of the present application, since the included angle between the connecting portion 1074 and the data line 1021 is an acute angle, and the included angle is less than or equal to 20°, the interval distance between two adjacent first transparent conductive portions 1071 at the connecting portion 1074 can be effectively increased, thereby improving the production yield of the display panel 01.

[0050] In some embodiments of the present application, the first substrate 10 in the display area AA further includes a first light-shielding layer 109. The first light-shielding layer 109 is disposed between the first transparent conductive layer 107 and the second transparent conductive layer 108. The first light-shielding layer 109 includes a plurality of first light-shielding portions 1091. The first light-shielding portion 1091 includes a first sub-light-shielding portion 1092, a second sub-light-shielding portion 1093, and an avoidance portion 1094. The first sub-light-shielding portion 1092 is correspondingly disposed with the source region 1033. The second sub-light-shielding portion 1093 is correspondingly disposed with the drain region 1034. The avoidance portion 1094 connects the first sub-light-shielding portion 1092 and the second sub-light-shielding portion 1093. Wherein, a notch 1095 is formed on one side of the avoidance portion 1094 close to the second portion 1073.

[0051] In the display panel 01 provided by the embodiments of the present application, the first light-shielding portion 1091 is correspondingly disposed with the transparent active layer 1031 to shield the transparent active layer 1031, so as to improve the device performance of the metal oxide thin film transistor including the transparent active layer 1031.

[0052] In the display panel 01 provided by the embodiments of the present application, when the second portion 1073 is closer to the data line 1021 on its left side, a notch 1095 is formed on one side of the avoidance portion 1094 corresponding to the left data line 1021 close to the second portion 1073, so as to avoid a short circuit problem between the first light-shielding portion 1091, the second portion 1073, and the second transparent conductive portion 1081 electrically connected to the second portion 1073, and improve the stability of the display panel 01.

[0053] In other embodiments of the present application, in the display panel 01 provided by the embodiments of the present application, when the second portion 1073 is closer to the data line 1021 on its right side, a notch 1095 is formed on one side of the avoidance portion 1094 corresponding to the data line 1021 on the right side near the second portion 1073, so as to avoid a short - circuit problem between the first light - shielding portion 1091, the second portion 1073, and the second transparent conductive portion 1081 electrically connected to the second portion 1073, and improve the stability of the display panel 01.

[0054] In some embodiments of the present application, the display panel 01 further includes a second substrate 20 and a liquid crystal layer 30. The second substrate 20 is disposed opposite to the first substrate 10, and the liquid crystal layer 30 is disposed between the first substrate 10 and the second substrate 20. Among them, the second substrate 20 includes: a second substrate 201; a second light - shielding layer 202 disposed on one side of the second substrate 201. Among them, the second light - shielding organic layer includes a plurality of second light - shielding portions 2021, and the extending direction of the second light - shielding portion 2021 is different from the extending direction of the first light - shielding portion 1091.

[0055] In the display panel 01 provided by the embodiments of the present application, since the second substrate 20 includes the second light - shielding layer 202, and the extending direction of the second light - shielding portion 2021 in the second light - shielding layer 202 is different from the extending direction of the first light - shielding portion 1091, therefore, light - shielding portions with different extending directions are respectively provided on the first substrate 10 and the second substrate 20. Furthermore, it is possible to avoid the problem that the wiring difficulty is greatly increased due to the need to form a grid - shaped light - shielding layer on the first substrate 10, and the interval distance between adjacent first light - shielding portions 1091 can be made smaller, improving the resolution of the display panel 01.

[0056] Figure 7 It is a schematic plan view of a color filter unit provided in Embodiment 1 of the present application. Combining Figure 5 and Figure 7 As shown, in some embodiments of the present application, the first substrate 10 of the display area AA further includes: a color filter layer 110 disposed between the first transparent conductive layer 107 and the first light - shielding layer 109. The color filter layer 110 includes a plurality of color filter units 1101. Each color filter unit 1101 includes a first filter unit 1102, a second filter unit 1103, and a third filter unit 1104. Among them, two adjacent first filter units 1102 are spaced apart, two adjacent second filter units 1103 are spaced apart, and two adjacent third filter units 1104 are spaced apart.

[0057] In the display panel 01 provided by the embodiment of the present application, since both the color filter layer 110 and the data line 1021 are integrated on the first substrate 10, the pixel region between the color filter unit 1101 and the adjacent data line 1021 can be aligned during film formation, with higher alignment accuracy, improving the display color deviation problem caused by the alignment accuracy problem of different substrates when the color filter unit 1101 and the data line 1021 are located on different substrates respectively. In addition, since the first light-shielding portion 1091 is further provided on the first substrate 10, the color filter unit 1101 and the first light-shielding portion 1091 can be aligned during film formation, with higher alignment accuracy. Secondly, since two adjacent first filter units 1102 are arranged at intervals, two adjacent second filter units 1103 are arranged at intervals, and two adjacent third filter units 1104 are arranged at intervals, that is, each color filter unit 1101 is independently arranged relative to its adjacent color filter unit 1101, thereby reducing the integration difficulty of the color filter layer 110 on the first substrate 10 and improving the production yield of the display panel 01. Optionally, the distance between two adjacent color filter units 1101 is 4-5 microns to reduce the planarization difficulty of the color filter layer 110.

[0058] In some embodiments of the present application, the first substrate 10 of the display area AA includes a composite functional layer M1, a first gate N111 insulating layer M2, the first metal layer 102, a first interlayer dielectric layer M3, a second interlayer dielectric layer M4, a second gate metal layer 111, a second gate insulating layer M5, the metal oxide semiconductor layer 103, a third gate insulating layer M6, a third gate metal layer 114, a third interlayer dielectric layer M7, a first barrier insulating layer M8, the first transparent conductive layer 107, a second barrier insulating layer M9, the color filter layer 110, a first planar layer M10, a first passivation layer M11, a first light-shielding layer 109, a second passivation layer M12, the second transparent conductive layer 108, a second planar layer M13, a third planar layer M14, a third transparent conductive layer 112, a third passivation layer M15, and a fourth transparent conductive layer 113, which are sequentially stacked on one side of the first substrate 101, wherein the at least one first insulating layer 104 includes the first interlayer dielectric layer M3, the second interlayer dielectric layer M4, and the second gate insulating layer M5, and the first via H1 penetrates through the second gate insulating layer M5, the second interlayer dielectric layer M4, and the first interlayer dielectric layer M3.

[0059] In a second aspect, an embodiment of the present application provides a display device, which includes a housing and the display panel 01 described in any one of the above, wherein the housing has an accommodating space, and the display panel 01 is disposed in the accommodating space.

[0060] Embodiment 2

[0061] Figure 8 It is a schematic diagram of the film layer structures of the first substrate and the second substrate provided in Embodiment 2 of the present application. Refer to Figure 8 As shown, on the first aspect, Embodiment 2 of the present application provides a display panel 01. The display panel 01 has a display area AA. The display panel 01 includes a first substrate 10. The first substrate 10 in the display area AA includes a first substrate 101, a first metal layer 102, and a metal oxide semiconductor layer 103. Among them, the first metal layer 102 is disposed on one side of the first substrate 101. The first metal layer 102 includes a plurality of data lines 1021 arranged at intervals in sequence. The metal oxide semiconductor layer 103 is disposed on the side of the first metal layer 102 away from the first substrate 101. The metal oxide semiconductor layer 103 includes a plurality of transparent active layers 1031. The transparent active layer 1031 includes a channel 1032 and source regions 1033 and drain regions 1034 located on both sides of the channel 1032. The source region 1033 is electrically connected to the data line 1021 through a via hole. Among them, the orthographic projections of the channel 1032, the source region 1033, and the drain region 1034 on the first substrate 101 all overlap with the orthographic projection of the data line 1021 on the first substrate 101.

[0062] It should be noted that the structure of the display panel 01 provided in Embodiment 2 of the present application is similar to the structure of the display panel 01 provided in Embodiment 1 of the present application. The same parts in Embodiment 2 of the present application will not be described in detail.

[0063] In some embodiments of the present application, the display panel 01 further has a non-display area NAA. The first substrate 10 in the non-display area NAA includes a first gate metal layer N11. The first gate metal layer N11 includes a plurality of first gates N111. The first gate N111 is used as the gate of the low-temperature polysilicon thin-film transistor disposed in the non-display area NAA. The first gate metal layer N11 and the first metal layer 102 are disposed in different layers.

[0064] In some embodiments of the present application, the first metal layer 102 is disposed on a side of the first interlayer dielectric layer M3 facing away from the first gate metal layer N11. The first substrate 10 of the display area AA further includes at least one first insulating layer 104, and the at least one first insulating layer 104 is disposed between the first metal layer 102 and the metal oxide semiconductor layer 103. Wherein, the source region 1033 is electrically connected to the data line 1021 through a first via hole H1 penetrating through the at least one first insulating layer 104. Wherein, the at least one first insulating layer 104 includes a second interlayer dielectric layer M4 and a second gate insulating layer M5, and the first via hole H1 penetrates through the second gate insulating layer M5 and the second interlayer dielectric layer M4.

[0065] In the display panel 01 provided by the embodiments of the present application, since the first metal layer 102 is disposed on a side of the first interlayer dielectric layer M3 facing away from the first gate metal layer N11, therefore, the distance between the first metal layer 102 and the first substrate 101 can be made larger, and the distance between the first metal layer 102 and the metal oxide semiconductor layer 103 can be made smaller with respect to the first gate metal layer N11. Furthermore, the number of film layers between the metal oxide semiconductor layer 103 and the first metal layer 102 can be reduced, that is, the number of film layers of the at least one first insulating layer 104 can be reduced, and the difficulty of opening the first via hole H1 can be reduced.

[0066] In a second aspect, Embodiment II of the present application provides a display device. The display device includes a housing and the display panel 01 described in any one of the above. Wherein, the housing has an accommodation space, and the display panel 01 is disposed in the accommodation space.

[0067] Embodiment III

[0068] Figure 9 It is a schematic diagram of the film layer structures of the first substrate and the second substrate provided by Embodiment III of the present application. Refer to Figure 9As shown, in a first aspect, Embodiment 3 of the present application provides a display panel 01. The display panel 01 has a display area AA. The display panel 01 includes a first substrate 10. The first substrate 10 in the display area AA includes a first substrate 101, a first metal layer 102, and a metal oxide semiconductor layer 103. Among them, the first metal layer 102 is disposed on one side of the first substrate 101, and the first metal layer 102 includes a plurality of data lines 1021 arranged at intervals in sequence; the metal oxide semiconductor layer 103 is disposed on the side of the first metal layer 102 away from the first substrate 101, and the metal oxide semiconductor layer 103 includes a plurality of transparent active layers 1031. The transparent active layer 1031 includes a channel 1032 and source regions 1033 and drain regions 1034 located on both sides of the channel 1032. The source region 1033 is electrically connected to the data line 1021 through a via. Among them, the positive projections of the channel 1032, the source region 1033, and the drain region 1034 on the first substrate 101 all overlap with the positive projection of the data line 1021 on the first substrate 101.

[0069] It should be noted that the structure of the display panel 01 provided in Embodiment 3 of the present application is similar to the structure of the display panel 01 provided in Embodiment 1 of the present application, and the same parts in Embodiment 3 of the present application will not be described in detail.

[0070] In some embodiments of the present application, the first substrate 10 in the display area AA further includes: at least one first insulating layer 104 disposed between the first metal layer 102 and the metal oxide semiconductor layer 103; a second metal layer 105 disposed on the side of the metal oxide semiconductor layer 103 away from the first substrate 101; at least one second insulating layer 106 disposed between the metal oxide semiconductor layer 103 and the second metal layer 105. Among them, the second metal layer 105 includes a plurality of bridging portions 1051. The bridging portions 1051 are electrically connected to the source regions 1033 through second vias H2 penetrating through the at least one second insulating layer 106, and the bridging portions 1051 are electrically connected to the data lines 1021 through third vias H3 penetrating through the at least one second insulating layer 106 and the at least one first insulating layer 104.

[0071] In the display panel 01 provided in the embodiments of the present application, the arrangement of the bridging portions 1051 can effectively reduce the resistance of the data lines 1021 and improve the transmission efficiency of data signals.

[0072] In some embodiments of the present application, the display panel 01 further has a non-display area NAA. The first substrate 10 of the non-display area NAA includes: a first gate metal layer N11, which includes a plurality of first gates N111. The first gates N111 are used as the gates of the low-temperature polysilicon thin-film transistors disposed in the non-display area NAA. Among them, the first gate metal layer N11 and the first metal layer 102 are disposed on the same layer and have the same material. The at least one first insulating layer 104 includes a first interlayer dielectric layer M3, a second interlayer dielectric layer M4, and a second gate insulating layer M5. The at least one second insulating layer 106 includes a third gate insulating layer M6 and a third interlayer dielectric layer M7. The second via hole H2 penetrates through the third gate insulating layer M6 and the third interlayer dielectric layer M7. The third via hole H3 penetrates through the third gate insulating layer M6, the third interlayer dielectric layer M7, the second gate insulating layer M5, the second interlayer dielectric layer M4, and the first interlayer dielectric layer M3.

[0073] In a second aspect, Embodiment III of the present application provides a display device. The display device includes a housing and the display panel 01 described in any one of the above. Among them, the housing has an accommodating space, and the display panel 01 is disposed in the accommodating space.

[0074] Embodiment IV

[0075] Figure 10 is a schematic diagram of the film layer structures of the first substrate and the second substrate provided in Embodiment III of the present application. Refer to Figure 10 As shown, in a first aspect, Embodiment III of the present application provides a display panel 01. The display panel 01 has a display area AA. The display panel 01 includes a first substrate 10. The first substrate 10 of the display area AA includes a first substrate 101, a first metal layer 102, and a metal oxide semiconductor layer 103. Among them, the first metal layer 102 is disposed on one side of the first substrate 101. The first metal layer 102 includes a plurality of data lines 1021 disposed at intervals in sequence. The metal oxide semiconductor layer 103 is disposed on the side of the first metal layer 102 away from the first substrate 101. The metal oxide semiconductor layer 103 includes a plurality of transparent active layers 1031. The transparent active layer 1031 includes a channel 1032 and source regions 1033 and drain regions 1034 located on both sides of the channel 1032. The source regions 1033 are electrically connected to the data lines 1021 through vias. Among them, the orthogonal projections of the channel 1032, the source regions 1033, and the drain regions 1034 on the first substrate 101 all overlap with the orthogonal projection of the data lines 1021 on the first substrate 101.

[0076] It should be noted that the structure of the display panel 01 provided in the fourth embodiment of the present application is similar to that of the display panel 01 provided in the third embodiment of the present application, and the same parts will not be described in detail in the fourth embodiment of the present application.

[0077] In some embodiments of the present application, the first metal layer 102 is disposed on a side of the first interlayer dielectric layer M3 away from the first gate metal layer N11. The first substrate 10 of the display area AA further includes: at least one first insulating layer 104 disposed between the first metal layer 102 and the metal oxide semiconductor layer 103; a second metal layer 105 disposed on a side of the metal oxide semiconductor layer 103 away from the first substrate 101; at least one second insulating layer 106 disposed between the metal oxide semiconductor layer 103 and the second metal layer 105. Wherein, the second metal layer 105 includes a plurality of bridging portions 1051. The bridging portions 1051 are electrically connected to the source regions 1033 through second vias H2 penetrating through the at least one second insulating layer 106, and the bridging portions 1051 are electrically connected to the data lines 1021 through third vias H3 penetrating through the at least one second insulating layer 106 and the at least one first insulating layer 104.

[0078] In the display panel 01 provided in the embodiment of the present application, since the first metal layer 102 is disposed on a side of the first interlayer dielectric layer M3 away from the first gate metal layer N11, therefore, the distance between the first metal layer 102 and the first substrate 101 can be made larger and the distance between the first metal layer 102 and the metal oxide semiconductor layer 103 can be made smaller with respect to the first gate metal layer N11. Furthermore, the number of film layers between the metal oxide semiconductor layer 103 and the first metal layer 102 can be reduced, that is, the number of film layers of the at least one first insulating layer 104 can be reduced, and thus the difficulty of forming the third via H3 can be reduced.

[0079] In a second aspect, the fourth embodiment of the present application provides a display device. The display device includes a housing and the display panel 01 described in any one of the above. Wherein, the housing has an accommodation space, and the display panel 01 is disposed in the accommodation space.

[0080] In summary, the embodiment of the present application provides a display panel and a display device. The display panel has a display area. The display panel includes a first substrate. The first substrate of the display area includes a first substrate, a first metal layer, and a metal oxide semiconductor layer. Among them, the first metal layer is disposed on one side of the first substrate, and the first metal layer includes a plurality of data lines arranged at intervals; the metal oxide semiconductor layer is disposed on the side of the first metal layer away from the first substrate, and the metal oxide semiconductor layer includes a plurality of transparent active layers. The transparent active layer includes a channel and source regions and drain regions located on both sides of the channel. The source region is electrically connected to the data line through a via hole; among them, the positive projections of the channel, the source region, and the drain region on the first substrate all overlap with the positive projection of the data line on the first substrate. In the display panel provided by the embodiment of the present application, since the positive projections of the channel, the source region, and the drain region in the transparent active layer on the first substrate all overlap with the positive projection of the data line on the first substrate, therefore, the overlapping area between the transparent active layer and the data line can be increased to form the transparent active layer in the area above the data line as much as possible, thereby reducing the area of the transparent active layer in the area between two adjacent data lines, reducing the width occupied by the transparent active layer in the arrangement direction of the data lines, and minimizing or eliminating as much as possible the portion of the transparent active layer that is inclined relative to the data line. Furthermore, when the pitch between two adjacent data lines is reduced and the resolution of the display panel is improved, the minimum pitch between two adjacent transparent active layers can be increased as much as possible, thereby improving the production yield of the display panel.

[0081] The above has introduced in detail a display panel and a display device provided by the embodiment of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A display panel, characterized in that, The display panel has a display area, and the display panel includes a first substrate. The first substrate of the display area includes: a first substrate; A first metal layer is disposed on one side of the first substrate, and the first metal layer includes a plurality of data lines that are sequentially spaced apart; A metal oxide semiconductor layer, disposed on a side of the first metal layer away from the first substrate, the metal oxide semiconductor layer comprising a plurality of transparent active layers, the transparent active layers comprising a channel and a source region and a drain region located on both sides of the channel, the source region being connected to the data line through a via hole; The orthographic projections of the channel, the source region, and the drain region on the first substrate all overlap with the orthographic projection of the data line on the first substrate.

2. The display panel according to claim 1, characterized in that, The first substrate of the display area further comprises: at least one first insulating layer disposed between the first metal layer and the metal oxide semiconductor layer; Wherein, the source region is connected to the data line through a first via hole penetrating the at least one first insulating layer.

3. The display panel according to claim 1, characterized in that, The first substrate of the display area further comprises: at least one first insulating layer disposed between the first metal layer and the metal oxide semiconductor layer; A second metal layer is disposed on a side of the metal oxide semiconductor layer away from the first substrate; at least one second insulating layer disposed between the metal oxide semiconductor layer and the second metal layer; The second metal layer includes a plurality of bridge portions, the bridge portions are connected to the source region through second via holes penetrating the at least one second insulating layer, and the bridge portions are connected to the data lines through third via holes penetrating the at least one second insulating layer and the at least one first insulating layer.

4. The display panel according to claim 2 or 3, characterized in that, The display panel further has a non-display area, and the first substrate of the non-display area includes: A first gate metal layer, comprising a plurality of first gates, wherein the first gates are used as gates of low-temperature polysilicon thin film transistors disposed in the non-display area; Wherein, the first gate metal layer is arranged at the same layer as the first metal layer and is made of the same material.

5. The display panel according to claim 1, characterized in that, The first substrate of the display area further comprises: A first transparent conductive layer is arranged on a side of the metal oxide semiconductor layer away from the first substrate, the first transparent conductive layer comprises a plurality of first transparent conductive portions, the first transparent conductive portions comprise a first portion and a second portion, and the first portion is connected to the drain region through a via hole; a second transparent conductive layer, disposed on a side of the first transparent conductive layer away from the first substrate, the second transparent conductive layer comprising a plurality of second transparent conductive portions, the second transparent conductive portions being connected to the second portion through vias; The second portion is located between two adjacent data lines, and the distances between the second portion and the two adjacent data lines are different.

6. The display panel according to claim 5, characterized in that, The first transparent conductive portion further includes a connecting portion connecting the first portion and the second portion, the connecting portion is inclined relative to the data line, and an angle between the connecting portion and the data line is an acute angle, and the angle is less than or equal to 20°.

7. The display panel according to claim 5, characterized in that, The first substrate of the display area further comprises: A first light-shielding layer is disposed between the first transparent conductive layer and the second transparent conductive layer. The first light-shielding layer includes a plurality of first light-shielding portions. Each first light-shielding portion includes a first sub-light-shielding portion, a second sub-light-shielding portion, and an avoidance portion. The first sub-light-shielding portion is correspondingly disposed with the source region, the second sub-light-shielding portion is correspondingly disposed with the drain region, and the avoidance portion connects the first sub-light-shielding portion and the second sub-light-shielding portion; Wherein, a notch is formed on one side of the avoidance portion close to the second portion.

8. The display panel according to claim 7, characterized in that, The display panel further includes a second substrate and a liquid crystal layer. The second substrate is disposed opposite to the first substrate, and the liquid crystal layer is disposed between the first substrate and the second substrate. Wherein, the second substrate includes: A second substrate; A second light-shielding layer disposed on one side of the second substrate; Wherein, the second light-shielding organic layer includes a plurality of second light-shielding portions, and the extending direction of the second light-shielding portions is different from that of the first light-shielding portions.

9. The display panel according to claim 7, characterized in that, The first substrate of the display area further includes: A color filter layer disposed between the first transparent conductive layer and the first light-shielding layer. The color filter layer includes a plurality of color filter units, and each color filter unit includes a first filter unit, a second filter unit, and a third filter unit. Wherein, two adjacent first filter units are spaced apart, two adjacent second filter units are spaced apart, and two adjacent third filter units are spaced apart.

10. A display device, characterized in that, The display device includes a housing and the display panel according to any one of claims 1-9. Wherein, the housing has an accommodation space, and the display panel is disposed in the accommodation space.

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