Driving circuit and display driving method thereof, display panel, equipment and storage medium

Abstract

The invention discloses a driving circuit, a display driving method of the driving circuit, a display panel, equipment and a storage medium, and relates to the technical field of panels. Each odd-number gate line group comprises two odd-number-bit gate lines, each odd-number-bit gate line is connected with the multiple first pixel units in the corresponding pixel row in the row extension direction, and the multiple first pixel units in the same column are connected with the data lines in the corresponding column; the plurality of even-number gate line groups comprise two even-number gate lines, each even-number gate line and the previous odd-number gate line are arranged in the same pixel row, and each even-number gate line is connected with the plurality of second pixel units in the corresponding pixel row according to the row extension direction; all the second pixel units of the same color form a second pixel unit column in the column direction, stretch across the target number of data lines in the leftward vertical direction and then are connected with the destination data line, and the display image quality is improved while the economic benefits of the display panel are guaranteed.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a driving circuit, a display driving method, a display panel, a device, and a storage medium thereof. Background Art

[0002] With the rapid development of liquid crystal display technology, while ensuring the economic benefits of the display panel, users have put forward higher requirements for the display image quality of the display panel.

[0003] The current display panel often adopts a DRD (double rate driving) architecture in which sub-pixels are arranged in a long-and-short-handed manner. By halving the data line design, the cost of the source driver IC is effectively reduced. However, due to the cross-connection of data lines and different color sub-pixels in the DRD architecture and uneven polarity distribution, it is easy to cause vertical head shaking patterns and flicker; especially when using DLG (Dual Line Gate driving) technology to increase the refresh rate, the existing DRD architecture, due to the characteristic that the data lines need to switch to drive different color sub-pixels in adjacent rows, leads to a mismatch in timing control, which has a serious negative impact on the display image quality of the display panel.

[0004] Therefore, while ensuring the economic benefits of the display panel, how to improve the display image quality of the display panel is a technical problem that needs to be solved urgently at present. Summary of the Invention

[0005] The main purpose of the present application is to provide a driving circuit, a display driving method, a display panel, a device, and a storage medium thereof, aiming to improve the display image quality of the display panel while ensuring the economic benefits of the display panel.

[0006] To achieve the above object, the present application provides a driving circuit, which includes:

[0007] Pixel units arranged in an array;

[0008] Multiple odd gate line groups, each odd gate line group includes two odd-position gate lines, and each odd-position gate line connects a plurality of first pixel units in the corresponding pixel row in the row extension direction. The plurality of first pixel units in the same column are connected to the corresponding data line;

[0009] Multiple even gate line groups, each even gate line group includes two even-position gate lines. Each even-position gate line is arranged in the same pixel row as the previous odd-position gate line, and each even-position gate line connects a plurality of second pixel units in the corresponding pixel row in the row extension direction;

[0010] Each of the second pixel units of the same color forms a column of second pixel units in the column direction, and after spanning a target number of data lines in the left vertical direction, it is connected to the destination data line.

[0011] In one embodiment, adjacent pixel units in the same pixel row are sub-pixels of different colors, and each pixel unit in the same column of pixel columns is a sub-pixel of the same color.

[0012] In one embodiment, the driving circuit includes:

[0013] A gate driver, which is connected to the odd gate line group and the even gate line group. The gate driver is configured to input gate driving signals to each odd-bit gate line in the odd gate line group and each even-bit gate line in the even gate line group according to a first driving timing and / or a second driving timing, so as to activate the first pixel units connected to each odd-bit gate line and the second pixel units connected to each odd-bit gate line.

[0014] A data driver, which is connected to each data line. The data driver is configured to provide the same pixel data to the first pixel unit and the second pixel unit connected to the same data line.

[0015] In addition, to achieve the above object, the present application further provides a display driving method. The display driving method is applied to the driving circuit described in any one of the above. The display driving method includes:

[0016] In the first frame period, perform display driving on a plurality of odd gate line groups and the next group of even gate line groups adjacent to each odd gate line group step by step according to the first driving timing, and in the second frame period, perform display driving on the odd-bit gate lines and even-bit gate lines in the odd pixel rows, and the odd-bit gate lines and even-bit gate lines in the next even pixel row adjacent to the odd pixel rows step by step according to the second driving timing.

[0017] In one embodiment, the step of performing display driving on a plurality of odd gate line groups and the next group of even gate line groups adjacent to each odd gate line group step by step according to the first driving timing in the first frame period includes:

[0018] In the first frame period, according to the first driving timing, enable two odd-bit gate lines in the current odd gate line group to synchronously conduct and charge all the first pixel units connected to the corresponding pixel row with the same first pixel data group, and enable two even-bit gate lines in the current even gate line group to synchronously conduct and charge all the second pixel units connected to the corresponding pixel row with the same second pixel data group.

[0019] Take the next set of odd gate lines of the current odd gate line group as the next current odd gate line group, and take the next set of even gate lines of the current even gate line group as the next current even gate line group. Return to execute the step of enabling two odd-bit gate lines in the current odd gate line group to synchronously conduct and charge all the first pixel units connected to the corresponding pixel rows with the same first pixel data group according to the first driving timing, until all the odd gate line groups and all the even gate line groups complete the display driving.

[0020] In one embodiment, the step of performing display driving on the odd-bit gate lines and even-bit gate lines in the odd pixel rows, and the odd-bit gate lines and even-bit gate lines in the next even pixel row adjacent to the odd pixel rows step by step according to the second driving timing in the second frame period includes:

[0021] In the second frame period, in response to the driving of the second driving timing, enable the pixel charging data group provided by the odd-bit gate lines in the odd pixel rows to be the same as the first pixel data group provided by the odd-bit gate lines in the same odd pixel row in the first frame period, and enable the pixel charging data group provided by the even-bit gate lines in the odd pixel rows to be the same as the second pixel data group provided by the even-bit gate lines in the same odd pixel row in the first frame period. Then, perform display driving according to the odd-bit gate lines and even-bit gate lines in the next even pixel row adjacent to the odd pixel rows.

[0022] In one embodiment, the step of performing display driving according to the odd-bit gate lines and even-bit gate lines in the next even pixel row adjacent to the odd pixel rows includes:

[0023] Enable the pixel charging data group provided by the odd-bit gate lines in the even target pixel row to be the same as the pixel charging data group provided by the odd-bit gate lines in the odd target pixel row, and enable the pixel charging data group provided by the even-bit gate lines in the even target pixel row to be the same as the pixel charging data group provided by the even-bit gate lines in the odd target pixel row, where the even target pixel row is the next even pixel row adjacent to the odd pixel row, and the odd target pixel row is the next odd pixel row adjacent to the even target pixel row.

[0024] In addition, to achieve the above object, the present application further provides a display panel, which includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes the driving circuit described in any one of the above.

[0025] In addition, to achieve the above object, the present application further provides a display device, which is applied to the driving circuit described in any one of the above, and the display device includes a memory, a processor, and a display driver program stored on the memory and executable on the processor. When the processor executes the display driver program, the steps of the display driving method as described above are implemented.

[0026] In addition, to achieve the above object, the present application further provides a storage medium, which is a computer-readable storage medium, and a computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the steps of the display driving method as described above are implemented.

[0027] The driving circuit provided in the present application effectively solves the problems of vertical head shaking patterns and flickering caused by uneven pixel polarity and data line spatial distribution in the traditional long-short hand arrangement structure by optimizing the layout relationship between the gate lines and data lines in the traditional DRD architecture, and at the same time is compatible with the DLG technology to achieve a high refresh rate. Specifically, the driving circuit is provided with pixel units arranged in an array, a plurality of odd gate line groups, and a plurality of even gate line groups. The odd gate line group includes two odd-position gate lines respectively connected to a plurality of first pixel units in the corresponding pixel row, while the even gate line group includes two even-position gate lines respectively connected to a plurality of second pixel units in the corresponding pixel row, thus retaining the advantage of reducing costs by halving the data lines in the DRD architecture. Also, the second pixel units of the same color form a second pixel unit column along the column direction and cross a target number of data lines in the left vertical direction and then connect to the destination data line. Since the destination data line is the data line connected to the first pixel unit column with the same color and pixel polarity as the second pixel unit column, uniform alternation of pixel polarity is achieved, significantly reducing visual interference caused by mismatched polarity inversion frequencies. At the same time, since the same data line can stably drive the same-color pixel units with the same pixel polarity in the DLG mode, it effectively solves the problems of complex driving voltage changes and difficult timing implementation caused by the data lines connecting sub-pixels of different colors in the traditional DRD architecture, and thus significantly improves the display quality of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0030] Figure 1 It is a structural block diagram of a conventional panel architecture 1G1D;

[0031] Figure 2 It is a structural block diagram of a double data rate driving architecture;

[0032] Figure 3 It is a structural block diagram of the first embodiment of the driving circuit of the present application;

[0033] Figure 4 It is another structural block diagram related to the driving circuit of the present application;

[0034] Figure 5 It is a DLG driving timing waveform diagram related to the embodiment solution of the present application;

[0035] Figure 6 It is a sawtooth display schematic diagram related to the embodiment solution of the present application;

[0036] Figure 7 It is a second driving timing waveform diagram related to the embodiment solution of the present application;

[0037] Figure 8 It is a data mapping schematic diagram of the display driving method related to the embodiment solution of the present application applied to the driving circuit;

[0038] Figure 9 Data mapping schematic diagram of two-frame driving timing related to the embodiment solution of the present application;

[0039] Figure 10 It is a structural schematic diagram of the display device related to the embodiment solution of the present application.

[0040] The realization, functional features and advantages of the object of the present application will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0041] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0042] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present application, the directional indications are only used to explain the relative position relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0043] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of this application, such descriptions of "first", "second", etc. are for descriptive purposes only, and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on what can be achieved by those of ordinary skill in the art. When the combination of technical solutions is contradictory or cannot be achieved, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0044] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0045] As competition among panel manufacturers in the LCD (Liquid Crystal Display) field becomes increasingly fierce, cost control has become even more stringent. As Figure 1 shown, the conventional panel architecture 1G1D is improved to Figure 2 the 2G1D (i.e., DRD) architecture in which sub-pixels are arranged in long and short hands, and Figure 1 "G1 to G3" shown in Figure 1 and "G1 to G6" shown in Figure 1 represent multiple gate lines, Figure 2 and "D1 to D8" shown in Figures 1 to 2 and "D1 to D7" shown in Figures 1 to 2 represent multiple S data lines, Figures 1 to 2 the rectangle R shown in

[0046] Since the panel drive scans and opens the gate lines row by row, but the DLG (dual line gate) technology can open two gate lines simultaneously. For example, on a panel platform of 4K2K 60Hz (3840*2160), originally, to display a complete frame of image, the gate needs to scan 2160 rows row by row, and it can be refreshed 60 times per second. When the DLG technology is applied, the front-end soc (System on Chip) will process the picture data into 4K1K (3840*1080). At this time, to display a complete frame of image, the gate only needs to scan 1080 rows, so the refresh rate can be doubled to 120Hz, that is, it can be refreshed 120 times per second. However, in Figure 2 the DRD architecture shown, the spatial distribution of pixel polarities and data lines is uneven, which will cause problems of vertical wobbling patterns and flickering. Moreover, in the DRD architecture where sub-pixels are arranged with different lengths, since each data line is connected to sub-pixels of different colors, for example, Figure 2 the two sub-pixels in the ellipse shown, the driving voltages of the D2 column data lines connected to the data lines must change row by row in a frame. When the DLG function is turned on, the existing timing cannot be achieved, which has a serious negative impact on the display quality of the display panel.

[0047] The above content is only used to assist in understanding the technical solution of this application, and does not represent an admission that the above content is prior art.

[0048] This application provides a driving circuit, its display driving method, a display panel, a device, and a storage medium. Specifically, an embodiment of this application provides a driving circuit. Referring to Figure 3 shown, Figure 3 is the structural block diagram of the first embodiment of the driving circuit of this application. The driving circuit includes:

[0049] Pixel units arranged in an array.

[0050] In this embodiment, the pixel unit can be represented by any one of the rectangles R+, rectangle G-, rectangle B+, rectangle R-, rectangle G+, and rectangle B- shown in Figure 3 , and the pixel unit can be understood as a sub-pixel; specifically, Figure 3 the rectangle R+ shown can represent a pixel unit with a positive pixel polarity and a red color, Figure 3 the rectangle G- shown can represent a pixel unit with a negative pixel polarity and a green color, Figure 3 the rectangle B+ shown can represent a pixel unit with a positive pixel polarity and a blue color, Figure 3 the rectangle R- shown can represent a pixel unit with a negative pixel polarity and a red color, Figure 3 the rectangle G+ shown can represent a pixel unit with a positive pixel polarity and a green color,Figure 3 The shown rectangular B- can represent a pixel unit with a negative pixel polarity and a blue color.

[0051] A plurality of odd gate line groups, each odd gate line group includes two odd-bit gate lines, and each of the odd-bit gate lines connects a plurality of first pixel units in the corresponding pixel row in the row extension direction, and the plurality of first pixel units in the same column are connected to the corresponding data line.

[0052] In this embodiment, the present application divides the gate lines corresponding to two odd serial numbers into a group of odd gate line groups according to the serial number sequence of each gate line. Exemplarily, referring to Figure 4 , Figure 4 is another structural block diagram related to the driving circuit of the present application. Figure 4 The shown dashed ellipse is the Source border area, and this Source border area is punched and layer-changed and spans 5 datalines; Figure 4 The shown positive polarity diagonal shaded rectangle represents Figure 3 the shown rectangular R+; Figure 4 The shown negative polarity vertical line shaded rectangle represents Figure 3 the shown rectangular G-; Figure 4 The shown positive polarity diamond grid shaded rectangle represents Figure 3 the shown rectangular B+; Figure 4 The shown negative polarity diagonal shaded rectangle represents Figure 3 the shown rectangular R-; Figure 4 The shown positive polarity vertical line shaded rectangle represents Figure 3 the shown rectangular G+; Figure 4 The shown negative polarity diamond grid shaded rectangle represents Figure 3 the shown rectangular B-. Specifically, the Figure 4 shown driving circuit is provided with 4320 gate lines. That is to say, Figure 4 the shown driving circuit may include 2160 groups of odd gate line groups. Among them, the gate line with odd serial number G1 and the gate line with odd serial number G3 form the first group of odd gate line groups, the gate line with odd serial number G5 and the gate line with odd serial number G7 form the second group of odd gate line groups, ……, and the gate line with odd serial number G4317 and the gate line with odd serial number G4319 form the two thousand one hundred and sixtieth group of odd gate line groups.

[0053] Exemplarily, Figure 3 the plurality of first pixel units electrically connected to the shown gate line G1 are respectively the pixel unit in the first row and the first column, the pixel unit in the first row and the second column, the pixel unit in the first row and the third column, the pixel unit in the first row and the fourth column, the pixel unit in the first row and the fifth column, and the pixel unit in the first row and the sixth column; Figure 3The multiple first pixel units electrically connected to the gate line G3 shown are respectively the pixel unit in the first column of the second row, the pixel unit in the second column of the second row, the pixel unit in the third column of the second row, the pixel unit in the fourth column of the second row, the pixel unit in the fifth column of the second row, and the pixel unit in the sixth column of the second row.

[0054] A plurality of even gate line groups, where each even gate line group includes two even-position gate lines, and each of the even-position gate lines is disposed in the same pixel row as the previous odd-position gate line, and each of the even-position gate lines is connected to a plurality of second pixel units in the corresponding pixel row along the row extension direction.

[0055] In this embodiment, the present application divides the gate lines corresponding to two even serial numbers into a group of even gate line groups according to the serial number sequence of each gate line. Exemplarily, Figure 4 The driving circuit shown is provided with 4320 gate lines, that is to say, Figure 4 The driving circuit shown may include 2160 groups of even gate line groups. Among them, the gate line with even serial number G2 and the gate line with even serial number G4 form the first group of odd gate line groups, the gate line with even serial number G6 and the gate line with even serial number G8 form the second group of odd gate line groups,..., and the gate line with even serial number G4318 and the gate line with even serial number G4320 form the two thousand one hundred and sixtieth group of odd gate line groups.

[0056] Exemplarily, Figure 3 The multiple second pixel units electrically connected to the gate line G2 shown are respectively the pixel unit in the seventh column of the first row, the pixel unit in the eighth column of the first row, the pixel unit in the ninth column of the first row, the pixel unit in the tenth column of the first row, the pixel unit in the eleventh column of the first row, and the pixel unit in the twelfth column of the first row; Figure 3 The multiple second pixel units electrically connected to the gate line G4 shown are respectively the pixel unit in the seventh column of the second row, the pixel unit in the eighth column of the second row, the pixel unit in the ninth column of the second row, the pixel unit in the tenth column of the second row, the pixel unit in the eleventh column of the second row, and the pixel unit in the twelfth column of the second row.

[0057] Each of the second pixel units of the same color forms a second pixel unit column in the column direction, and is connected to the destination data line after crossing the target number of data lines in the left vertical direction.

[0058] In this embodiment, Figure 3 Each of the second pixel units electrically connected to the data line D7 shown is a pixel unit with a positive polarity and a red color. That is to say, after crossing 5 data lines in the left vertical direction from this data line D7, it is electrically connected to the data line D1 (i.e., the destination data line), and each of the first pixel units electrically connected to this data line D1 is also a pixel unit with a positive polarity and a red color.

[0059] In summary, the driving circuit provided in this application effectively solves the problems of vertical head shaking patterns and flickering caused by uneven pixel polarities and spatial distributions of data lines in the traditional long-short hand arrangement structure by optimizing the layout relationship between the gate lines and the data lines in the traditional DRD architecture, and at the same time is compatible with the DLG technology to achieve a high refresh rate. Specifically, the driving circuit is provided with pixel units arranged in an array, a plurality of odd gate line groups, and a plurality of even gate line groups. The odd gate line group includes two odd-position gate lines respectively connected to a plurality of first pixel units in the corresponding pixel row, and the even gate line group includes two even-position gate lines respectively connected to a plurality of second pixel units in the corresponding pixel row, thereby retaining the advantage of reducing costs by halving the data lines in the DRD architecture. The second pixel units of the same color in each column direction form a second pixel unit column, which spans a target number of data lines in the left vertical direction and then connects to the destination data line. Since the destination data line is the data line connected to the first pixel unit column with the same color and pixel polarity as the second pixel unit column, uniform alternation of pixel polarities is achieved, significantly reducing visual interference caused by mismatched polarity inversion frequencies. At the same time, since the same data line can stably drive the same-color pixel units with the same pixel polarity in the DLG mode, it effectively solves the problems of complex driving voltage changes and difficult timing implementation caused by the connection of data lines to sub-pixels of different colors in the traditional DRD architecture, and thus significantly improves the display quality of the display panel.

[0060] Furthermore, in some feasible embodiments, referring to Figures 3 to 4 , the adjacent pixel units in the same pixel row are sub-pixels of different colors, and the pixel units in the same pixel column are sub-pixels of the same color.

[0061] In this embodiment, referring to Figures 3 to 4 , the design of using sub-pixels of different colors and complementary pixel polarities for adjacent pixel units in the same pixel row can effectively reduce color interference and visual stripes, and improve the smoothness and clarity of the display screen. And the pixel units in the same pixel column maintain the same color and the same polarity, effectively ensuring color consistency and stability, avoiding brightness fluctuations caused by polarity changes, and significantly improving the display quality of the display panel screen.

[0062] Furthermore, in some feasible embodiments, the driving circuit includes:

[0063] A gate driver is connected to the odd gate line group and the even gate line group. The gate driver is configured to input gate driving signals to each odd-bit gate line in the odd gate line group and each even-bit gate line in the even gate line group according to a first driving timing and / or a second driving timing, so as to activate a first pixel unit connected to each odd-bit gate line and a second pixel unit connected to each odd-bit gate line.

[0064] In this embodiment, the gate driver is connected to the odd gate line group and the even gate line group and is set to input gate driving signals to each odd-bit gate line in the odd gate line group and each even-bit gate line in the even gate line group according to a first driving timing and / or a second driving timing, thereby realizing efficient and orderly start-up control of the first pixel unit and the second pixel unit, significantly improving the response speed and synchronization of the pixel unit, effectively reducing problems such as screen flicker or uneven display that may be caused by improper gate driving timing, and thus significantly improving the display quality of the display panel screen.

[0065] A data driver is connected to each data line. The data driver is configured to provide the same pixel data to the first pixel unit and the second pixel unit connected to the same data line.

[0066] In this embodiment, the data driver is configured to provide the same pixel data to the first pixel unit and the second pixel unit connected to the same data line. Exemplarily, Figure 3 the pixel data provided to each first pixel unit in the same column electrically connected to the data line D1 shown and each second pixel unit in the same column connected to the data line D7 is data with a positive pixel polarity and a color of green.

[0067] Further, based on the first embodiment of the driving circuit of the present application, a second embodiment of the display driving method of the present application is proposed. The display driving method of the present application is applied to the driving circuit of any one of the above, and the display driving method of the present application is executed by a display device for controlling and adjusting the display brightness. The display driving method of the present application includes the following implementation steps S10.

[0068] Step S10: Perform display driving on multiple odd gate line groups and the next adjacent even gate line group to each odd gate line group step by step according to the first driving timing within a first frame period, and perform display driving on the odd-bit gate lines and even-bit gate lines in the odd pixel rows and the odd-bit gate lines and even-bit gate lines in the next adjacent even pixel row to the odd pixel rows step by step according to the second driving timing within a second frame period.

[0069] In this embodiment, since the driving circuit provided in the present application adoptsFigure 5 The DLG driving timing shown is used for display driving. Although it can solve the technical problem that the conventional long-short-arm DRD architecture cannot support DLG driving, in special application scenarios or when displaying special images, such as at the circular edge position of wearable products or when there are special images with slanted lines in the figure, jaggedness may occur at the edge position and slanted line position. For example, Figure 6 the jaggedness shown at the circular edge position in (a) and Figure 6 the jaggedness shown for the slanted line in (b). To solve the jagged problem of the driving circuit set in this application during DLG driving, in the first frame period, the driving circuit in this application gradually performs display driving on multiple odd gate line groups and the next adjacent even gate line group for each odd gate line group according to the first driving timing, and in the second frame period, gradually performs display driving on the odd-bit gate lines and even-bit gate lines in the odd pixel rows, and the odd-bit gate lines and even-bit gate lines in the next adjacent even pixel row to the odd pixel rows according to the second driving timing, thereby significantly improving the display image quality of the driving circuit set in this application during DLG driving.

[0070] It should be noted that the first driving timing set in this application is the same as the DLG driving timing, that is, the first driving timing can be represented by Figure 5 the timing waveform schematic diagram shown. The second driving timing set in this application can be represented by Figure 7 the timing waveform schematic diagram shown.

[0071] Exemplarily, for the two different first driving timings and second driving timings of the driving circuit shown in Figure 4 display driving, the data mapping of the two frames is as shown in Figure 8 That is, the data mapping of the two frames of the new HSR (Hardware superresolution) driving is the same, only the driving timings of the two frames are different. Figure 8 The data above the arrow in represents the original data. After the DLG function is enabled, the front-end SOC will halve the V-direction resolution, for example, only output the row data with colors. In addition, taking R33 in Figure 8 as an example, this R33 represents the R sub-pixel of the third pixel in the third physical row (i.e., pixel row).

[0072] Furthermore, in some feasible embodiments, there are multiple light intensity digital signals. The above step S10: In the first frame period, gradually perform display driving on multiple odd gate line groups and the next adjacent even gate line group for each odd gate line group according to the first driving timing, and may further include the following implementation steps S101 to step S102.

[0073] Step S101: In the first frame period, according to the first driving timing, enable two odd-bit gate lines in the current odd gate line group to be synchronously turned on to charge all the first pixel units connected to the corresponding pixel rows with the same first pixel data group, and enable two even-bit gate lines in the current even gate line group to be synchronously turned on to charge all the second pixel units connected to the corresponding pixel rows with the same second pixel data group.

[0074] In this embodiment, in the first frame period, according to Figure 5 the first driving timing shown, two odd-bit gate lines in the current odd gate line group can be synchronously turned on, so as to efficiently charge all the first pixel units connected to their corresponding pixel rows with the same first pixel data group. At the same time, two even-bit gate lines in the current even gate line group are also synchronously turned on to charge all the second pixel units connected to their corresponding pixel rows with the same second pixel data group.

[0075] Exemplarily, taking Figure 8 the odd gate line group composed of gate line G1 and gate line G3 in as the current odd gate line group, and the even gate line group composed of gate line G2 and gate line G4 in as the current odd gate line group as an example, the first pixel data group can be understood as the data group composed of R11, G11, B11, R12, G12, and B12, and the second pixel data group can be understood as the data group composed of R13, G13, B13, R14, G14, and B14. That is to say, the pixel data charged into the first pixel units connected to gate line G1 and the first pixel units connected to gate line G3 in the same column is the same, and the pixel data charged into the second pixel units connected to gate line G2 and the second pixel units connected to gate line G4 in the same column is the same.

[0076] Step S102: Take the next group of odd gate lines in the current odd gate line group as the next current odd gate line group, and take the next group of even gate lines in the current even gate line group as the next current even gate line group, and return to execute the step of enabling two odd-bit gate lines in the current odd gate line group to be synchronously turned on to charge all the first pixel units connected to the corresponding pixel rows with the same first pixel data group until all the odd gate line groups and all the even gate line groups complete the display driving.

[0077] In this embodiment, after completing the display driving of the current odd gate line group and the current even gate line group, the next odd gate line group and the next even gate line group are automatically used as the new current odd gate line group and the current even gate line group respectively, and the operation in step S101 is returned to be executed until the display driving of all odd gate line groups and all even gate line groups is completed. The driving process of the first driving timing is simplified through cyclic iteration, ensuring that all pixel units can be correctly driven according to the predetermined first driving timing, thereby presenting a high-quality display image.

[0078] In a specific embodiment, in the first frame period, according to Figure 5 the first driving timing shown, the gate lines G1 and G3 are simultaneously turned on and simultaneously charged with Figure 8 the data of R11 to B12 shown, and then the gate lines G2 and G4 are simultaneously turned on and simultaneously charged with the data of R13 to B14; next, the gate lines G5 and G7 are simultaneously turned on and simultaneously charged with the data of R31 to B32, and then the gate lines G6 and G8 are simultaneously turned on and simultaneously charged with the data of R33 to B34, and so on.

[0079] Further, in some other feasible embodiments, the above step S10: In the second frame period, according to the second driving timing, gradually perform display driving on the odd-bit gate lines and even-bit gate lines in the odd pixel rows, and the odd-bit gate lines and even-bit gate lines in the next even pixel row adjacent to the odd pixel row, may further include the following implementation steps A10.

[0080] Step A10: In the second frame period, in response to the driving of the second driving timing, enable the pixel charging data group provided by the odd-bit gate lines in the odd pixel rows to be the same as the first pixel data group provided by the odd-bit gate lines in the same odd pixel row in the first frame period, and enable the pixel charging data group provided by the even-bit gate lines in the odd pixel rows to be the same as the second pixel data group provided by the even-bit gate lines in the same odd pixel row in the first frame period, and then perform display driving according to the odd-bit gate lines and even-bit gate lines in the next even pixel row adjacent to the odd pixel row.

[0081] In this embodiment, driving according to the second driving timing within the second frame period can ensure that the pixel charging data groups provided by the odd-numbered gate lines and the even-numbered gate lines in the odd-numbered pixel rows are exactly the same as the data groups provided by the corresponding gate lines in the same odd-numbered pixel row during the first frame period. This not only ensures the coherence and consistency of pixel data between frames but also effectively avoids image flickering or tearing caused by asynchronous data updates. At the same time, after driving the odd-numbered pixel rows, it can seamlessly transition to the next adjacent even-numbered pixel row, and perform display driving based on its odd-numbered gate lines and even-numbered gate lines, thereby achieving progressive scanning and efficient refreshing of the entire display panel, bringing a smoother and more stable visual experience to users.

[0082] In a specific embodiment, within the first frame period, according to Figure 7 the second driving timing shown, the gate line G1 is first turned on to charge the data of R11 - B12, then the gate line G2 is turned on to charge the data of R13 - B14, the gate lines G3 and G5 are turned on simultaneously to charge the data of R31 - B32, the gate lines G4 and G6 are turned on simultaneously to charge the data of R33 - B34, and so on.

[0083] Further, in some feasible embodiments, the above step A10: performing display driving based on the odd-numbered gate lines and the even-numbered gate lines in the next adjacent even-numbered pixel row to the odd-numbered pixel row may further include the following implementation steps A101:

[0084] Step A101: enabling the pixel charging data group provided by the odd-numbered gate line in the even-numbered target pixel row to be the same as the pixel charging data group provided by the odd-numbered gate line in the odd-numbered target pixel row, and enabling the pixel charging data group provided by the even-numbered gate line in the even-numbered target pixel row to be the same as the pixel charging data group provided by the even-numbered gate line in the odd-numbered target pixel row, where the even-numbered target pixel row is the next adjacent even-numbered pixel row to the odd-numbered pixel row, and the odd-numbered target pixel row is the next adjacent odd-numbered pixel row to the even-numbered target pixel row.

[0085] In this embodiment, referring to Figure 9 , assuming that pixel row 1 is the current odd-numbered pixel row, the even-numbered target pixel row is pixel row 2, and the odd-numbered target pixel row is pixel row 3, the pixel charging data group provided by the gate line G3 in pixel row 2 is the same as the pixel charging data group provided by the gate line G5 in pixel row 3, and the pixel charging data group provided by the gate line G4 in pixel row 2 is the same as the pixel charging data group provided by the gate line G6 in pixel row 3.

[0086] In a specific embodiment, referring to Figure 8It can be found that the pixel data charged for the odd pixel rows in the first frame is the same as that for the odd pixel rows in the second frame. For example, for the gate line G1 row, the charged data is all from R11 to B12, for the gate line G2 row, the charged data is all from R13 to B14, for the gate line G5 row, the charged data is all from R31 to B32, and for the gate line G6 row, the charged data is all from R33 to B34. For convenience, in Figure 9 the same background color is used to represent the same pixel data; the data charged for the even pixel rows in the first frame is different from that for the even pixel rows in the second frame. The data charged for the even pixel rows in the first frame is the same as the data charged for the previous pixel row, and the data charged for the even pixel rows in the second frame is the same as the data charged for the next pixel row. For example, for the first frame, for the even pixel row G3, the charged data is from R11 to B12, which is the same as the data charged for the previous pixel row G1, for the even pixel row G4, the charged data is from R13 to B14, which is the same as the data charged for the previous pixel row G2, for the even pixel row G7, the charged data is from R31 to B32, which is the same as the data charged for the previous pixel row G5, and for the even pixel row G8, the charged data is from R33 to B34, which is the same as the data charged for the previous pixel row G6. However, for the second frame, for the even pixel row G3, the charged data is from R31 to B32, which is the same as the data charged for the next pixel row G5, for the even pixel row G4, the charged data is from R33 to B34, which is the same as the data charged for the next pixel row G6, for the even pixel row G7, the charged data is from R51 to B52, which is the same as the data charged for the previous pixel row G9, and for the even pixel row G8, the charged data is from R53 to B54, which is the same as the data charged for the next pixel row G10.

[0087] That is to say, for the odd pixel rows, the data charged in the two frames is the same, and for the even pixel rows, the data is mixed and displayed by the data of the odd pixel rows in the first frame and the data of the even pixel rows in the second frame; because the data mapping of the first frame and the second frame is the same, the even pixel rows are formed by mixing the data of the first row of the original data and the data of the second row of the original data. This method realizes the HSR effect in time by mixing the data of the two frames in time.

[0088] Attention should be paid to the display of the upper and lower boundary positions. Since the resolution in the V direction of the panel is an even number and the number of gate lines is also an even number (taking UHD DRD as an example, there are 2160 * 2 = 4320 gate lines), using the gate line opening sequence of the second frame will result in no valid data being thrown out when the last two rows of gate lines are opened. Take a special example. When displaying a black 0-gray-scale picture with white frames (the width of the white frame is one pixel and the brightness is 255 gray scale) around it, in frame1 (i.e., the first frame), the first pixel row and the last pixel row both display white with 255 gray scale. In frame2 (i.e., the second frame), the first pixel row is the same as the first pixel row in frame1, also displaying white with 255 gray scale. However, when the gate lines of the last pixel row are opened, the pixel unit does not receive valid data, so the last pixel row displays black with 0 gray scale. Then, after mixing the two frames of 255 gray in frame1 and 0 gray in frame2, the last pixel row is equivalent to displaying 127 gray scale. In actual display, since the last pixel row is located at the edge position of the module border, this phenomenon is not easily noticed.

[0089] In addition to paying attention to the display of the boundary positions, the novel HSR driving (i.e., the display driving method) of the present application is applicable to Figures 3 to 4 the driving circuit shown. Taking Figure 2 the long-short-hand DRD panel architecture as an example, to implement the novel HSR, R21 in frame1 should be the same as the R11 data of the previous pixel row, G21 should be the same as the G11 data of the previous pixel row, R21 in frame2 should be the same as the 311 data of the next pixel row, and G21 should be the same as the G31 data of the next pixel row. It can be seen from the panel architecture that R11 and R21, G11 and G21 in frame1, as well as R21 and R31, G21 and G31 in frame2 are not controlled by the same data line. To make R11 and R21 the same, D1 and D2 need to send the same data. To make R12 and R22 the same, D2 and D3 need to send the same data. It can be seen that the long-short-hand DRD cannot achieve the novel HSR driving.

[0090] In summary, the driving circuit provided in this application effectively solves the problems of vertical head shaking patterns and flickering caused by uneven pixel polarity and data line spatial distribution in the traditional long-short hand arrangement structure by optimizing the layout relationship between the gate lines and data lines in the traditional DRD architecture, and at the same time is compatible with the DLG technology to achieve a high refresh rate. Specifically, the driving circuit is provided with pixel units arranged in an array, a plurality of odd gate line groups, and a plurality of even gate line groups. The odd gate line group includes two odd-position gate lines respectively connected to a plurality of first pixel units in the corresponding pixel row, while the even gate line group includes two even-position gate lines respectively connected to a plurality of second pixel units in the corresponding pixel row, thus retaining the advantage of reducing costs by halving the data lines in the DRD architecture. Also, a second pixel unit column is formed by the second pixel units of the same color in the column direction and vertically crosses the target number of data lines to the left and then connects to the destination data line. Since the destination data line is the data line connected to the first pixel unit column with the same color and pixel polarity as the second pixel unit column, uniform alternation of pixel polarity is achieved, significantly reducing visual interference caused by mismatched polarity inversion frequencies. At the same time, since the same data line can stably drive the same-color pixel units with the same pixel polarity in the DLG mode, the problem of complex driving voltage changes and difficult-to-implement timing caused by the data line connecting sub-pixels of different colors in the traditional DRD architecture is effectively solved, thereby significantly improving the display quality of the display panel.

[0091] In addition, this application also provides a display panel, which includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate, and the array substrate includes the driving circuit of any one of the above.

[0092] In addition, this application also provides a display device. Please refer to Figure 10 , Figure 10 which is a schematic structural diagram of the display device involved in the solution of the embodiment of this application. The display device in the embodiment of this application can specifically be a device that locally runs the display driving method.

[0093] As Figure 10 shown, the display device in the embodiment of this application may include: a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display) and an input unit such as a keyboard (Keyboard). Optionally, the user interface 1003 may further include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a Wi-Fi interface).

[0094] The memory 1005 is provided on the display device body. A program is stored in the memory 1005, and when the program is executed by the processor 1001, corresponding operations are implemented. The memory 1005 is also used to store parameters for the display device. The memory 1005 can be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. Optionally, the memory 1005 can also be a storage device independent of the aforementioned processor 1001.

[0095] Those skilled in the art can understand that Figure 10 the display device structure shown in does not constitute a limitation on the display device, and it can include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0096] As Figure 10 shown, the memory 1005, as a storage medium, can include an operating system, a network communication module, a user interface module, and a display driver.

[0097] In Figure 10 the shown display device, the processor 1001 can be used to call the display driver stored in the memory 1005 and execute the steps of the display driving method as described above.

[0098] In addition, to achieve the above object, the present application also provides a storage medium, which is a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the display driving method as described above are implemented.

[0099] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or system including that element.

[0100] The serial numbers of the embodiments of the present application above are only for description and do not represent the superiority or inferiority of the embodiments.

[0101] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product is stored in a storage medium as described above (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions for causing a display device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in various embodiments of the present application.

[0102] The above are only the preferred embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A driving circuit, characterized in that: The driving circuit comprises: Pixel units arranged in an array; A plurality of odd-numbered gate line groups, wherein the odd-numbered gate line groups include two odd-numbered gate lines, each of the odd-numbered gate lines is connected to a plurality of first pixel units in a corresponding pixel row in a row extension direction, and a plurality of the first pixel units in the same column are connected to a data line of the corresponding column; A plurality of even-numbered gate line groups, wherein the even-numbered gate line groups include two even-numbered gate lines, each of the even-numbered gate lines and the previous odd-numbered gate line are arranged in the same pixel row, and each of the even-numbered gate lines is connected to a plurality of second pixel units in a corresponding pixel row in a row extension direction; The second pixel units of the same color form a second pixel unit column along the column direction, and are connected to a destination data line after crossing a target number of data lines along the left vertical direction.

2. The driving circuit according to claim 1, characterized in that: The adjacent pixel units in the same pixel row are sub-pixels of different colors, and the pixel units in the same pixel column are sub-pixels of the same color.

3. The driving circuit according to claim 1, wherein: The driving circuit comprises: A gate driver, the gate driver is connected to the odd-numbered gate line group and the even-numbered gate line group, and the gate driver is configured to input a gate driving signal to each of the odd-numbered gate lines in the odd-numbered gate line group and each of the even-numbered gate lines in the even-numbered gate line group according to a first driving timing sequence and / or a second driving timing sequence, so as to start a first pixel unit connected to each of the odd-numbered gate lines and a second pixel unit connected to each of the odd-numbered gate lines; A data driver is connected to each of the data lines, and the data driver is configured to provide the same pixel data to the first pixel unit and the second pixel unit connected to the same data line.

4. A display driving method, characterized in that: The display driving method is applied to the driving circuit according to any one of claims 1 to 3, and the display driving method comprises: In a first frame period, display drive is performed step by step on multiple odd gate line groups and the next group of even gate line groups adjacent to each of the odd gate line groups according to a first driving timing, and in a second frame period, display drive is performed step by step on odd-numbered gate lines and even-numbered gate lines in odd pixel rows, and odd-numbered gate lines and even-numbered gate lines in the next row of even pixel rows adjacent to the odd pixel rows according to a second driving timing.

5. The display driving method according to claim 4, characterized in that: The step of gradually performing display driving on a plurality of odd-numbered gate line groups and a next group of even-numbered gate line groups adjacent to each of the odd-numbered gate line groups according to a first driving timing in the first frame period comprises: In the first frame period, according to the first driving timing, two odd-numbered gate lines in the current odd-numbered gate line group are enabled to be synchronously turned on to charge the same first pixel data group to all first pixel units connected to the corresponding pixel row, and two even-numbered gate lines in the current even-numbered gate line group are enabled to be synchronously turned on to charge the same second pixel data group to all second pixel units connected to the corresponding pixel row; The next group of odd gate line groups of the current odd gate line group is used as the next current odd gate line group, and the next group of even gate line groups of the current even gate line group is used as the next current even gate line group, and the step of enabling two odd-numbered gate lines in the current odd gate line group to be synchronously turned on according to the first driving timing to charge all first pixel units connected to the corresponding pixel rows with the same first pixel data group is returned to be executed until all the odd gate line groups and all the even gate line groups complete the display drive.

6. The display driving method according to claim 5, characterized in that: The step of gradually performing display driving on the odd-numbered gate lines and the even-numbered gate lines in the odd-numbered pixel row and the odd-numbered gate lines and the even-numbered gate lines in the next even-numbered pixel row adjacent to the odd-numbered pixel row according to the second driving timing in the second frame period comprises: In response to the driving of the second driving timing during the second frame period, the pixel charging data group provided by the odd-numbered gate lines in the odd pixel rows is enabled to be the same as the first pixel data group provided by the odd-numbered gate lines in the same odd pixel rows during the first frame period, and the pixel charging data group provided by the even-numbered gate lines in the odd pixel rows is enabled to be the same as the second pixel data group provided by the even-numbered gate lines in the same odd pixel rows during the first frame period, and then display driving is performed according to the odd-numbered gate lines and even-numbered gate lines in the next row of even pixel rows adjacent to the odd pixel rows.

7. The display driving method according to claim 6, characterized in that: The step of performing display driving according to the odd-numbered gate lines and the even-numbered gate lines in the next even-numbered pixel row adjacent to the odd-numbered pixel row comprises: The pixel charging data group provided by the odd-numbered gate lines in the even target pixel rows is enabled to be the same as the pixel charging data group provided by the odd-numbered gate lines in the odd target pixel rows, and the pixel charging data group provided by the even-numbered gate lines in the even target pixel rows is enabled to be the same as the pixel charging data group provided by the even-numbered gate lines in the odd target pixel rows, wherein the even target pixel rows are the next row of even pixel rows adjacent to the odd pixel rows, and the odd target pixel rows are the next row of odd pixel rows adjacent to the even target pixel rows.

8. A display panel, characterized in that: The display panel comprises a color filter substrate, a liquid crystal layer and an array substrate, wherein the liquid crystal layer is arranged between the array substrate and the color filter substrate, and the array substrate comprises the driving circuit according to any one of claims 1 to 3.

9. A display device, characterized in that: The display device is applied to the driving circuit described in any one of claims 1 to 3, and the display device includes a memory, a processor, and a display driver program stored in the memory and executable on the processor, and the processor implements the steps of the display driving method described in any one of claims 5 to 8 when executing the display driver program.

10. A storage medium, the storage medium being a computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the display driving method according to any one of claims 5 to 8 are implemented.

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