A photosensitive detector with an asymmetric isolation structure and a preparation method thereof

Abstract

The present invention discloses a photodetector with an asymmetric isolation structure and a method for fabricating the same, belonging to the field of photodetectors. By fabricating a thick shallow trench filling layer in the readout region, where the shallow trench isolation density is high, and a thin shallow trench filling layer in the photosensitive region, where the shallow trench isolation density is low, an asymmetric isolation structure is formed. In this structure, the photosensitive region is close to the deep trench electrode, achieving better dark current suppression. The readout region, on the other hand, is further away from the deep trench electrode, mitigating the hot carrier injection effect caused by excessively high local electric fields. This also reduces the threshold voltage of the transistor in the readout region, thereby extending the life of the photodetector.

Description

Technical Field

[0001] The invention relates to a photosensitive detector with an asymmetric isolation structure and a preparation method thereof, and belongs to the field of photoelectric detectors. Background Art

[0002] Photodetectors are widely used in military, medical, automotive, and mobile applications. As demand for image sensor performance in these fields increases, the optimization and iteration of photodetectors are essentially following the "Moore's Law" principle: as pixel size decreases, the pixel integration density per chip increases simultaneously, roughly doubling every two years. However, as detector size decreases, crosstalk between pixels becomes increasingly prominent and difficult to resolve using conventional methods.

[0003] The current mainstream photodetectors are charge coupled devices (CCDs) and CMOS image sensors (CISs). Among them, the basic photosensitive unit of the CCD is a plurality of MOS capacitors connected in series. By applying appropriate voltages to the gates of each adjacent MOS capacitor, the functions of photocharge collection, pixel isolation and charge transfer are realized, and finally the signal charge in the MOS capacitors connected in series is transferred to the readout node step by step to realize the quantization and reset of the light-generated signal. CIS currently adopts an active pixel sensor (APS) structure. The photosensitive part of the pixel is a photodiode. Compared with the CCD, which must share a set of readout circuits for multiple photosensitive units, the CIS can provide a readout module with a source follower (SF) as the core for each photodiode, thereby avoiding excessive charge transfer. A Chinese invention patent with publication number CN107658321A proposes a dual-transistor photodetector, which, after collecting photoelectrons in its photosensitive area, changes the threshold of its read transistor through the effect of floating gate coupling to realize signal reading. This detector structure combines the advantages of high full well density of CCD and random access of CIS, and has a simple layout structure, which is more suitable for miniaturization and high-density integration of pixels.

[0004] In existing technologies, when pixel sizes shrink below 10µm, both CCDs, CMOS image sensors, and dual-transistor photodetectors utilize back-side illumination (BSI) technology. This technology offers orders of magnitude improvements in quantum efficiency compared to front-side illumination (FSI) technology, but also significantly increases the difficulty of pixel isolation. Ideally, BSI requires complete optical and electrical isolation of the 3-10µm bulk silicon region of the pixel array. Micron-scale pixels typically utilize a combination of shadow trench isolation (STI), backside deep trench isolation (BDTI), and doping isolation to minimize signal crosstalk. As pixel size continues to shrink, alignment issues between STI and BDTI, as well as annealing and diffusion issues in doping isolation, become increasingly significant, leading to a sharp decrease in pixel duty cycle and even failure of the isolation structure to function properly. The Chinese invention patent, publicly disclosed as CN118866913A, proposes a novel deep trench isolation structure for dual-transistor photodetectors. Using ultra-high aspect ratio etching and atomic layer deposition techniques, this structure physically isolates pixels and eliminates electrical crosstalk. However, this invention fails to consider the differing isolation requirements between the pixel readout and photosensitive areas, making it difficult to achieve a balanced balance between pixel dark current and stability. Summary of the Invention

[0005] In order to improve the dark current suppression effect, the present invention provides a photosensitive detector with an asymmetric structure, wherein the photosensitive detector includes a substrate and a pixel isolation structure, wherein the pixel isolation structure is a deep trench isolation structure penetrating the substrate, and the substrate is isolated into a plurality of substrate pixel units by the deep trench isolation structure;

[0006] In each substrate pixel unit, the two opposite sides of the substrate are respectively recorded as the front side and the back side, wherein the front side of the substrate includes the active area and the shallow trench isolation, and the active area is divided into the photosensitive area and the reading area by the shallow trench isolation;

[0007] The deep trench isolation structure includes a deep trench penetrating the substrate, a first isolation medium and a deep trench electrode, wherein the first isolation medium includes a linear oxide layer and a shallow trench filling layer, the linear oxide layer is located between the deep trench and the substrate, and the deep trench electrode and the shallow trench filling layer are sequentially filled in the deep trench from the back to the front of the substrate; wherein the filling height of the shallow trench filling layer in the deep trench isolation structure in the reading area is higher than the filling height of the shallow trench filling layer in the deep trench isolation structure in the photosensitive area.

[0008] Optionally, a filling height of the shallow trench filling layer in the deep trench isolation structure within the read region is the same as a height of the shallow trench isolation.

[0009] Optionally, the material of the deep trench electrode is metal, intrinsic or doped single crystal silicon, polycrystalline silicon, or amorphous silicon.

[0010] Optionally, the linear oxide layer is a single layer or a composite layer of insulating material.

[0011] Optionally, the material of the shallow trench filling layer is a single layer or composite layer of insulating material, including a single layer of silicon dioxide, a single layer of silicon nitride, a silicon dioxide / silicon nitride composite layer, a silicon dioxide / silicon nitride / silicon dioxide composite layer, a silicon dioxide / aluminum oxide / silicon dioxide composite layer, etc.

[0012] Optionally, the substrate is p-type doped or n-type doped.

[0013] The present invention also provides a composite dielectric gate dual-transistor photosensitive detector with an asymmetric isolation structure, wherein the composite dielectric gate dual-transistor photosensitive detector has the pixel isolation structure of the above-mentioned photosensitive detector; the composite dielectric gate dual-transistor photosensitive detector includes a composite dielectric gate capacitor and a composite dielectric gate transistor, wherein the photosensitive area includes the composite dielectric gate capacitor and the reading area includes the composite dielectric gate transistor.

[0014] The present invention also provides a CMOS image sensor with an asymmetric isolation structure, wherein the CMOS image sensor has the pixel isolation structure of the above-mentioned photosensitive detector; the CMOS image sensor includes a photosensitive diode, a transfer transistor, a floating node, a reset transistor, a source follower transistor and an address selection transistor, wherein the photosensitive area includes the photosensitive diode, and the reading area includes the transfer transistor, the floating node, the reset transistor, the source follower transistor and the address selection transistor.

[0015] The invention also provides a method for preparing a photosensitive detector having an asymmetric isolation structure, the method for preparing the above-mentioned photosensitive detector comprising:

[0016] Step 1: prepare a substrate, wherein the substrate is p-type doped or n-type doped;

[0017] Step 2: forming a deep trench extending from the front surface of the substrate to the back surface of the substrate by photolithography using a hard mask, wherein the hard mask includes a sacrificial oxide layer and a baked silicon nitride layer;

[0018] Step 3: using chemical vapor deposition to grow a linear oxide layer on the inner wall of the deep trench;

[0019] Step 4, filling the deep trench with deep trench electrodes;

[0020] Step 5: etching a shallow groove extending from the front side of the substrate to the other side at a designated position according to the mask;

[0021] Step 6, using an anti-reflective material as a photoresist layer, wherein the thickness of the photoresist layer in the area with a high shallow groove density is lower than the thickness of the photoresist layer in the area with a low shallow groove density;

[0022] Step 7: Continue etching the photoresist layer and the deep trench electrode according to the thickness of the photoresist layer to form new shallow trenches at the deep trench electrode, wherein the height of the new shallow trenches formed in the area with high shallow trench density is higher than the height of the new shallow trenches formed in the area with low shallow trench density;

[0023] Step 8, filling the shallow groove etched in step 5 and the new shallow groove etched in step 7, respectively forming a complete shallow groove isolation, a reading area shallow groove filling layer, and a photosensitive area shallow groove filling layer;

[0024] Step 9: remove the silicon nitride layer and the sacrificial oxide layer to form a complete pixel isolation structure, and separate the substrate into independent pixel units through the pixel isolation structure.

[0025] Optionally, the anti-reflective material includes spin-coated organic carbon, polyimide derivatives, aromatic compounds, silicon oxynitride, titanium nitride, silicon-containing polymers and silane coupling agents.

[0026] The beneficial effects of the present invention are:

[0027] A photodetector with an asymmetric structure and its fabrication method achieve low dark current and high pixel stability at a low cost. The asymmetric photodetector uses deep trench isolation to separate substrates to form multiple pixel units, enabling physical isolation between pixel units at submicron dimensions. In terms of fabrication process, an anti-reflective material with poor fluidity but good adhesion is selected as the photolithography layer to prepare the shallow trench filling layer in the deep trench isolation. The shallow trench filling layer is fabricated in a single pass to achieve varying thicknesses depending on the shallow trench isolation density. Combining the design of a conventional CMOS image sensor with a composite dielectric gate dual-transistor photodetector, a thicker shallow trench filling layer can be fabricated in the readout region with a high shallow trench isolation density, while a thinner shallow trench filling layer can be fabricated in the photosensitive region with a low shallow trench isolation density. Due to the varying shallow trench filling layer thicknesses, the photosensitive region is closer to the deep trench electrode, resulting in better dark current suppression. The distance between the readout region and the deep trench electrode mitigates hot carrier injection caused by excessively high local electric fields, while also reducing the threshold voltage of the transistor in the readout region, thereby extending the life of the photodetector. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 This is a schematic diagram of a single pixel plan of a photosensitive detector with an asymmetric isolation structure.

[0030] Figure 2 It is along Figure 1 XX' is a schematic cross-sectional view of a single pixel of a photosensitive detector with an asymmetric isolation structure.

[0031] Figure 3 It is a planar schematic diagram of a pixel array of a photodetector with an asymmetric isolation structure.

[0032] Figure 4 It is along Figure 3 XX' is a cross-sectional diagram of a pixel array of a photodetector with an asymmetric isolation structure.

[0033] Figure 5 It is a planar schematic diagram of a pixel array of a composite dielectric gate dual-transistor photodetector with an asymmetric isolation structure.

[0034] Figure 6 It is along Figure 5 XX' is a cross-sectional diagram of a pixel array of a composite dielectric gate dual-transistor photodetector with an asymmetric isolation structure.

[0035] Figure 7 It is a planar schematic diagram of a pixel array of a CMOS image sensor with an asymmetric isolation structure.

[0036] Figure 8 It is along Figure 7 XX' is a schematic cross-sectional diagram of a pixel array of a CMOS image sensor with an asymmetric isolation structure.

[0037] Figure 9 It is a schematic flow chart of a method for preparing an asymmetric isolation structure photosensitive detector according to the present invention.

[0038] Figures 10 to 17 It is a cross-sectional schematic diagram of a device prepared in each step of a method for preparing an asymmetric isolation structure photosensitive detector of the present invention. DETAILED DESCRIPTION

[0039] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0040] Example 1

[0041] This embodiment provides a photosensitive detector with an asymmetric isolation structure, such as Figures 1 to 4 As shown, the photosensitive detector includes a substrate 100 and a pixel isolation structure 200, wherein the pixel isolation structure 200 is a deep trench isolation (DTI) structure, and the deep trench isolation penetrates the substrate 100 to form a plurality of substrate pixel units. Figure 1 and Figure 2 is a planar schematic diagram and a cross-sectional schematic diagram of a single pixel, Figure 3 and Figure 4 Schematic diagrams of the plane and cross-section corresponding to multiple pixels.

[0042] For the convenience of subsequent description, the two opposite sides of the substrate 100 are respectively referred to as the front side 110 and the back side 120. Figure 2 As shown, the front surface 110 of each pixel unit substrate 100 includes an active area 111 and a shallow trench isolation 112 . The active area 111 is divided by the shallow trench isolation 112 into a photosensitive area 110 b having a photoelectric conversion function and a reading area 110 a having a quantized photoelectric signal.

[0043] The deep trench isolation (DTI) structure includes a deep trench penetrating the substrate, a first isolation dielectric 210, and a deep trench electrode 220. The first isolation dielectric 210 includes a linear oxide layer 211 and a shallow trench filling layer 212. The linear oxide layer 211 is located between the deep trench and the substrate 100. The deep trench electrode 220 and the shallow trench filling layer 212 are sequentially filled in the deep trench along the direction from the back side 120 to the front side 110 of the substrate 100. The shallow trench filling layer 212 adjacent to the reading area 110a is recorded as the reading area shallow trench filling layer 212a, and the shallow trench filling layer 212 adjacent to the photosensitive area 110b is recorded as the photosensitive area shallow trench filling layer 212b. The filling height of the reading area shallow trench filling layer 212a is higher than the filling height of the photosensitive area shallow trench filling layer 212b.

[0044] In practical applications, the filling height of the shallow trench filling layer 212a in the read region can be set to the same height as the shallow trench isolation 112. Under typical operating voltage conditions, a lower voltage is applied to the deep trench electrode 220 than to the substrate 100, causing hole accumulation at the interface between the first isolation dielectric 210 and the substrate 100, suppressing the generation and recombination of interface states, reducing the dark current of the pixel, and improving the quantum efficiency of the pixel. Because the filling height of the shallow trench filling layer 212b in the photosensitive region is lower than the filling height of the shallow trench filling layer 212a in the read region, under the action of the voltage of the deep trench electrode 220, the interface has a wider spatial protection effect, and the benefits of dark current and other performance are higher. However, the read region 110a does not require interface protection. An overly thin shallow trench filling layer 212 will instead cause the local electric field in the transistor channel in the read region 110a to be too high, which can easily cause a series of parasitic effects such as hot carrier injection and drain-induced barrier lowering, reducing the stability and service life of the pixel. Therefore, the shallow trench filling layer 212a in the reading region needs to be thicker to ensure that the deep trench electrode 220 is appropriately away from the transistors in the reading region 110a and to control the influence of parasitic effects within a reasonable value.

[0045] During operation, the photosensitive region 110b forms a depletion region under the control of the operating voltage. This depletion region contacts the first isolation dielectric 210, creating a large number of interface states at the boundary between the first isolation dielectric 210 and the substrate 100, generating a large dark current. However, when a suitable negative voltage, lower than that applied to the deep trench electrode 220 relative to the substrate 100, is applied, the depletion region is pushed away from the boundary between the first isolation dielectric 210 and the substrate 100. A hole accumulation layer forms at the interface of the first isolation dielectric 210 near the substrate 100, adjacent to the deep trench electrode 220. This hole accumulation layer suppresses carrier generation and, in turn, dark current. However, the interface of the first isolation dielectric 210 near the substrate 100, adjacent to the shallow trench fill layer 212, is less susceptible to the influence of the deep trench electrode 220, and the dark current generation rate remains high. Therefore, when the thickness of the shallow groove filling layer 212b in the photosensitive area is reduced, the distance between the deep groove electrode 220 and the photosensitive area 110b is closer, which can more effectively protect the interface of the first isolation medium 210 in the photosensitive area 110b and reduce the dark current.

[0046] In the above-described photodetector with an asymmetric isolation structure, substrate 100 can be any suitable substrate known in the art, including silicon, germanium, silicon nitride, silicon carbide, gallium arsenide, gallium phosphide, etc. Substrate 100 can be p-type doped or n-type doped, with the p-type being used as an example in this embodiment.

[0047] The material of the deep trench electrode 220 includes metal, intrinsic or doped single crystal silicon, polycrystalline silicon, or amorphous silicon, and preferably a material with good electrical conductivity.

[0048] The linear oxide layer 211 is a single layer or composite layer of insulating material, such as a single SiO2 layer, a single Si3N4 layer, a SiO2 / Si3N4 composite layer, a SiO2 / Si3N4 / SiO2 composite layer, a SiO2 / Al2O3 composite layer, or a SiO2 / TaO composite layer. For materials with the same physical thickness of SiO2, Si3N4, and SiO2, SiO2 has lower interface states, while Si3N4 provides a superior barrier to dopant diffusion. Other materials also have their own advantages and disadvantages. Therefore, if process conditions permit, rationally configuring the linear oxide layer 211 as a composite layer of multiple materials can leverage the advantages of each material, often resulting in a more competitive pixel performance improvement than a single layer.

[0049] The shallow trench filling layer 212 is made of insulating material, and may be a single silicon dioxide layer, a single silicon nitride layer, a silicon dioxide / silicon nitride composite layer, a silicon dioxide / silicon nitride / silicon dioxide composite layer, or a silicon dioxide / aluminum oxide / silicon dioxide composite layer.

[0050] like Figure 3 and Figure 4 As shown, when the same substrate 100 is isolated into a plurality of pixel units by deep trenches, adjacent pixel units share the corresponding deep trench isolation structure.

[0051] The pixel unit includes a CMOS image sensor and a composite dielectric gate dual-transistor photodetector. Both photodetectors have their own photosensitive area and reading area. The following examples 2 and 3 respectively introduce the photodetector device structure with an asymmetric isolation structure using the composite dielectric gate dual-transistor photodetector and the CMOS image sensor as pixel units.

[0052] Example 2

[0053] Reference Figure 5 and Figure 6 The pixel unit is configured as a composite dielectric gate dual-transistor photodetector 160, comprising a composite dielectric gate transistor 161 and a composite dielectric gate capacitor 162. Composite dielectric gate transistor 161 and composite dielectric gate capacitor 162 share the same substrate, first insulating dielectric layer, first gate, second insulating dielectric layer, and second gate. The specific structure is described in Chinese invention patent publication number CN102938409A. In composite dielectric gate dual-transistor photodetector 160, readout region 110a includes composite dielectric gate transistor 161, and photosensitive region 110b includes composite dielectric gate capacitor 162. Readout region 110a has a higher shallow trench isolation (STI) 112 density than photosensitive region 110b. STI density refers to the ratio of the area of ​​the STI within a corresponding region to the area of ​​the region.

[0054] The composite dielectric gate dual-transistor photosensitive detector 160 with an asymmetric isolation structure provided in this embodiment is different from the existing composite dielectric gate dual-transistor photosensitive detector mainly in that in the deep trench isolation structure used to isolate each pixel, the filling height of the shallow trench filling layer 212a in the reading area is higher than the filling height of the shallow trench filling layer 212b in the photosensitive area. The remaining structures have not been improved and will not be further introduced.

[0055] Example 3

[0056] Reference Figure 7 and Figure 8 The pixel unit is configured as a CMOS image sensor 150, including a photodiode 151, a transfer transistor 152, a floating node 153, a source follower transistor 154, an address transistor 155, and a reset transistor 156. In the CMOS image sensor, the readout region 110a includes the transfer transistor 152, the floating node 153, the source follower transistor 154, the address transistor 155, and the reset transistor 156. The photosensitive region 110b includes the photodiode 151. The readout region 110a has a higher shallow trench isolation 112 density than the photosensitive region 110b. The shallow trench isolation density refers to the ratio of the area of ​​the shallow trench isolation region in the corresponding region to the area of ​​the region.

[0057] The CMOS image sensor with an asymmetric isolation structure provided in this embodiment differs from existing CMOS image sensors primarily in that, in the deep trench isolation structure used to isolate pixels, the filling height of the shallow trench filling layer 212a in the reading area is higher than the filling height of the shallow trench filling layer 212b in the photosensitive area. The remaining structures have not been improved and are therefore not further described.

[0058] Example 4

[0059] This embodiment provides a method for preparing a photosensitive detector with an asymmetric isolation structure, which can be used to prepare the photosensitive detector with an asymmetric isolation structure described in the above embodiment. Figure 9 The execution steps of the preparation method are: Figures 10 to 17 It is a cross-sectional schematic diagram corresponding to each step of preparing a photosensitive detector array according to the preparation method of the present invention.

[0060] First, a substrate 100 is provided. The substrate 100 is of p-type or n-type, and the present embodiment takes the p-type substrate as an example. The substrate 100 has a front surface 110 and a back surface 120 that are opposite to each other.

[0061] A deep trench extending from the front surface 110 of the substrate 100 to the back surface 120 of the substrate is formed by photolithography using a hard mask, wherein the hard mask includes a sacrificial oxide layer 101 and a baked silicon nitride layer 102. Figure 10 shown.

[0062] A linear oxide layer 211 is grown on the inner wall of the deep trench using chemical vapor deposition, such as Figure 11 shown.

[0063] Filling the deep trench electrode 220, such as Figure 12 shown.

[0064] A shallow groove extending from the front surface 110 of the substrate to the other side is etched at a designated position according to the mask, such as Figure 13 Then, an anti-reflective material layer with poor fluidity and good adhesion is used as a photoresist layer, wherein the thickness of the photoresist layer is low in the area with high shallow groove density, and the thickness of the photoresist layer is high in the area with low shallow groove density, as shown in FIG. Figure 14 shown.

[0065] According to the thickness of the photoresist layer, the photoresist layer and the deep groove electrode 220 are continuously etched to form a new shallow groove at the deep groove electrode 220, such as Figure 15 shown.

[0066] Fill the shallow groove extending from the substrate front surface 110 to the other side and the new shallow groove formed at the deep groove electrode 220 etched at the specified position according to the mask, and form a complete shallow groove isolation, a reading area shallow groove filling layer 212a and a photosensitive area shallow groove filling layer 212b, respectively. Figure 16 shown.

[0067] like Figure 17 As shown, the baked silicon nitride layer 102 and the sacrificial oxide layer 101 are removed to form a complete pixel isolation structure 200. The pixel isolation structure 200 separates the substrate 100 into independent pixel units. The thickness of the shallow trench filling layer is positively correlated with the density of the shallow trench isolation.

[0068] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0069] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A photosensitive detector with an asymmetric isolation structure, characterized in that: The photosensitive detector comprises a substrate (100) and a pixel isolation structure (200), wherein the pixel isolation structure (200) is a deep trench isolation structure penetrating the substrate (100), and the substrate (100) is isolated into a plurality of substrate pixel units by the deep trench isolation structure; In each substrate pixel unit, two opposite sides of the substrate are respectively recorded as a front side (110) and a back side (120), wherein the front side (110) of the substrate (100) includes an active area (111) and a shallow trench isolation (112), and the active area (111) is divided into a photosensitive area (110b) and a reading area (110a) by the shallow trench isolation (112); The deep trench isolation structure comprises a deep trench penetrating a substrate, a first isolation medium (210), and a deep trench electrode (220), wherein the first isolation medium (210) comprises a linear oxide layer (211) and a shallow trench filling layer (212), the linear oxide layer (211) being located between the deep trench and the substrate (100), and the deep trench electrode (220) and the shallow trench filling layer (212) being sequentially filled in the deep trench along a direction from the back side (120) to the front side (110) of the substrate (100); wherein the filling height of the shallow trench filling layer (212) in the deep trench isolation structure in the reading area (110a) is higher than the filling height of the shallow trench filling layer (212) in the deep trench isolation structure in the photosensitive area (110b); and the reading area has a higher shallow trench isolation density than the photosensitive area. The filling height of the shallow trench filling layer (212) in the deep trench isolation structure within the reading area (110a) is the same as the height of the shallow trench isolation (112).

2. The photosensitive detector according to claim 1, characterized in that The material of the deep groove electrode (220) is one of metal, intrinsic or doped single crystal silicon, polycrystalline silicon, and amorphous silicon.

3. The photosensitive detector according to claim 1, characterized in that The linear oxide layer (211) is a single layer or a composite layer of insulating material.

4. The photosensitive detector according to claim 1, characterized in that The shallow groove filling layer (212) is a single layer or a composite layer of insulating material.

5. The photosensitive detector according to claim 1, characterized in that: The substrate is p-type doped or n-type doped.

6. A composite dielectric gate dual-transistor photodetector with an asymmetric isolation structure, characterized in that: The composite dielectric gate dual-transistor photosensitive detector has the pixel isolation structure (200) of the photosensitive detector according to any one of claims 1 to 5; the composite dielectric gate dual-transistor photosensitive detector includes a composite dielectric gate capacitor and a composite dielectric gate transistor, wherein the photosensitive area includes the composite dielectric gate capacitor and the reading area includes the composite dielectric gate transistor.

7. A CMOS image sensor with an asymmetric isolation structure, characterized in that: The CMOS image sensor has a pixel isolation structure (200) of a photosensitive detector according to any one of claims 1 to 6; the CMOS image sensor comprises a photosensitive diode, a transfer transistor, a floating node, a reset transistor, a source follower transistor and an address transistor, wherein the photosensitive area comprises the photosensitive diode, and the reading area comprises the transfer transistor, the floating node, the reset transistor, the source follower transistor and the address transistor.

8. A method for preparing a photosensitive detector with an asymmetric isolation structure, characterized in that: The method is used to prepare the photosensitive detector according to any one of claims 1 to 5, comprising: Step 1: prepare a substrate, wherein the substrate is p-type doped or n-type doped; Step 2: forming a deep trench extending from the front surface of the substrate to the back surface of the substrate by photolithography using a hard mask, wherein the hard mask includes a sacrificial oxide layer and a baked silicon nitride layer; Step 3: using chemical vapor deposition to grow a linear oxide layer on the inner wall of the deep trench; Step 4, filling the deep trench with deep trench electrodes; Step 5: etching a shallow groove extending from the front side of the substrate to the other side at a designated position according to the mask; Step 6, using an anti-reflective material as a photoresist layer, wherein the thickness of the photoresist layer in the area with a high shallow groove density is lower than the thickness of the photoresist layer in the area with a low shallow groove density; Step 7: Continue etching the photoresist layer and the deep trench electrode according to the thickness of the photoresist layer to form new shallow trenches at the deep trench electrode, wherein the height of the new shallow trenches formed in the area with high shallow trench density is higher than the height of the new shallow trenches formed in the area with low shallow trench density; Step 8, filling the shallow groove etched in step 5 and the new shallow groove etched in step 7, respectively forming a complete shallow groove isolation, a reading area shallow groove filling layer, and a photosensitive area shallow groove filling layer; Step 9: remove the silicon nitride layer and the sacrificial oxide layer to form a complete pixel isolation structure, and separate the substrate into independent pixel units through the pixel isolation structure.

9. The method according to claim 8, characterized in that The antireflective materials include spin-coated organic carbon, polyimide derivatives, aromatic compounds, silicon oxynitride, titanium nitride, silicon-containing polymers, and silane coupling agents.

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