Display panel motherboard, preparation method thereof and evaporation equipment

Abstract

The display panel mother board provided by the present application can be directly tested after evaporation, the confirmation time of evaporation effect is short, signal shunting is avoided, and the risk of abnormal light-on test is reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a display panel mother board, a preparation method thereof and an evaporation equipment. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on Light Emitting Diode (LED) technology have been widely used in mobile phones, televisions, notebook computers, desktop computers and other consumer electronic products due to their high image quality, power saving, thin body and wide application range. OLED has become the mainstream of display devices. In the preparation process of traditional display panel, fine metal mask (FMM) is usually used to realize the patterning of light-emitting pixels. FMM technology is mature and has rich mass production experience. However, FMM technology also has the problems of limited precision, high development cost and long development cycle. The fine metal mask-free technology eliminates the limitations of traditional OLED process on display screen size, resolution and other screen performance, and has the advantages of high performance, full size and agile delivery. The patents CN118251982A, CN116648095A, CN117062489A, CN118742138A, CN118678783A, CN118660598A, CN118675450A, CN118824188A and CN118781966A disclose the related content of fine metal mask-free technology, which are referred to.

[0003] However, the process performance of the current OLED display product needs to be improved. SUMMARY

[0004] Therefore, the purpose of the present disclosure is to provide a display panel mother board, a preparation method thereof and an evaporation equipment to improve the test efficiency, avoid the shunting of lighting test signals and reduce the risk of lighting test abnormalities.

[0005] To achieve the above-mentioned purpose, the present disclosure discloses a display panel mother board, which comprises a first edge extending along a first direction and a second edge extending along a second direction, the first direction being perpendicular to the second direction, and the display panel mother board comprises:

[0006] a substrate;

[0007] a plurality of sub-panel groups, the plurality of sub-panel groups are arranged in sequence along the first direction of the substrate, and each of the sub-panel groups comprises a plurality of sub-panels, and the plurality of sub-panels in the same sub-panel group are arranged in sequence along the second direction on the substrate;

[0008] A first test pad group is provided with a plurality of first test pad groups, and the plurality of first test pad groups are connected one-to-one with the plurality of sub-panel groups. The first test pad group is used to input a first test signal to the corresponding sub-panel group, and the plurality of sub-panels in each sub-panel group simultaneously receive the first test signal.

[0009] A second test pad group is provided with a plurality of second test pad groups, and the plurality of second test pad groups are arranged one-to-one with the plurality of sub-panel groups. The second test pad group is simultaneously connected with the sub-panels in the corresponding sub-panel group. The second test pad group is used to input a second test signal different from the first test signal to the sub-panels in the corresponding sub-panel group.

[0010] Further, a plurality of signal lines are provided, and the plurality of signal lines are arranged one-to-one with the plurality of sub-panel groups. The same signal line is simultaneously connected with the corresponding first test pad group and second test pad group.

[0011] Further, each signal line includes a signal main line and a plurality of signal branch lines connected with the signal main line. The signal main line is connected with the second test pad group, and the plurality of signal branch lines are connected one-to-one with the plurality of first test pad groups.

[0012] Further, the plurality of signal branch lines are arranged in parallel with each other, and the signal branch lines are arranged in the first direction,

[0013] The plurality of signal branch lines are arranged in sequence in the second direction.

[0014] Further, the signal main line is arranged in the second direction, and the plurality of signal branch lines connected with the plurality of sub-panels in the same sub-panel group are connected with the same signal main line.

[0015] Further, the first test pad groups of the plurality of sub-panels arranged in the same row in the first direction are located in the same row.

[0016] Further, the second test pad group is located at both ends of the signal main line.

[0017] Further, the plurality of second test pad groups are located close to the first edge, and the plurality of second test pad groups are arranged in the first direction. A plurality of second test pad groups connected with different signal main lines are arranged at intervals on the first edge. The second edge is adjacent to the first edge.

[0018] Further, the first test signal includes electrical signals of different frequencies and different amplitudes, and / or the second test signal includes a constant voltage signal.

[0019] Further, the plurality of sub-panel groups are arranged uniformly along a first direction.

[0020] Further, the plurality of sub-panels are arranged uniformly along a second direction.

[0021] Further, the first test pad group is arranged in a rectangular array on the substrate.

[0022] Further, the first test pad group and the second test pad group are made of a conductive metal.

[0023] The conductive metal includes at least one of copper, silver, and aluminum.

[0024] A method for manufacturing a display panel mother board as described above, the display panel mother board comprising a first edge and a second edge, the method comprising the following steps:

[0025] Shielding a second test pad group on the first edge of the display panel mother board with a shield plate;

[0026] Evaporating the display panel mother board after shielding;

[0027] After evaporation, removing the shield plate and inputting a second test signal to the sub-panels in the sub-panel group through the second test pad group.

[0028] An evaporation apparatus for evaporating a display panel mother board as described above, the evaporation apparatus comprising:

[0029] An evaporation chamber;

[0030] A support structure arranged in the evaporation chamber for supporting the display panel mother board;

[0031] An evaporation source arranged between a pair of support structures for evaporating the display panel mother board;

[0032] A shield plate configured to cover a plurality of second test pad groups on the first edge of the display panel mother board.

[0033] Compared with the prior art, the display panel mother board provided by the present disclosure is subjected to a lighting test through a first test pad after evaporation and packaging are completed, each sub-panel in each sub-panel group is connected in parallel with each other, and the first test pad group corresponding to each sub-panel is connected with the same second test pad group. Each sub-panel in a column of sub-panels simultaneously receives a first test signal, effectively avoiding the shunting of the first test signal during the lighting test, and reducing the risk of lighting test abnormalities. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the present disclosure or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are only embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0035] Figure 1 A schematic diagram of the whole surface evaporation of the display panel motherboard in the prior art;

[0036] Figure 2 A schematic diagram of the test signal in the display panel motherboard in the prior art;

[0037] Figure 3 A schematic diagram of a pixel structure in a sub-panel of the display panel motherboard in the embodiments of the present disclosure;

[0038] Figure 4 A schematic diagram of the whole surface evaporation of the display panel motherboard in the embodiments of the present disclosure;

[0039] Figure 5 A schematic diagram of the second test signal in the embodiments of the present disclosure;

[0040] Figure 6 A schematic diagram of the first test signal in the embodiments of the present disclosure;

[0041] Figure 7 A schematic diagram of the structure of the evaporation equipment in the embodiments of the present disclosure;

[0042] Figure 8 A schematic diagram of the evaporation process of the evaporation equipment in the embodiments of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail with reference to the specific embodiments and the drawings.

[0044] It should be noted that, unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure shall be understood as their common meanings to those skilled in the art to which the embodiments of the present disclosure belong. The terms "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships may also change accordingly.

[0045] In the field of OLED (Organic Light-Emitting Diode) display technology, improving product resolution, reducing cost, and shortening development cycle have always been important goals pursued by the industry. Traditional OLED manufacturing processes often use FMM (Fine Metal Mask) for RGB pixel preparation, but FMM has the problems of high cost and long development cycle, which seriously limits the large-scale production and market competitiveness of OLED products. In recent years, a FMM-free RGB self-alignment pixelization technology has emerged, which has significant advantages and can achieve pixel-level packaging, effectively reduce the PDL Gap (Pixel Definition Layer Gap), and thus greatly improve the resolution of OLED products. However, the existing FMM-free RGB self-alignment pixelization technology still has many deficiencies in the process.

[0046] In the existing FMM-free RGB self-alignment pixelization technology, after each type of pixel is evaporated and packaged, a plurality of processes such as yellow light, development, wet etching, stripping, etc. need to be completed in turn, and then a lap impedance test needs to be performed, and finally the product is shipped to a lighting station for the first time. The entire process, the evaporation evaluation period of one color is relatively long, short for 3-4 days, long for 6-8 days. If the evaporation effect is not ideal, re-evaporation will further delay a large amount of time, seriously affecting production efficiency.

[0047] In order to improve the production efficiency of the FMM-free RGB self-alignment pixelization technology product, the applicant has researched the current process procedures, such as Figure 1 , 2As shown, a schematic diagram of test points on an existing display panel motherboard is shown, the display panel motherboard is provided with a plurality of unit test pad groups 101 and a plurality of lighting test pad groups 102; the plurality of lighting test pad groups 102 are connected one by one with the sub-panels 210 and are used to input first test signals to the sub-panels 210 for lighting test; the unit test pad groups 101 are arranged at both ends of the plurality of first test pad groups in the same row and are used to input second test signals to the sub-panels 210 for unit test. During evaporation, the unit test pad groups 101 are shielded by the baffle 500 to avoid deposition of evaporation material on the unit test pad groups 101 during evaporation. Therefore, after evaporation is completed, the second test signals can be directly input through the unit test pad groups 101 for unit test to test whether the light emission of the sub-panels 210 in the first direction X1 is normal and to obtain the evaporation effect in time, greatly improving the production efficiency. However, the above-mentioned display panel motherboard has the problem of signal shunting during lighting test. In the above-mentioned related technology, during lighting test of the display panel motherboard, the first test signals are input to the sub-panels 210 through the lighting test pad groups 102, and the first test signals flow not only to the sub-panels 210 connected with the lighting test pad groups 102 but also shunt to other sub-panels 210 in the second direction X2 of the sub-panels 210 through the unit test lead, causing the problem of shunting of the first test signals. The signal shunting easily leads to abnormal lighting test, reduces the production efficiency and is extremely easy to misjudge.

[0048] Based on the above research findings of the applicant, a display panel mother board is proposed, which comprises a plurality of first test pad groups 300 and second test pad groups 400, the first test pad groups 300 are connected one-to-one with the sub-panels 210, the first test pad groups 300 are used to input first test signals to the corresponding sub-panels 210, and a plurality of sub-panels 210 in each sub-panel group 200 simultaneously receive the first test signals; a plurality of second test pad groups 400 are arranged one-to-one with the plurality of sub-panel groups 200, the second test pad groups 400 are simultaneously connected with the sub-panels 210 in the corresponding sub-panel groups 200, and the second test pad groups 400 are used to input second test signals to the sub-panels 210 in the corresponding sub-panel groups 200. Compared with the display panel mother board in the related art, the position of the second test pad group 400 is adjusted in the display panel mother board provided in the present application, and unit testing can be performed by inputting the second test signal to the sub-panel group 200 through the second test pad group 400. During evaporation, the baffle 500 shields the second test pad group 400, so as to avoid that the evaporation material is deposited on the second test pad group 400 during evaporation. After evaporation is completed, the second test signal can be directly input through the second test pad group 400 for unit testing, so as to test whether the light emitting condition of the sub-panel group 200 in the second direction X2 is normal, to timely obtain the evaporation effect, and to greatly improve the production efficiency. Meanwhile, the problem of signal shunting existing in the display panel mother board in the related art is also solved. After evaporation and packaging are completed, the sub-panel group 200 is tested by the first test pad group 300, since each sub-panel 210 in each sub-panel group 200 is connected in parallel with each other, and the corresponding first test pad group 300 of each sub-panel 210 is connected with the same second test pad group 400, each sub-panel 210 in a column of sub-panels 210 can simultaneously receive the first test signal, which effectively avoids the shunting of the light-on test signal and reduces the risk of light-on test abnormality. The unit testing is used to test whether the light emitting function of the sub-panel group 200 is normal through the second test pad group 400, one second test pad group 400 tests one sub-panel group 200, and one second test pad group 400 comprises at least one second test pad; the light-on test is used to test whether the light emitting function of each sub-panel 210 is normal through the first test pad group 300, one first test pad group 300 tests one sub-panel 210, and one first test pad group 300 comprises at least one first test pad.

[0049] Figure 3 is a pixel structure cross-sectional schematic view of a sub-panel of the display panel mother board provided in the embodiments of the present application. Referring to Figure 3Exemplarily, the sub-panel can comprise: a substrate 60, a pixel definition layer PDL located on one side of the substrate 60, and an isolation structure 50 located on a side of the pixel definition layer PDL away from the substrate 60. The pixel definition layer PDL encloses a plurality of pixel openings, and the isolation structure 50 encloses a plurality of isolation openings, each pixel opening corresponding to each isolation opening. The display panel mother board can comprise at least one sub-panel, and the sub-panel is composed of a pixel circuit and a light-emitting device OLED. The pixel circuit can be disposed in the substrate 60. At least part of the light-emitting device OLED is disposed in the pixel opening and comprises a first electrode 41, a light-emitting layer 42 and a second electrode 43 which are sequentially stacked in a direction away from the substrate 60. Exemplarily, the first electrode 41 of the light-emitting device OLED is its anode, and the second electrode 43 is its cathode. Based on the isolation effect of the isolation structure 50, a self-alignment pixelation technology without a fine metal mask (FMM) can be realized. Specifically, the isolation structure 50 can comprise a first isolation part 51 and a second isolation part 52 which are sequentially stacked in a direction away from the substrate 60. The orthographic projection of the first isolation part 51 on the substrate 60 is located in the orthographic projection of the second isolation part 52 on the substrate 60, and the area of the orthographic projection of the first isolation part 51 on the substrate 60 is smaller than the area of the orthographic projection of the second isolation part 52 on the substrate 60. Based on the arrangement of the isolation structure 50, each light-emitting layer 42 and each second electrode 43 can be evaporated into the corresponding pixel opening without the fine metal mask. Based on the isolation effect of the isolation structure 50, a pixel encapsulation structure 44 can be formed on a side of each second electrode 43 away from the substrate 60, so as to independently encapsulate each light-emitting device OLED.

[0050] Figure 4 is a display panel mother board whole surface evaporation schematic diagram provided by an embodiment of the present application. Referring to Figure 4Exemplarily, a display panel motherboard includes a first edge 110 extending along a first direction X1 and a second edge extending along a second direction X2, the first direction X1 being perpendicular to the second direction X2. The display panel motherboard includes a substrate 100, a plurality of sub-panel groups 200, a plurality of first test pad groups 300, and a plurality of second test pad groups 400. The substrate 100 is configured to provide a support structure for some components included in the display panel motherboard. The plurality of sub-panel groups 200 are core components for the display panel motherboard to realize image display. The plurality of sub-panel groups 200 are arranged in sequence along the first direction X1 of the substrate 100, and each of the plurality of sub-panel groups 200 includes a plurality of sub-panels 210 arranged in sequence along the second direction X2 perpendicular to the first direction X1 on the substrate 100. The plurality of first test pad groups 300 are arranged in one-to-one correspondence with the plurality of sub-panels 210, and the first test pad groups 300 are configured to input first test signals to the corresponding sub-panels 210. The plurality of sub-panels 210 in each of the plurality of sub-panel groups 200 simultaneously receive the first test signals. The plurality of second test pad groups 400 are arranged in one-to-one correspondence with the plurality of sub-panel groups 200, and the second test pad groups 400 are simultaneously connected to the sub-panels 210 in the corresponding sub-panel groups 200. The second test pad groups 400 are configured to input second test signals different from the first test signals to the sub-panels 210 in the corresponding sub-panel groups 200.

[0051] Specifically, the plurality of sub-panel groups 200 are arranged in sequence along the first direction X1, and the plurality of sub-panels 210 are arranged in sequence along the second direction X2, so as to ensure that the plurality of sub-panels 210 are arranged in a rectangular array on the substrate 100, thereby ensuring the overall uniformity of the display panel motherboard. In this embodiment, the substrate 100 is in a rectangular shape, and the first edge 110 of the substrate 100 extends along the first direction X1. The display panel motherboard includes the first edge 110 and a second edge adjacent to the first edge. The first edge 110 is provided with a plurality of second test pad groups 400 connected to different signal main lines 411. The plurality of second test pad groups 400 are arranged in sequence along the first direction X1 and located close to the first edge 110. The second edge is adjacent to the first edge.

[0052] For example, the plurality of sub-panel groups 200 are eight groups arranged in sequence along the first direction X1 of the substrate 100. Each of the eight groups of sub-panel groups 200 includes four sub-panels 210 arranged in sequence along the second direction X2.

[0053] The light-on test device needs to be matched in the light-on test. The light-on test device includes a plurality of test heads, and the plurality of test heads are arranged one by one corresponding to the first test pad group 300 of each sub-panel 210 in the sub-panel group 200. When the light-on test is performed, the light-on test device can simultaneously test each sub-panel 210 in the sub-panel group 200. Since each sub-panel 210 in the same sub-panel group 200 is connected in parallel, the light-on test between the sub-panels 210 in the same sub-panel group 200 will not cause light-on abnormality due to signal shunting when the light-on test is simultaneously performed. Specifically, in the present embodiment, one sub-panel group 200 includes four sub-panels 210 arranged in the second direction X2 in sequence, and the light-on test device includes four test heads arranged in the second direction X2 in sequence. During the test, the four test heads simultaneously connect to the first test pad group 300 of the four sub-panels 210 in the sub-panel group 200. Since each sub-panel 210 in the same sub-panel group 200 is connected to each other, the four sub-panels 210 arranged in the second direction X2 in sequence will not cause light-on abnormality due to shunting when the light-on test is performed. The first test pad group 300 is used for testing, and the light-emitting function of each sub-panel and whether it is normal are tested.

[0054] The substrate 100 plays a key role in the performance and stability of the entire display panel mother board. The substrate 100 used in the present display panel mother board is made of glass material with good flatness, insulation and thermal stability. This is because the glass material can provide a stable attachment basis for subsequent sub-panel groups, test pads and other components, ensuring that the relative positions between the components remain accurate during the manufacture and use of the display panel mother board, and avoiding display abnormalities caused by deformation of the substrate 100.

[0055] As Figure 6The first test pad group 300 is used to input a first test signal to the corresponding sub-panel 210 during the lighting test process of the display panel motherboard, for detecting the light emitting performance of the sub-panel. The plurality of first test pad groups 300 are connected to the plurality of sub-panels 210 one by one. This precise correspondence ensures that each sub-panel 210 can independently receive a test signal, thereby achieving individual detection of each sub-panel 210. The first test pad group 300 adopts a metal material with good electrical conductivity, such as copper, silver, aluminum, etc. These metal materials have low resistance, which can effectively reduce the loss of the test signal during transmission, ensuring that the test signal can be accurately and stably transmitted to the sub-panel 210. In terms of manufacturing process, the first test pad group 300 is usually manufactured by photolithography and etching process. First, a layer of photoresist is coated on the substrate 100, and then the designed first test pad group pattern is transferred to the photoresist by photolithography technology. Then, the unwanted metal layer is removed by etching process, thereby forming the precise structure of the first test pad group 300. During the etching process, the etching time and the concentration of the etching solution need to be strictly controlled to ensure the dimensional accuracy and edge quality of the first test pad group 300. The accuracy of the photolithography process directly affects the size and shape of the first test pad group, while the control of the etching process relates to the surface flatness and edge perpendicularity of the pad. If the etching time is too long or the etching solution concentration is too high, it may cause the pad size to become smaller or the edge to appear jagged; if the etching time is too short or the etching solution concentration is too low, it may cause excess metal layer to remain, affecting the conductivity of the pad and the accuracy of the test.

[0056] The layout of the first test pad group 300 on the substrate 100 adopts a rectangular array arrangement. This layout has multiple advantages. On the one hand, since the sub-panels 210 are arranged in a rectangular array on the substrate 100, the rectangular array arrangement of the first test pad group 300 facilitates connection with the sub-panels 210, ensuring the accuracy and stability of the connection. On the other hand, the rectangular array arrangement is conducive to the wiring and transmission of the test signal, allowing the test signal to be evenly distributed to each first test pad group 300, improving the efficiency and accuracy of the test. With the continuous development of display technology, the performance requirements for the first test pad group are becoming higher and higher. In order to meet the higher precision test requirements, a special conductive polymer can be coated on the surface of the first test pad group. These conductive polymers not only have good electrical conductivity, but also can enhance the electrical connection stability between the test pad and the sub-panel, reduce noise interference during signal transmission, and further improve the accuracy of the test.

[0057] During the test, the first test signal usually adopts an electrical signal with different frequencies and amplitudes. By inputting different first test signals to the sub-panel 210, the luminous performance, response speed, current-voltage characteristics and other parameters of the sub-panel can be detected. For example, by inputting a pulse signal with a specific frequency, the response time of the sub-panel, i.e. the time delay from receiving the signal to starting to emit light, can be detected. By analyzing these test data, problems existing in the sub-panel, such as uneven luminous brightness and slow response speed, can be found in time, so as to perform quality screening and optimization on the display panel motherboard.

[0058] The second test pad group 400 is used to be arranged in one-to-one correspondence with the plurality of sub-panel groups 200, and is connected with the sub-panels 210 in the corresponding sub-panel group 200 at the same time. Its function is to input the second test signal to the sub-panels 210 in the corresponding sub-panel group 200, for overall performance testing of the sub-panel group. Referring to Figure 5 During the unit test, the second test signal is transmitted to the sub-panels 210 in the corresponding sub-panel group 200 through the second test pad group 400. Similar to the first test pad group 300, the material of the second test pad group 400 is also selected from at least one of metals with good electrical conductivity, such as copper, silver and aluminum. In terms of connection mode, the second test pad group 400 is electrically connected with the sub-panels 210 through the signal lines 410. Among them, the second test pad group 400 is used to perform unit test to test the luminous function and normality of each sub-panel.

[0059] In order to improve the test accuracy and reliability of the second test pad group 400, the design of the second test pad group 400 can be optimized, such as adopting a multi-layer metal structure, adding one or more metal layers with special properties on the basis of the traditional metal pad. For example, a layer of gold (Au) is plated on the surface of the copper pad. Gold has good oxidation resistance and electrical conductivity, which can effectively improve the service life and signal transmission performance of the pad. At the same time, some small protrusions or groove structures can be arranged on the surface of the pad to increase the contact area between the pad and the test fixture and improve the stability of the connection. In addition, intelligent test pad technology can also be adopted to integrate some sensors or processors in the second test pad group 400 to monitor the transmission of the test signal and the performance parameters of the sub-panel in real time, and to preliminarily analyze and process the test results, thereby improving the intelligent level of the test.

[0060] The signal lines 410 connect the second test pad group 400 and the first test pad group 300, and a plurality of signal lines 410 are arranged in one-to-one correspondence with the plurality of sub-panel groups 200, so as to ensure that each sub-panel group 200 can independently receive the test signal.

[0061] As Figure 5As shown, each signal line 410 includes a signal main line 411 and a plurality of signal branch lines 412 connected to the signal main line 411. The signal main line 411 is connected to the second test pad group 400, and the plurality of signal branch lines 412 are connected to the plurality of first test pad groups 300 one by one. This structural design enables the second test signal to be transmitted from the second test pad group 400 to each signal branch line 412 through the signal main line 411, and ultimately to the sub-panel 210.

[0062] As shown, the signal branch lines 412 are arranged in parallel with each other, and the parallel connection has a plurality of advantages. First, parallel connection can ensure that each first test pad group 300 can obtain the same test signal voltage, avoiding signal differences caused by different signal transmission paths. Second, parallel connection improves the reliability of test signal transmission to a certain extent. When a signal branch line 412 fails, other branch lines can still transmit signals normally, without affecting the entire test process. Figure 5 As shown, the signal branch lines 412 are arranged in parallel with each other, and the parallel connection has a plurality of advantages. First, parallel connection can ensure that each first test pad group 300 can obtain the same test signal voltage, avoiding signal differences caused by different signal transmission paths. Second, parallel connection improves the reliability of test signal transmission to a certain extent. When a signal branch line 412 fails, other branch lines can still transmit signals normally, without affecting the entire test process.

[0063] Figure 5 As shown, the signal branch lines 412 extend along the first direction X1, and the plurality of signal branch lines 412 are arranged in sequence along the second direction X2. This layout matches the arrangement of the sub-panel group 200 and the sub-panel 210, facilitating efficient transmission of test signals. The signal branch lines 412 extending along the first direction X1 can reduce the length of signal transmission and reduce signal transmission loss. The signal branch lines 412 arranged in sequence along the second direction X2 facilitate connection with the first test pad group 300, ensuring the accuracy and stability of the connection.

[0064] In addition, the signal main line 411 extends along the second direction X2, and the plurality of signal branch lines 412 connected to the same sub-panel 210 in the same sub-panel group 200 are connected to the same signal main line 411. The length needs to be matched according to the width of the display panel motherboard. The longer signal main line 411 can simultaneously connect all sub-panels 210 in a sub-panel group 200. The second test pad group 400 is located at both ends of the signal main line 411 and at the first edge 110 of the substrate 100, facilitating protection by the baffle 500 during evaporation and reducing external interference. This layout also simplifies the wiring complexity of the signal lines and improves overall test efficiency. By precisely controlling the length and position of the signal lines, the stability and consistency of the test signals are ensured, further optimizing the performance of the display panel motherboard. In addition, the signal main line 411 is made of high-conductivity material, effectively reducing signal transmission loss and improving signal transmission speed. Precise length design and material selection ensure the stability and efficiency of the test signals, further improving the overall performance and reliability of the display panel motherboard.

[0065] ​In this embodiment, the plurality of signal lines 410 are arranged in one-to-one correspondence with the plurality of sub-panel groups 200, and the same signal line 410 is connected to the corresponding first test pad group 300 and second test pad group 400 at the same time. In terms of connection mode, the second test pad group 400 is electrically connected to the sub-panel 210 through the signal line 410. The second test pad group 400 is located at both ends of the signal main line 411 and at the position of the first edge 110 of the substrate 100. Among them, the display panel mother board includes the first edge 110 and the second edge. The plurality of second test pad groups 400 are located close to the first edge 110, and the plurality of second test pad groups 400 are arranged along the first direction X1, and the first edge 110 is provided with a plurality of second test pad groups 400 connected to different signal main lines 411 at intervals; the second edge is adjacent to the first edge 110. This position design has many considerations. First, the second test pad group 400 is arranged at the position close to the first edge 110 of the substrate 100, which facilitates the connection of the test interface during the manufacturing process of the display panel mother board. On the production line, the test equipment can quickly and accurately connect with the second test pad group 400 located at the first edge 110 through a special test fixture, improving the efficiency of the test. In the test process, the type and parameters of the second test signal are set according to different test purposes. For example, when performing the brightness uniformity test of the sub-panel group, the second test signal can be a constant voltage signal, and by detecting the luminous brightness of each sub-panel 210 under the voltage signal, it is judged whether the brightness uniformity of the sub-panel group meets the requirements. If it is found that the luminous brightness of a certain sub-panel is greatly different from that of other sub-panels, it means that the sub-panel may have a problem and needs to be further checked and repaired.

[0066] In this embodiment, the baffle 500 is arranged at the position of the first edge 110 of the substrate 100, and its main function is to shield the second test pad group 400. In the evaporation process of the display panel mother board, the baffle 500 plays a key role. When the display panel mother board is subjected to full-area evaporation, the baffle 500 can effectively shield the second test pad group 400, preventing the deposition of evaporation material on the second test pad group 400, thereby ensuring the conductivity and test accuracy of the second test pad group 400. The material selection of the baffle 500 needs to consider multiple factors, such as high temperature resistance, chemical stability and mechanical strength, etc. Generally, the baffle 500 is made of ceramic material or metal material. Ceramic material has good high temperature resistance and chemical stability, and can withstand high temperature and chemical gas erosion in the evaporation process without causing pollution to the test pad and other components. Metal material has high mechanical strength, which can ensure the stability and reliability of the baffle 500 during use. When designing the shape of the baffle, the shape of the display panel mother board and the position of the second test pad group need to be considered to ensure that the baffle can completely cover the second test pad group.

[0067] In the production process of the display panel motherboard, the installation and disassembly of the baffle 500 are carried out according to the operation procedures. Before the evaporation process, it is necessary to accurately install the baffle 500 at the position of the first edge 110 of the substrate 100, and ensure the shielding effect of the second test pad group 400. During the installation process, a special clamp or positioning device needs to be used to ensure the accurate position of the baffle. Specifically, a camera can be installed on the clamp, and the camera can accurately determine whether the baffle completely shields the second test pad group. After the evaporation is completed, the baffle 500 is disassembled, and care should be taken to avoid damaging the display panel motherboard during disassembly. After each use, the baffle 500 can be cleaned and inspected to ensure that the surface is free of residual evaporation materials and impurities, so as to ensure the performance of the next use. With the continuous progress of the display panel motherboard manufacturing process, the performance requirements of the baffle are also constantly improving. For example, in some high-precision evaporation processes, the shielding precision of the baffle is extremely high. In order to meet this requirement, laser processing technology can be used to manufacture the edge of the baffle 500. By accurately controlling the energy and processing parameters of the laser, a very smooth and accurate edge can be obtained, effectively improving the shielding effect of the baffle 500. In addition, a self-cleaning coating can be applied to the surface of the baffle. Under light conditions, the coating can decompose the organic impurities on the surface, keep the baffle 500 clean, reduce the cleaning frequency, and improve the production efficiency.

[0068] In operation, first, the baffle 500 is used to shield the second test pad group 400 of the first edge 110 of the substrate 100 during the whole evaporation of the display panel motherboard, so as to avoid the deposition of evaporation materials on the second test pad group 400 during evaporation, so as to directly perform unit testing after evaporation is completed, timely judge the evaporation effect, reduce the time cost of waiting for the detection result, and improve the production efficiency. And after the subsequent process is completed, the light test is carried out normally. Since each sub-panel 210 in each sub-panel group 200 is connected in parallel with each other, and the first test pad group corresponding to each sub-panel is connected with the same second test pad group, each sub-panel 210 in a column of sub-panels 210 simultaneously receives the first test signal, effectively avoiding the shunt of the first test signal of the light test, reducing the risk of light test abnormity, and ensuring the accuracy of the test result. In addition, the design of the baffle 500 also needs to consider the high temperature resistance performance to adapt to the high temperature environment in the evaporation process, prevent deformation or damage, and further improve the overall manufacturing quality of the display panel motherboard. In a high temperature environment, the material selection of the baffle 500 is particularly important, and materials with high temperature resistance and strong stability such as ceramics or special alloys need to be selected. At the same time, the structure design should also consider the heat dissipation performance to avoid performance degradation due to high temperature. Through optimization design, the baffle 500 not only can effectively shield the pad, but also can maintain stability in the high temperature evaporation process, and ensure the smooth progress of the display panel motherboard manufacturing process.

[0069] Based on the same inventive concept, the present application also provides a preparation method of the display panel mother board as described above, and the preparation method specifically comprises the following steps:

[0070] The second test pad group 400 located on the first edge 110 of the display panel mother board is shielded by the baffle 500;

[0071] The display panel mother board after shielding is subjected to evaporation;

[0072] After evaporation, the baffle 500 is removed, and the second test signal is input to the sub-panel 210 in the corresponding sub-panel group 200 through the second test pad group 400.

[0073] In the present application, the baffle 500 shields the second test pad group 400 during evaporation, so as to avoid the deposition of evaporation material on the second test pad group 400 during evaporation. After evaporation is completed, the second test signal can be directly input to the second test pad group 400 for unit testing, so as to test whether the light-emitting condition of the sub-panel group 200 in the second direction X2 is normal, to obtain the evaporation effect in time, and to greatly improve the production efficiency.

[0074] Based on the same inventive concept, as shown in Figure 7 , the present application also provides an evaporation device for evaporating the display panel mother board as described above, and the evaporation device comprises an evaporation chamber 10, a support structure 30, an evaporation source 20 and a baffle 500. The support structure 30 is arranged in the evaporation chamber 10 and is used for supporting the display panel mother board. The evaporation source 20 is arranged between a pair of support structures 30 and is used for evaporating the display panel mother board.

[0075] The baffle 500 is arranged to cover a plurality of second test pad groups 400 on the first edge 110 of the display panel mother board.

[0076] It should be noted that the evaporation source 20 comprises a rotatable nozzle, which can control the direction and range of the evaporation material. As Figure 8 , the evaporation source 20 in the present embodiment can simultaneously or separately evaporate the display panel mother boards on the two support structures 30 by the rotatable nozzle, thereby improving the evaporation efficiency. The evaporation source 20 is movably arranged, thereby improving the uniformity of evaporation and effectively improving the evaporation quality. By using the baffle 500 to shield the second test pad group 400 during evaporation, the deposition of evaporation material on the second test pad group 400 during evaporation is avoided, so as to directly perform unit testing after evaporation is completed, to timely judge the evaporation effect, to reduce the time cost of waiting for the detection result, and to improve the production efficiency.

[0077] It is noted that some embodiments have been described as providing a particular structure or combination of elements. It is intended that elements can be combined in other configurations that are not specifically described in the embodiments. Thus, for example, a presently available mechanism can be used instead of or in addition to the mechanism described herein to perform a described function or action. Again, where described implementations include "more than one" element or component, implementations can include two or more such elements or components. Where described implementations include "at least one" element or component, implementations can include one or more such elements or components. Where described implementations include "at least one of two or more specified elements, implementations can include any single one of the specified elements, or any combination of two or more of the specified elements.

[0078] It is intended that the disclosure and examples presented herein cover all such alternatives, modifications, and variations of the embodiments of the present disclosure as fall within the broad scope of the appended claims. Accordingly, any and all such modifications, variations, or equivalents that fall within the scope of the present disclosure should be construed as being within the scope of the present disclosure.

Claims

1. A display panel motherboard, characterized in that, The display panel motherboard comprises a first edge extending along a first direction and a second edge extending along a second direction, the first direction being perpendicular to the second direction, and the display panel motherboard comprises: a substrate; a plurality of sub-panel groups, the plurality of sub-panel groups being arranged in sequence along a first direction of the substrate, and each of the sub-panel groups comprising a plurality of sub-panels, and the plurality of sub-panels in the same sub-panel group being arranged in sequence along a second direction on the substrate; a plurality of first test pad groups, the plurality of first test pad groups being arranged in one-to-one correspondence with the plurality of sub-panels, the first test pad groups being configured to input first test signals to the corresponding sub-panels, and the plurality of sub-panels in each of the sub-panel groups simultaneously receiving the first test signals; a plurality of second test pad groups, the plurality of second test pad groups being arranged in one-to-one correspondence with the plurality of sub-panel groups, the second test pad groups being simultaneously connected to the sub-panels in the corresponding sub-panel groups, and the second test pad groups being configured to input second test signals different from the first test signals to the sub-panels in the corresponding sub-panel groups; and a plurality of signal lines, the plurality of signal lines being electrically connected to the plurality of sub-panel groups, and each of the signal lines being simultaneously connected to the corresponding first test pad group and second test pad group, each of the signal lines comprising a signal main line and a plurality of signal branch lines connected to the signal main line, the signal main line being connected to the second test pad group, and the plurality of signal branch lines being connected to the plurality of first test pad groups in one-to-one correspondence.

2. The display panel motherboard of claim 1, wherein, The plurality of signal branch lines are arranged in parallel with each other, the signal branch lines extend along the first direction, the plurality of signal branch lines extend along the second direction.

3. The display panel mother board of claim 1, wherein, The signal main line extends along the second direction, and the plurality of signal branch lines connected to the plurality of sub-panels in the same sub-panel group are connected to the same signal main line.

4. The display panel mother board of claim 1, wherein, The second test pad group is located at both ends of the signal main line.

5. The display panel motherboard of claim 1, wherein the plurality of second test pad groups are located close to the first edge, the plurality of second test pad groups are arranged in sequence along the first direction, a plurality of second test pad groups connected to different signal main lines are arranged at intervals on the first edge, and the second edge is adjacent to the first edge.

6. The display panel mother board of claim 1, wherein, The first test pad groups of the plurality of sub-panels arranged in the same row along the first direction are located in the same row.

7. The display panel mother board of claim 1, wherein, The first test signal comprises electrical signals of different frequencies and different amplitudes, and / or the second test signal comprises a constant voltage signal.

8. The display panel mother board of claim 1, wherein, The plurality of sub-panel groups are arranged at intervals along the first direction.

9. The display panel mother board of claim 1, wherein, The plurality of sub-panels are arranged at intervals along the second direction.

10. The display panel mother board of claim 1, wherein, The first test pad groups are arranged in a rectangular array on the substrate.

11. The display panel mother board of claim 1, wherein, The materials of the first test pad groups and the second test pad groups comprise conductive metals. The conductive metals comprise at least one of copper, silver, and aluminum.

12. A method of manufacturing a display panel mother sheet according to any one of claims 1 to 11, characterized in that, The preparation method comprises the following steps: A baffle is used to shield a second test pad group on the first edge of the display panel mother board; The display panel mother board is subjected to evaporation after being shielded; The baffle is removed after evaporation and a second test signal is input to the sub-panels in the sub-panel group through the second test pad group.

13. An evaporation apparatus, characterized by An evaporation apparatus for evaporating a display panel mother board as claimed in any one of claims 1 to 11, the evaporation apparatus comprising: An evaporation chamber; A support structure arranged in the evaporation chamber for supporting the display panel mother board; An evaporation source arranged between a pair of the support structures for evaporating the display panel mother board; A baffle configured to cover a plurality of second test pad groups on a first edge of the display panel mother board.

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