Display device

Abstract

The display device may include: a substrate including a display area including sub-pixels and a non-display area adjacent to the display area; a first electrode disposed on the substrate; a second electrode disposed on the substrate; a light emitting structure disposed on the first electrode and the second electrode in the display area; and a third electrode disposed on the light emitting structure in the display area, and the third electrode disposed on the second electrode in at least a portion of the non-display area.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0184949, filed with the Korean Intellectual Property Office (KIPO) on December 18, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0004] As information technology develops, the importance of display devices as a connection medium between users and information is emerging. In response, the use of display devices such as liquid crystal display devices and organic light emitting display devices is increasing.

[0005] Recently, head-mounted display (HMD) devices are being developed. An HMD is a display device that realizes virtual reality (VR) or augmented reality (AR), in which a user wears an HMD in the form of glasses or a helmet, and a focus is formed at a distance close to the user's eyes. A high-resolution panel can be applied to the HMD, and thus, pixels that can be applied to the high-resolution panel are desired. Summary of the Invention

[0006] One aspect of the present disclosure is to provide a display device that reduces leakage current.

[0007] Another aspect of the present disclosure is to provide a method of manufacturing a display device.

[0008] To achieve the aspects of the present disclosure, a display device may include: a substrate including a display area including a plurality of sub-pixels and a non-display area adjacent to the display area; a first electrode disposed on the substrate; a second electrode disposed on the substrate; a light-emitting structure disposed on the first electrode and the second electrode in the display area; and a third electrode disposed on the light-emitting structure in the display area, and the third electrode is disposed on the second electrode in at least a part of the non-display area.

[0009] In an embodiment, the third electrode may be in electrical contact with the second electrode in at least the part of the non-display area.

[0010] In an embodiment, the third electrode may be electrically connected to the first electrode in at least the part of the non-display area.

[0011] In an embodiment, the third electrode may be electrically connected to a conductive pattern disposed under the first electrode in at least the part of the non-display area.

[0012] In an embodiment, the display device may further include an insulating layer disposed on the first electrode and including an opening exposing at least a portion of the first electrode, and the second electrode may be disposed on the insulating layer.

[0013] In an embodiment, the third electrode may extend to the insulating layer in at least a portion of the non-display area.

[0014] In an embodiment, the light-emitting structure may fill the opening, and the light-emitting structure may be entirely disposed on the insulating layer in the display area.

[0015] In an embodiment, the light-emitting structure may include: a first light-emitting unit; a second light-emitting unit disposed on the first light-emitting unit; and a connection layer disposed between the first light-emitting unit and the second light-emitting unit, and the connection layer electrically connects the first light-emitting unit and the second light-emitting unit.

[0016] In an embodiment, at the lowest gray level, the voltage applied to the second electrode may be less than the voltage of the first electrode.

[0017] In an embodiment, the second electrode may be disposed in a boundary region between at least two of the plurality of sub-pixels, and the at least two of the plurality of sub-pixels may be adjacent to each other.

[0018] To achieve aspects of the present disclosure, a method of manufacturing a display device may include: providing a substrate including a display area including a plurality of sub-pixels and a non-display area disposed adjacent to the display area; forming a first electrode on the substrate; applying an insulating layer to cover the first electrode; forming a second electrode on the insulating layer; exposing at least a portion of the first electrode by patterning the insulating layer; forming a light-emitting structure on the first electrode and the second electrode in the display area; and forming a third electrode on the light-emitting structure.

[0019] In an embodiment, the third electrode may be formed on the second electrode in at least a portion of the non-display area.

[0020] In an embodiment, the third electrode may electrically contact the second electrode in at least a portion of the non-display area.

[0021] In an embodiment, the third electrode may be electrically connected to the first electrode in at least a portion of the non-display area.

[0022] In an embodiment, the third electrode may be electrically connected to a conductive pattern disposed under the first electrode in at least a part of the non-display region.

[0023] In an embodiment, the third electrode may be formed on the light-emitting structure in the display region, and the third electrode is disposed on the insulating layer in at least a part of the non-display region.

[0024] In an embodiment, the light-emitting structure may fill an opening of the insulating layer exposing at least a part of the first electrode, and the light-emitting structure may be entirely disposed on the insulating layer in the display region.

[0025] In an embodiment, the light-emitting structure may include: a first light-emitting unit; a second light-emitting unit disposed on the first light-emitting unit; and a connection layer disposed between the first light-emitting unit and the second light-emitting unit and electrically connecting the first light-emitting unit and the second light-emitting unit.

[0026] In an embodiment, at the lowest gray level, the voltage applied to the second electrode may be less than the voltage of the first electrode.

[0027] In an embodiment, the second electrode may be disposed in a boundary region between at least two of the plurality of sub-pixels, and at least two of the plurality of sub-pixels may be adjacent to each other.

[0028] A display device according to an embodiment of the present disclosure may reduce leakage current flowing between adjacent sub-pixels among the plurality of sub-pixels by forming a current path through which leakage current may flow via a leakage electrode.

[0029] A display device according to an embodiment of the present disclosure may reduce noise caused by coupling between adjacent sub-pixels by forming a leakage electrode in a boundary region between sub-pixels and applying a constant voltage to the leakage electrode.

[0030] A method of manufacturing a display device according to an embodiment of the present disclosure may reduce the number of contact holes and masks used in the process by connecting a cathode electrode to an anode electrode or a conductive pattern in a region where a light-emitting structure is not formed.

[0031] However, the effects of the present disclosure are not limited to the above effects, and various extensions may be made without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other features of the present disclosure will become more apparent by describing embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0033] Figure 1 is a schematic block diagram showing an embodiment of a display device;

[0034] Figure 2 is showing Figure 1 an embodiment of any one of a plurality of sub-pixels of;

[0035] Figure 3 is showing Figure 1 an embodiment of a schematic plan view of a display panel of;

[0036] Figure 4 is showing Figure 3 an exploded schematic perspective view of a part of a display panel of;

[0037] Figure 5 is showing Figure 4 an embodiment of a schematic plan view of a pixel of;

[0038] Figure 6 is a schematic cross-sectional view taken along line I-I' of; Figure 5 ;

[0039] Figure 7 is showing an embodiment of a light-emitting structure included in any one of a first light-emitting element to a third light-emitting element included in; Figure 6 ;

[0040] Figure 8 is showing an embodiment of a light-emitting structure included in any one of a first light-emitting element to a third light-emitting element included in; Figure 6 ;

[0041] Figure 9 is showing Figure 4 another embodiment of any one of a plurality of pixels of;

[0042] Figure 10 is showing Figure 4 yet another embodiment of any one of a plurality of pixels of;

[0043] Figure 11 is a flowchart showing a method of manufacturing a display device according to an embodiment of the present disclosure;

[0044] Figure 12 is showing Figure 11 a schematic view of step S200 of;

[0045] Figure 13 is showing Figure 11 a schematic view of step S300 of;

[0046] Figure 14 is showing Figure 11Schematic diagram of step S400;

[0047] Figure 15 is a schematic diagram showing Figure 11 Schematic diagram of step S500;

[0048] Figure 16 is a schematic diagram showing Figure 11 Schematic diagram of step S600;

[0049] Figure 17 is a schematic diagram showing Figure 11 Schematic diagram of step S700;

[0050] Figure 18 is a schematic cross-sectional view of a part of a display device according to an embodiment of the present disclosure;

[0051] Figure 19 is a schematic diagram showing Figure 6 circuits of a first light-emitting element, a second light-emitting element, and a leakage element;

[0052] Figure 20 is a schematic diagram showing a circuit of leakage current;

[0053] Figure 21 is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure;

[0054] Figure 22 is a schematic block diagram showing an embodiment of a display system;

[0055] Figure 23 is a schematic diagram showing Figure 22 an application example of the display system; and

[0056] Figure 24 is a schematic diagram showing a head-mounted display device worn by a user. Detailed Description of the Embodiments

[0057] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present disclosure are described, and descriptions of other parts are omitted to avoid obscuring the subject matter of the present disclosure. In addition, the present disclosure may be implemented in other forms and is not limited to the embodiments described herein. However, the embodiments described herein are provided to describe in sufficient detail to enable those skilled in the art to which the present disclosure pertains to easily implement the technical spirit of the present disclosure.

[0058] Unless the context clearly indicates otherwise, as used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms.

[0059] Throughout the specification, when a part is "connected" to another part, this includes not only the case where the part is "directly connected", but also the case where the part is "indirectly connected" to another element, with yet another element intervening between the part and the other element. The terms used herein are for describing specific embodiments and are not intended to limit the disclosure. Throughout the specification, unless otherwise stated, when a particular part "includes" something, this means that the part may also include another component without excluding the other component. "At least any one of X, Y, and Z" and "at least any one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). Here, "and / or" includes all combinations of one or more corresponding configurations. For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the conjunctive or disjunctive sense and can be understood to be equivalent to "and / or".

[0060] In the specification and claims, for purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0061] Here, terms such as "first" and "second" may be used to describe various components, but these components are not limited to these terms. These terms are used to distinguish one component from another. Thus, without departing from the scope disclosed herein, the first component may refer to the second component.

[0062] Spatial relative terms such as "beneath" and "above" may be used for descriptive purposes to describe the relationship between one element or feature and another (or other) element or feature as shown in the drawings. In addition to the directions depicted in the drawings, spatial relative terms are also intended to include other directions in use, operation, and / or manufacture. For example, when the device shown in the drawings is turned upside down, an element depicted as being "beneath" another element or feature is in the direction of being "above" the other element or feature. Thus, in an embodiment, the term "beneath" can include both upward and downward directions. Additionally, the device may be oriented in other directions (e.g., rotated 90 degrees or in other directions), and thus the spatial relative terms used herein are to be interpreted accordingly.

[0063] The various embodiments are described with reference to the drawings that schematically illustrate ideal embodiments. Accordingly, it will be appreciated that the shapes can vary, for example, according to tolerances and / or manufacturing techniques. Thus, the embodiments disclosed herein should not be construed as limited to the specific shapes shown and should be construed to include, for example, shape variations that occur due to manufacturing. As described above, the shapes shown in the drawings may not represent the actual shapes of the regions of the device, and the embodiments are not limited thereto.

[0064] The terms "overlap" or "overlapped" mean that a first object can be above, below, or to one side of a second object, and vice versa. In addition, the term "overlap" can include laminating, stacking, facing or confronting, extending over, covering, or partially covering, or any other suitable term that one of ordinary skill in the art would recognize and understand.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms, such as those defined in a general dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0066] Figure 1 is a schematic block diagram showing an embodiment of a display device.

[0067] Referring to Figure 1 , the display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0068] The display panel 110 may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through first gate lines GL1 to m-th gate lines GLm. The sub-pixels SP may be connected to the data driver 130 through first data lines DL1 to n-th data lines DLn. Each of m and n is an integer greater than 0.

[0069] Each of the plurality of sub-pixels SP may include at least one light-emitting element configured to generate light. Accordingly, each of the plurality of sub-pixels SP may generate light of a specific color (such as red, green, blue, cyan, magenta, or yellow). Two or more of the sub-pixels SP among the sub-pixels SP may constitute one pixel PXL. For example, as Figure 1 shown, three sub-pixels SP may constitute one pixel PXL.

[0070] The gate driver 120 can be connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 can output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS can include a start signal indicating the start of each frame and a horizontal synchronization signal for outputting the gate signal synchronously with the timing of applying the data signal, etc.

[0071] In an embodiment, the first emission control lines EL1 to the m-th emission control lines ELm connected to the sub-pixels SP in the row direction can also be provided. The gate driver 120 can include an emission control driver configured to control the first emission control lines EL1 to the m-th emission control lines ELm, and the emission control driver can operate under the control of the controller 150.

[0072] The gate driver 120 can be provided on one side of the display panel 110. However, the embodiment is not limited thereto. For example, the gate driver 120 can be divided into two or more physically and / or logically separate drivers, and such drivers can be provided on one side of the display panel 110 and on the other side of the display panel 110 opposite to that side. As described above, according to the embodiment, the gate driver 120 can be provided around the display panel 110 in various shapes.

[0073] The data driver 130 can be connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the n-th data line DLn. The data driver 130 can receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS. In an embodiment, the data control signal DCS can include a source start pulse, a source shift clock, a source output enable signal, etc.

[0074] The data driver 130 can apply a data signal having a gray-scale voltage corresponding to the image data DATA to the first data line DL1 to the n-th data line DLn using the voltage from the voltage generator 140. In the case where the gate signal is applied to each of the first gate line GL1 to the m-th gate line GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLm. Therefore, the corresponding sub-pixels SP can generate light corresponding to the data signal. Therefore, an image can be displayed on the display panel 110.

[0075] In an embodiment, the gate driver 120 and the data driver 130 can include complementary metal oxide semiconductor (CMOS) circuit elements.

[0076] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 may be configured to generate multiple voltages and supply the generated voltages to components of the display device 100. For example, the voltage generator 140 may be configured to generate a voltage by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0077] The voltage generator 140 may generate a first power voltage VDD and a second power voltage VSS, and the generated first power voltage VDD and second power voltage VSS may be supplied to the sub-pixel SP. The first power voltage VDD may have a relatively high voltage level, and the second power voltage VSS may have a voltage level lower than that of the first power voltage VDD. In other embodiments, the first power voltage VDD or the second power voltage VSS may be provided by an external device of the display device 100.

[0078] The voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a predetermined or selected reference voltage may be applied to the first data line DL1 to the nth data line DLn, and the voltage generator 140 may generate such a reference voltage.

[0079] The controller 150 may control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0080] The controller 150 may convert the input image data IMG such that the input image data IMG is suitable for the display device 100 or the display panel 110, and the controller 150 outputs image data DATA. In an embodiment, the controller 150 may output the image data DATA by aligning the input image data IMG such that the input image data IMG is suitable for the sub-pixels SP in units of rows.

[0081] Two or more components among the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. As Figure 1As shown, data driver 130, voltage generator 140, and controller 150 may be included in driver integrated circuit DIC. Data driver 130, voltage generator 140, and controller 150 may be functionally separate components within one driver integrated circuit DIC. In other embodiments, at least one of data driver 130, voltage generator 140, and controller 150 may be provided as a component different from driver integrated circuit DIC.

[0082] Display device 100 may include at least one temperature sensor 160. Temperature sensor 160 may be configured to sense the temperature around temperature sensor 160 and generate temperature data TEP indicating the sensed temperature. In an embodiment, temperature sensor 160 may be disposed adjacent to display panel 110 and / or driver integrated circuit DIC.

[0083] Controller 150 may control various operations of display device 100 in response to temperature data TEP. In an embodiment, controller 150 may adjust the brightness of an image output from display panel 110 in response to temperature data TEP. For example, controller 150 may control data signals and first power voltage VDD and second power voltage VSS by controlling components such as data driver 130 and voltage generator 140.

[0084] Figure 2 is a schematic block diagram showing Figure 1 an example of any one of a plurality of sub-pixels. In Figure 2 among, Figure 1 among the plurality of sub-pixels SP of, the sub-pixel SPij arranged in the i-th row (i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is an integer greater than or equal to 1 and less than or equal to n) is shown as an example.

[0085] Referring to Figure 2 , sub-pixel SPij may include sub-pixel circuit SPC and light-emitting element LD.

[0086] Light-emitting element LD may be connected between first power voltage node VDDN and second power voltage node VSSN. First power voltage node VDDN may be a node for transmitting Figure 1 the first power voltage VDD of, and second power voltage node VSSN may be a node for transmitting Figure 1 the second power voltage VSS of.

[0087] The anode electrode AE of the light-emitting element LD can be connected to the first power voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD can be connected to the second power voltage node VSSN. For example, the anode electrode AE of the light-emitting element LD can be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0088] The sub-pixel circuit SPC can be connected to Figure 1 the i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm of Figure 1 the i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line ELm of Figure 1 and the j-th data line DLj among the first data line DL1 to the n-th data line DLn of. The sub-pixel circuit SPC can be configured to control the light-emitting element LD according to the signals received through such signal lines.

[0089] The sub-pixel circuit SPC can operate in response to the gate signal received through the i-th gate line GLi. The i-th gate line GLi can include one or more sub-gate lines. In an embodiment, as Figure 2 shown in, the i-th gate line GLi can include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described above, in the case where the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to the gate signals received through the corresponding sub-gate lines.

[0090] The sub-pixel circuit SPC can operate in response to the emission control signal received through the i-th emission control line ELi. In an embodiment, the i-th emission control line ELi can include one or more sub-emission control lines. In the case where the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC can operate in response to the emission control signals received through the corresponding sub-emission control lines.

[0091] The sub-pixel circuit SPC can receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the multiple gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. In response to the emission control signal received through the i-th emission control line ELi, the sub-pixel circuit SPC can adjust the current flowing from the first power voltage node VDDN to the second power voltage node VSSN through the light-emitting element LD according to the stored voltage. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0092] Figure 3 is a schematic plan view showing Figure 1 an embodiment of a display panel.

[0093] Referring to Figure 3 , as Figure 1 an embodiment of the display panel 110, the display panel DP may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be provided around the display area DA.

[0094] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0095] In the case where the display panel DP is used as a display screen of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, or an augmented reality (AR) device, etc., the display panel DP may be positioned very close to the user's eyes. A relatively high integration degree of the sub-pixels SP may be desired. To increase the integration degree of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on the substrate SUB, which is a silicon substrate. A display device 100 (referring to Figure 1 ) including the display panel DP formed on the substrate SUB which is a silicon substrate may be referred to as an OLED on silicon (OLEDoS) display device.

[0096] The sub-pixels SP may be provided in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix shape along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a shape. The first direction DR1 may be a row direction, and the second direction DR2 may be a column direction.

[0097] Two or more of the plurality of sub-pixels SP may constitute one pixel PXL.

[0098] Components for controlling the sub-pixels SP may be provided in the non-display area NDA on the substrate SUB. For example, lines (such as Figure 1 the first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn) connected to the sub-pixels SP may be provided in the non-display area NDA.

[0099] Figure 1At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 may be integrated in the non-display area NDA of the display panel DP. In an embodiment, Figure 1 the gate driver 120 may be mounted on the display panel DP and may be disposed in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented as an integrated circuit separate from the display panel DP. In an embodiment, the temperature sensor 160 may be disposed in the non-display area NDA to sense the temperature of the display panel DP.

[0100] The pad PD may be disposed in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixel SP through a wire. For example, the pad PD may be connected to the sub-pixel SP through the first data line DL1 to the nth data line DLn.

[0101] The pad PD may connect the display panel DP to other components of the display device 100 (refer to Figure 1 ). In an embodiment, the voltage and signals for the operation of the components included in the display panel DP may be provided from Figure 1 the driver integrated circuit DIC. For example, the first data line DL1 to the nth data line DLn may be connected to the driver integrated circuit DIC through the pad PD. For example, the first power voltage VDD (refer to Figure 1 ) and the second power voltage VSS (refer to Figure 1 ) may be received from the driver integrated circuit DIC through the pad PD. For example, in the case where the gate driver 120 is mounted on the display panel DP, the gate control signal GCS (refer to Figure 1 ) may be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0102] In an embodiment, the circuit board may be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. The circuit board may be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC may be mounted on the circuit board to be electrically connected to the pad PD.

[0103] In an embodiment, the display area DA may have various shapes. The display area DA may have a closed-loop shape including straight edges and / or curved edges. For example, the display area DA may have shapes such as a polygon, a circle, a semi-circle, and an ellipse.

[0104] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially circular. In an embodiment, the display panel DP may be bendable, foldable, or rollable. In these cases, the display panel DP and / or the substrate SUB may include materials having flexible properties.

[0105] Figure 4 is a schematic exploded perspective view of a part of the display panel shown. In Figure 3 For the sake of clear and concise description, a part of the display panel DP corresponding to two of the multiple pixels PXL, namely the first pixel PXL1 and the second pixel PXL2, is schematically shown. A part of the display panel DP corresponding to the remaining pixels may be configured similarly. Figure 4 In Figure 3 For the sake of clear and concise description, a part of the display panel DP corresponding to two of the multiple pixels PXL, namely the first pixel PXL1 and the second pixel PXL2, is schematically shown. A part of the display panel DP corresponding to the remaining pixels may be configured similarly.

[0106] Referring to Figure 3 and Figure 4 each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiments are not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0107] In Figure 4 when viewed from a third direction DR3 that intersects the first direction DR1 and the second direction DR2, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 have a quadrilateral shape and have equal dimensions to each other. However, the embodiments are not limited thereto. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be modified to have various shapes.

[0108] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a packaging layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0109] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In still other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0110] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer PCL may be used as at least a part of circuit elements and lines, etc. The conductive patterns may include copper, but the embodiments are not limited thereto.

[0111] The circuit elements may include sub-pixel circuits SPC for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (refer to Figure 2 ). The sub-pixel circuit SPC may include transistors and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping with the semiconductor portion. In an embodiment, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes overlapping with each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3, and an insulating layer is between the electrodes.

[0112] The lines of the pixel circuit layer PCL may include signal lines (such as gate lines, emission control lines, data lines, etc.) connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. These lines may also include lines connected to Figure 2 the first power voltage node VDDN. These lines may also include lines connected to Figure 2 the second power voltage node VSSN.

[0113] The light-emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0114] The anode electrode AE may be disposed on the pixel circuit layer PCL. The anode electrode AE may contact the circuit elements of the pixel circuit layer PCL. The anode electrode AE may include an opaque conductive material capable of reflecting light, but the embodiments are not limited thereto.

[0115] The pixel defining layer PDL may include openings OP exposing a part of each of the plurality of anode electrodes AE. The openings OP of the pixel defining layer PDL may be understood as emission regions corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively.

[0116] In an embodiment, the pixel defining layer PDL may expose a part of each of the plurality of anode electrodes AE, but the present disclosure is not limited thereto. For example, the pixel defining layer PDL may expose the entirety of each of the plurality of anode electrodes AE, and there may be no portion where the pixel defining layer PDL and the anode electrode AE overlap.

[0117] In an embodiment, the pixel defining layer PDL may include an inorganic material. The pixel defining layer PDL may include inorganic layers stacked on one another. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0118] The light emitting structure EMS may be disposed on the anode electrode AE exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS may include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, a hole transport layer configured to transport holes, and the like.

[0119] In an embodiment, the light emitting structure EMS may fill the opening OP of the pixel defining layer PDL and may be entirely disposed on the pixel defining layer PDL. In other words, the light emitting structure EMS may extend across the first sub-pixel SP1 to the third sub-pixel SP3. At least a part of the layers in the light emitting structure EMS may be disconnected or bent at the boundaries between the first sub-pixel SP1 to the third sub-pixel SP3. However, the embodiment is not limited thereto. For example, the portions of the light emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each of the plurality of portions may be disposed in the opening OP of the pixel defining layer PDL.

[0120] The cathode electrode CE may be disposed on the light emitting structure EMS. The cathode electrode CE may extend across the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the cathode electrode CE may be provided as a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3.

[0121] The cathode electrode CE may be a thin metal layer having a thickness sufficient to transmit light emitted from the light emitting structure EMS. The cathode electrode CE may be formed of a metal material or a transparent conductive material to have a relatively thin thickness. In an embodiment, the cathode electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc oxide tin, or gallium tin oxide. In other embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited thereto.

[0122] It is understandable that any one of the plurality of anode electrodes AE, a part of the light-emitting structure EMS overlapping therewith, and a part of the cathode electrode CE overlapping therewith constitute a light-emitting element LD (refer to Figure 2 ). In other words, each of the plurality of light-emitting elements LD in the first sub-pixel SP1 to the third sub-pixel SP3 may include an anode electrode AE, a part of the light-emitting structure EMS overlapping with the anode electrode AE, and a part of the cathode electrode CE overlapping with the anode electrode AE. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode electrode AE and electrons injected from the cathode electrode CE can be transmitted to the light-emitting layer of the light-emitting structure EMS to form excitons, and when the excitons transition from the excited state to the ground state, light can be generated. The brightness of the light can be determined according to the amount of current flowing through the light-emitting layer. According to the configuration of the light-emitting layer, the wavelength range of the generated light can be determined.

[0123] The encapsulation layer TFE can be provided on the cathode electrode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be configured to prevent the penetration of oxygen and / or moisture, etc. into the light-emitting element layer LDL. In an embodiment, the encapsulation layer TFE may include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked. For example, the inorganic layer may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ), etc. For example, the organic layer may include an organic insulating material such as acrylic resin (polyacrylate resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0124] To improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE may further include a thin film containing aluminum oxide (Al x O y ). The thin film including aluminum oxide may be positioned on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0125] The thin film including aluminum oxide can be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited thereto. The encapsulation layer TFE may further include a thin film formed of at least one of various materials suitable for improving the encapsulation efficiency.

[0126] The optical function layer OFL can be provided on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0127] The color filter layer CFL may be disposed between the encapsulation layer TFE and the lens array LA. The color filter layer CFL is configured to filter the light emitted from the light-emitting structure EMS and selectively output light corresponding to the wavelength range or color of each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively, and each of the plurality of color filters CF may allow light corresponding to the wavelength range of the corresponding sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 may allow red light to pass through, the color filter corresponding to the second sub-pixel SP2 may allow green light to pass through, and the color filter corresponding to the third sub-pixel SP3 may allow blue light to pass through. At least a part of the color filter CF may be omitted according to the light emitted from the light-emitting structure EMS of each sub-pixel.

[0128] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the plurality of lenses LS may improve the light output efficiency by outputting the light emitted from the light-emitting structure EMS to the intended path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. In an embodiment, the lens may include an organic material. In an embodiment, the lens may include an acrylate material. However, the material of the lens LS is not limited thereto.

[0129] In an embodiment, compared with the opening OP of the pixel defining layer PDL, at least a part of the color filter CF of the color filter layer CFL and at least a part of the lens LS of the lens array LA may be shifted in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2. Specifically, in the central region of the display area DA, when observed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be aligned with or overlap the center of the opening OP of the corresponding pixel defining layer PDL. For example, in the central region of the display area DA, the opening OP of the pixel defining layer PDL may completely overlap the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when observed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be shifted from the center of the opening OP of the corresponding pixel defining layer PDL. For example, in the region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel defining layer PDL may partially overlap the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, the light emitted from the light-emitting structure EMS can be effectively output in the normal direction of the display surface. At the periphery (outskirt) of the display area DA, the light emitted from the light-emitting structure EMS can be effectively output in a direction inclined at a predetermined or selected angle with respect to the normal direction of the display surface.

[0130] The overcoat layer OC may be provided on the lens array LA. The overcoat layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the light-emitting structure EMS, and / or the pixel circuit layer PCL. The overcoat layer OC may include various materials suitable for protecting the underlying layers from foreign substances such as dust or moisture. For example, the overcoat layer OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the overcoat layer OC may include an epoxy resin, but the embodiment is not limited thereto. The overcoat layer OC may have a refractive index lower than that of the lens array LA.

[0131] The cover window CW may be provided on the overcoat layer OC. The cover window CW may be configured to protect the underlying layers. The cover window CW may have a refractive index higher than that of the overcoat layer OC. The cover window CW may include glass, but the embodiment is not limited thereto. For example, the cover window CW may be a packaging glass configured to protect the components provided thereunder. In other embodiments, the cover window CW may be omitted.

[0132] Figure 5 is a schematic plan view showing Figure 4 an embodiment of the pixel. The remaining pixels may be configured similarly to the first pixel PXL1 and the second pixel PXL2.

[0133] Reference Figure 4 and Figure 5 , the first pixel PXL1 and the second pixel PXL2 may each include first to third sub-pixels SP1 to SP3 arranged in a first direction DR1.

[0134] The first sub-pixel SP1 may include a first emission area EMA1 and a non-emission area NEA around the first emission area EMA1. The second sub-pixel SP2 may include a second emission area EMA2 and a non-emission area NEA around the second emission area EMA2. The third sub-pixel SP3 may include a third emission area EMA3 and a non-emission area NEA around the third emission area EMA3.

[0135] The first emission area EMA1 may be an area that emits light from a portion of the light-emitting structure EMS (reference Figure 4 ) corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area that emits light from a portion of the light-emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area that emits light from a portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3. As referred to Figure 5 above, each emission area may be understood as an opening OP of a pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3.

[0136] The leakage electrode LCE may be provided in a boundary area between the first to third sub-pixels SP1 to SP3. The leakage electrode LCE may be provided not only in a boundary area between adjacent sub-pixels (e.g., sub-pixels SP1 to SP3), but also in a boundary area between adjacent pixels (e.g., pixels PXL1 and PXL2).

[0137] The leakage electrode LCE will be described in detail later.

[0138] Figure 6 is a schematic cross-sectional view taken along line I-I’ of Figure 5 .

[0139] Reference Figure 6 , a substrate SUB and a pixel circuit layer PCL provided on the substrate SUB may be provided.

[0140] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon germanium.

[0141] The pixel circuit layer PCL may be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first sub-pixel SP1 to the third sub-pixel SP3. For example, the substrate SUB and the pixel circuit layer PCL may include the transistor T_SP1 of the first sub-pixel SP1, the transistor T_SP2 of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be any one of the plurality of transistors included in the sub-pixel circuit SPC (refer to Figure 2 ) of the first sub-pixel SP1, the transistor T_SP2 of the second sub-pixel SP2 may be any one of the plurality of transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 may be any one of the plurality of transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. In Figure 6 , for the sake of clear and concise description, one of the plurality of transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0142] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0143] The source region SRA and the drain region DRA may be disposed in the substrate SUB. A well WL formed by an ion implantation process may be disposed in the substrate SUB, and the source region SRA and the drain region DRA may be spaced apart from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0144] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA, and the gate electrode GE may be disposed in the pixel circuit layer PCL. The gate electrode GE may be spaced apart from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0145] The multiple layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers, and such conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA through a drain connection portion DRC passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA through a source connection portion SRC passing through one or more insulating layers.

[0146] Since the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are connected to different circuit elements and / or lines, the transistor T_SP1 of the first sub-pixel SP1 can be provided as any one of a plurality of transistors of the first sub-pixel SP1.

[0147] Each of the transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 can be configured similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0148] As described above, the substrate SUB and the pixel circuit layer PCL can include circuit elements of each of the first sub-pixel SP1 to the third sub-pixel SP3.

[0149] The via layer VIAL can be provided on the pixel circuit layer PCL. The via layer VIAL can cover the pixel circuit layer PCL and can have an overall flat surface. The via layer VIAL can be configured to planarize the steps on the pixel circuit layer PCL. The via layer VIAL can include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon carbonitride (SiCN), but the embodiments are not limited thereto.

[0150] The light-emitting element layer LDL can be provided on the via layer VIAL. The light-emitting element layer LDL can include a first reflective electrode RE1 to a third reflective electrode RE3, a planarization layer PLNL, a first anode electrode AE1 to a third anode electrode AE3, a pixel defining layer PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0151] On the via layer VIAL, the first reflective electrode RE1 to the third reflective electrode RE3 can be respectively provided in the first sub-pixel SP1 to the third sub-pixel SP3. Each of the first reflective electrode RE1 to the third reflective electrode RE3 can contact a circuit element provided in the pixel circuit layer PCL through a via penetrating the via layer VIAL.

[0152] The first reflective electrode RE1 to the third reflective electrode RE3 can be used as a total reflection mirror that reflects the light emitted from the light-emitting structure EMS toward the display surface (or the cover window CW). The first reflective electrode RE1 to the third reflective electrode RE3 can include a metal material suitable for reflecting light. Each of the first reflective electrode RE1 to the third reflective electrode RE3 can include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti) and / or an alloy of two or more materials selected from them, but the embodiments are not limited thereto.

[0153] In an embodiment, a connection electrode may be disposed under each of the first reflective electrode RE1 to the third reflective electrode RE3. The connection electrode may improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connection electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), or the like, but the embodiment is not limited thereto. In the embodiment, the corresponding reflective electrode may be positioned between the multilayers of the connection electrode.

[0154] A buffer pattern BFP may be disposed under at least one of the first reflective electrode RE1 to the third reflective electrode RE3. The buffer pattern BFP may include an inorganic material such as silicon carbonitride, but the embodiment is not limited thereto. By disposing the buffer pattern BFP, the height in the third direction DR3 of the corresponding reflective electrode can be adjusted. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0155] The first reflective electrode RE1 to the third reflective electrode RE3 may act as a total reflection mirror, and the cathode electrode CE may act as a semi-reflection mirror. The light emitted from the light-emitting layer of the light-emitting structure EMS may be amplified by reciprocating at least partially between the corresponding reflective electrode and the cathode electrode CE, and the amplified light may be output through the cathode electrode CE. As described above, the distance between each reflective electrode and the cathode electrode CE can be understood as the resonance distance of the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0156] The first sub-pixel SP1 may have a resonance distance shorter than that of another sub-pixel by virtue of the buffer pattern BFP. The resonance distance adjusted as described above may allow light in a specific wavelength range (e.g., red light) to be effectively and efficiently amplified. Therefore, the first sub-pixel SP1 can effectively and efficiently output light in the corresponding wavelength range.

[0157] In Figure 6In [the above], the buffer pattern BFP can be provided to the first sub-pixel SP1 and may not be provided to the second sub-pixel SP2 and the third sub-pixel SP3, but the embodiments are not limited thereto. The buffer pattern may also be provided to at least one of the second sub-pixel SP2 and the third sub-pixel SP3 to adjust the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the buffer pattern BFP may also be provided to the second sub-pixel SP2, and the resonance distance of the second sub-pixel SP2 may be adjusted. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue respectively, the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE, and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0158] To planarize the steps between the first reflective electrode RE1 to the third reflective electrode RE3, a planarization layer PLNL may be disposed on the via layer VIAL and the first reflective electrode RE1 to the third reflective electrode RE3. The planarization layer PLNL generally may cover the first reflective electrode RE1 to the third reflective electrode RE3 and the via layer VIAL and may have a flat surface. In an embodiment, the planarization layer PLNL may be omitted.

[0159] On the planarization layer PLNL, first anode electrodes AE1 to third anode electrodes AE3 respectively overlapping the first reflective electrode RE1 to the third reflective electrode RE3 may be disposed. When observed in the third direction DR3, the first anode electrodes AE1 to the third anode electrodes AE3 may respectively have a shape similar to the shape of Figure 6 the first emission regions EMA1 to the third emission regions EMA3. The first anode electrodes AE1 to the third anode electrodes AE3 are respectively connected to the first reflective electrode RE1 to the third reflective electrode RE3. The first anode electrode AE1 may be connected to the first reflective electrode RE1 through a first via VIA1 passing through the planarization layer PLNL. The second anode electrode AE2 may be connected to the second reflective electrode RE2 through a second via VIA2 passing through the planarization layer PLNL. The third anode electrode AE3 may be connected to the third reflective electrode RE3 through a third via VIA3 passing through the planarization layer PLNL.

[0160] In an embodiment, the first anode electrodes AE1 to the third anode electrodes AE3 may include a transparent conductive material (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x)、at least one of indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the materials of the first anode electrode AE1 to the third anode electrode AE3 are not limited thereto. For example, the first anode electrode AE1 to the third anode electrode AE3 may include titanium nitride.

[0161] In an embodiment, an insulating layer may also be provided for adjusting the height of one or more of the first anode electrode AE1 to the third anode electrode AE3. The insulating layer may be disposed between one or more of the first anode electrode AE1 to the third anode electrode AE3 and the corresponding reflective electrode. The planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue respectively, the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE. The pixel defining layer PDL may be disposed on the first anode electrode AE1 to the third anode electrode AE3 and a part of the planarization layer PLNL. The pixel defining layer PDL may include an opening OP exposing a part of each of the first anode electrode AE1 to the third anode electrode AE3. The opening OP of the pixel defining layer PDL may define the light emitting region of each of the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the pixel defining layer PDL may be disposed in Figure 5 the non-emitting area NEA of, and may define Figure 5 the first emission area EMA1 to the third emission area EMA3 of.

[0162] In an embodiment, the pixel defining layer PDL may include an inorganic insulating layer. Each of the plurality of inorganic insulating layers may include at least one of silicon oxide (SiO x ) and silicon nitride (SiN x ). For example, the pixel defining layer PDL may include a first inorganic insulating layer to a third inorganic insulating layer stacked on each other, and each of the first inorganic insulating layer to the third inorganic insulating layer may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ). However, the embodiment is not limited thereto. The first inorganic insulating layer to the third inorganic insulating layer may have a stepped cross-section in a region adjacent to the opening OP.

[0163] The leakage electrode LCE may be disposed in the boundary area BDA between adjacent sub-pixels. In other words, the leakage electrode LCE may be disposed in Figure 3 each of the plurality of boundary areas between the sub-pixels SP of.

[0164] The leakage electrode LCE can form a current path through which a leakage current flowing along the light-emitting structure EMS to adjacent sub-pixels (e.g., sub-pixels SP1 to SP3) can flow in the boundary region BDA. A detailed description in this regard will be described later.

[0165] The light-emitting structure EMS can be disposed on the anode electrodes AE1 to AE3 exposed by the openings OP of the pixel defining layer PDL. The light-emitting structure EMS can be disposed on the leakage electrode LCE disposed on the pixel defining layer PDL. The light-emitting structure EMS can fill the openings OP of the pixel defining layer PDL and can be disposed entirely across the first sub-pixel SP1 to the third sub-pixel SP3.

[0166] The cathode electrode CE can be disposed on the light-emitting structure EMS. The cathode electrode CE can be commonly provided to the first sub-pixel SP1 to the third sub-pixel SP3. The cathode electrode CE can be commonly provided to the leakage electrode LCE. The cathode electrode CE can serve as a semi-reflecting mirror that partially transmits and partially reflects the light emitted from the light-emitting structure EMS.

[0167] The first anode electrode AE1, a part of the light-emitting structure EMS overlapping with the first anode electrode AE1, and a part of the cathode electrode CE overlapping with the first anode electrode AE1 can constitute the first light-emitting element LD1. The second anode electrode AE2, a part of the light-emitting structure EMS overlapping with the second anode electrode AE2, and a part of the cathode electrode CE overlapping with the second anode electrode AE2 can constitute the second light-emitting element LD2. The third anode electrode AE3, a part of the light-emitting structure EMS overlapping with the third anode electrode AE3, and a part of the cathode electrode CE overlapping with the third anode electrode AE3 can constitute the third light-emitting element LD3.

[0168] The leakage electrode LCE, a part of the light-emitting structure EMS overlapping with the leakage electrode LCE, and a part of the cathode electrode CE overlapping with the leakage electrode LCE can constitute the leakage element LLD.

[0169] The encapsulation layer TFE can be disposed on the cathode electrode CE. The encapsulation layer TFE can prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL.

[0170] The optical function layer OFL can be disposed on the encapsulation layer TFE. In an embodiment, the optical function layer OFL can be attached to the encapsulation layer TFE through the adhesive layer APL. For example, the optical function layer OFL can be separately manufactured and attached to the encapsulation layer TFE through the adhesive layer APL. The adhesive layer APL can also perform the function of protecting the underlying layer including the encapsulation layer TFE.

[0171] The optical functional layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include a first color filter CF1 to a third color filter CF3 corresponding to a first sub-pixel SP1 to a third sub-pixel SP3, respectively. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may allow light in different wavelength ranges to pass through. For example, the first color filter CF1 to the third color filter CF3 may allow red, green, and blue light to pass through, respectively.

[0172] In an embodiment, the first color filter CF1 to the third color filter CF3 may partially overlap in a boundary region BDA. In other embodiments, the first color filter CF1 to the third color filter CF3 may be spaced apart from each other, and a black matrix may be provided between the first color filter CF1 to the third color filter CF3.

[0173] The lens array LA may be disposed on the color filter layer CFL. The lens array LA may include a first lens LS1 to a third lens LS3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. Each of the first lens LS1, the second lens LS2, and the third lens LS3 may improve the light output efficiency by outputting the light emitted from the first light-emitting element LD1 to the third light-emitting element LD3 to an intended path.

[0174] Figure 7 is a schematic cross-sectional view showing an embodiment of a light-emitting structure included in any one of the first light-emitting element to the third light-emitting element included in Figure 6

[0175] Referring to Figure 7 , the light-emitting structure EMS may have a tandem structure in which a first light-emitting unit EU1 and a second light-emitting unit EU2 are stacked on each other. In each of the first light-emitting element LD1 to the third light-emitting element LD3 and the leakage element LLD (refer to Figure 6 ), the light-emitting structure EMS may be configured substantially the same.

[0176] Each of the first light-emitting unit EU1 and the second light-emitting unit EU2 may include at least one light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0177] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and if necessary, each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may further include a hole buffer layer, an electron blocking layer, etc. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same or different configurations from each other.

[0178] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same or different configurations from each other.

[0179] A connection layer, which may be provided in the form of a charge generation layer CGL, may be disposed between the first light emitting unit EU1 and the second light emitting unit EU2 to connect the first light emitting unit EU1 and the second light emitting unit EU2 to each other. In an embodiment, the charge generation layer CGL may have a stacked structure of a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include p-type dopants (such as HAT-CN, TCNQ, and NDP-9), and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the embodiment is not limited thereto.

[0180] In an embodiment, the first emission layer EML1 and the second emission layer EML2 may emit light of different colors. The light emitted from each of the first emission layer EML1 and the second emission layer EML2 may be mixed and observed as white light. For example, the first emission layer EML1 may emit blue light, and the second emission layer EML2 may emit yellow light. In an embodiment, the second emission layer EML2 may include a structure in which a first sub-emission layer configured to emit red light and a second sub-emission layer configured to emit green light are stacked on each other. The red light and the green light may be mixed, and thus yellow light may be provided. An intermediate layer configured to perform a function of transporting holes and / or blocking electron transport may also be disposed between the first sub-emission layer and the second sub-emission layer.

[0181] In other embodiments, the first emission layer EML1 and the second emission layer EML2 may emit light of the same color.

[0182] The light emitting structure EMS may be formed by methods such as vacuum deposition or inkjet printing, but the embodiment is not limited thereto.

[0183] Figure 8 shows what is included in Figure 6Schematic cross-sectional view of another embodiment of the light-emitting structure in any one of the first to third light-emitting elements.

[0184] Referring to Figure 8 , the light-emitting structure EMS’ may have a series structure in which the first to third light-emitting units EU1’ to EU3’ are stacked on top of each other. In Figure 6 each of the first to third light-emitting elements LD1 to LD3 and the leakage element LLD, the light-emitting structure EMS’ may be configured substantially the same.

[0185] Each of the first to third light-emitting units EU1’ to EU3’ may include a light-emitting layer that generates light according to the applied current. The first light-emitting unit EU1’ may include a first light-emitting layer EML1’, a first electron transport unit ETU1’, and a first hole transport unit HTU1’. The first light-emitting layer EML1’ may be disposed between the first electron transport unit ETU1’ and the first hole transport unit HTU1’. The second light-emitting unit EU2’ may include a second light-emitting layer EML2’, a second electron transport unit ETU2’, and a second hole transport unit HTU2’. The second light-emitting layer EML2’ may be disposed between the second electron transport unit ETU2’ and the second hole transport unit HTU2’. The third light-emitting unit EU3’ may include a third light-emitting layer EML3’, a third electron transport unit ETU3’, and a third hole transport unit HTU3’. The third light-emitting layer EML3’ may be disposed between the third electron transport unit ETU3’ and the third hole transport unit HTU3’.

[0186] Each of the first to third hole transport units HTU1’ to HTU3’ may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer and an electron blocking layer, etc. The first to third hole transport units HTU1’ to HTU3’ may have the same or different configurations from each other.

[0187] Each of the first to third electron transport units ETU1’ to ETU3’ may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer and a hole blocking layer, etc. The first to third electron transport units ETU1’ to ETU3’ may have the same or different configurations from each other.

[0188] The first charge generation layer CGL1’ may be disposed between the first light-emitting unit EU1’ and the second light-emitting unit EU2’. The second charge generation layer CGL2’ may be disposed between the second light-emitting unit EU2’ and the third light-emitting unit EU3’.

[0189] In an embodiment, the first light-emitting layer EML1' to the third light-emitting layer EML3' may generate light of different colors. The light emitted from each of the first light-emitting layer EML1' to the third light-emitting layer EML3' may be mixed and may be observed as white light. For example, the first light-emitting layer EML1' may generate blue light, the second light-emitting layer EML2' may generate green light, and the third light-emitting layer EML3' may generate red light.

[0190] In other embodiments, two or more of the first light-emitting layer EML1' to the third light-emitting layer EML3' may generate light of the same color.

[0191] Unlike Figure 7 and Figure 8 shown, Figure 6 the light-emitting structure EMS may include one light-emitting unit in each of the first light-emitting element LD1 to the third light-emitting element LD3 and the leakage element LLD. The light-emitting units included in each of the first light-emitting element LD1 to the third light-emitting element LD3 may be configured to emit light of different colors. For example, the light-emitting unit of the first light-emitting element LD1 may emit red light, the light-emitting unit of the second light-emitting element LD2 may emit green light, and the light-emitting unit of the third light-emitting element LD3 may emit blue light. Unlike Figure 6 shown, the light-emitting units of the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each of the plurality of light-emitting units of the first sub-pixel SP1 to the third sub-pixel SP3 may be disposed in the opening OP of the pixel defining layer PDL. At least a part of the color filters CF1 to CF3 may be omitted.

[0192] Figure 9 is a schematic plan view showing Figure 4 another embodiment of any one of the plurality of pixels.

[0193] Referring to Figure 9 , the first pixel PXL1' may include the first sub-pixel SP1' to the third sub-pixel SP3'.

[0194] The first sub-pixel SP1' may include a first emission region EMA1' and a non-emission region NEA' surrounding the first emission region EMA1'. The second sub-pixel SP2' may include a second emission region EMA2' and a non-emission region NEA' surrounding the second emission region EMA2'. The third sub-pixel SP3' may include a third emission region EMA3' and a non-emission region NEA' surrounding the third emission region EMA3'.

[0195] The first sub-pixel SP1' and the second sub-pixel SP2' can be arranged in the second direction DR2. The third sub-pixel SP3' can be arranged in the first direction DR1 with respect to each of the first sub-pixel SP1' and the second sub-pixel SP2'.

[0196] The second sub-pixel SP2' can have an area larger than that of the first sub-pixel SP1', and the third sub-pixel SP3' can have an area larger than that of the second sub-pixel SP2'. Accordingly, the second emission region EMA2' can have an area larger than that of the first emission region EMA1', and the third emission region EMA3' can have an area larger than that of the second emission region EMA2'. However, the embodiments are not limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' can have substantially the same area, and the third sub-pixel SP3' can have an area larger than that of each of the first sub-pixel SP1' and the second sub-pixel SP2'. As described above, the areas of the first sub-pixel SP1' to the third sub-pixel SP3' can vary according to the embodiments.

[0197] Similarly, the leakage electrode LCE can be disposed in the boundary region between the first sub-pixel SP1' to the third sub-pixel SP3'. The leakage electrode LCE can be disposed not only in the boundary region between the sub-pixels (e.g., the sub-pixels SP1' to SP3'), but also in the boundary region between the pixels adjacent to each other.

[0198] Figure 10 is a schematic plan view showing Figure 4 yet another embodiment of any one of a plurality of pixels.

[0199] Referring to Figure 10 , the first pixel PXL1'' can include a first sub-pixel SP1'' to a third sub-pixel SP3''. The first sub-pixel SP1'' can include a first emission region EMA1'' and a non-emission region NEA'' around the first emission region EMA1''. The second sub-pixel SP2'' can include a second emission region EMA2'' and a non-emission region NEA'' around the second emission region EMA2''. The third sub-pixel SP3'' can include a third emission region EMA3'' and a non-emission region NEA'' around the third emission region EMA3''.

[0200] When observed in the third direction DR3, the first sub-pixel SP1'' to the third sub-pixel SP3'' can have a polygonal shape. For example, the shapes of the first sub-pixel SP1'' to the third sub-pixel SP3'' can be a hexagonal shape as shown in Figure 10 .

[0201] When viewed in the third direction DR3, the first to third emission areas EMA1" to EMA3" may have a circular shape. However, the embodiment is not limited thereto. For example, each of the first to third emission areas EMA1" to EMA3" may have other polygonal shapes.

[0202] The first subpixel SP1" and the third subpixel SP3" may be arranged in the first direction DR1. The second subpixel SP2" may be disposed in a direction (or an oblique direction) inclined at an acute angle based on the second direction DR2 with respect to the first subpixel SP1".

[0203] Similarly, the leakage electrode LCE can be set in the boundary area between the first sub-pixel SP1" to the third sub-pixel SP3". The leakage electrode LCE can be set not only in the boundary area between sub-pixels (for example, sub-pixels SP1" to SP3"), but also in the boundary area between pixels adjacent to each other.

[0204] Figure 5 , Figure 9 and Figure 10 The sub-pixel SP shown in FIG. Figure 1 ) is only an example, and the embodiment is not limited thereto. Each pixel may include two or more sub-pixels SP, the sub-pixels SP may be arranged in various methods, the respective sub-pixels SP may have various shapes, and their respective emission areas EMA1, EMA2, and EMA3 may also have various shapes.

[0205] Figure 11 is a flowchart illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0206] Reference Figure 11 , a method for manufacturing a display device may include: providing a substrate including a display area provided with sub-pixels and a non-display area provided around the display area (S100); forming an anode electrode on the substrate (S200); applying an insulating layer (e.g., a pixel defining layer) to cover the anode electrode (S300); forming a leakage electrode on the insulating layer (S400); exposing at least a portion of the anode electrode by patterning the insulating layer (S500); forming a light emitting structure on the anode electrode and the leakage electrode in the display area (S500); and forming a cathode electrode on the light emitting structure (S600).

[0207] In the following, reference Figures 12 to 17 The present disclosure is described in detail.

[0208] Figure 12 It is shown Figure 11 A schematic diagram of step S200 is shown in FIG. Figure 13 It is shown Figure 11Schematic diagram of step S300 Figure 14 shows Figure 11 Schematic diagram of step S400 Figure 15 shows Figure 11 Schematic diagram of step S500 Figure 16 shows Figure 11 Schematic diagram of step S600, and Figure 17 shows Figure 11 Schematic diagram of step S700

[0209] For convenience of description Figures 13 to 17 only the pixel defining layer PDL is shown as a single layer, and the present disclosure is not limited thereto

[0210] Referring to Figure 12 , an anode electrode AE can be formed on the via layer VIAL. The anode electrode AE can be coated on the via layer VIAL, and the anode electrode AE can be patterned to dispose a light-emitting element LD in the display area DA (refer to Figure 2 ).

[0211] The anode electrode AE formed in the non-display area NDA can be connected to the cathode electrode CE (refer to Figure 17 described later), and a second power voltage VSS (refer to Figure 2 ) can be transmitted to the cathode electrode CE (refer to Figure 17 described later).

[0212] In an embodiment, the anode electrode AE disposed in the non-display area NDA is shown to be shorter than the anode electrode AE disposed in the display area DA. However, in the present disclosure, the present disclosure is not limited to the length of the anode electrode AE in the non-display area NDA

[0213] Referring to Figure 13 , the pixel defining layer PDL can be coated to cover the anode electrode AE. For example, the pixel defining layer PDL can be coated to cover the anode electrode AE and the via layer VIAL

[0214] Referring to Figure 14 , a leakage electrode LCE can be formed on the pixel defining layer PDL. The leakage electrode LCE can be coated on the pixel defining layer PDL, the leakage electrode LCE can be patterned, and the leakage electrode LCE can be disposed between the anode electrodes AE

[0215] In an embodiment, the leakage electrode LCE disposed in the non-display area NDA is shown to be shorter than the leakage electrode LCE disposed in the display area DA. However, in the present disclosure, the present disclosure is not limited to the length of the leakage electrode LCE in the non-display area NDA

[0216] Referring toFigure 15 , the pixel defining layer PDL can be patterned to expose at least a part of the anode electrode AE. For example, the pixel defining layer PDL can include openings OP that expose a part of each of the plurality of anode electrodes AE, and the openings OP can correspond to the emission regions EMA1 (refer to Figure 5 ) to EMA3 (refer to Figure 5 ).

[0217] In Figure 15 , the pixel defining layer PDL is shown to expose a part of each anode electrode AE, but the present disclosure is not limited thereto. For example, the pixel defining layer PDL can expose the entirety of each of the plurality of anode electrodes AE, and there may be no overlapping portion between the pixel defining layer PDL and the anode electrode AE.

[0218] The leakage electrode LCE can be shorter than the distance between the openings OP. In the case where the pixel defining layer PDL exposes the entirety of each of the plurality of anode electrodes AE, the leakage electrode LCE can be shorter than the distance between the anode electrodes AE.

[0219] In the case where the leakage electrode LCE is coated after patterning the pixel defining layer PDL, the anode electrode AE may be damaged during the process of patterning the leakage electrode LCE (i.e., during the process of removing the leakage electrode LCE in the emission regions EMA1 (refer to Figure 5 ) to EMA3 (refer to Figure 5 ). Therefore, in order to prevent damage, the pixel defining layer PDL can be patterned after forming the leakage electrode LCE.

[0220] Refer to Figure 16 , a light emitting structure EMS can be formed in the first region A1. The first region A1 can include the display region DA. That is to say, the light emitting structure EMS can be provided on the anode electrode AE and the leakage electrode LCE in the display region DA.

[0221] The light emitting structure EMS can fill the openings OP of the pixel defining layer PDL and can be completely formed on the pixel defining layer PDL. Therefore, leakage current can flow through the charge generation layer CGL (refer to Figure 7 ) between adjacent sub-pixels. However, since the leakage electrode LCE is provided, the leakage current between adjacent sub-pixels can be reduced. A detailed description in this regard will be described later.

[0222] In the embodiment, it is shown that the first region A1 and the display region DA are different, but the present disclosure is not limited thereto. For example, the first region A1 and the display region DA can coincide.

[0223] Refer to Figure 17, a cathode electrode CE can be formed on the light-emitting structure EMS in the display area DA. The cathode electrode CE can be completely formed on the light-emitting structure EMS in the first area A1 including the display area DA.

[0224] The cathode electrode CE can be formed on the pixel definition layer PDL in the second area A2 where the light-emitting structure EMS is not formed. For example, the cathode electrode CE can be completely formed on the pixel definition layer PDL in the second area A2 including a part of the non-display area NDA.

[0225] The cathode electrode CE can be formed on the leakage electrode LCE in at least a part (e.g., the second area A2) of the non-display area NDA. For example, the cathode electrode CE can contact the leakage electrode LCE in at least a part (e.g., the second area A2) of the non-display area NDA.

[0226] Therefore, a voltage (e.g., the second power voltage VSS (refer to Figure 1 )) same as the voltage of the cathode electrode CE can be applied to the leakage electrode LCE. As Figure 5 shown, the leakage electrode LCE can be integrally formed in a grid shape throughout the display area DA and the non-display area NDA. Therefore, a voltage same as the voltage of the cathode electrode CE can be applied to the entire leakage electrode LCE.

[0227] The cathode electrode CE can be connected to the anode electrode AE in at least a part (e.g., the second area A2) of the non-display area NDA. The cathode electrode CE can receive the second power voltage VSS (refer to Figure 1 ) through the anode electrode AE in the non-display area NDA. The anode electrode AE can receive the first power voltage VDD (refer to Figure 1 ) through the conductive pattern provided under the anode electrode AE.

[0228] As described above, since the cathode electrode CE is connected to the anode electrode AE in the second area A2 where the light-emitting structure EMS is not formed, the number of contact holes and masks used in the process can be reduced.

[0229] Figure 18 is a schematic cross-sectional view of a part of a display device according to an embodiment of the present disclosure.

[0230] For ease of description, Figure 18 only some configurations are shown, and the rest are omitted. For ease of description, Figure 18 it is shown that the conductive pattern BP can be directly provided under the via layer VIAL. However, the conductive pattern BP does not have to be directly provided under the via layer VIAL, and a pattern provided under the via layer VIAL is sufficient as the conductive pattern BP.

[0231] Since, except that the cathode electrode CE is connected to the conductive pattern BP disposed under the anode electrode AE in the second region A2, the display device according to the embodiment may be substantially the same as Figure 1 the configuration of the display device, the same reference numerals and symbols are used for the same or similar components, and redundant descriptions are omitted.

[0232] Referring to Figure 18 , in at least a part of the non-display area NDA (e.g., the second region A2), the cathode electrode CE may be connected to the conductive pattern BP disposed under the anode electrode AE. For example, the conductive pattern BP may be a conductive pattern of the same layer as the first conductive pattern CP1 (refer to Figure 6 ) and the second conductive pattern CP2 (refer to Figure 6 ). For example, the second power supply voltage VSS (refer to Figure 1 ) may be applied to the conductive pattern BP, and may be provided to the cathode electrode CE through the conductive pattern BP.

[0233] The present disclosure is not limited to the type of the conductive pattern disposed under the anode electrode AE, and the conductive material disposed under the anode electrode AE is sufficient as the conductive pattern.

[0234] Figure 19 is a schematic diagram showing Figure 6 the circuits of the first light-emitting element and the second light-emitting element and the leakage element.

[0235] In Figure 19 , for clear and concise description, the circuits corresponding to two of the light-emitting elements LD1 to LD3 corresponding to Figure 6 are shown. The circuits corresponding to the remaining light-emitting elements may be configured similarly.

[0236] For ease of description, Figure 19 it is assumed that the first light-emitting element LD1, the second light-emitting element LD2, and the leakage element LLD have Figure 7 the structure.

[0237] Referring to Figure 19 , the first light-emitting unit EU1 of the light-emitting elements LD1 and LD2 may be connected to the anode electrode AE and the charge generation layer CGL. The second light-emitting unit EU2 of the first light-emitting element LD1 and the second light-emitting element LD2 may be connected to the charge generation layer CGL and the cathode electrode CE.

[0238] The charge generation layer CGL and the cathode electrode CE can be shared by the light-emitting elements LD1 and LD2 and the leakage element LLD. Accordingly, the first light-emitting unit EU1 of the leakage element LLD can also be connected to the charge generation layer CGL, and the second light-emitting unit EU2 of the leakage element LLD can also be connected to the charge generation layer CGL and the cathode electrode CE.

[0239] The first light-emitting unit EU1 of the leakage element LLD can be connected to the leakage electrode LCE. As described above, the leakage electrode LCE can be connected to the cathode electrode CE.

[0240] Figure 20 is a schematic diagram of a circuit showing the leakage current.

[0241] Referring to Figure 20 , as described above, the charge generation layer CGL and the cathode electrode CE can be shared by the light-emitting elements LD1 and LD2 and the leakage element LLD. Accordingly, in the case where the first light-emitting element LD1 emits light and the second light-emitting element LD2 does not emit light, the leakage current can flow along the charge generation layer CGL of the first light-emitting element LD1.

[0242] At least a part of the leakage current can flow to the second light-emitting unit EU2 of the leakage element LLD. Ideally, there is no resistance in the charge generation layer CGL between the light-emitting elements LD1 and LD2, but in reality, there is resistance, and the leakage current flowing to the second light-emitting element LD2 may be greater than the leakage current flowing to the leakage current element LLD. Accordingly, the leakage current flowing to the second light-emitting element LD2 can be reduced.

[0243] At the lowest gray level, the voltage applied to the leakage electrode LCE (e.g., the second power voltage VSS (refer to Figure 1 )) can be less than the voltage of the anode electrode AE. Accordingly, the current can not flow through the first light-emitting unit EU1 connected to the leakage electrode LCE, and the first light-emitting unit EU1 can act as a capacitor. Since the first light-emitting unit EU1 acts as a capacitor, even if a leakage current occurs, the voltage of the charge generation layer CGL connected to the leakage electrode LCE can increase slowly.

[0244] In the case where any one of the sub-pixels adjacent to each other emits light, one sub-pixel may affect the other sub-pixel due to coupling. That is, noise may appear in the other sub-pixel. Since the leakage electrode LCE is formed in the boundary region between the sub-pixels (i.e., the light-emitting elements LD1 and LD2), and a constant voltage (e.g., the second power voltage VSS (refer to Figure 1 )) is applied to the leakage electrode, the noise due to the coupling between the adjacent sub-pixels can be reduced.

[0245] Figure 21It is a schematic cross-sectional view of a display device according to an embodiment of the present disclosure. Figure 21 is another example of a cross-sectional view taken along Figure 5 the line I-I'.

[0246] Since the display device according to the embodiment can be substantially the same as the configuration of the Figure 6 display device except that the pixel defining layer PDL is omitted, the same reference numerals and symbols are used for the same or similar components, and redundant descriptions are omitted.

[0247] Referring to Figure 21 , a leakage electrode LCE can be formed on the planarization layer PLNL. For example, the leakage electrode LCE can be formed on the same layer as the first to third anode electrodes AE1, AE2, and AE3. For example, the leakage electrode LCE can be formed by the same process as the first to third anode electrodes AE1, AE2, and AE3. However, the leakage electrode LCE does not necessarily have to be formed by the same process.

[0248] The leakage electrode LCE can be disposed between the anode electrodes AE1 to AE3. The length of the leakage electrode LCE can be shorter than the distance between the anode electrodes AE1 to AE3.

[0249] The light-emitting structure EMS can be disposed on the anode electrodes AE1 to AE3 and the leakage electrode LCE. For example, the light-emitting structure EMS can be entirely disposed on the planarization layer PLNL, the anode electrodes AE1 to AE3, and the leakage electrode LCE.

[0250] Figure 22 It is a schematic block diagram showing an embodiment of a display system.

[0251] Referring to Figure 22 , the display system 1000 can include a processor 1100 and one or more display devices 1210 and 1220. Similarly, the display system 1000 can reduce the leakage current flowing between adjacent sub-pixels through the leakage electrode.

[0252] The processor 1100 can perform various tasks and calculations. In an embodiment, the processor 1100 can include an application processor, a graphics processor, a microprocessor, and a central processing unit (CPU), etc. The processor 1100 can be connected to other components of the display system 1000 through a bus system and can control other components.

[0253] In Figure 22In this, the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 can be connected to the first display device 1210 through a first channel CH1 and can be connected to the second display device 1220 through a second channel CH2.

[0254] Through the first channel CH1, the processor 1100 can transmit first image data IMG1 and a first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be configured similarly to the display device 100 described in the reference Figure 1 The first image data IMG1 and the first control signal CTRL1 can be respectively provided as Figure 1 the input image data IMG and the control signal CTRL.

[0255] Through the second channel CH2, the processor 1100 can transmit second image data IMG2 and a second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be configured similarly to the display device 100 described in the reference Figure 1 The second image data IMG2 and the second control signal CTRL2 can be respectively provided as Figure 1 the input image data IMG and the control signal CTRL.

[0256] The display system 1000 can include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation device, and an ultra-mobile personal computer (UMPC). The display system 1000 can include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0257] Figure 23 is a schematic perspective view showing Figure 22 an application example of the display system.

[0258] Referring to Figure 23 , Figure 22 the display system 1000 can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0259] The head-mounted display device 2000 may include a head mounting band 2100 and a display device housing 2200. The head mounting band 2100 may be connected to the display device housing 2200. The head mounting band 2100 may include a horizontal band and / or a vertical band for fixing the head-mounted display device 2000 to the user's head. The horizontal band may be configured to surround the side portions of the user's head, and the vertical band may be configured to surround the upper portion of the user's head. However, the embodiments are not limited thereto. For example, the head mounting band 2100 may be implemented in the form of a spectacle frame or a helmet form, etc.

[0260] The display device housing 2200 may accommodate Figure 22 the first display device 1210 and the second display device 1220. The display device housing 2200 may also accommodate Figure 22 the processor 1100.

[0261] Figure 24 is a schematic diagram showing a head-mounted display device worn by a user.

[0262] Referring to Figure 24 , in the head-mounted display device 2000, the first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 may be provided. The head-mounted display device 2000 may also include one or more lenses LLNS and RLNS.

[0263] In the display device housing 2200, the right-eye lens RLNS may be provided between the first display panel DP1 and the user's right eye. In the display device housing 2200, the left-eye lens LLNS may be provided between the second display panel DP2 and the user's left eye.

[0264] The image output from the first display panel DP1 may be displayed to the user's right eye through the right-eye lens RLNS. The right-eye lens RLNS may refract the light from the first display panel DP1 to direct the light from the first display panel DP1 to the user's right eye. The right-eye lens RLNS may perform an optical function for adjusting the viewing distance between the first display panel DP1 and the user's right eye.

[0265] The image output from the second display panel DP2 may be displayed to the user's left eye through the left-eye lens LLNS. The left-eye lens LLNS may refract the light from the second display panel DP2 to direct it to the user's left eye. The left-eye lens LLNS may perform an optical function for adjusting the viewing distance between the second display panel DP2 and the user's left eye.

[0266] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a flat cross-section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. Each display panel may output images respectively corresponding to the sub-regions of the multi-channel lens, and the output images may pass through their respective corresponding sub-regions and may be observed by a user.

[0267] Although specific embodiments and application examples are described herein, other embodiments and modifications can be derived from the above description. Therefore, the spirit of the present disclosure is not limited to these embodiments, but extends to include various obvious modifications and equivalents.

[0268] The present disclosure can be applied to a display device and an electronic device including the display device. For example, the present disclosure can be applied to a digital TV, a 3D TV, a mobile phone, a smart phone, a tablet personal computer, a VR device, a PC, a home electronic device, a notebook computer, a personal digital assistant (PDA), a PMP, a digital camera, a music player, a portable game console, and a navigation system, etc.

[0269] Although described with reference to the above embodiments, it should be understood that those skilled in the art can make various modifications and changes to the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, wherein: The display device comprises: Substrate, including: A display area including a plurality of sub-pixels; and a non-display area, adjacent to the display area; A first electrode is disposed on the substrate; A second electrode is disposed on the substrate; a light emitting structure, disposed on the first electrode and the second electrode in the display area; and A third electrode is disposed on the light emitting structure in the display area, and the third electrode is disposed on the second electrode in at least a portion of the non-display area.

2. The display device according to claim 1, wherein: The third electrode electrically contacts the second electrode in the at least a portion of the non-display area.

3. The display device according to claim 1, wherein: The third electrode is electrically connected to the first electrode in the at least a portion of the non-display area.

4. The display device according to claim 1, wherein: The third electrode is electrically connected to a conductive pattern disposed under the first electrode in the at least a portion of the non-display area.

5. The display device according to claim 1, wherein: The display device further includes: an insulating layer disposed on the first electrode and including an opening exposing at least a portion of the first electrode, Wherein, the second electrode is arranged on the insulating layer.

6. The display device according to claim 5, wherein: The third electrode extends to the insulating layer in the at least a portion of the non-display area.

7. The display device according to claim 5, wherein: The light emitting structure fills the opening, and The light emitting structure is completely disposed on the insulating layer in the display area.

8. The display device according to claim 1, wherein: The light emitting structure comprises: a first light emitting unit; A second light emitting unit is disposed on the first light emitting unit; and The connection layer is disposed between the first light emitting unit and the second light emitting unit, and the connection layer electrically connects the first light emitting unit and the second light emitting unit.

9. The display device according to claim 1, wherein: At the lowest gray level, the voltage applied to the second electrode is smaller than the voltage of the first electrode.

10. The display device according to claim 1, wherein: The second electrode is disposed in a boundary region between at least two of the plurality of sub-pixels, and The at least two of the plurality of sub-pixels are adjacent to each other.

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