Preparation method of nonvolatile two-end storage unit and product thereof

Abstract

The invention discloses a preparation method of a nonvolatile two-end storage unit and a product thereof. The preparation method comprises the following steps: providing a lower dielectric layer which surrounds a first region lower electrode metal connecting layer and enables the upper surface of the first region lower electrode metal connecting layer to be exposed; forming an isolation stack layer at least covering the first region lower electrode metal connection layer; etching in the isolation stack layer based on the patterned photomask layer to form a first region lower electrode interconnecting through hole, wherein the bottom of the first region lower electrode interconnecting through hole is at least partially contacted with the first region lower electrode metal connecting layer; and forming a first stacking layer comprising a first lower electrode metal layer, a first switching layer and a first upper electrode metal layer in the first region lower electrode interconnection through hole. According to the preparation method, the first stack layer is formed in the first region lower electrode interconnection through hole, and only one patterned photomask layer is used, so that the preparation of the first lower electrode metal layer and the first upper electrode metal layer is realized, the production cost is reduced, the preparation process is simplified, the problem of mutual alignment of the upper electrode and the lower electrode is avoided, and the preparation difficulty is reduced.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a method for fabricating a non-volatile two-terminal memory cell and its product. Background Art

[0002] A resistive random access memory (RRAM) is a non-volatile two-terminal memory cell that stores information based on the change in the resistance of a material, and is usually composed of a lower electrode, a switching layer, and an upper electrode. In the prior art, during the fabrication process of a resistive random access memory, two lithographies are required to separately fabricate the lower electrode and the upper electrode. Due to the manufacturing steps, generally, the fabrication of the lower electrode and the upper electrode of a resistive random access memory each requires a different patterned photomask layer, which greatly increases the production cost, and the fabrication process is also relatively complex. At the same time, such a fabrication method also involves the problem of alignment between the lower electrode and the upper electrode during the fabrication of the lower electrode and the upper electrode, which makes the fabrication of the resistive random access memory difficult.

[0003] In view of this, there is an urgent need to provide a method for fabricating a non-volatile two-terminal memory cell, which can reduce the number of patterned photomask layers used while realizing the fabrication of the lower electrode and the upper electrode of the non-volatile two-terminal memory cell, thereby reducing the production cost of the non-volatile two-terminal memory cell, simplifying the fabrication process, and avoiding the problem of alignment between the lower electrode and the upper electrode, and reducing the fabrication difficulty of the non-volatile two-terminal memory cell. Summary of the Invention

[0004] To at least solve one or more of the above-mentioned technical problems, this disclosure proposes solutions for a method for fabricating a non-volatile two-terminal memory cell and its product in multiple aspects.

[0005] In a first aspect, this disclosure provides a method for fabricating a non-volatile two-terminal memory cell, the fabrication method including: providing a lower dielectric layer 120 that surrounds a first-region lower electrode metal connection layer 111 and has its upper surface exposed; forming an isolation stack layer 130 that at least covers the first-region lower electrode metal connection layer 111; etching a first-region lower electrode interconnection via 141 in the isolation stack layer 130 based on a patterned photomask layer, the bottom of the first-region lower electrode interconnection via 141 at least partially contacting the first-region lower electrode metal connection layer 111; forming a first stack layer 250 including a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253 in the first-region lower electrode interconnection via 141.

[0006] In some embodiments, the upper surface of the first stack layer 250 is flush with the upper surface of the isolation stack layer 130.

[0007] In some embodiments, a first stacked layer 250 flush with the upper surface of the isolation stacked layer 130 is formed in the first-region lower electrode interconnection via hole 141, including: depositing and forming at least the first lower electrode metal layer 251 on the inner wall and bottom of the first-region lower electrode interconnection via hole 141 and the first switching layer 252 covering the first lower electrode metal layer 251; forming a sacrificial layer 270 on the first switching layer 252 and making the sacrificial layer 270 at least fill the remaining space of the first-region lower electrode interconnection via hole 141; removing the first lower electrode metal layer 251, the first switching layer 252, and the sacrificial layer 270 outside the first-region lower electrode interconnection via hole 141 region, and removing the sacrificial layer 270 in the first-region lower electrode interconnection via hole 141 region; forming the first upper electrode metal layer 253 in the region of the first-region lower electrode interconnection via hole 141 where the sacrificial layer 270 has been removed, such that the upper surface of the first upper electrode metal layer 253 is flush with the upper surface of the isolation stacked layer 130.

[0008] In some embodiments, the first upper electrode metal layer 253 includes a first upper electrode metal first sub-layer 2531 and a first upper electrode metal second sub-layer 2532, and the first upper electrode metal first sub-layer 2531 is located between the first switching layer 252 and the first upper electrode metal second sub-layer 2532; a first stacked layer 250 flush with the upper surface of the isolation stacked layer 130 is formed in the first-region lower electrode interconnection via hole 141, including: depositing and forming at least the first lower electrode metal layer 251, the first switching layer 252 covering the first lower electrode metal layer 251, and the first upper electrode metal first sub-layer 2531 covering the first switching layer 252 on the inner wall and bottom of the first-region lower electrode interconnection via hole 141; forming a sacrificial layer 270 on the first upper electrode metal first sub-layer 2531 and making the sacrificial layer 270 at least fill the remaining space of the first-region lower electrode interconnection via hole 141; removing the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal first sub-layer 2531, and the sacrificial layer 270 outside the first-region lower electrode interconnection via hole 141 region, and removing the sacrificial layer 270 in the first-region lower electrode interconnection via hole 141 region; forming the first upper electrode metal second sub-layer 2532 in the region of the first-region lower electrode interconnection via hole 141 where the sacrificial layer 270 has been removed, such that the upper surface of the first upper electrode metal second sub-layer 2532 is flush with the upper surface of the isolation stacked layer 130.

[0009] In some embodiments, after forming the first stacked layer 250, a blocking layer 230 covering at least the upper surface of the first stacked layer 250 is formed.

[0010] In some embodiments, after forming the blocking layer 230, a first region upper electrode metal connection layer 191 is formed that penetrates the blocking layer 230 and has a bottom surface in contact with the upper surface of the first upper electrode metal layer 253.

[0011] In a second aspect, the present disclosure provides a non-volatile two-terminal memory cell, the non-volatile two-terminal memory cell including: a lower dielectric layer 120 that surrounds a first region lower electrode metal connection layer 111 and exposes its upper surface; an isolation stack layer 130 that at least covers the first region lower electrode metal connection layer 111; a first region lower electrode via 141 that is formed in the isolation stack layer 130, and a bottom of the first region lower electrode via 141 is at least partially in contact with the first region lower electrode metal connection layer 111; a first stack layer 250 that is located within the first region lower electrode via 141, the first stack layer 250 including a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253.

[0012] In some embodiments, the non-volatile two-terminal memory cell further includes: a blocking layer 230 that at least covers the upper surface of the first stack layer 250, and a first region upper electrode metal connection layer 191 that penetrates the blocking layer 230, and a bottom of the first region upper electrode metal connection layer 191 is in contact with the upper surface of the first upper electrode metal layer 253.

[0013] In a third aspect, the present disclosure provides a memory that includes one or more non-volatile two-terminal memory cells according to embodiments of the present disclosure.

[0014] In a fourth aspect, the present disclosure provides an electronic device that includes the memory according to embodiments of the present disclosure.

[0015] By means of the preparation scheme of the non-volatile two-terminal memory cell provided above, embodiments of the present disclosure form a first stack layer in a first region lower electrode via to implement the preparation of the first lower electrode metal layer and the first upper electrode metal layer of the non-volatile two-terminal memory cell using only one patterning photomask layer, reducing production costs, simplifying the preparation process, avoiding the problem of alignment between the lower electrode and the upper electrode, and reducing the preparation difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary rather than restrictive manner, and identical or corresponding reference numerals represent identical or corresponding parts, wherein:

[0017] Figures 1A - 1F Shows a schematic cross-sectional structure diagram of a prior art non-volatile two-terminal memory cell;

[0018] Figure 2 Shows an exemplary structural block diagram of a method for fabricating a non-volatile two-terminal memory cell according to some embodiments of the present application;

[0019] Figures 3A - 3N Shows a schematic cross-sectional structure diagram of a semiconductor of a method for fabricating a non-volatile two-terminal memory cell according to some embodiments of the present disclosure;

[0020] Figures 4A - 4N Shows a schematic cross-sectional structure diagram of a semiconductor of a method for fabricating a non-volatile two-terminal memory cell according to some other embodiments of the present disclosure;

[0021] Figures 5A - 5H Shows a schematic cross-sectional structure diagram of a semiconductor of a method for fabricating a non-volatile two-terminal memory cell according to yet some other embodiments of the present disclosure.

[0022] Names of reference numerals:

[0023] 111 - First region lower electrode metal connection layer, 112 - Second region lower electrode metal connection layer, 120 - Lower dielectric layer, 130 - Isolation stack layer, 131 - Isolation stack first sub-layer, 132 - Isolation stack second sub-layer, 141 - First region lower electrode interconnection via, 151 - Second lower electrode metal layer, 1511 - Second lower electrode metal first sub-layer, 1512 - Second lower electrode metal second sub-layer, 152 - Second switching layer, 153 - Second upper electrode metal layer, 154 - Upper electrode hard mask layer, 159 - Sidewall, 170 - Upper dielectric layer, 191 - First region upper electrode metal connection layer, 192 - Second region upper electrode metal connection layer;

[0024] 230 - Blocking layer, 250 - First stack layer, 251 - First lower electrode metal layer, 2511 - First lower electrode metal first sub-layer, 2512 - First lower electrode metal second sub-layer, 252 - First switching layer, 253 - First upper electrode metal layer, 2531 - First upper electrode metal first sub-layer, 2532 - First upper electrode metal second sub-layer, 270 - Sacrificial layer. Detailed implementation manners

[0025] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0026] It should be understood that the terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0027] It should also be understood that the terms used in this disclosure specification are for the purpose of describing particular embodiments only and are not intended to limit this disclosure. As used in this disclosure specification and claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms. It should be further understood that the term "and / or" as used in this disclosure specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0028] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when", or "once", or "in response to determining", or "in response to detecting". Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as meaning "once determined", or "in response to determining", or "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]".

[0029] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0030] Figures 1A - 1F A schematic semiconductor cross-sectional structure diagram of preparing a non-volatile two-terminal storage cell in the prior art is shown.

[0031] Figure 1A A schematic semiconductor cross-sectional structure diagram of forming the second lower electrode metal sub-layer 1511 in the prior art is shown.

[0032] As Figure 1A shown, a lower dielectric layer 120 is provided to surround the first region lower electrode metal connection layer 111 and expose its upper surface. By a thin film deposition process, an isolation stack layer 130 is deposited on the upper surface of the first region lower electrode metal connection layer 111 and the upper surface of the lower dielectric layer 120. Among them, the isolation stack layer 130 may include an isolation stack sub-layer 131 and an isolation stack second sub-layer 132, and the isolation stack second sub-layer 132 covers the upper surface of the isolation stack sub-layer 131. By a photolithography process and an etching process, a first region lower electrode interconnection via 141 is formed in the isolation stack layer 130. By processes such as a thin film deposition process and chemical mechanical polishing, a second lower electrode metal sub-layer 1511 is formed in the first region lower electrode interconnection via 141.

[0033] Figure 1B Shows a schematic semiconductor cross-sectional structure diagram of depositing a second lower electrode metal bilayer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154 in the prior art.

[0034] As Figure 1B shown, the second lower electrode metal bilayer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 are sequentially deposited above the isolation stack layer 130 and the first sub-layer of the second lower electrode metal 1511 by a thin film deposition process. The first sub-layer of the second lower electrode metal 1511 and the second lower electrode metal bilayer 1512 covering the first sub-layer of the second lower electrode metal 1511 form the second lower electrode metal layer 151. The upper electrode hard mask layer 154 can be a conductive hard mask layer or a non-conductive hard mask layer.

[0035] Figure 1C Shows a schematic semiconductor cross-sectional structure diagram of etching the second lower electrode metal bilayer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 in the prior art.

[0036] As Figure 1C shown, a photolithography process and an etching process are used to etch a part of the second lower electrode metal bilayer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 to form a stacked structure.

[0037] Figure 1D Shows a schematic semiconductor cross-sectional structure diagram of depositing a sidewall 159 in the prior art.

[0038] As Figure 1D shown, the sidewall 159 is deposited on the exposed areas of the second lower electrode metal bilayer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 after etching. The sidewall 159 can be a single layer or multiple layers, and covers all the sides of the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154, as well as at least a part of the sides of the second lower electrode metal bilayer 1512.

[0039] Figure 1E Shows a schematic semiconductor cross-sectional structure diagram of etching the sidewall 159 and the second lower electrode metal bilayer 1512 in the prior art.

[0040] As Figure 1EAs shown, the deposited sidewall 159 and the second lower electrode metal bilayer 1512 are etched, and the etching stops at the upper surface of the isolation stack layer 130, so that the sidewall 159 wraps all the side surfaces of the second lower electrode metal bilayer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154.

[0041] Figure 1F The schematic cross-sectional structure diagram of the semiconductor for forming the first region upper electrode metal connection layer 191 in the prior art is shown.

[0042] As Figure 1F shown, an upper dielectric layer 170 is deposited in the exposed area of the above-formed structure, and a first region upper electrode interconnection via hole is formed in the upper dielectric layer 170 through a photolithography process and an etching process, and a first region upper electrode metal connection layer 191 is formed in the first region upper electrode interconnection via hole. When the upper electrode hard mask layer 154 is a conductive hard mask layer, the first region upper electrode interconnection via hole can partially penetrate into the upper electrode hard mask layer 154 to conduct the first region upper electrode metal connection layer 191, the upper electrode hard mask layer 154, and the second upper electrode metal layer 153. When the upper electrode hard mask layer 154 is a non-conductive hard mask layer, the first region upper electrode interconnection via hole can penetrate through the upper electrode hard mask layer 154 to conduct the first region upper electrode metal connection layer 191 and the second upper electrode metal layer 153. The first lower electrode metal sublayer 1511 and the second lower electrode metal bilayer 1512 of the second lower electrode metal layer 151 are in contact with each other. The second lower electrode metal layer 151 is in contact with the first region lower electrode metal connection layer 111 to conduct the second lower electrode metal layer 151 and the first region lower electrode metal connection layer 111.

[0043] In the process of fabricating a non-volatile two-terminal memory cell in the prior art, when forming the first sub-layer 1511 of the second lower electrode metal, a first-region lower electrode interconnection via 141 is formed in the isolation stack layer 130 through a photolithography process and an etching process, and the first sub-layer 1511 of the second lower electrode metal is deposited within the first-region lower electrode interconnection via 141; when forming the second sub-layer 1512 of the second lower electrode metal, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154, photolithography and etching processes are required to etch the second sub-layer 1512 of the second lower electrode metal, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154. Thus, forming the first sub-layer 1511 of the second lower electrode metal and forming the second sub-layer 1512 of the second lower electrode metal, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 both require a patterned mask layer formed by a corresponding mask plate. Due to the manufacturing steps, generally, the fabrication of the lower electrode and the upper electrode of the non-volatile two-terminal memory cell each requires a different patterned mask layer, which greatly increases the production cost and the fabrication process is also relatively complex. At the same time, such a fabrication method also involves the problem of alignment between the lower electrode and the upper electrode during the fabrication of the lower electrode and the upper electrode, which makes the fabrication of the non-volatile two-terminal memory cell difficult.

[0044] In view of this, the embodiments of the present disclosure provide a fabrication solution for a non-volatile two-terminal memory cell, which forms a first stack layer 250 in the first-region lower electrode interconnection via 141 to achieve the formation of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 of the non-volatile two-terminal memory cell using only one patterned mask layer, reducing the fabrication cost, shortening the fabrication process flow of the non-volatile two-terminal memory cell, and reducing the fabrication difficulty.

[0045] Figure 2 An exemplary structural block diagram of a method 200 for fabricating a non-volatile two-terminal memory cell according to some embodiments of the present application is shown.

[0046] As Figure 2 shown, in step S210, a lower dielectric layer 120 surrounding the first-region lower electrode metal connection layer 111 and having its upper surface exposed is provided. In step S220, an isolation stack layer 130 covering at least the first-region lower electrode metal connection layer 111 is formed. In step S230, a first-region lower electrode interconnection via 141 is formed in the isolation stack layer 130 based on a patterned mask layer, and the bottom of the first-region lower electrode interconnection via 141 at least partially contacts the first-region lower electrode metal connection layer 111. In step S240, a first stack layer 250 including a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253 is formed in the first-region lower electrode interconnection via 141.

[0047] The following is based on Figure 2 the preparation process of a non-volatile two-terminal memory cell, in combination with Figures 3A - 3N the schematic semiconductor cross-sectional structure shown in

[0048] Figure 3A The schematic semiconductor cross-sectional structure of the lower dielectric layer 120 according to an embodiment of the present application is shown.

[0049] As Figure 3A shown, a lower dielectric layer 120 surrounding the first-region lower electrode metal connection layer 111 and having its upper surface exposed is provided.

[0050] Specifically, the material used for the first-region lower electrode metal connection layer 111 can be copper metal. The most important advantages of copper metal compared with other metals are high electrical conductivity, high thermal conductivity, corrosion resistance, appropriate strength, easy processability, etc. In the embodiment of the present application, the first-region lower electrode metal connection layer 111 can also use other metals as needed, which is not limited herein.

[0051] The material used for the lower dielectric layer 120 can be silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, low dielectric constant (Low-k) material, etc. More specifically, the low dielectric constant (Low-k) material can be porous silicon dioxide, fluorinated silicon glass, etc. In the embodiment of the present application, the lower dielectric layer 120 can also select other materials according to the actual application scenario and process requirements, which is not limited herein.

[0052] In the process of providing the lower dielectric layer 120 surrounding the first-region lower electrode metal connection layer 111 and having its upper surface exposed, it can be formed by various known processes, and the embodiment of the present application has no limitation in this regard. For example, the process of providing the lower dielectric layer 120 surrounding the first-region lower electrode metal connection layer 111 and having its upper surface exposed includes: First, provide the lower dielectric layer 120, form a layer of photoresist on the lower dielectric layer 120, selectively expose the photoresist through an exposure machine, develop and remove the exposed or unexposed part of the photoresist, etch or deposit to form a pattern in the exposed area, remove the remaining photoresist, continue to form the required groove through dry etching or wet etching, and form the remaining part after etching into the lower dielectric layer 120. Then, deposit a metal material in the groove. Finally, perform a planarization process on the metal material to form the first-region lower electrode metal connection layer 111, so that the upper surface of the first-region lower electrode metal connection layer 111 is flush with the upper surface of the lower dielectric layer 120. Thus, the lower dielectric layer 120 surrounding the first-region lower electrode metal connection layer 111 and having its upper surface exposed is obtained.

[0053] By providing a lower dielectric layer 120 that surrounds the first-zone lower electrode metal connection layer 111 and exposes its upper surface, in a multi-layer metal interconnect structure, the first-zone lower electrode metal connection layer 111 and the subsequently formed first lower electrode metal layer 251 can be isolated from other irrelevant parts. Thereby preventing current from flowing in unwanted paths and avoiding short circuits and leakage.

[0054] Figure 3B The semiconductor cross-sectional structure diagram of depositing the isolation stack layer 130 according to an embodiment of the present application is shown.

[0055] As Figure 3B shown, through a thin-film deposition process, the isolation stack layer 130 is deposited on the upper surface of the first-zone lower electrode metal connection layer 111 and the upper surface of the lower dielectric layer 120. Among them, the isolation stack layer 130 may include an isolation stack first sub-layer 131 and an isolation stack second sub-layer 132, and the isolation stack second sub-layer 132 covers the upper surface of the isolation stack first sub-layer 131.

[0056] In some embodiments of the present application, during the formation of the isolation stack layer 130, at least the deposited isolation stack layer 130 should cover the first-zone lower electrode metal connection layer 111.

[0057] Specifically, the isolation stack first sub-layer 131 can be made of a silicon nitride (SiN) thin film or a doped silicon carbide (NDC, Nitride Doped Silicon Carbide) thin film, and the isolation stack second sub-layer 132 can be made of a low-temperature oxide layer (LTO, Low Temperature Oxide), a silicon dioxide layer (SiO2), or a silicon-rich oxide layer (SRO, Silicon Rich Oxide), etc. In the embodiments of the present application, the isolation stack first sub-layer 131 and the isolation stack second sub-layer 132 can also be selected from other materials according to actual application scenarios and process requirements, which are not limited herein.

[0058] By depositing the isolation stack first sub-layer 131 and the isolation stack second sub-layer 132, the first-zone lower electrode metal connection layer 111 can be protected from damage in subsequent steps.

[0059] Figure 3C The semiconductor cross-sectional structure diagram of forming the first-zone lower electrode interconnection via 141 according to an embodiment of the present application is shown.

[0060] As Figure 3C shown, the first-zone lower electrode interconnection via 141 is etched in the isolation stack layer 130.

[0061] In an embodiment of the present application, the first-zone lower electrode interconnection via 141 is mainly formed by lithography technology and can be fabricated using various known processes. There are no limitations in this regard in the embodiments of the present application. For example, the preparation process of the first-zone lower electrode interconnection via 141 includes: forming a photoresist on the upper surface of the isolation stack layer 130, selectively exposing the photoresist through an exposure machine, developing to remove the exposed or unexposed portions of the photoresist to form a patterned photomask layer. Then, the isolation stack layer 130 not covered by the patterned photomask layer is etched by dry etching or wet etching to form the first-zone lower electrode interconnection via 141, and the bottom of the first-zone lower electrode interconnection via 141 is at least partially in contact with the first-zone lower electrode metal connection layer 111. After forming the first-zone lower electrode interconnection via 141, the patterned photomask layer is removed.

[0062] In an embodiment of the present application, the first-zone lower electrode interconnection via 141 can be designed as a frustum-shaped structure with a larger upper end and a smaller lower end, such as a frustum of a cone structure or a frustum of a trapezoid structure, etc. Designing the first-zone lower electrode interconnection via 141 as a frustum-shaped structure determines the cross-sectional shape of each layer of the stack layer subsequently deposited in the first-zone lower electrode interconnection via 141, which can not only ensure the required contact area between the layers of the stack layer subsequently deposited in the first-zone lower electrode interconnection via 141 but also effectively reduce the overall volume of the stack layer.

[0063] In an embodiment of the present application, the first-zone lower electrode interconnection via 141 can also be selected with other structural shapes according to actual application scenarios and process requirements, which are not limited herein.

[0064] In an embodiment of the present application, the cross-sectional shape of the first-zone lower electrode interconnection via 141 is an inverted trapezoid.

[0065] In an embodiment of the present application, the upper base width of the inverted trapezoid is greater than the lower base width of the inverted trapezoid, and the upper base width of the inverted trapezoid is greater than The lower base width of the inverted trapezoid is greater than

[0066] In an embodiment of the present application, the angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

[0067] In other embodiments of the present application, the size of the first-zone lower electrode interconnection via 141 can also be set based on the size of the first stack layer 250 to be formed in the first-zone lower electrode interconnection via 141 subsequently and the process adopted during the deposition of the first stack layer 250.

[0068] Figure 3D The semiconductor cross-sectional structure diagram showing the deposition of the first lower electrode metal layer 251 and the first switching layer 252 in the embodiment of the present application is shown.

[0069] As Figure 3DAs shown, a first lower electrode metal layer 251 and a first switching layer 252 covering the first lower electrode metal layer 251 are sequentially deposited on the upper surface of the isolation stack layer 130, on the inner wall and the bottom of the first region lower electrode interconnection via hole 141.

[0070] In an embodiment of the present application, during the deposition of the first lower electrode metal layer 251, at least the deposited first lower electrode metal layer 251 and the first switching layer 252 should cover the inner wall and the bottom of the first region lower electrode interconnection via hole 141.

[0071] In an embodiment of the present application, the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 form an electrical connection through the first region lower electrode interconnection via hole 141.

[0072] In an embodiment of the present application, the first lower electrode metal layer 251 can be a single-layer or multi-layer structure, and the material used can be one of TiN (titanium nitride), Ti (titanium), Ta (tantalum), W (tungsten), etc. The same metal material can also be used for the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111, so that the first lower electrode metal layer 251 and the first region lower electrode metal connection layer 111 are in close contact to avoid the appearance of holes.

[0073] In a preferred embodiment of the present application, the first lower electrode metal layer 251 adopts a two-layer structure.

[0074] Figure 3E The semiconductor cross-sectional structure diagram of depositing the first lower electrode metal layer 251 and the first switching layer 252 in the preferred embodiment is shown.

[0075] As Figure 3E shown, the first lower electrode metal layer 251 includes a first lower electrode metal first sub-layer 2511 and a first lower electrode metal second sub-layer 2512 covering the upper surface of the first lower electrode metal first sub-layer 2511.

[0076] Specifically, the material used for the first lower electrode metal first layer 2511 can be TiN (titanium nitride), and the material used for the first lower electrode metal second layer 2512 can be W (tungsten). The first lower electrode metal second layer 2512 can serve as a connection layer between the first lower electrode metal first layer 2511 and the first switching layer 252. By setting the material of the first lower electrode metal second layer 2512 to be W (tungsten), not only can the better thermal conductivity of the first lower electrode metal second layer 2512 be ensured, the resistance of the first lower electrode metal second layer 2512 can be guaranteed to be small, so that heat can be quickly conducted, heat dissipation can be promoted, and heat generation can be reduced, thereby reducing the thermal damage to the prepared non-volatile two-terminal storage unit. By setting the material of the first lower electrode metal second layer 2512 to be W (tungsten), the higher inertness of the first lower electrode metal second layer 2512 can also be ensured, so that a chemical reaction between the first lower electrode metal second layer 2512 and the first switching layer 252 can be avoided, and the thermal stability of the prepared non-volatile two-terminal storage unit can be guaranteed.

[0077] In an embodiment of the present application, the material of the foregoing first switching layer 252 can be a metal oxide such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), tantalum oxide (TaO), etc., which is used to change the resistance between the first lower electrode metal layer 251 and the subsequently deposited upper electrode metal layer. The first switching layer 252 can also be selected from other materials according to the actual application scenario and process requirements, which are not limited herein.

[0078] Figure 3F The semiconductor cross-sectional structure diagram showing the filling of the sacrificial layer 270 in the first region lower electrode interconnection via hole 141 in the embodiment of the present application is shown.

[0079] As Figure 3F shown, the sacrificial layer 270 is filled on the first switching layer 252, and the upper surface of the first switching layer 252 is covered by the sacrificial layer 270.

[0080] In an embodiment of the present application, during the formation of the sacrificial layer 270, at least the remaining space of the first region lower electrode interconnection via hole 141 is filled with the formed sacrificial layer 270.

[0081] Specifically, the sacrificial layer 270 can be made of a carbon coating (SOC, spin on carbon) material. Since the carbon coating material has good fluidity, the surface of the formed sacrificial layer 270 is flat, and the sacrificial layer 270 can accurately cover every corner of the remaining space of the first region lower electrode via hole 141. It not only effectively isolates the interference of the external environment to the first region lower electrode via hole 141, but also serves as a solid barrier to protect the first lower electrode metal layer 251 and the first switching layer 252 in the first region lower electrode via hole 141 from damage.

[0082] Figure 3G The semiconductor cross-sectional structure diagram of etching the first lower electrode metal layer 251, the first switching layer 252, and the sacrificial layer 270 according to the embodiment of the present application is shown.

[0083] As Figure 3G shown, the first lower electrode metal layer 251, the first switching layer 252, and the sacrificial layer 270 outside the first region lower electrode via hole 141 area are etched, and the remaining sequentially stacked first lower electrode metal layer 251, first switching layer 252, and sacrificial layer 270 are filled in the first region lower electrode via hole 141.

[0084] In the embodiment of the present application, the first lower electrode metal layer 251, the first switching layer 252, and the sacrificial layer 270 outside the first region lower electrode via hole 141 area are etched by a Blanket ETCH process. The Blanket ETCH process refers to the process of removing all or part of the thin film on the surface of the semiconductor layer. This etching process is opposite to the aforementioned process of etching with a patterned mask layer. In the aforementioned process of etching with a patterned mask layer, the pattern of the patterned mask layer is transferred to the isolation stack layer 130, while in the process of etching the first lower electrode metal layer 251, the first switching layer 252, and the sacrificial layer 270 by the Blanket ETCH process, there is no involvement of using a patterned mask layer.

[0085] Specifically, during the process of etching the first lower electrode metal layer 251, the first switching layer 252, and the sacrificial layer 270 outside the first region lower electrode via hole 141 area by the Blanket ETCH process, a maskless back-etching is performed on the entire plane of the above-formed structure on the etching machine table until the first lower electrode metal layer 251 and the first switching layer 252 in the first region lower electrode via hole 141 are exposed, then the etching is stopped, and the exposed parts of the remaining first lower electrode metal layer 251, the exposed parts of the first switching layer 252, and the upper surface of the sacrificial layer 270 are made flush.

[0086] Due to the protection of the sacrificial layer 270 for the first lower electrode metal layer 251 and the first switching layer 252, the first lower electrode metal layer 251 and the first switching layer 252 in the first-region lower electrode through-hole 141 can be avoided from being damaged during the etching process.

[0087] Figure 3H The schematic cross-sectional structure diagram of the semiconductor for removing the remaining sacrificial layer 270 according to the embodiment of the present application is shown.

[0088] As Figure 3H shown, the sacrificial layer 270 in the region of the first-region lower electrode through-hole 141 is removed.

[0089] In the embodiment of the present application, the Asher process is used to etch and remove the sacrificial layer 270 in the region of the first-region lower electrode through-hole 141, and the etching stops at the surface of the first switching layer 252. The Asher process uses plasma reaction for etching to precisely etch the corresponding semiconductor material layer while avoiding damage to adjacent structures. The Asher process can etch only specific materials based on the chemical reaction kinetic parameters of different semiconductor materials without affecting other materials, thereby reducing the damage to the surface of the corresponding semiconductor material layer.

[0090] Compared with the Blanket ETCH process, the main feature of the Asher process is that it highly depends on the material chemical differences. It is not only limited to etching in the vertical direction. Usually, it does not require photoresist or hard mask to define patterns or similar means, and has little damage to non-target surfaces. It is often used for sacrificial layer removal, surface cleaning and pretreatment, etc., especially suitable for scenarios with extremely high atomic-level accuracy requirements in advanced processes below 5nm.

[0091] By using the Asher process to etch and remove the sacrificial layer 270 in the region of the first-region lower electrode through-hole 141, damage to the surface of the first switching layer 252 is avoided.

[0092] Figure 3I The schematic cross-sectional structure diagram of the semiconductor for depositing the first upper electrode metal layer 253 according to the embodiment of the present application is shown.

[0093] As Figure 3I shown, the first upper electrode metal layer 253 is deposited on the upper surface of the isolation stack layer 130, the exposed region of the first lower electrode metal layer 251, and the exposed region of the first switching layer 252.

[0094] In the embodiment of the present application, during the process of depositing the first upper electrode metal layer 253 material, at least the remaining space of the first-region lower electrode through-hole 141 should be filled with the formed first upper electrode metal layer 253 material.

[0095] Figure 3JA schematic cross-sectional structure diagram of a semiconductor showing a part of the material of the first upper electrode metal layer 253 removed according to an embodiment of the present application is shown.

[0096] As Figure 3J shown, by using a planarization process, a part of the material of the first upper electrode metal layer 253 is removed, and the upper surface of the first upper electrode metal layer 253 in the region of the first region lower electrode interconnection via 141 is made flush with the upper surface of the isolation stack layer 130, thereby forming a first stack layer 250 including a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253 in the first region lower electrode interconnection via 141.

[0097] Specifically, during the planarization process, chemical mechanical polishing (CMP) technology can be adopted.

[0098] In summary, in the embodiment of the present application, after the first region lower electrode interconnection via 141 is formed, steps such as depositing the first lower electrode metal layer 251, depositing the first switching layer 252, depositing the sacrificial layer 270, etching using a blanket etch process, etching using an asher process, depositing the first upper electrode metal layer 253, and planarization processing are required to make the upper surface of the first stack layer 250 flush with the upper surface of the isolation stack layer 130.

[0099] In the embodiment of the present application, when the first region lower electrode interconnection via 141 is designed as a trapezoidal structure, since the first lower electrode metal layer 251 covers the inner wall and bottom of the first region lower electrode interconnection via 141, the first switching layer 252 covers the first lower electrode metal layer 251, and the first upper electrode metal layer 253 covers the first switching layer 252, the contact area between the layers of the first stack layer 250 is increased. Thereby, the contact stability between the first lower electrode metal layer 251 and the first upper electrode metal layer 253 and the first switching layer 252 can be improved, thereby improving the device performance, and it is beneficial to the formation of the conductive filaments of the non-volatile two-terminal memory cell prepared.

[0100] In the embodiment of the present application, the aforementioned first upper electrode metal layer 253 can be a single-layer or multi-layer structure.

[0101] In a preferred embodiment of the present application, the first upper electrode metal layer 253 adopts a two-layer structure.

[0102] Figure 3K A schematic cross-sectional structure diagram of a semiconductor showing that both the first lower electrode metal layer 251 and the first upper electrode metal layer 253 are two layers in a preferred embodiment of the present application is shown.

[0103] As Figure 3KAs shown, the first lower electrode metal layer 251 includes a first lower electrode metal sub-layer 2511 and a first lower electrode metal second sub-layer 2512 covering the surface of the first lower electrode metal sub-layer 2511, and the first upper electrode metal layer 253 includes a first upper electrode metal sub-layer 2531 and a first upper electrode metal second sub-layer 2532 covering the surface of the first upper electrode metal sub-layer 2531.

[0104] Specifically, the material used for the first upper electrode metal sub-layer 2531 is more easily oxidized than the material used for the first upper electrode metal second sub-layer 2532. The material used for the first upper electrode metal sub-layer 2531 can be AlN (aluminum nitride), and the material used for the first upper electrode metal second sub-layer 2532 can be TiN (titanium nitride). The first upper electrode metal sub-layer 2531 and the first upper electrode metal second sub-layer 2532 can also use other materials, which are not limited here.

[0105] The material used for the first upper electrode metal sub-layer 2531 is more easily oxidized than the material used for the first upper electrode metal second sub-layer 2532. The purpose is that, as the upper electrode of the non-volatile two-terminal storage unit, the first upper electrode metal sub-layer 2531 provides metal ions for the first switching layer 252, but prevents the first upper electrode metal sub-layer 2531 from being oxidized and causing adverse effects, such as problems like reduced conductivity. Therefore, the first upper electrode metal second sub-layer 2532, which is less easily oxidized relative to the first upper electrode metal sub-layer 2531, covers the first upper electrode metal sub-layer 2531, thereby reducing the possibility of the first upper electrode metal sub-layer 2531 being oxidized and ensuring that the characteristics of the non-volatile two-terminal storage unit are not affected.

[0106] In an embodiment of the present application, after the formed first stacked layer 250, a first region upper electrode metal connection layer 191 is formed above the first stacked layer 250.

[0107] Figure 3L The semiconductor cross-sectional structure diagram showing the formation of the upper dielectric layer 170 and the first region upper electrode metal connection layer 191 in the embodiment of the present application is shown.

[0108] As Figure 3LAs shown, an upper dielectric layer 170 is deposited on the upper surface of the above-formed structure, and a first-region upper-electrode interconnection via hole is formed in the upper dielectric layer 170 through a photolithography process and an etching process, and a first-region upper-electrode metal connection layer 191 is filled in the first-region upper-electrode interconnection via hole. The bottom of the first-region upper-electrode metal connection layer 191 is in contact with the upper surface of the first upper-electrode metal layer 253. The entire lower surface of the bottom of the first-region upper-electrode metal connection layer 191 is in contact with the upper surface of the first upper-electrode metal layer 253, enabling sufficient contact between the first-region upper-electrode metal connection layer 191 and the first upper-electrode metal layer 253, and preventing partial lower surface of the bottom of the first-region upper-electrode metal connection layer 191 from contacting the upper surface of the first lower-electrode metal layer 251 to cause a short circuit.

[0109] Specifically, the material used for the upper dielectric layer 170 can be silicon nitride (Si3N4). In the embodiments of the present application, the upper dielectric layer 170 can also be selected according to actual application scenarios and process requirements, and other materials are not limited herein.

[0110] The upper dielectric layer 170 can isolate the first upper-electrode metal layer 253 and the first-region upper-electrode metal connection layer 191 from other parts, thereby preventing current from flowing on unnecessary paths and avoiding the occurrence of short circuits and leakage phenomena.

[0111] Specifically, the first-region upper-electrode metal connection layer 191 can be made of copper metal. In the embodiments of the present application, the first-region upper-electrode metal connection layer 191 can also be made of other metals according to needs, and other metals are not limited herein.

[0112] In a preferred embodiment of the present application, the first upper-electrode metal layer 253 includes a first upper-electrode metal first sub-layer 2531 and a first upper-electrode metal second sub-layer 2532 covering the surface of the first upper-electrode metal first sub-layer 2531, and when the material used for the first upper-electrode metal first sub-layer 2531 is more easily oxidized than the material used for the first upper-electrode metal second sub-layer 2532, the bottom of the first-region upper-electrode interconnection via hole is in contact with the upper surface of the first upper-electrode metal second sub-layer 2532.

[0113] Figure 3M A schematic cross-sectional structure diagram of a semiconductor showing the formation of the upper dielectric layer 170 and the first-region upper-electrode metal connection layer 191 in a preferred embodiment of the present application is shown.

[0114] As Figure 3MAs shown, the first upper electrode metal layer 253 includes a first upper electrode metal sub-layer 2531 and a second upper electrode metal sub-layer 2532 covering the surface of the first upper electrode metal sub-layer 2532. When the material used for the first upper electrode metal sub-layer 2531 is more easily oxidized than the material used for the second upper electrode metal sub-layer 2532, the bottom of the first region upper electrode metal connection layer 191 formed is in contact with the upper surface of the second upper electrode metal sub-layer 2532. The entire lower surface of the bottom of the first region upper electrode metal connection layer 191 is in contact with the upper surface of the second upper electrode metal sub-layer 2532, enabling the first region upper electrode metal connection layer 191 to be in full contact with the second upper electrode metal sub-layer 2532 and preventing partial contact between the lower surface of the bottom of the first region upper electrode metal connection layer 191 and the upper surface of the first lower electrode metal layer 251, which could cause a short circuit.

[0115] By having the bottom of the aforementioned first region upper electrode metal connection layer 191 in contact with the upper surface of the second upper electrode metal sub-layer 2532, it can be prevented that when the first region upper electrode metal connection layer 191 contacts the first upper electrode metal sub-layer 2531, the first upper electrode metal sub-layer 2531 is easily oxidized to generate high-limited oxides, which would affect the conduction between the first region upper electrode metal connection layer 191 and the first upper electrode metal layer 253.

[0116] Figure 3N A schematic cross-sectional structure diagram of a semiconductor for forming a non-volatile two-terminal memory cell region and a peripheral circuit region according to an embodiment of the present application is shown.

[0117] As Figure 3N shown, during the preparation process of the non-volatile two-terminal memory cell of the embodiment of the present application, a second region lower electrode metal connection layer 112 in the peripheral circuit region and a second region upper electrode metal connection layer 192 in the peripheral circuit region can also be generated.

[0118] Specifically, during the process of providing a lower dielectric layer 120 that surrounds the first region lower electrode metal connection layer 111 and exposes its upper surface, a second region lower electrode metal connection layer 112 in the peripheral circuit region is also provided. Among them, the second region lower electrode metal connection layer 112 in the peripheral circuit region is also surrounded by the lower dielectric layer 120, and the upper surface of the second region lower electrode metal connection layer 112 is exposed.

[0119] The structure, material used, and preparation process of the second region lower electrode metal connection layer 112 in the peripheral circuit region can be the same as those of the first region lower electrode metal connection layer 111, and will not be elaborated here.

[0120] Specifically, the isolation stack layer 130 and the upper dielectric layer 170 can be etched in the peripheral circuit region, and the etching is stopped at the upper surface of the second region lower electrode metal connection layer 112 in the peripheral circuit region, forming the second region upper electrode interconnection through holes in the peripheral circuit region. Then, the second region upper electrode metal connection layer 192 is formed in the second region upper electrode interconnection through holes in the peripheral circuit region, connecting the second region upper electrode metal connection layer 192 and the second region lower electrode metal connection layer 112. Thus, the preparation of the semiconductor structure in the peripheral circuit region is completed.

[0121] The structure, materials used, and preparation process of the second region upper electrode metal connection layer 192 in the peripheral circuit region can be the same as those of the first region upper electrode metal connection layer 191, and will not be elaborated here.

[0122] Next, based on Figure 2 the preparation process of the non-volatile two-terminal memory cell preparation method, combined with Figures 4A - 4N the schematic cross-sectional semiconductor structure diagram shown, the exemplary process flow of the non-volatile two-terminal memory cell preparation method 200 using other embodiments of the present application will be described in detail.

[0123] Among them, the preparation steps of the non-volatile two-terminal memory cell combined with Figures 4A - 4D are the same as those of the non-volatile two-terminal memory cell combined with Figures 3A - 3D shown, so no further description will be given here.

[0124] Figure 4E shows the schematic cross-sectional semiconductor structure diagram of depositing the first upper electrode metal sub-layer 2531 in the embodiment of the present application.

[0125] In the embodiment of the present application, at least the deposited first upper electrode metal sub-layer 2531 should cover the inner wall and bottom of the first region lower electrode interconnection through hole 141.

[0126] Figure 4F shows the schematic cross-sectional semiconductor structure diagram of filling the sacrificial layer 270 in the first region lower electrode interconnection through hole 141 in the embodiment of the present application.

[0127] As Figure 4F shown, the sacrificial layer 270 is formed on the first upper electrode metal sub-layer 2531, and the sacrificial layer 270 covers the upper surface of the first upper electrode metal sub-layer 2531.

[0128] In the embodiment of the present application, during the formation of the sacrificial layer 270, at least the formed sacrificial layer 270 should fill the remaining space of the first region lower electrode interconnection through hole 141.

[0129] Specifically, the sacrificial layer 270 can be made of a carbon coating (SOC, spin on carbon) material. Since the carbon coating material has good fluidity, the surface of the formed sacrificial layer 270 is flat, and the sacrificial layer 270 can accurately cover every corner of the remaining space of the first-zone lower electrode interconnection via 141. It not only effectively isolates the interference of the external environment to the first-zone lower electrode interconnection via 141, but also serves as a solid barrier to protect the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal sub-layer 2531 in the first-zone lower electrode interconnection via 141 from being damaged.

[0130] Figure 4G The semiconductor cross-sectional structure diagram showing the etching of the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal sub-layer 2531, and the sacrificial layer 270 according to an embodiment of the present application is shown.

[0131] As Figure 4G shown, the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal sub-layer 2531, and the sacrificial layer 270 outside the first-zone lower electrode interconnection via 141 region are etched, and the remaining successively stacked first lower electrode metal layer 251, first switching layer 252, first upper electrode metal sub-layer 2531, and sacrificial layer 270 fill the first-zone lower electrode interconnection via 141.

[0132] In the embodiment of the present application, a Blanket ETCH process is used to etch the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal sub-layer 2531, and the sacrificial layer 270 outside the first-zone lower electrode interconnection via 141 region. The Blanket ETCH process refers to the process of removing all or part of the thin film on the surface of the semiconductor layer. This etching process is opposite to the aforementioned process of etching with a patterned mask layer. In the process of etching the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal sub-layer 2531, and the sacrificial layer 270 using the Blanket ETCH process, no mask plate is involved.

[0133] Specifically, during the etching process of the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal sub-layer 2531, and the sacrificial layer 270 outside the area of the first-region lower electrode interconnection via 141 using the Blanket ETCH process, a maskless back-etching is performed on the entire plane of the structure formed above on the etching machine table until the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal sub-layer 2531 in the first-region lower electrode interconnection via 141 are exposed, then the etching is stopped, and the upper surfaces of the remaining first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal sub-layer 2531, and the sacrificial layer 270 are made flush.

[0134] Due to the protection of the sacrificial layer 270 for the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal sub-layer 2531, the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal sub-layer 2531 in the first-region lower electrode interconnection via 141 can be avoided from being damaged during the etching process.

[0135] Figure 4H The schematic cross-sectional structure diagram of the semiconductor showing the removal of the remaining sacrificial layer 270 in the embodiment of the present application is shown.

[0136] As Figure 4H shown, the sacrificial layer 270 in the area of the first-region lower electrode interconnection via 141 is removed.

[0137] In the embodiment of the present application, the Asher process is used to remove the sacrificial layer 270 in the area of the first-region lower electrode interconnection via 141, and the etching is stopped at the surface of the first upper electrode metal sub-layer 2531. The Asher process uses plasma reaction for etching to precisely etch the corresponding semiconductor material layer while avoiding damage to adjacent structures. The Asher process can etch only specific materials based on the chemical reaction kinetic parameters of different semiconductor materials without affecting other materials, thereby reducing the damage to the surface of the corresponding semiconductor material layer.

[0138] By using the Asher process to etch and remove the sacrificial layer 270 in the area of the first-region lower electrode interconnection via 141, damage to the surface of the first upper electrode metal sub-layer 2531 is avoided.

[0139] Figure 4I The schematic cross-sectional structure diagram of the semiconductor showing the deposition of the second upper electrode metal sub-layer 2532 in the embodiment of the present application is shown.

[0140] As Figure 4IAs shown, a second sub-layer 2532 of the first upper electrode metal is deposited on the upper surface of the isolation stack layer 130, the exposed area of the first lower electrode metal layer 251, the exposed area of the first switching layer 252, and the exposed area of the first sub-layer 2531 of the first upper electrode metal.

[0141] In an embodiment of the present application, during the deposition of the second sub-layer 2532 of the first upper electrode metal, at least the remaining space of the first area lower electrode through-hole 141 should be filled by the formed second sub-layer 2532 of the first upper electrode metal.

[0142] Figure 4J A schematic cross-sectional structure diagram of a semiconductor showing the removal of part of the material of the second sub-layer 2532 of the first upper electrode metal in an embodiment of the present application is shown.

[0143] As Figure 4J shown, using a planarization process, part of the material of the second sub-layer 2532 of the first upper electrode metal is removed, and the upper surface of the second sub-layer 2532 of the first upper electrode metal within the area of the first area lower electrode through-hole 141 is made flush with the upper surface of the isolation stack layer 130, thereby forming a first stack layer 250 including the first lower electrode metal layer 251, the first switching layer 252, the first sub-layer 2531 of the first upper electrode metal, and the second sub-layer 2532 of the first upper electrode metal within the first area lower electrode through-hole 141. Moreover, the first sub-layer 2531 of the first upper electrode metal and the second sub-layer 2532 of the first upper electrode metal form the first upper electrode metal layer 253.

[0144] Specifically, during the planarization process, a chemical mechanical planarization technique (CMP, Chemical Mechanical Polishing) can be adopted.

[0145] In summary, it can be seen that in an embodiment of the present application, after the formation of the first area lower electrode through-hole 141, steps such as depositing the first lower electrode metal layer 251, depositing the first switching layer 252, depositing the first sub-layer 2531 of the first upper electrode metal, depositing the sacrificial layer 270, etching using a blanket etch process, etching using an Asher process, depositing the second sub-layer 2532 of the first upper electrode metal, and planarization processing are required to make the upper surface of the first stack layer 250 flush with the upper surface of the isolation stack layer 130.

[0146] In an embodiment of the present application, when the first region lower electrode interconnection via 141 is designed as a trapezoidal structure, since the first lower electrode metal layer 251 covers the inner wall and bottom of the first region lower electrode interconnection via 141, the first switching layer 252 covers the first lower electrode metal layer 251, the first upper electrode metal first sub-layer 2531 covers the first switching layer 252, and the first upper electrode metal second sub-layer 2532 covers the first upper electrode metal first sub-layer 2531, the contact area between the layers of the first stacked layer 250 is increased. Thereby, the contact stability between the first lower electrode metal layer 251, the first switching layer 252, the first upper electrode metal first sub-layer 2531, and the first upper electrode metal second sub-layer 2532 can be improved, thereby improving the device performance, and it is beneficial to the formation of the conductive filaments of the non-volatile two-terminal storage unit prepared.

[0147] In an embodiment of the present application, the aforementioned first lower electrode metal layer 251 may be a multi-layer structure.

[0148] In a preferred embodiment of the present application, the first lower electrode metal layer 251 adopts a two-layer structure.

[0149] Figure 4K The schematic cross-sectional structure diagram of the semiconductor shows that both the first lower electrode metal layer 251 and the first upper electrode metal layer 253 in the preferred embodiment of the present application are two layers.

[0150] As Figure 4K shown, the first lower electrode metal layer 251 includes a first lower electrode metal first sub-layer 2511 and a first lower electrode metal second sub-layer 2512 covering the surface of the first lower electrode metal first sub-layer 2511, and the first upper electrode metal layer 253 includes a first upper electrode metal first sub-layer 2531 and a first upper electrode metal second sub-layer 2532 covering the surface of the first upper electrode metal first sub-layer 2531.

[0151] Specifically, the material used for the first upper electrode metal first sub-layer 2531 is more easily oxidized than the material used for the first upper electrode metal second sub-layer 2532. The material used for the first upper electrode metal first sub-layer 2531 may be AlN (aluminum nitride), and the material used for the first upper electrode metal second sub-layer 2532 may be TiN (titanium nitride). The first upper electrode metal first sub-layer 2531 and the first upper electrode metal second sub-layer 2532 may also use other materials, which are not limited here.

[0152] The material used for the first upper electrode metal first layer 2531 is more easily oxidized than the material used for the first upper electrode metal second layer 2532. The purpose is that, as the upper electrode of the non-volatile two-terminal storage unit, the first upper electrode metal first layer 2531 provides metal ions for the first switching layer 252, but prevents the first upper electrode metal first layer 2531 from being oxidized and causing adverse effects, such as problems like reduced conductivity. Therefore, the first upper electrode metal second layer 2532, which is less easily oxidized than the first upper electrode metal first layer 2531, covers the first upper electrode metal first layer 2531 to reduce the possibility of the first upper electrode metal first layer 2531 being oxidized and ensure that the characteristics of the non-volatile two-terminal storage unit are not affected.

[0153] In an embodiment of the present application, after the first stacked layer 250 is formed, a first region upper electrode metal connection layer 191 is formed above the first stacked layer 250.

[0154] Figure 4L The semiconductor cross-sectional structure diagram showing the formation of the upper dielectric layer 170 and the first region upper electrode metal connection layer 191 in the embodiment of the present application is shown.

[0155] As Figure 4L shown, the upper dielectric layer 170 is deposited on the upper surface of the above-formed structure, and a first region upper electrode interconnection via is formed in the upper dielectric layer 170 through a photolithography process and an etching process, and the first region upper electrode metal connection layer 191 is filled in the first region upper electrode interconnection via. The entire lower surface of the bottom of the first region upper electrode metal connection layer 191 is in contact with the upper surface of the first upper electrode metal layer 253, enabling the first region upper electrode metal connection layer 191 to be in full contact with the first upper electrode metal layer 253 and preventing partial lower surfaces of the bottom of the first region upper electrode metal connection layer 191 from being in contact with the upper surface of the first lower electrode metal layer 251 to cause a short circuit.

[0156] Specifically, the material used for the upper dielectric layer 170 can be silicon nitride (Si3N4). In the embodiment of the present application, the upper dielectric layer 170 can also be selected according to the actual application scenario and process requirements to use other materials, which are not limited herein.

[0157] The upper dielectric layer 170 can isolate the first upper electrode metal layer 253 and the first region upper electrode metal connection layer 191 from other parts, thereby preventing current from flowing in an unnecessary path and avoiding the occurrence of short circuits and leakage phenomena.

[0158] Specifically, the first region upper electrode metal connection layer 191 can be made of copper metal. In the embodiment of the present application, the first region upper electrode metal connection layer 191 can also be made of other metals according to needs, which are not limited herein.

[0159] In a preferred embodiment of the present application, the first upper electrode metal layer 253 includes a first upper electrode metal first sub-layer 2531 and a first upper electrode metal second sub-layer 2532 covering the surface of the first upper electrode metal first sub-layer 2531. When the material used for the first upper electrode metal first sub-layer 2531 is more easily oxidized than the material used for the first upper electrode metal second sub-layer 2532, the bottom of the first region upper electrode interconnection via contacts the upper surface of the first upper electrode metal second sub-layer 2532, that is, the bottom of the first region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal second sub-layer 2532.

[0160] Figure 4M The schematic semiconductor cross-sectional structure diagram of the upper dielectric layer 170 and the first region upper electrode metal connection layer 191 in a preferred embodiment of the present application is shown.

[0161] As Figure 4M shown, the first upper electrode metal layer 253 includes a first upper electrode metal first sub-layer 2531 and a first upper electrode metal second sub-layer 2532 covering the surface of the first upper electrode metal first sub-layer 2531. When the material used for the first upper electrode metal first sub-layer 2531 is more easily oxidized than the material used for the first upper electrode metal second sub-layer 2532, the bottom of the formed first region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal second sub-layer 2532. The entire lower surface of the bottom of the first region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal second sub-layer 2532, enabling the first region upper electrode metal connection layer 191 to be in full contact with the first upper electrode metal second sub-layer 2532 and preventing partial lower surface of the bottom of the first region upper electrode metal connection layer 191 from contacting the upper surface of the first lower electrode metal layer 251 to cause a short circuit.

[0162] By the bottom of the aforementioned first region upper electrode metal connection layer 191 contacting the upper surface of the first upper electrode metal second sub-layer 2532, it is possible to prevent the first upper electrode metal first sub-layer 2531 from easily oxidizing to generate high-limited oxides when the first region upper electrode metal connection layer 191 contacts the first upper electrode metal first sub-layer 2531, which affects the conduction between the first region upper electrode metal connection layer 191 and the first upper electrode metal layer 253.

[0163] Figure 4N The schematic semiconductor cross-sectional structure diagram of forming the non-volatile two-terminal memory cell region and the peripheral circuit region in an embodiment of the present application is shown.

[0164] As Figure 4N shown, during the preparation process of the non-volatile two-terminal memory cell in an embodiment of the present application, the second region lower electrode metal connection layer 112 in the peripheral circuit region and the second region upper electrode metal connection layer 192 in the peripheral circuit region can also be prepared.

[0165] Specifically, during the process of providing the lower dielectric layer 120 that surrounds the first region lower electrode metal connection layer 111 and exposes its upper surface, the second region lower electrode metal connection layer 112 in the peripheral circuit region is also provided. Among them, the second region lower electrode metal connection layer 112 in the peripheral circuit region is also surrounded by the lower dielectric layer 120, and the upper surface of the second region lower electrode metal connection layer 112 in the peripheral circuit region is exposed.

[0166] The structure, the materials used, and the preparation process of the second region lower electrode metal connection layer 112 in the peripheral circuit region can be the same as those of the first region lower electrode metal connection layer 111, and will not be elaborated here.

[0167] Specifically, the isolation stack layer 130 and the upper dielectric layer 170 can be etched in the peripheral circuit region, and the etching is stopped at the upper surface of the second region lower electrode metal connection layer 112 in the peripheral circuit region to form the second region upper electrode via in the peripheral circuit region. Then, the second region upper electrode metal connection layer 192 is formed in the second region upper electrode via in the peripheral circuit region to connect the second region upper electrode metal connection layer 192 and the second region lower electrode metal connection layer 112. Thus, the preparation of the semiconductor structure in the peripheral circuit region is completed.

[0168] The structure, the materials used, and the preparation process of the second region upper electrode metal connection layer 192 in the peripheral circuit region can be the same as those of the first region upper electrode metal connection layer 191, and will not be elaborated here.

[0169] Finally, based on Figure 2 the preparation process of the non-volatile two-terminal memory cell preparation method, combined with Figures 5A - 5H the schematic diagram of the semiconductor cross-sectional structure shown, the exemplary process flow of the non-volatile two-terminal memory cell preparation method 200 using some other embodiments of the present application is described in detail.

[0170] Among them, the preparation steps of the non-volatile two-terminal memory cell combined with Figures 5A - 5C are the same as the preparation steps of the non-volatile two-terminal memory cell combined with Figures 3A - 3C shown, so they will not be described in detail here.

[0171] Figure 5D shows the schematic diagram of the semiconductor cross-sectional structure of depositing the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 in the embodiments of the present application.

[0172] As Figure 5DAs shown, a first lower electrode metal layer 251, a first switching layer 252 covering the first lower electrode metal layer 251, and a first upper electrode metal layer 253 covering the first switching layer 252 are sequentially deposited on the upper surface of the isolation stack layer 130, the inner wall and the bottom of the first region lower electrode interconnection via hole 141. During the deposition of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253, at least the inner wall and the bottom of the first region lower electrode interconnection via hole 141 should be covered.

[0173] When depositing multi-layer materials, due to reasons such as uneven deposition rates in different regions, the deposition amount of materials in some regions may be insufficient, forming depressions, as Figure 5D shown, above the first region lower electrode interconnection via hole 141, the first upper electrode metal layer 253 has a depression towards the first region lower electrode interconnection via hole 141.

[0174] Figure 5E The semiconductor cross-sectional structure diagram showing the removal of part of the materials of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 in the embodiment of the present application is shown.

[0175] As Figure 5E shown, by using planarization treatment, part of the materials of the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 are removed, so that the exposed part of the first lower electrode metal layer 251, the exposed part of the first switching layer 252, and the upper surface of the first upper electrode metal layer 253 are flush with the upper surface of the isolation stack layer 130, thereby forming a first stack layer 250 including the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 in the first region lower electrode interconnection via hole 141.

[0176] Specifically, during the planarization treatment process, chemical mechanical planarization technology (CMP, Chemical Mechanical Polishing) can be adopted.

[0177] In the case where there is a part of the downward depression during deposition, planarization treatment is generally adopted because if etching is used, it is difficult to control the etching progress and it is easy to etch off other useful parts.

[0178] In summary, in the embodiment of the present application, after depositing the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253, planarization treatment is adopted to make the upper surface of the first stack layer 250 flush with the upper surface of the isolation stack layer 130.

[0179] In an embodiment of the present application, after the first stacked layer 250 is formed and before the first region upper electrode metal connection layer 191 is formed above the first stacked layer 250, a blocking layer 230 is formed on the upper surface of the first stacked layer 250 and the upper surface of the isolation stacked layer 130.

[0180] Figure 5F The schematic semiconductor cross-sectional structure diagram of forming the blocking layer 230 according to the embodiment of the present application is shown.

[0181] As Figure 5F shown, the blocking layer 230 is formed on the upper surface of the first stacked layer 250 and the upper surface of the isolation stacked layer 130.

[0182] Specifically, the blocking layer can also be formed only on the upper surface of the first stacked layer 250, or the blocking layer 230 can be formed on the upper surface of the first stacked layer 250 and a part of the upper surface of the isolation stacked layer 130. The blocking layer 230 can be a single-layer structure or a multi-layer structure, and the blocking layer 230 can be formed by a thin film deposition process.

[0183] The blocking layer 230 can be made of at least one material among amorphous carbon, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxide, and silicon carbonitride.

[0184] When planarizing the first lower electrode metal layer 251, the first switching layer 252, and the first upper electrode metal layer 253 as described above, it is easy for atoms of each layer to be freed, thus there is a risk of contacting other materials in subsequent steps, resulting in short circuits or leakage. By the above operation of forming the blocking layer 230, such risks can be effectively avoided.

[0185] Figure 5G The schematic semiconductor cross-sectional structure diagram of forming the first region upper electrode metal connection layer 191 after forming the blocking layer 230 according to the embodiment of the present application is shown.

[0186] As Figure 5GAs shown, after forming the blocking layer 230, during the process of forming the first-region upper electrode metal connection layer 191, an upper dielectric layer 170 is deposited on the upper surface of the first stack layer 250 and the upper surface of the isolation stack layer 130, and a first-region upper electrode via hole is formed in the upper dielectric layer 170 and the blocking layer 230 through a photolithography process and an etching process, and the first-region upper electrode metal connection layer 191 is filled in the first-region upper electrode via hole. That is, the formed first-region upper electrode metal connection layer 191 penetrates through the blocking layer 230 and its bottom contacts the first upper electrode metal layer 253. The entire lower surface of the bottom of the first-region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal layer 253, so that the first-region upper electrode metal connection layer 191 is in full contact with the first upper electrode metal layer 253, and it is prevented that a partial lower surface of the bottom of the first-region upper electrode metal connection layer 191 contacts the upper surface of the first lower electrode metal layer 251 to cause a short circuit.

[0187] In some embodiments of the present application, the first upper electrode metal layer 253 includes a first upper electrode metal sub-layer 2531 and a first upper electrode metal second sub-layer 2532 covering the surface of the first upper electrode metal sub-layer 2531, and the material used for the first upper electrode metal sub-layer 2531 is more easily oxidized than the material used for the first upper electrode metal second sub-layer 2532. After forming the blocking layer 230, that is, the first-region upper electrode metal connection layer 191 penetrates through the blocking layer 230, and its bottom contacts the upper surface of the first upper electrode metal second sub-layer 2532.

[0188] Figure 5H The schematic diagram of the semiconductor cross-section structure of forming the first-region upper electrode metal connection layer 191 after forming the blocking layer 230 according to the embodiment of the present application is shown.

[0189] As Figure 5H As shown, after forming the blocking layer 230, during the process of forming the first-region upper electrode metal connection layer 191, an upper dielectric layer 170 is deposited on the upper surface of the first stack layer 250 and the upper surface of the isolation stack layer 130, and a first-region upper electrode via hole is formed in the upper dielectric layer 170 and the blocking layer 230 through a photolithography process and an etching process, and the first-region upper electrode metal connection layer 191 is filled in the first-region upper electrode via hole, so that the formed first-region upper electrode metal connection layer 191 penetrates through the blocking layer 230, and its bottom contacts the upper surface of the first upper electrode metal second sub-layer 2532. The entire lower surface of the bottom of the first-region upper electrode metal connection layer 191 contacts the upper surface of the first upper electrode metal second sub-layer 2532, so that the first-region upper electrode metal connection layer 191 is in full contact with the first upper electrode metal second sub-layer 2532, and it is prevented that a partial lower surface of the bottom of the first-region upper electrode metal connection layer 191 contacts the upper surface of the first lower electrode metal layer 251 to cause a short circuit.

[0190] Similarly, in the process of fabricating the non-volatile two-terminal memory cell of the embodiments of the present application, a second-region lower electrode metal connection layer 112 in the peripheral circuit region and a second-region upper electrode metal connection layer 192 in the peripheral circuit region can also be formed.

[0191] Specifically, in the process of providing the lower dielectric layer 120 that surrounds the first-region lower electrode metal connection layer 111 and exposes its upper surface, a second-region lower electrode metal connection layer 112 in the peripheral circuit region is also provided. Among them, the second-region lower electrode metal connection layer 112 under the peripheral circuit region is also surrounded by the lower dielectric layer 120, and the upper surface of the second-region lower electrode metal connection layer 112 in the peripheral circuit region is exposed.

[0192] The structure, materials used, and fabrication process of the second-region lower electrode metal connection layer 112 in the peripheral circuit region can be the same as those of the first-region lower electrode metal connection layer 111, and will not be elaborated here.

[0193] Specifically, the isolation stack layer 130, the blocking layer 230, and the upper dielectric layer 170 can be etched in the peripheral circuit region, penetrating the blocking layer 230, and the etching is stopped at the upper surface of the second-region lower electrode metal connection layer 112 in the peripheral circuit region to form a second-region upper electrode via hole in the peripheral circuit region. Then, a second-region upper electrode metal connection layer 192 is formed in the second-region upper electrode via hole in the peripheral circuit region to connect the second-region upper electrode metal connection layer 192 and the second-region lower electrode metal connection layer 112. Thus, the semiconductor structure fabrication in the peripheral circuit region is completed.

[0194] The structure, materials used, and fabrication process of the second-region upper electrode metal connection layer 192 in the peripheral circuit region can be the same as those of the first-region upper electrode metal connection layer 191, and will not be elaborated here.

[0195] In summary, by means of the preparation solution of the non-volatile two-terminal storage unit provided above, in the embodiments of the present disclosure, by forming the first stacked layer 250 in the first-region lower electrode interconnection via 141, the preparation of the first lower electrode metal layer 251 and the first upper electrode metal layer 253 of the non-volatile two-terminal storage unit can be achieved by only using one patterned photomask layer, thereby shortening the preparation cost of the non-volatile two-terminal storage unit and simplifying the process flow. At the same time, since only one patterned photomask layer is used, that is, alignment is only performed when forming the first-region lower electrode interconnection via 141, and alignment is not required when forming the second stacked layer (i.e., the stack of the second lower electrode metal first layer 1511, the second lower electrode metal second layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154), the complexity of the process is reduced, and problems such as changes in contact resistance caused by poor alignment are avoided, improving the stability and reliability of the prepared non-volatile two-terminal storage unit. In addition, by forming the first stacked layer 250 in the first-region lower electrode interconnection via 141 in the present application, the height of the formed first stacked layer 250 is reduced compared to the second stacked layer in the prior art, so that the formed first stacked layer 250 in the present application is more easily embedded between the first-region lower electrode metal connection layer 111 and the first-region upper electrode metal connection layer 191. Thus, the integration degree of the formed non-volatile two-terminal storage unit can be improved, the current path can be shortened, the resistance can be reduced, and the performance of the formed non-volatile two-terminal storage unit can be improved.

[0196] In this embodiment, a non-volatile two-terminal storage unit is provided. The non-volatile two-terminal storage unit includes: a lower dielectric layer 120, the lower dielectric layer 120 surrounding the first-region lower electrode metal connection layer 111 and exposing its upper surface; an isolation stacked layer 130, the isolation stacked layer 130 at least covering the first-region lower electrode metal connection layer 111; a first-region lower electrode interconnection via 141, the first-region lower electrode interconnection via 141 being formed in the isolation stacked layer 130, and the bottom of the first-region lower electrode interconnection via 141 at least partially contacting the first-region lower electrode metal connection layer 111; a first stacked layer 250, located in the first-region lower electrode interconnection via 141, the first stacked layer 250 including a first lower electrode metal layer 251, a first switching layer 252, and a first upper electrode metal layer 253.

[0197] In this embodiment, a non-volatile two-terminal memory cell is further provided. The non-volatile two-terminal memory cell includes: a blocking layer 230 covering at least the upper surface of the first stacked layer 250, and a first-region upper electrode metal connection layer 191 penetrating the blocking layer 230, and the bottom of the first-region upper electrode metal connection layer 191 is in contact with the upper surface of the first upper electrode metal layer 253. The entire lower surface of the bottom of the first-region upper electrode metal connection layer 191 is in contact with the upper surface of the first upper electrode metal layer 253, so that the first-region upper electrode metal connection layer 191 is in full contact with the first upper electrode metal layer 253, and prevents partial lower surface of the bottom of the first-region upper electrode metal connection layer 191 from contacting the upper surface of the first lower electrode metal layer 251 to cause a short circuit.

[0198] In an embodiment of the present application, the foregoing non-volatile two-terminal memory cell can be prepared by the preparation method 200 of the non-volatile two-terminal memory cell in any of the foregoing embodiments.

[0199] After obtaining the non-volatile two-terminal memory cell, a second-region lower electrode metal connection layer 112 in the peripheral circuit region and a second-region upper electrode metal connection layer 192 in the peripheral circuit region can be further prepared, so as to obtain a further semiconductor device.

[0200] For the specific structure diagram, reference can be made to Figures 3A - 3N 、 Figures 4A - 4N and Figures 5A - 5H , which will not be described herein again.

[0201] For the above-mentioned non-volatile two-terminal memory cell, since the photomask layer is saved, and the manufacturing method facilitates the formation and alignment of the lower electrode through-holes and the upper electrode through-holes of the non-volatile two-terminal memory cell, the preparation process flow of the non-volatile two-terminal memory cell can be shortened, and the preparation difficulty can be reduced, thereby reducing the preparation cost.

[0202] In this embodiment, a memory is provided. The memory includes one or more non-volatile two-terminal memory cells in any of the foregoing embodiments. These non-volatile two-terminal memory cells can be arranged in a specific manner for storing instructions or data. Since the memory adopts the above-mentioned non-volatile two-terminal memory cell, the yield of the memory can be improved, and the manufacturing cost of the memory can be reduced.

[0203] In this embodiment, an electronic device is provided. The electronic device includes the memory in the embodiment of the present application. The electronic device may further include a processor; wherein, the processor is configured to execute program instructions, and the memory is configured to store program instructions. When the program instructions are loaded and executed by the processor, the electronic device executes according to a specific method. Since the electronic device adopts the above-mentioned memory, the possibility of quality problems in the memory in the electronic device can be reduced, and the hardware cost of the electronic device can be reduced.

[0204] Although several embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many variations, changes and alternative approaches can be thought of by those skilled in the art without departing from the spirit and scope of the present disclosure. It should be understood that various alternatives to the embodiments of the present disclosure described herein may be employed in practicing the present disclosure. The appended claims are intended to define the scope of protection of the present disclosure and thus cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for preparing a non-volatile two-terminal storage unit, characterized in that: The preparation method comprises: Providing a lower dielectric layer (120) surrounding the first region lower electrode metal connection layer (111) and exposing its upper surface; forming an isolation stacking layer (130) that at least covers the lower electrode metal connection layer (111) of the first region; Based on the patterned mask layer, a first region lower electrode interconnection through hole (141) is formed in the isolation stack layer (130), wherein the bottom of the first region lower electrode interconnection through hole (141) at least partially contacts the first region lower electrode metal connection layer (111); A first stacked layer (250) including a first lower electrode metal layer (251), a first switching layer (252) and a first upper electrode metal layer (253) is formed in the first region lower electrode interconnection through hole (141).

2. The preparation method according to claim 1, characterized in that: The upper surface of the first stacked layer (250) is flush with the upper surface of the isolation stacked layer (130).

3. The preparation method according to claim 2, characterized in that: A first stacking layer (250) flush with the upper surface of the isolation stacking layer (130) is formed in the first region lower electrode interconnection through hole (141), comprising: Forming the first lower electrode metal layer (251) and the first switching layer (252) covering the first lower electrode metal layer (251) at least on the inner wall and bottom of the lower electrode interconnection through hole (141) in the first region; forming a sacrificial layer (270) on the first switching layer (252), so that the sacrificial layer (270) at least fills the remaining space of the lower electrode interconnection through hole (141) of the first region; Removing the first lower electrode metal layer (251), the first switching layer (252) and the sacrificial layer (270) outside the region of the lower electrode interconnection through hole (141) in the first region, and removing the sacrificial layer (270) in the region of the lower electrode interconnection through hole (141) in the first region; The first upper electrode metal layer (253) is formed in the region of the first region lower electrode interconnection through hole (141) from which the sacrificial layer (270) is removed, so that the upper surface of the first upper electrode metal layer (253) is flush with the upper surface of the isolation stack layer (130).

4. The preparation method according to claim 3, characterized in that: In the process of removing the first lower electrode metal layer (251), the first switching layer (252) and the sacrificial layer (270) outside the region of the first region lower electrode interconnection through hole (141), a non-patterned etching process or a CMP process is adopted.

5. The preparation method according to claim 3, characterized in that: In the process of removing the sacrificial layer (270) in the region of the lower electrode interconnection through hole (141) in the first region, an Asher process is adopted.

6. The preparation method according to claim 3, characterized in that: After forming the first upper electrode metal layer (253), a first region upper electrode metal connection layer (191) is formed, the bottom of which contacts the upper surface of the first upper electrode metal layer (253).

7. The preparation method according to claim 2, characterized in that: The first upper electrode metal layer (253) comprises a first upper electrode metal layer (2531) and a first upper electrode metal layer (2532), wherein the first upper electrode metal layer (2531) is located between the first switching layer (252) and the first upper electrode metal layer (2532); A first stacking layer (250) flush with the upper surface of the isolation stacking layer (130) is formed in the first region lower electrode interconnection through hole (141), comprising: Forming the first lower electrode metal layer (251), the first switching layer (252) covering the first lower electrode metal layer (251), and the first upper electrode metal layer (2531) covering the first switching layer (252) at least on the inner wall and bottom of the lower electrode interconnection through hole (141) in the first region; Forming a sacrificial layer (270) on the first upper electrode metal layer (2531), so that the sacrificial layer (270) at least fills the remaining space of the lower electrode interconnection through hole (141) in the first region; Removing the first lower electrode metal layer (251), the first switching layer (252), the first upper electrode metal layer (2531) and the sacrificial layer (270) outside the region of the lower electrode interconnection through hole (141) in the first region, and removing the sacrificial layer (270) in the region of the lower electrode interconnection through hole (141) in the first region; The first upper electrode metal binary layer (2532) is formed in the area of ​​the first region lower electrode interconnection through hole (141) from which the sacrificial layer (270) has been removed, so that the upper surface of the first upper electrode metal binary layer (2532) is flush with the upper surface of the isolation stack layer (130).

8. The preparation method according to claim 7, characterized in that: In the process of removing the first lower electrode metal layer (251), the first switching layer (252), the first upper electrode metal layer (2531) and the sacrificial layer (270) outside the area of ​​the lower electrode interconnection through hole (141) in the first zone, a non-patterned etching process or a CMP process is adopted.

9. The preparation method according to claim 7, characterized in that: In the process of removing the sacrificial layer (270) in the region of the lower electrode interconnection through hole (141) in the first region, an Asher process is adopted.

10. The preparation method according to claim 7, characterized in that: After forming the first upper electrode metal binary layer (2532), a first region upper electrode metal connection layer (191) is formed, the bottom of which contacts the upper surface of the first upper electrode metal binary layer (2532).

11. The preparation method according to claim 2, characterized in that: After forming the first stacked layer (250), a blocking layer (230) is formed to cover at least the upper surface of the first stacked layer (250).

12. The preparation method according to claim 11, characterized in that: After forming the blocking layer (230), a first region upper electrode metal connection layer (191) is formed which penetrates the blocking layer (230) and whose bottom contacts the upper surface of the first upper electrode metal layer (253).

13. The preparation method according to claim 1, characterized in that: The first upper electrode metal layer (253) includes a first upper electrode metal layer (2531) and a first upper electrode metal layer (2532) covering the surface of the first upper electrode metal layer (2531), wherein the material used for the first upper electrode metal layer (2531) is more easily oxidized than the material used for the first upper electrode metal layer (2532).

14. The preparation method according to claim 1, characterized in that: The first lower electrode metal layer (251) comprises a first lower electrode metal first layer (2511) and a first lower electrode metal second layer (2512) covering the surface of the first lower electrode metal first layer (2511).

15. The preparation method according to claim 1, characterized in that: The cross-sectional shape of the lower electrode interconnection through hole (141) in the first region is an inverted trapezoid.

16. The preparation method according to claim 15, characterized in that: The width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid, and the width of the upper base of the inverted trapezoid is greater than The lower base width of the inverted trapezoid is greater than 17. The preparation method according to claim 15, characterized in that: The angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

18. A non-volatile two-terminal storage unit, characterized in that: The non-volatile two-terminal storage unit comprises: A lower dielectric layer (120), the lower dielectric layer (120) surrounds the first region lower electrode metal connection layer (111) and leaves its upper surface exposed; An isolation stacked layer (130), the isolation stacked layer (130) at least covering the first region lower electrode metal connection layer (111); A first region lower electrode interconnection through hole (141), wherein the first region lower electrode interconnection through hole (141) is formed in the isolation stack layer (130), and the bottom of the first region lower electrode interconnection through hole (141) at least partially contacts the first region lower electrode metal connection layer (111); The first stacked layer (250) is located in the lower electrode interconnection through hole (141) of the first region, and the first stacked layer (250) includes a first lower electrode metal layer (251), a first switching layer (252) and a first upper electrode metal layer (253).

19. The non-volatile two-terminal memory cell according to claim 18, characterized in that: The non-volatile two-terminal storage unit also includes: a blocking layer (230) covering at least the upper surface of the first stacked layer (250), and The first region upper electrode metal connection layer (191) penetrates the blocking layer (230), and the bottom of the first region upper electrode metal connection layer (191) contacts the upper surface of the first upper electrode metal layer (253).

20. A memory, characterized in that: The memory comprises one or more non-volatile two-terminal memory cells according to claim 18 or 19.

21. An electronic device, characterized in that: The electronic device comprises the memory according to claim 20.

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