Preparation method of nonvolatile two-end storage unit and product thereof

Abstract

The invention discloses a preparation method of a nonvolatile two-end storage unit and a product thereof. The preparation method comprises the following steps: stacking a first dielectric layer on a first region lower electrode metal connecting layer and a second region lower electrode metal connecting layer; forming a lower electrode interconnection through hole based on the first graphical photomask layer; forming a storage unit stacking layer above the first region lower electrode interconnection through hole, wherein the storage unit stacking layer is in contact with the upper surface of the first region lower electrode interconnection through hole; forming a second dielectric layer in the first region and the second region; forming an upper electrode interconnection through hole based on the first graphical photomask layer; and forming a first region upper electrode metal connecting layer and a second region upper electrode metal connecting layer in the upper electrode interconnection through hole. The preparation of the nonvolatile two-end storage unit is realized by adopting a patterned photomask layer, so that the preparation process flow of the nonvolatile two-end storage unit is shortened, the preparation cost is reduced, and the alignment precision of a lower electrode interconnection through hole and an upper electrode interconnection through hole is improved.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology. More specifically, this disclosure relates to a method for fabricating a non-volatile two-terminal memory cell and its product. Background Art

[0002] A resistive random access memory (RRAM) is a non-volatile two-terminal memory cell that stores information based on the change in the resistance of a material, and is typically composed of a bottom electrode, a switching layer, and a top electrode. In the prior art, during the fabrication process of a resistive random access memory, two lithography steps are required to separately fabricate the bottom electrode and the top electrode. Due to the manufacturing steps, generally, the fabrication of the bottom electrode and the top electrode of a resistive random access memory each requires a different patterned photomask layer, which significantly increases the production cost and the fabrication process is also relatively complex. At the same time, such a fabrication method also involves the problem of alignment between the bottom electrode and the top electrode during the fabrication process of the bottom electrode and the top electrode, which makes the fabrication of the resistive random access memory difficult.

[0003] In view of this, there is an urgent need to provide a method for fabricating a non-volatile two-terminal memory cell, which can reduce the number of patterned photomask layers used while realizing the fabrication of the bottom electrode and the top electrode of the non-volatile two-terminal memory cell, thereby reducing the production cost of the non-volatile two-terminal memory cell, simplifying the fabrication process, and avoiding the problem of alignment between the bottom electrode and the top electrode, and reducing the fabrication difficulty of the non-volatile two-terminal memory cell. Summary of the Invention

[0004] To at least solve one or more of the above-mentioned technical problems, this disclosure proposes solutions for a method for fabricating a non-volatile two-terminal memory cell and its product in multiple aspects.

[0005] In a first aspect, the present disclosure provides a method for fabricating a non-volatile two-terminal storage cell. The fabrication method includes: stacking a first dielectric layer 130 on the upper surfaces of a first-region lower electrode metal connection layer 111 located in a first region and a second-region lower electrode metal connection layer 112 located in a second region; forming, based on a first patterned mask layer 391, a first-region lower electrode interconnection via hole 141 in the first dielectric layer 130 that contacts the upper surface of the first-region lower electrode metal connection layer 111 and a second-region lower electrode interconnection via hole 142 that contacts the upper surface of the second-region lower electrode metal connection layer 112; forming a storage cell stack layer 350 above the first-region lower electrode interconnection via hole 141, where the storage cell stack layer 350 contacts the upper surface of the first-region lower electrode interconnection via hole 141; forming a second dielectric layer 170 in the first region and the second region; forming, based on the first patterned mask layer 391, a first-region upper electrode interconnection via hole 181 and a second-region upper electrode interconnection via hole 182 in the second dielectric layer 170; forming a first-region upper electrode metal connection layer 191 in the first-region upper electrode interconnection via hole 181 and a second-region upper electrode metal connection layer 192 in the second-region upper electrode interconnection via hole 182, where the first-region upper electrode metal connection layer 191 is electrically connected to the first-region lower electrode metal connection layer 111 and the second-region upper electrode metal connection layer 192 is electrically connected to the second-region lower electrode metal connection layer 112.

[0006] In some embodiments, forming a second-region upper electrode metal connection layer 192 in the second-region upper electrode interconnection via hole 182, where the second-region upper electrode metal connection layer 192 is electrically connected to the second-region lower electrode metal connection layer 112, includes: after forming the second-region lower electrode interconnection via hole 142, forming a second-region functional layer 342 that partially fills the second-region lower electrode interconnection via hole 142, where the second-region functional layer 342 is electrically connected to the second-region lower electrode metal connection layer 112; after forming the second-region upper electrode interconnection via hole 182, forming a second-region upper electrode metal connection layer 192 in the second-region upper electrode interconnection via hole 182, where the second-region upper electrode metal connection layer 192 is electrically connected to the second-region functional layer 342.

[0007] In some embodiments, the upper surface of the second-region functional layer 342 is lower than the upper surface of the first dielectric layer 130.

[0008] In some embodiments, a second-region functional layer 342 is formed to partially fill the second-region lower electrode interconnect via 142, and an upper surface of the second-region functional layer 342 is lower than an upper surface of the first dielectric layer 130, including: before forming the memory cell stack layer 350, forming a second-region second lower electrode metal sub-layer 15112 that fills the second-region lower electrode interconnect via 142, with an upper surface of the second-region second lower electrode metal sub-layer 15112 flush with the upper surface of the first dielectric layer 130; during the process of forming the memory cell stack layer 350, the second-region second lower electrode metal sub-layer 15112 in the second-region lower electrode interconnect via 142 is partially removed to form the second-region functional layer 342.

[0009] In a second aspect, the present disclosure provides a non-volatile two-terminal memory cell, where the non-volatile two-terminal memory cell includes: a first dielectric layer 130 stacked on upper surfaces of a first-region lower electrode metal connection layer 111 in a first region and a second-region lower electrode metal connection layer 112 in a second region; a first-region lower electrode interconnect via 141 formed in the first dielectric layer 130 based on a first patterned photomask layer 391 and in contact with the upper surface of the first-region lower electrode metal connection layer 111; a second-region lower electrode interconnect via 142 formed in the first dielectric layer 130 based on the first patterned photomask layer 391 and in contact with the upper surface of the second-region lower electrode metal connection layer 112; a memory cell stack layer 350 in contact with the upper surface of the first-region lower electrode interconnect via 141; a second dielectric layer 170 formed in the first region and the second region; a first-region upper electrode interconnect via 181 and a second-region upper electrode interconnect via 182 formed in the second dielectric layer 170 based on the first patterned photomask layer 391 and penetrating the second dielectric layer 170; a first-region upper electrode metal connection layer 191 formed in the first-region upper electrode interconnect via 181 and electrically connected to the first-region lower electrode metal connection layer 111; and a second-region upper electrode metal connection layer 192 formed in the second-region upper electrode interconnect via 182 and electrically connected to the second-region lower electrode metal connection layer 112.

[0010] In some embodiments, the non-volatile two-terminal memory cell further includes: a second-region functional layer 342 formed in the second-region lower electrode interconnect via 142, with an upper surface of the second-region functional layer 342 lower than the upper surface of the first dielectric layer 130, the second-region functional layer 342 being electrically connected to the second-region lower electrode metal connection layer 112, and the second-region upper electrode metal connection layer 192 being electrically connected to the second-region functional layer 342.

[0011] In some embodiments, the bottom of the second-region upper electrode metal connection layer 192 contacts the upper surface of the second-region functional layer 342, and the bottom of the second-region functional layer 342 contacts the upper surface of the second-region lower electrode metal connection layer 112.

[0012] In some embodiments, the bottom of the second-region upper electrode metal connection layer 192 contacts the upper surface of the second-region lower electrode metal connection layer 112.

[0013] In a third aspect, the present disclosure provides a memory, wherein the memory includes one or more non-volatile two-terminal memory cells according to any embodiment of the present disclosure.

[0014] In a fourth aspect, the present disclosure provides an electronic device, wherein the electronic device includes the memory according to the embodiments of the present disclosure.

[0015] By means of the preparation scheme of the non-volatile two-terminal memory cell provided above, in the embodiments of the present disclosure, the first-region lower electrode interconnection holes 141 located in the memory cell array region 80 and the second-region lower electrode interconnection holes 142 located in the peripheral circuit region 90 are simultaneously etched based on the first patterning mask layer 391, and based on the first patterning mask layer 391, the first-region upper electrode interconnection holes 181 located in the memory cell array region 80 and the second-region upper electrode interconnection holes 182 located in the peripheral circuit region 90 can also be simultaneously etched in subsequent steps. It is possible to realize the preparation of the non-volatile two-terminal memory cell by using only one layer of patterning mask layer, thereby shortening the preparation process flow of the non-volatile two-terminal memory cell and reducing the preparation cost. Further, by using the same patterning mask layer (i.e., the first patterning mask layer 391) as a mask for etching the lower electrode interconnection holes (i.e., the first-region lower electrode interconnection holes 141 located in the memory cell array region 80 and the second-region lower electrode interconnection holes 142 located in the peripheral circuit region 90) to etch the upper electrode interconnection holes (i.e., the first-region upper electrode interconnection holes 181 located in the memory cell array region 80 and the second-region upper electrode interconnection holes 182 located in the peripheral circuit region 90), the alignment accuracy of the lower electrode interconnection holes and the upper electrode interconnection holes can be improved, avoiding problems such as changes in contact resistance caused by poor alignment, and improving the stability and reliability of the formed non-volatile two-terminal memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary rather than restrictive manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0017] Figures 1A - 1IShows a schematic cross-sectional structure diagram of a prior art non-volatile two-terminal storage cell;

[0018] Figure 2 Shows an exemplary structural block diagram of a method for fabricating a non-volatile two-terminal storage cell according to some embodiments of the present application;

[0019] Figures 3A - 3I Shows a schematic cross-sectional structure diagram of a method for fabricating a non-volatile two-terminal storage cell according to some embodiments of the present disclosure;

[0020] Figures 4A - 4I Shows a schematic cross-sectional structure diagram of a method for fabricating a non-volatile two-terminal storage cell according to some other embodiments of the present disclosure.

[0021] Reference numerals:

[0022] 110 - Lower electrode metal connection layer, 111 - Lower electrode metal connection layer in the first region, 112 - Lower electrode metal connection layer in the second region, 120 - Lower dielectric layer, 130 - First dielectric layer, 141 - Lower electrode interconnection via in the first region, 142 - Lower electrode interconnection via in the second region, 1511 - Second lower electrode metal sub-layer, 15111 - First region second lower electrode metal sub-layer, 15112 - Second region second lower electrode metal sub-layer, 1512 - Second lower electrode metal second sub-layer, 152 - Second switching layer, 153 - Second upper electrode metal layer, 154 - Upper electrode hard mask layer, 159 - Sidewall, 170 - Second dielectric layer, 181 - Upper electrode interconnection via in the first region, 182 - Upper electrode interconnection via in the second region, 191 - Upper electrode metal connection layer in the first region, 192 - Upper electrode metal connection layer in the second region;

[0023] 342 - Second region functional layer, 350 - Storage cell stack layer, 380 - Lower electrode hard mask layer, 381 - Lower electrode hard mask first sub-layer, 382 - Lower electrode hard mask second sub-layer, 391 - First patterned photomask layer, 393 - Third patterned photomask layer, 394 - Fourth patterned photomask layer;

[0024] 80 - Storage cell array region, 90 - Peripheral circuit region. Detailed embodiments

[0025] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0026] It should be understood that the terms "comprising" and "including" as used in the specification and claims of this application indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0027] It should also be understood that the terms used in the specification of this application are merely for the purpose of describing specific embodiments and are not intended to limit this application. As used in the specification and claims of this application, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms. It should be further understood that the term "and / or" as used in the specification and claims of this application refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0028] It should also be understood that, for ease of description, spatial relative terms such as "below", "beneath", "under", "above", "on" etc. may be used herein to describe the relationship of one element or component to another (or other) element or component as shown in the figures. When an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0029] The following will describe in detail the specific embodiments of this application with reference to the accompanying drawings.

[0030] Figures 1A - 1I A schematic cross-sectional structure diagram of a semiconductor for preparing a non-volatile two-terminal storage unit in the prior art is shown.

[0031] Figure 1A A schematic cross-sectional structure diagram of a semiconductor for forming a third patterned mask layer 393 in the prior art is shown.

[0032] As Figure 1A shown, a semiconductor structure having multiple layers is provided, and a third patterned mask layer 393 is formed above the semiconductor structure. Specifically, the pattern of the third patterned mask layer 393 can be used to define the pattern of the first region lower electrode interconnection vias 141 located in the storage unit array region 80 formed subsequently.

[0033] Specifically, after the semiconductor structure is processed, the formed structure is successively: a lower electrode metal connection layer 110 surrounded by a lower dielectric layer 120, a first dielectric layer 130, a lower electrode hard mask layer 380, and a third patterned mask layer 393.

[0034] Among them, the lower electrode metal connection layer 110 includes a first-region lower electrode metal connection layer 111 located in the memory cell array region 80 and a second-region lower electrode metal connection layer 112 located in the peripheral circuit region 90. The first-region lower electrode metal connection layer 111 and the second-region lower electrode metal connection layer 112 are separated by the lower dielectric layer 120 to prevent short circuits from forming between two first-region lower electrode metal connection layers 111, between two second-region lower electrode metal connection layers 112, or between the first-region lower electrode metal connection layer 111 and the second-region lower electrode metal connection layer 112. At the same time, the upper surfaces of the first-region lower electrode metal connection layer 111 and the second-region lower electrode metal connection layer 112 are exposed, and the upper surfaces of the first-region lower electrode metal connection layer 111, the second-region lower electrode metal connection layer 112, and the upper surface of the lower dielectric layer 120 are flush.

[0035] The first dielectric layer 130 is deposited on the upper surface of the lower electrode metal connection layer 110 surrounded by the lower dielectric layer 120 through a thin film deposition process. The first dielectric layer 130 can be composed of multiple layers.

[0036] The lower electrode hard mask layer 380 is deposited on the upper surface of the first dielectric layer 130 through a thin film deposition process. The lower electrode hard mask layer 380 can be composed of multiple layers. In the embodiment of the present application, the lower electrode hard mask layer 380 can include a lower electrode hard mask first sub-layer 381 and a lower electrode hard mask second sub-layer 382.

[0037] A third patterned mask layer 393 is formed above the lower electrode hard mask second sub-layer 382, and its pattern can be used to define the pattern of the first-region lower electrode interconnection via 141 formed subsequently in the memory cell array region 80.

[0038] Figure 1B Shows a schematic cross-sectional structure diagram of a semiconductor for forming the first-region lower electrode interconnection via 141 in the prior art.

[0039] As Figure 1B Shown, based on the third patterned mask layer 393, the exposed lower electrode hard mask layer 380 is etched until the corresponding position of the first dielectric layer 130 is exposed. The remaining lower electrode hard mask layer 380 forms a patterned lower electrode hard mask layer, and the aforementioned third patterned mask layer 393 is removed. Then, the exposed first dielectric layer 130 is etched using the patterned lower electrode hard mask layer as a mask, the first-region lower electrode interconnection via 141 is formed in the first dielectric layer 130, and the remaining lower electrode hard mask layer 380 is removed.

[0040] Specifically, the first-region lower electrode interconnection via hole 141 is located in the memory cell array region 80, and its bottom contacts the upper surface of the first-region lower electrode metal connection layer 111. The cross-sectional shape and size of the first-region lower electrode interconnection via hole 141 are not limited. Preferably, the cross-sectional shape of the first-region lower electrode interconnection via hole 141 is an inverted trapezoid, the upper base width of the inverted trapezoid is greater than the lower base width of the inverted trapezoid, and the upper base width of the inverted trapezoid is greater than the lower base width of the inverted trapezoid is greater than the included angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

[0041] Figure 1C The semiconductor cross-sectional structure diagram of depositing the second lower electrode metal sub-layer 1511 in the prior art is shown.

[0042] As Figure 1C shown, the second lower electrode metal sub-layer 1511 is deposited in the first-region lower electrode interconnection via hole 141 and on the upper surface of the first dielectric layer 130 through a thin film deposition process, so that the second lower electrode metal sub-layer 1511 at least fills the first-region lower electrode interconnection via hole 141.

[0043] Figure 1D The semiconductor cross-sectional structure diagram of planarizing the second lower electrode metal sub-layer 1511 in the prior art is shown.

[0044] As Figure 1D shown, the second lower electrode metal sub-layer 1511 is planarized to form the first-region second lower electrode metal sub-layer 15111. Specifically, the first-region second lower electrode metal sub-layer 15111 fills the first-region lower electrode interconnection via hole 141, and the upper surface of the first-region second lower electrode metal sub-layer 15111 is flush with the upper surface of the first dielectric layer 130.

[0045] Figure 1E The semiconductor cross-sectional structure diagram of forming the memory cell stack layer 350 and the sidewall 159 in the prior art is shown.

[0046] As Figure 1EAs shown, a memory cell stack layer 350 is deposited on the upper surface of the first dielectric layer 130 and the upper surface of the first region second lower electrode metal sub-layer 15111. The memory cell stack layer 350 includes a second lower electrode metal sub-layer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154. Then, a photolithography process and an etching process are used to etch the second lower electrode metal sub-layer 1512, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154. Then, sidewalls 159 are deposited on the exposed regions of the etched second lower electrode metal sub-layer 1512, the second switching layer 152, the second upper electrode metal layer 153, the upper electrode hard mask layer 154, and the first dielectric layer 130. Then, the deposited sidewalls 159 are etched, and the etching process is stopped at the upper surface of the first dielectric layer 130, so that the etched sidewalls 159 can wrap the memory cell stack layer 350 laterally.

[0047] Figure 1F FIG. shows a schematic semiconductor cross-sectional structure of depositing the second dielectric layer 170 in the prior art.

[0048] As Figure 1F shown, a second dielectric layer 170 is deposited on the surface of the exposed first dielectric layer 130, the surface of the exposed memory cell stack layer 350, and the surface of the exposed sidewalls 159.

[0049] Figure 1G FIG. shows a schematic semiconductor cross-sectional structure of forming the fourth patterned mask layer 394 in the prior art.

[0050] As Figure 1G shown, a fourth patterned mask layer 394 is formed in the structure formed above. The fourth patterned mask layer 394 is located above the second dielectric layer 170. Among them, the pattern of the fourth patterned mask layer 394 is different from the pattern of the third patterned mask layer 393. Specifically, the pattern of the fourth patterned mask layer 394 can be used to define the patterns of the first region upper electrode via 181 formed in the memory cell array region 80 and the second region upper electrode via 182 formed in the peripheral circuit region 90 subsequently.

[0051] Figure 1H FIG. shows a schematic semiconductor cross-sectional structure of forming the first region upper electrode via 181 and the second region upper electrode via 182 in the prior art.

[0052] As Figure 1HAs shown, based on the fourth patterned photomask layer 394, a first-region upper electrode interconnection via 181 is formed in the second dielectric layer 170 and the upper electrode hard mask layer 154 through a photolithography process and an etching process, and a second-region upper electrode interconnection via 182 is formed in the second dielectric layer 170 and the first dielectric layer 130. Among them, the first-region upper electrode interconnection via 181 is located in the memory cell array region 80, and its bottom contacts the memory cell stack layer 350; the second-region upper electrode interconnection via 182 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second-region lower electrode metal connection layer 112. Then, the fourth patterned photomask layer 394 is removed.

[0053] Figure 1I FIG. shows a schematic semiconductor cross-sectional structure of forming a first-region upper electrode metal connection layer 191 and a second-region upper electrode metal connection layer 192 in the prior art.

[0054] As Figure 1I shown, the first-region upper electrode metal connection layer 191 is filled in the first-region upper electrode interconnection via 181, and the second-region upper electrode metal connection layer 192 is filled in the second-region upper electrode interconnection via 182. The first-region upper electrode metal connection layer 191 is located in the memory cell array region 80, and its bottom contacts the memory cell stack layer 350; the second-region upper electrode metal connection layer 192 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second-region lower electrode metal connection layer 112.

[0055] In the prior art, during the preparation of the lower electrode and the upper electrode of the non-volatile two-terminal memory cell, 1 layer of patterned photomask layer (i.e., the third patterned photomask layer 393 mentioned above) is required during the etching of the first dielectric layer 130 to form the lower electrode interconnection via (i.e., the first-region lower electrode interconnection via 141 mentioned above), and 1 layer of patterned photomask layer (i.e., the fourth patterned photomask layer 394 mentioned above) is required during the etching of the second dielectric layer 170 to form the upper electrode interconnection via (i.e., the first-region upper electrode interconnection via 181 and the second-region upper electrode interconnection via 182 mentioned above). Thus, at least 2 different patterned photomask layers are required in the prior art to implement the preparation of the non-volatile two-terminal memory cell. This greatly increases the production cost, and the preparation process is also relatively complex. At the same time, such a preparation method also involves the problem of alignment between the lower electrode and the upper electrode during the preparation of the lower electrode and the upper electrode, which makes the preparation of the non-volatile two-terminal memory cell difficult.

[0056] In view of this, embodiments of the present disclosure provide a preparation solution for a non-volatile two-terminal storage unit. After etching lower electrode interconnection vias (i.e., the first-region lower electrode interconnection via 141 and the second-region lower electrode interconnection via 142 hereinafter) based on a certain patterned photomask layer (i.e., the first patterned photomask layer 391 hereinafter), upper electrode interconnection vias (i.e., the first-region upper electrode interconnection via 181 and the second-region upper electrode interconnection via 182 hereinafter) can be etched based on the same patterned photomask layer (i.e., the first patterned photomask layer 391 hereinafter), so as to achieve the formation of lower electrode interconnection vias and upper electrode interconnection vias of the non-volatile two-terminal storage unit by using only one layer of patterned photomask layer, for the preparation of the lower electrode and the upper electrode, reduce the preparation cost, shorten the preparation process flow of the non-volatile two-terminal storage unit, and reduce the preparation difficulty.

[0057] Figure 2 The exemplary structural block diagram of the preparation method of the non-volatile two-terminal storage unit according to some embodiments of the present application is shown.

[0058] As Figure 2 shown, the preparation method 200 of the non-volatile two-terminal storage unit includes the following steps: In step S210, a first dielectric layer 130 is stacked on the upper surface of the first-region lower electrode metal connection layer 111 located in the first region and the upper surface of the second-region lower electrode metal connection layer 112 located in the second region; In step S220, based on the first patterned photomask layer 391, in the first dielectric layer 130, a first-region lower electrode interconnection via 141 in contact with the upper surface of the first-region lower electrode metal connection layer 111 and a second-region lower electrode interconnection via 142 in contact with the upper surface of the second-region lower electrode metal connection layer 112 are formed; In step S230, a storage unit stack layer 350 is formed above the first-region lower electrode interconnection via 141, and the storage unit stack layer 350 is in contact with the upper surface of the first-region lower electrode interconnection via 141; In step S240, a second dielectric layer 170 is formed in the first region and the second region; In step S250, based on the first patterned photomask layer 391, a first-region upper electrode interconnection via 181 and a second-region upper electrode interconnection via 182 are formed in the second dielectric layer 170; In step S260, a first-region upper electrode metal connection layer 191 is formed in the first-region upper electrode interconnection via 181, and a second-region upper electrode metal connection layer 192 is formed in the second-region upper electrode interconnection via 182, wherein the first-region upper electrode metal connection layer 191 is electrically connected to the first-region lower electrode metal connection layer 111, and the second-region upper electrode metal connection layer 192 is electrically connected to the second-region lower electrode metal connection layer 112.

[0059] Based Figure 2 on the preparation process of the preparation method of the non-volatile two-terminal storage unit, the following combines Figures 3A - 3IThe schematic diagram of the semiconductor cross-sectional structure shown describes in detail the exemplary process flow of the method 200 for manufacturing a non-volatile two-terminal memory cell using some embodiments of the present application.

[0060] Figures 3A - 3I The schematic diagram of the semiconductor cross-sectional structure of the method for manufacturing a non-volatile two-terminal memory cell according to some embodiments of the present disclosure is shown.

[0061] Figure 3A The schematic diagram of the semiconductor cross-sectional structure of forming the first patterned photomask layer 391 according to an embodiment of the present application is shown.

[0062] As Figure 3A shown, a semiconductor structure with multiple layers is provided, and a first patterned photomask layer 391 is formed above the semiconductor structure. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the first-region lower electrode via holes 141 located in the memory cell array region 80 and the second-region lower electrode via holes 142 located in the peripheral circuit region 90 formed subsequently.

[0063] Specifically, the semiconductor structure is processed to form the following structures in sequence: the lower electrode metal connection layer 110 surrounded by the lower dielectric layer 120, the first dielectric layer 130, the lower electrode hard mask layer 380, and the first patterned photomask layer 391.

[0064] Among them, the lower electrode metal connection layer 110 includes the first-region lower electrode metal connection layer 111 located in the memory cell array region 80 and the second-region lower electrode metal connection layer 112 located in the peripheral circuit region 90. The first-region lower electrode metal connection layer 111 and the second-region lower electrode metal connection layer 112 are separated by the lower dielectric layer 120 to prevent short circuits from forming between two first-region lower electrode metal connection layers 111, between two second-region lower electrode metal connection layers 112, or between the first-region lower electrode metal connection layer 111 and the second-region lower electrode metal connection layer 112. At the same time, the upper surfaces of the first-region lower electrode metal connection layer 111 and the second-region lower electrode metal connection layer 112 are exposed, and the upper surfaces of the first-region lower electrode metal connection layer 111, the second-region lower electrode metal connection layer 112, and the upper surface of the lower dielectric layer 120 are flush.

[0065] The number of the first-region lower electrode metal connection layers 111 can be one or multiple. The materials used for the first-region lower electrode metal connection layers 111 and the second-region lower electrode metal connection layers 112 can be the same or different. The materials used for the first-region lower electrode metal connection layers 111 and the second-region lower electrode metal connection layers 112 can be copper metal. The main advantages of copper metal compared with other metals are high electrical conductivity, high thermal conductivity, corrosion resistance, appropriate strength, easy processability and formability, etc. In the embodiments of the present application, the first-region lower electrode metal connection layers 111 and the second-region lower electrode metal connection layers 112 can also adopt other metals as required, which are not limited herein.

[0066] Specifically, the material used for the lower dielectric layer 120 can be silicon dioxide (SiO2), silicon nitride (Si3N4), polyimide, low dielectric constant (Low-k) material, etc. More specifically, the low dielectric constant (Low-k) material can be porous silicon dioxide, fluorinated silicon glass, etc. In the embodiments of the present application, the lower dielectric layer 120 can also select other materials according to the actual application scenarios and process requirements, which are not limited herein.

[0067] Specifically, in the process of surrounding the lower electrode metal connection layer 110 with the lower dielectric layer 120, it can be formed by using various known processes, and the embodiments of the present application have no limitation in this regard.

[0068] For example, when surrounding the first-region lower electrode metal connection layers 111 and the second-region lower electrode metal connection layers 112 with the lower dielectric layer 120 and exposing the upper surfaces of the first-region lower electrode metal connection layers 111 and the second-region lower electrode metal connection layers 112, this part of the process includes: First, provide the lower dielectric layer 120, form a patterned photomask layer on the lower dielectric layer 120, selectively expose the photoresist through an exposure machine, develop and remove the exposed or unexposed part of the photoresist, etch or deposit to form a pattern in the exposed area, remove the remaining photoresist, and continue to form the required first grooves in the storage cell array region 80 and the second grooves in the peripheral circuit region 90 through dry etching or wet etching, and the number of the first grooves can be single or multiple. Then, deposit a metal material in the first grooves and the second grooves. Finally, perform a planarization process on the metal material to respectively form the first-region lower electrode metal connection layers 111 and the second-region lower electrode metal connection layers 112, so that the upper surfaces of the first-region lower electrode metal connection layers 111, the upper surfaces of the second-region lower electrode metal connection layers 112 and the upper surface of the lower dielectric layer 120 are flush. Thus, the lower electrode metal connection layer 110 surrounded by the lower dielectric layer 120 is obtained, and the upper surfaces of the first-region lower electrode metal connection layers 111 and the upper surfaces of the second-region lower electrode metal connection layers 112 are exposed.

[0069] Specifically, the lower electrode metal connection layer 110 surrounded by the lower dielectric layer 120 can isolate the first-region lower electrode metal connection layer 111 from other irrelevant parts; it can also isolate the second-region lower electrode metal connection layer 112 from other irrelevant parts. Thus, it prevents current from flowing on unnecessary paths and avoids short circuits and leakage. For example, it avoids direct connection between two first-region lower electrode metal connection layers 111, between two second-region lower electrode metal connection layers 112, or between the first-region lower electrode metal connection layer 111 and the second-region lower electrode metal connection layer 112, which may cause short circuits.

[0070] Specifically, the first dielectric layer 130 is formed on the upper surfaces of the first-region lower electrode metal connection layer 111, the second-region lower electrode metal connection layer 112, and the exposed lower dielectric layer 120. The first dielectric layer 130 can be formed by a thin film deposition process. The first dielectric layer 130 can be a single layer or multiple layers. For example, the first dielectric layer 130 can include a first dielectric sub-layer and a second dielectric sub-layer stacked in sequence. The first dielectric sub-layer can be made of a silicon nitride (SiN) thin film or a nitrided silicon carbide (NDC) thin film, and the second dielectric sub-layer can be made of a low-temperature oxide layer (LTO), a silicon dioxide layer (SiO2), or a silicon-rich oxide layer (SRO), etc. In the embodiments of the present application, the first dielectric sub-layer and the second dielectric sub-layer can also be selected from other materials according to actual application scenarios and process requirements, which are not limited herein.

[0071] Through the first dielectric layer 130, the first-region second lower electrode metal sub-layer 15111 and the second-region functional layer 342 (including the second-region second lower electrode metal sub-layer 15112) can be protected to prevent external damage to the first-region second lower electrode metal sub-layer 15111 and the second-region functional layer 342 (including the second-region second lower electrode metal sub-layer 15112).

[0072] Specifically, the lower electrode hard mask layer 380 is formed above the first dielectric layer 130. The lower electrode hard mask layer 380 can be formed by a thin film deposition process. The lower electrode hard mask layer 380 can include a first lower electrode hard mask sub-layer 381 and a second lower electrode hard mask sub-layer 382. The first lower electrode hard mask sub-layer 381 and the second lower electrode hard mask sub-layer 382 can be made of the same material or different materials. The first lower electrode hard mask sub-layer 381 and the second lower electrode hard mask sub-layer 382 can be made of at least one material selected from amorphous carbon, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, carbon oxide, and carbon nitride.

[0073] Specifically, the first patterned mask layer 391 can use positive photoresist or negative photoresist. The first patterned mask layer 391 is formed by using various known processes, and the embodiments of the present application have no limitations in this regard. For example, a mask layer is coated above the lower electrode hard mask layer 380, the mask layer is exposed, and an exposed area and a non-exposed area are formed on the mask layer. Then, the exposed mask layer is developed to remove the mask layer in the exposed area or the non-exposed area, forming the first patterned mask layer 391. Among them, when the positive photoresist is used for the mask layer, the mask layer in the exposed area changes from being insoluble in the developer to being soluble in the developer and is removed during development. When the negative photoresist is used for the mask layer, the mask layer in the exposed area changes from being soluble in the developer to being insoluble in the developer and is not removed during development. Thus, when the negative photoresist is used for the mask layer, the mask layer in the non-exposed area is removed.

[0074] Figure 3B The schematic cross-sectional structure diagram of the semiconductor for forming the first-region lower electrode interconnection via 141 and the second-region lower electrode interconnection via 142 according to the embodiment of the present application is shown.

[0075] As Figure 3B As shown, based on the first patterned mask layer 391, the exposed lower electrode hard mask layer 380 is etched until the corresponding position of the first dielectric layer 130 is exposed. The remaining lower electrode hard mask layer 380 forms a patterned lower electrode hard mask layer, and the aforementioned first patterned mask layer 391 is removed. Then, the exposed first dielectric layer 130 is etched using the patterned lower electrode hard mask layer as a mask, the first-region lower electrode interconnection via 141 and the second-region lower electrode interconnection via 142 are formed in the first dielectric layer 130, and the remaining lower electrode hard mask layer 380 is removed.

[0076] Specifically, the first-region lower electrode interconnection via 141 is located in the storage cell array region 80, and its bottom contacts the upper surface of the first-region lower electrode metal connection layer 111. The second-region lower electrode interconnection via 142 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second-region lower electrode metal connection layer 112. Among them, both the first-region lower electrode interconnection via 141 and the second-region lower electrode interconnection via 142 can be designed as a frustum-shaped structure with a larger upper end and a smaller lower end, such as a frustum of a cone structure or a frustum of a trapezoid structure, etc. In the embodiment of the present application, the first-region lower electrode interconnection via 141 and the second-region lower electrode interconnection via 142 can also be selected with other structural shapes according to the actual application scenario and process requirements, and are not limited herein.

[0077] In this embodiment, the cross-sectional shape of the first-region lower electrode interconnection via 141 is an inverted trapezoid, the upper base width of the inverted trapezoid is greater than the lower base width of the inverted trapezoid, and the upper base width of the inverted trapezoid is greater than the lower base width of the inverted trapezoid is greater than the included angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

[0078] Specifically, since the first - area lower - electrode inter - connection vias 141 located in the memory cell array region 80 correspond to the subsequently formed first - area upper - electrode inter - connection vias 181 located in the memory cell array region 80, and the second - area lower - electrode inter - connection vias 142 located in the peripheral circuit region 90 correspond to the subsequently formed second - area upper - electrode inter - connection vias 182 located in the peripheral circuit region 90. Thus, the first - area lower - electrode inter - connection vias 141, the second - area lower - electrode inter - connection vias 142, the first - area upper - electrode inter - connection vias 181, and the second - area upper - electrode inter - connection vias 182 can be etched based on the first patterning photomask layer 391.

[0079] Figure 3C The semiconductor cross - sectional structure diagram of depositing the first sub - layer 1511 of the second lower - electrode metal in the embodiment of the present application is shown.

[0080] As Figure 3C shown, the first sub - layer 1511 of the second lower - electrode metal is deposited in the first - area lower - electrode inter - connection vias 141, the second - area lower - electrode inter - connection vias 142, and on the upper surface of the first dielectric layer 130 through a thin - film deposition process, so that the first sub - layer 1511 of the second lower - electrode metal fills the first - area lower - electrode inter - connection vias 141 and the second - area lower - electrode inter - connection vias 142.

[0081] In the embodiment of the present application, during the deposition of the first sub - layer 1511 of the second lower - electrode metal, the first sub - layer 1511 of the second lower - electrode metal can also be deposited only on the inner walls and bottoms of the first - area lower - electrode inter - connection vias 141 and the second - area lower - electrode inter - connection vias 142, or on the inner walls and bottoms of the first - area lower - electrode inter - connection vias 141 and the second - area lower - electrode inter - connection vias 142 and on a part of the upper surface of the first dielectric layer 130, but at least the deposited first sub - layer 1511 of the second lower - electrode metal should fill the first - area lower - electrode inter - connection vias 141 and the second - area lower - electrode inter - connection vias 142.

[0082] Figure 3D The semiconductor cross - sectional structure diagram of planarizing the first sub - layer 1511 of the second lower - electrode metal in the embodiment of the present application is shown.

[0083] As Figure 3DAs shown, planarization is performed on the second lower electrode metal sub-layer 1511 to form a first-region second lower electrode metal sub-layer 15111 and a second-region second lower electrode metal sub-layer 15112, respectively. Specifically, the first-region second lower electrode metal sub-layer 15111 fills the first-region lower electrode interconnection vias 141, and the second-region second lower electrode metal sub-layer 15112 fills the second-region lower electrode interconnection vias 142. The upper surfaces of the first-region second lower electrode metal sub-layer 15111, the second-region second lower electrode metal sub-layer 15112, and the first dielectric layer 130 are flush.

[0084] Specifically, during the planarization process, chemical mechanical planarization technology (CMP, Chemical Mechanical Polishing) can be used.

[0085] Specifically, the first-region second lower electrode metal sub-layer 15111 is electrically connected to the first-region lower electrode metal connection layer 111, and the second-region second lower electrode metal sub-layer 15112 is electrically connected to the second-region lower electrode metal connection layer 112.

[0086] In this embodiment, the bottom of the first-region second lower electrode metal sub-layer 15111 contacts the upper surface of the first-region lower electrode metal connection layer 111, and the bottom of the second-region second lower electrode metal sub-layer 15112 contacts the upper surface of the second-region lower electrode metal connection layer 112.

[0087] Specifically, the first-region second lower electrode metal sub-layer 15111 and the second-region second lower electrode metal sub-layer 15112 can be single-layer or multi-layer. The first-region second lower electrode metal sub-layer 15111 and the second-region second lower electrode metal sub-layer 15112 can be made of one or several of titanium (Ti), tungsten (W), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), etc. In the embodiments of the present application, the first-region second lower electrode metal sub-layer 15111 and the first-region lower electrode metal connection layer 111 can be made of the same metal material, and the second-region second lower electrode metal sub-layer 15112 and the second-region lower electrode metal connection layer 112 can be made of the same metal material, so that the first-region second lower electrode metal sub-layer 15111 is in close contact with the first-region lower electrode metal connection layer 111, and the second-region second lower electrode metal sub-layer 15112 is in close contact with the second-region lower electrode metal connection layer 112, avoiding holes between the two materials due to different thermal expansion coefficients of different materials caused by thermal expansion and contraction.

[0088] Figure 3E A schematic semiconductor cross-sectional structure diagram of forming a memory cell stack layer 350 and a sidewall 159 according to an embodiment of the present application is shown.

[0089] As Figure 3E shown, a memory cell stack layer 350 is deposited on the upper surface of the exposed first dielectric layer 130, the upper surface of the first-region second lower electrode metal sub-layer 15111, and the upper surface of the second-region second lower electrode metal sub-layer 15112. The memory cell stack layer 350 includes a second lower electrode metal sub-layer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154. Next, a photolithography process and an etching process are used to etch the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154. Then, a sidewall 159 is deposited on the etched second switching layer 152, second upper electrode metal layer 153, upper electrode hard mask layer 154, and the exposed area of the first dielectric layer 130. The deposited sidewall 159 and the second lower electrode metal sub-layer 1512 are etched, and the etching process is stopped at the upper surface of the first dielectric layer 130, so that the etched sidewall 159 can wrap the memory cell stack layer 350 laterally.

[0090] In an embodiment of the present application, during the etching process of the deposited sidewall 159 and the second lower electrode metal sub-layer 1512, part or all of the second-region second lower electrode metal sub-layer 15112 will be consumed due to over-etching. In this embodiment, part of the second-region second lower electrode metal sub-layer 15112 is consumed, and the finally remaining part forms the second-region functional layer 342.

[0091] At this time, the first-region second lower electrode metal sub-layer 15111 and the second-region functional layer 342 are made of the same material, and the thickness of the first-region second lower electrode metal sub-layer 15111 is not less than the thickness of the second-region functional layer 342.

[0092] The function of the second-region functional layer 342 includes at least the following two aspects. Taking the second-region lower electrode metal connection layer 112 as a copper wire as an example.

[0093] First, the second-region functional layer 342 is used here as a barrier. The second-region functional layer 342 covers the copper wire. After the upper surface of the second-region lower electrode metal connection layer 112 exposes copper (i.e., after forming the second-region lower electrode through-hole 142), by covering the second-region functional layer 342, the copper on the upper surface of the second-region lower electrode metal connection layer 112 can be prevented from being oxidized or the oxidation diffusion can be slowed down, and at the same time, the QTime (Queue Time or process time interval) of the manufacturing process can be increased.

[0094] Secondly, the second-region functional layer 342 can be used as an etch stop layer. When etching is performed above the second-region functional layer 342, it serves as a stop layer for the etching process, thereby effectively controlling the accuracy of etch stop and preventing damage to the copper wire (i.e., the second-region lower electrode metal connection layer 112) caused by etching into it.

[0095] Preferably, the thickness range of the second-region functional layer 342 is between . When the thickness is lower than , it will result in too small a thickness of the second-region functional layer 342, posing a risk of being etched through, causing the function of the second-region functional layer 342 to fail; on the other hand, the second-region functional layer 342 with too small a thickness has too high a preparation cost in actual production. When the thickness is greater than , the second-region functional layer 342 will significantly increase the resistivity of the conductive metal connection lines in the peripheral circuit region 90. Therefore, when the thickness of the second-region functional layer 342 is between , it can not only avoid a significant increase in resistivity but also ensure prevention of being etched through and failure of the function, while being convenient for preparation in actual production.

[0096] Specifically, the second lower electrode metal two-layer 1512 can use the same material or different materials as the aforementioned first-region second lower electrode metal one-layer 15111. The materials used for the second lower electrode metal two-layer 1512 can include one or several of titanium (Ti), tungsten (W), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), etc.

[0097] Specifically, the material of the second switching layer 152 can include metal oxides such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), tantalum oxide (TaO), etc., which is used to change the resistance between the second lower electrode metal two-layer 1512 and the second upper electrode metal layer 153. In the embodiments of the present application, the second switching layer 152 can also be selected from other materials according to actual application scenarios and process requirements, which are not limited herein.

[0098] Specifically, the materials used for the second upper electrode metal layer 153 can include one or several of gold (Au), platinum (Pt), copper (Cu), and aluminum (Al), etc. In the embodiments of the present application, the second upper electrode metal layer 153 can also be selected from other materials according to actual application scenarios and process requirements, which are not limited herein.

[0099] Specifically, the upper electrode hard mask layer 154 can be made of at least one material among amorphous carbon, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxide, and silicon carbonitride. The upper electrode hard mask layer 154 is used to protect the underlying second upper electrode metal layer 153 during subsequent fabrication processes. The upper electrode hard mask layer 154 can be a non-conductive layer.

[0100] Figure 3F The semiconductor cross-sectional structural schematic diagram of forming the second dielectric layer 170 according to an embodiment of the present application is shown.

[0101] As Figure 3F shown, the second dielectric layer 170 is deposited on the surface of the exposed first dielectric layer 130, the surface of the exposed memory cell stack layer 350, the surface of the exposed sidewall 159, and the upper surface of the second region functional layer 342. After deposition, the upper surface of the second dielectric layer 170 is at least higher than the upper surface of the memory cell stack layer 350 and fills the remaining space of the second region lower electrode interconnection via 142.

[0102] Figure 3G The semiconductor cross-sectional structural schematic diagram of forming the first patterned photomask layer 391 according to an embodiment of the present application is shown.

[0103] As Figure 3G shown, the first patterned photomask layer 391 is formed above the second dielectric layer 170. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the first region upper electrode interconnection via 181 formed in the memory cell array region 80 and the second region upper electrode interconnection via 182 formed in the peripheral circuit region 90 in the subsequent formation.

[0104] Figure 3H The semiconductor cross-sectional structural schematic diagram of forming the first region upper electrode interconnection via 181 and the second region upper electrode interconnection via 182 according to an embodiment of the present application is shown.

[0105] As Figure 3H shown, based on the first patterned photomask layer 391, the exposed second dielectric layer 170 and the upper electrode hard mask layer 154 are etched until the corresponding positions of the second upper electrode metal layer 153 are exposed, and the exposed second dielectric layer 170 is etched until the corresponding positions of the second region functional layer 342 are exposed. The first region upper electrode interconnection via 181 is formed in the second dielectric layer 170 and the upper electrode hard mask layer 154, and the second region upper electrode interconnection via 182 is formed in the second dielectric layer 170. Among them, the first region upper electrode interconnection via 181 is located in the memory cell array region 80, and its bottom contacts the memory cell stack layer 350; the second region upper electrode interconnection via 182 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second region functional layer 342. Then, the first patterned photomask layer 391 is removed.

[0106] Specifically, the bottom of the first-region upper electrode interconnection via 181 is in contact with the second upper electrode metal layer 153, and the bottom of the second-region upper electrode interconnection via 182 is in contact with the second-region functional layer 342.

[0107] Figure 3I The semiconductor cross-sectional structure diagram showing the formation of the first-region upper electrode metal connection layer 191 and the second-region upper electrode metal connection layer 192 according to an embodiment of the present application is shown.

[0108] As Figure 3I shown, the first-region upper electrode metal connection layer 191 is filled in the first-region upper electrode interconnection via 181, and the second-region upper electrode metal connection layer 192 is filled in the second-region upper electrode interconnection via 182. The first-region upper electrode metal connection layer 191 is located in the memory cell array region 80, and its bottom is in contact with the memory cell stack layer 350; the second-region upper electrode metal connection layer 192 is located in the peripheral circuit region 90, and its bottom is in contact with the upper surface of the second-region functional layer 342.

[0109] Specifically, the second upper electrode metal layer 153 is electrically connected to the first-region upper electrode metal connection layer 191, and the second-region functional layer 342 is electrically connected to the second-region upper electrode metal connection layer 192.

[0110] Specifically, the material used for the second dielectric layer 170 may be silicon nitride (Si3N4). In the embodiments of the present application, the second dielectric layer 170 may also be selected according to actual application scenarios and process requirements to use other materials, which are not limited herein.

[0111] Specifically, the second dielectric layer 170 can isolate the second upper electrode metal layer 153 and the first-region upper electrode metal connection layer 191 from non-connected regions, and isolate the second-region upper electrode metal connection layer 192 from non-connected regions, thereby preventing current from flowing on unnecessary paths and avoiding the occurrence of short circuits and leakage phenomena.

[0112] Specifically, the first-region upper electrode metal connection layer 191 and the second-region upper electrode metal connection layer 192 may be made of a conductive material such as copper metal. In the embodiments of the present application, the first-region upper electrode metal connection layer 191 and the second-region upper electrode metal connection layer 192 may also be made of other metals according to needs, which are not limited herein.

[0113] In summary, by means of the preparation solution of the non-volatile two-terminal storage cell provided above, in the embodiment of the present disclosure, the first region lower electrode interconnection via holes 141 located in the storage cell array region 80 and the second region lower electrode interconnection via holes 142 located in the peripheral circuit region 90 are simultaneously etched based on the first patterned mask layer 391, and based on the first patterned mask layer 391, the first region upper electrode interconnection via holes 181 located in the storage cell array region 80 and the second region upper electrode interconnection via holes 182 located in the peripheral circuit region 90 can also be simultaneously etched in subsequent steps. It is possible to realize the preparation of the non-volatile two-terminal storage cell by using only one layer of patterned mask layer, thereby shortening the preparation process flow of the non-volatile two-terminal storage cell and reducing the preparation cost. Further, by using the same patterned mask layer (i.e., the first patterned mask layer 391) as a mask for etching the lower electrode interconnection via holes (i.e., the first region lower electrode interconnection via holes 141 located in the storage cell array region 80 and the second region lower electrode interconnection via holes 142 located in the peripheral circuit region 90) to etch the upper electrode interconnection via holes (i.e., the first region upper electrode interconnection via holes 181 located in the storage cell array region 80 and the second region upper electrode interconnection via holes 182 located in the peripheral circuit region 90), the alignment accuracy of the lower electrode interconnection via holes and the upper electrode interconnection via holes can be improved, problems such as changes in contact resistance caused by poor alignment can be avoided, and the stability and reliability of the formed non-volatile two-terminal storage cell are improved.

[0114] Next, based on Figure 2 the preparation process of the preparation method of the non-volatile two-terminal storage cell, combined with Figures 4A - 4I the semiconductor cross-sectional structure diagram shown, the exemplary process flow of the preparation method 200 of the non-volatile two-terminal storage cell according to other embodiments of the present application is described in detail.

[0115] Among them, the preparation steps of the non-volatile two-terminal storage cell combined with Figures 4A - 4D are the same as the preparation steps of the non-volatile two-terminal storage cell combined with Figures 3A - 3D shown, so they will not be described in detail here.

[0116] Figure 4E shows the semiconductor cross-sectional structure diagram of forming the storage cell stack layer 350 and the sidewall 159 according to the embodiment of the present application.

[0117] As Figure 4EAs shown, a memory cell stack layer 350 is deposited on the upper surface of the exposed first dielectric layer 130, the upper surface of the first-region second lower electrode metal sub-layer 15111, and the upper surface of the second-region second lower electrode metal sub-layer 15112. The memory cell stack layer 350 includes a second lower electrode metal bilayer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154. Subsequently, the second switching layer 152, the second upper electrode metal layer 153, and the upper electrode hard mask layer 154 are etched using a photolithography process and an etching process. Then, sidewalls 159 are deposited on the etched second switching layer 152, second upper electrode metal layer 153, upper electrode hard mask layer 154, and the exposed area of the first dielectric layer 130. The deposited sidewalls 159 and the second lower electrode metal bilayer 1512 are etched, and the etching is stopped at the upper surface of the first dielectric layer 130, so that the etched sidewalls 159 can wrap the memory cell stack layer 350 laterally.

[0118] In an embodiment of the present application, during the etching process of the deposited sidewalls 159 and the second lower electrode metal bilayer 1512, part or all of the second-region second lower electrode metal sub-layer 15112 may be consumed due to over-etching. Figure 3E Differently, in this embodiment, all of the second-region second lower electrode metal sub-layer 15112 is consumed, and the upper surface of the second-region lower electrode metal connection layer 112 is exposed.

[0119] Relative to Figure 3E the technical solution, this technical solution does not require a specific device for controlling the thickness of the remaining part of the second-region second lower electrode metal sub-layer 15112, and the manufacturing process is relatively simple and the cost is relatively low.

[0120] Specifically, the second lower electrode metal bilayer 1512 may be made of the same material or different materials as the aforementioned first-region second lower electrode metal sub-layer 15111. The material used for the second lower electrode metal bilayer 1512 may include one or several of titanium (Ti), tungsten (W), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), etc.

[0121] Specifically, the material of the second switching layer 152 may include metal oxides such as nickel oxide (NiO), titanium oxide (TiO), zinc oxide (ZnO), zirconium oxide (ZrO), hafnium oxide (HfO), tantalum oxide (TaO), etc., which is used to change the resistance between the second lower electrode metal bilayer 1512 and the second upper electrode metal layer 153. In an embodiment of the present application, the second switching layer 152 may also be selected from other materials according to the actual application scenario and process requirements, which are not limited herein.

[0122] Specifically, the material used for the second upper electrode metal layer 153 may include one or several of gold (Au), platinum (Pt), copper (Cu), aluminum (Al), etc. In the embodiments of the present application, the second upper electrode metal layer 153 may also be selected according to actual application scenarios and process requirements for other materials, which are not limited herein.

[0123] Specifically, the upper electrode hard mask layer 154 may be made of at least one material among amorphous carbon, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxide, and silicon carbonitride. The upper electrode hard mask layer 154 is used to protect the second upper electrode metal layer 153 below it during subsequent manufacturing processes. The upper electrode hard mask layer 154 may be a non-conductive layer.

[0124] Figure 4F The semiconductor cross-sectional structure diagram of forming the second dielectric layer 170 in the embodiments of the present application is shown.

[0125] As Figure 4F shown, the second dielectric layer 170 is deposited on the surfaces of the exposed first dielectric layer 130, the exposed memory cell stack layer 350, and the upper surfaces of the exposed sidewalls 159. After deposition, the upper surface of the second dielectric layer 170 is at least higher than the upper surface of the memory cell stack layer 350 and fills the remaining space of the second region lower electrode interconnection via 142.

[0126] Figure 4G The semiconductor cross-sectional structure diagram of forming the first patterned photomask layer 391 in the embodiments of the present application is shown.

[0127] As Figure 4G shown, the first patterned photomask layer 391 is formed above the second dielectric layer 170. Specifically, the pattern of the first patterned photomask layer 391 can be used to define the patterns of the first region upper electrode interconnection vias 181 formed in the memory cell array region 80 and the second region upper electrode interconnection vias 182 formed in the peripheral circuit region 90 subsequently.

[0128] Figure 4H The semiconductor cross-sectional structure diagram of forming the first region upper electrode interconnection vias 181 and the second region upper electrode interconnection vias 182 in the embodiments of the present application is shown.

[0129] As Figure 4HAs shown, based on the first patterned mask layer 391, the exposed second dielectric layer 170 and the upper electrode hard mask layer 154 are etched until the corresponding positions of the second upper electrode metal layer 153 are exposed, and the exposed second dielectric layer 170 is etched until the corresponding positions of the second region lower electrode metal connection layer 112 are exposed. A first region upper electrode interconnect via 181 is formed in the second dielectric layer 170 and the upper electrode hard mask layer 154, and a second region upper electrode interconnect via 182 is formed in the second dielectric layer 170. Among them, the first region upper electrode interconnect via 181 is located in the memory cell array region 80, and its bottom contacts the memory cell stack layer 350; the second region upper electrode interconnect via 182 is located in the peripheral circuit region 90 and is in contact with Figure 3H In a technical solution different from that of

[0130] Specifically, the bottom of the first region upper electrode interconnect via 181 contacts the second upper electrode metal layer 153, and the bottom of the second region upper electrode interconnect via 182 directly contacts the second region lower electrode metal connection layer 112.

[0131] Figure 4I FIG. shows a schematic semiconductor cross-sectional structure of forming a first region upper electrode metal connection layer 191 and a second region upper electrode metal connection layer 192 according to an embodiment of the present application.

[0132] As Figure 4I shown, the first region upper electrode metal connection layer 191 is filled in the first region upper electrode interconnect via 181, and the second region upper electrode metal connection layer 192 is filled in the second region upper electrode interconnect via 182. The first region upper electrode metal connection layer 191 is located in the memory cell array region 80, and its bottom contacts the memory cell stack layer 350; the second region upper electrode metal connection layer 192 is located in the peripheral circuit region 90, and its bottom contacts the upper surface of the second region lower electrode metal connection layer 112.

[0133] Specifically, the second upper electrode metal layer 153 is electrically connected to the first region upper electrode metal connection layer 191, and the second region lower electrode metal connection layer 112 is electrically connected to the second region upper electrode metal connection layer 192.

[0134] Specifically, the material of the second dielectric layer 170 can be silicon nitride (Si3N4). In the embodiment of the present application, the second dielectric layer 170 can also be selected according to actual application scenarios and process requirements, and other materials are not limited herein.

[0135] Specifically, the second dielectric layer 170 can isolate the second upper electrode metal layer 153 and the first region upper electrode metal connection layer 191 from the non-connection region, and isolate the second region upper electrode metal connection layer 192 from the non-connection region. Thus, it can prevent current from flowing on unnecessary paths, avoiding the occurrence of short circuit and leakage phenomena.

[0136] Specifically, the first region upper electrode metal connection layer 191 and the second region upper electrode metal connection layer 192 can adopt conductive materials such as copper metal. In the embodiments of the present application, the first region upper electrode metal connection layer 191 and the second region upper electrode metal connection layer 192 can also adopt other metals as needed, which are not limited herein.

[0137] In summary, by means of the above-provided preparation scheme for the non-volatile two-terminal storage unit, in the embodiments of the present disclosure, the first region lower electrode through-holes 141 located in the storage unit array region 80 and the second region lower electrode through-holes 142 located in the peripheral circuit region 90 are simultaneously etched based on the first patterned photomask layer 391. Moreover, based on the first patterned photomask layer 391, the first region upper electrode through-holes 181 located in the storage unit array region 80 and the second region upper electrode through-holes 182 located in the peripheral circuit region 90 can also be simultaneously etched in subsequent steps. It can realize the preparation of the non-volatile two-terminal storage unit by only using one layer of patterned photomask layer, thereby shortening the preparation process flow of the non-volatile two-terminal storage unit and reducing the preparation cost. Further, using the same patterned photomask layer (i.e., the first patterned photomask layer 391) as the mask for etching the lower electrode through-holes (i.e., the first region lower electrode through-holes 141 located in the storage unit array region 80 and the second region lower electrode through-holes 142 located in the peripheral circuit region 90) to etch the upper electrode through-holes (i.e., the first region upper electrode through-holes 181 located in the storage unit array region 80 and the second region upper electrode through-holes 182 located in the peripheral circuit region 90) can improve the alignment accuracy of the lower electrode through-holes and the upper electrode through-holes, avoid problems such as changes in contact resistance caused by poor alignment, and improve the stability and reliability of the formed non-volatile two-terminal storage unit.

[0138] In one embodiment of the present application, a non-volatile two-terminal storage cell is further provided. The non-volatile two-terminal storage cell includes a first dielectric layer 130 stacked on the upper surfaces of the first-region lower electrode metal connection layer 111 in the first region and the second-region lower electrode metal connection layer 112 in the second region; a first-region lower electrode through-connection hole 141 formed in the first dielectric layer 130 based on the first patterning mask layer 391 and in contact with the upper surface of the first-region lower electrode metal connection layer 111; a second-region lower electrode through-connection hole 142 formed in the first dielectric layer 130 based on the first patterning mask layer 391 and in contact with the upper surface of the second-region lower electrode metal connection layer 112; a storage cell stack layer 350 in contact with the upper surface of the first-region lower electrode through-connection hole 141; a second dielectric layer 170 formed in the first region and the second region; a first-region upper electrode through-connection hole 181 and a second-region upper electrode through-connection hole 182 formed in the second dielectric layer 170 based on the first patterning mask layer 391 and penetrating the second dielectric layer 170; a first-region upper electrode metal connection layer 191 formed in the first-region upper electrode through-connection hole 181 and electrically connected to the first-region lower electrode metal connection layer 111; and a second-region upper electrode metal connection layer 192 formed in the second-region upper electrode through-connection hole 182 and electrically connected to the second-region lower electrode metal connection layer 112.

[0139] The cross-sectional shape and size of the first-region lower electrode through-connection hole 141 are not limited. Preferably, the cross-sectional shape of the first-region lower electrode through-connection hole 141 is an inverted trapezoid, the upper base width of the inverted trapezoid is greater than the lower base width of the inverted trapezoid, and the upper base width of the inverted trapezoid is greater than the lower base width of the inverted trapezoid is greater than the angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

[0140] In one embodiment of the present application, the non-volatile two-terminal storage cell further includes a second-region functional layer 342. The second-region functional layer 342 is formed in the second-region lower electrode through-connection hole 142. The upper surface of the second-region functional layer 342 is lower than the upper surface of the first dielectric layer 130. The second-region functional layer 342 is electrically connected to the second-region lower electrode metal connection layer 112, and the second-region upper electrode metal connection layer 192 is electrically connected to the second-region functional layer 342.

[0141] In one embodiment of the present application, the non-volatile two-terminal storage cell further includes a first-region second lower electrode metal sub-layer 15111. The upper surface of the first-region second lower electrode metal sub-layer 15111 is flush with the upper surface of the first dielectric layer 130. The first-region second lower electrode metal sub-layer 15111 is electrically connected to the first-region lower electrode metal connection layer 111, and the first-region upper electrode metal connection layer 191 is electrically connected to the first-region second lower electrode metal sub-layer 15111.

[0142] In an embodiment of the present application, the storage cell stack layer 350 includes a second lower electrode metal bilayer 1512, a second switching layer 152, a second upper electrode metal layer 153, and an upper electrode hard mask layer 154 stacked in sequence. The non-volatile two-terminal storage cell may further include sidewalls 159, and the sidewalls 159 can wrap the storage cell stack layer 350 on the side.

[0143] In an embodiment of the present application, the bottom of the second-region upper electrode metal connection layer 192 contacts the upper surface of the second-region functional layer 342, and the bottom of the second-region functional layer 342 contacts the upper surface of the second-region lower electrode metal connection layer 112, so that the second-region lower electrode metal connection layer 112 and the second-region upper electrode metal connection layer 192 are indirectly connected through the second-region functional layer 342.

[0144] In an embodiment of the present application, the second-region functional layer 342 may not exist in the second-region lower electrode interconnection via 142, and the second-region lower electrode metal connection layer 112 and the second-region upper electrode metal connection layer 192 are directly connected, that is, the bottom of the second-region lower electrode metal connection layer 112 contacts the upper surface of the second-region upper electrode metal connection layer 192.

[0145] For the above non-volatile two-terminal storage cell, since the patterning mask layer is saved and the manufacturing method facilitates the formation and alignment of the lower electrode interconnection via and the upper electrode interconnection via of the non-volatile two-terminal storage cell, the preparation process flow of the non-volatile two-terminal storage cell can be shortened, and the preparation difficulty can be reduced, thereby reducing the preparation cost.

[0146] In an embodiment of the present application, a memory is further provided, and the memory includes one or more non-volatile two-terminal storage cells of the embodiments of the present application. Since the above non-volatile two-terminal storage cell is adopted in the memory, the yield of the memory can be improved, and the manufacturing cost of the memory can be reduced.

[0147] In an embodiment of the present application, an electronic device is further provided, and the electronic device includes the memory of the embodiments of the present application. Since the above memory is adopted in the electronic device, the possibility of quality problems in the memory of the electronic device can be reduced, and the hardware cost of the electronic device can be reduced.

[0148] Although several embodiments of the present application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many variations, modifications, and alternative ways will occur to those skilled in the art without departing from the spirit and scope of the present application. It should be understood that various alternatives to the embodiments of the present application described herein may be employed in practicing the present application. The appended claims are intended to define the scope of the present application and thus cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for preparing a non-volatile two-terminal storage unit, characterized in that: The preparation method comprises: A first dielectric layer (130) is stacked on an upper surface of a first region lower electrode metal connection layer (111) located in the first region and an upper surface of a second region lower electrode metal connection layer (112) located in the second region; Based on the first patterned mask layer (391), a first region lower electrode interconnection through hole (141) in contact with the upper surface of the first region lower electrode metal connection layer (111) and a second region lower electrode interconnection through hole (142) in contact with the upper surface of the second region lower electrode metal connection layer (112) are formed in the first dielectric layer (130); forming a memory cell stacking layer (350) above the first region lower electrode interconnection through hole (141), wherein the memory cell stacking layer (350) is in contact with the upper surface of the first region lower electrode interconnection through hole (141); forming a second dielectric layer (170) in the first region and the second region; Based on the first patterned mask layer (391), forming a first region upper electrode interconnection through hole (181) and a second region upper electrode interconnection through hole (182) in the second dielectric layer (170); A first-region upper electrode metal connection layer (191) is formed in the first-region upper electrode interconnection through hole (181), and a second-region upper electrode metal connection layer (192) is formed in the second-region upper electrode interconnection through hole (182), wherein the first-region upper electrode metal connection layer (191) is electrically connected to the first-region lower electrode metal connection layer (111), and the second-region upper electrode metal connection layer (192) is electrically connected to the second-region lower electrode metal connection layer (112).

2. The preparation method according to claim 1, characterized in that: A second region upper electrode metal connection layer (192) is formed in the second region upper electrode interconnection through hole (182), wherein the second region upper electrode metal connection layer (192) is electrically connected to the second region lower electrode metal connection layer (112), comprising: After forming the second-region lower electrode interconnection through hole (142), forming a second-region functional layer (342) partially filling the second-region lower electrode interconnection through hole (142), the second-region functional layer (342) being electrically connected to the second-region lower electrode metal connection layer (112); After forming the second-region upper electrode interconnection through hole (182), a second-region upper electrode metal connection layer (192) is formed in the second-region upper electrode interconnection through hole (182), and the second-region upper electrode metal connection layer (192) is electrically connected to the second-region functional layer (342).

3. The preparation method according to claim 2, characterized in that: The upper surface of the second region functional layer (342) is lower than the upper surface of the first dielectric layer (130).

4. The preparation method according to claim 3, characterized in that: Forming a second region functional layer (342) partially filling the second region lower electrode interconnection through hole (142), wherein the upper surface of the second region functional layer (342) is lower than the upper surface of the first dielectric layer (130), comprising: Before forming the memory cell stack layer (350), forming a second region second lower electrode metal first layer (15112) filling the second region lower electrode interconnection through hole (142), wherein the upper surface of the second region second lower electrode metal first layer (15112) is flush with the upper surface of the first dielectric layer (130); In the process of forming the memory cell stack layer (350), the second region second lower electrode metal layer (15112) in the second region lower electrode interconnection through hole (142) is partially removed to form the second region functional layer (342).

5. The preparation method according to claim 4, characterized in that: Forming a second dielectric layer (170) in the second region includes: After forming the second region functional layer (342) in the second region lower electrode interconnection through hole (142), forming the second dielectric layer (170) in the second region, the second dielectric layer (170) covers the upper surface of the second region functional layer (342) and at least fills the remaining space of the second region lower electrode interconnection through hole (142).

6. The preparation method according to claim 1 or 4, characterized in that: A first region upper electrode metal connection layer (191) is formed in the first region upper electrode interconnection through hole (181), wherein the first region upper electrode metal connection layer (191) is electrically connected to the first region lower electrode metal connection layer (111), comprising: After forming the first-region lower electrode interconnection through hole (141), forming the first-region second lower electrode metal layer (15111) filling the first-region lower electrode interconnection through hole (141), the upper surface of the first-region second lower electrode metal layer (15111) is flush with the upper surface of the first dielectric layer (130), and the first-region second lower electrode metal layer (15111) is electrically connected to the first-region lower electrode metal connection layer (111); After forming the first region upper electrode interconnection through hole (181), a first region upper electrode metal connection layer (191) is formed in the first region upper electrode interconnection through hole (181), the first region upper electrode metal connection layer (191) is in contact with the storage unit stacking layer (350), and the first region upper electrode metal connection layer (191) is electrically connected to the first region second lower electrode metal layer (15111).

7. The preparation method according to claim 6, characterized in that: A method for forming a first region second lower electrode metal layer (15111) filling the first region lower electrode interconnection through hole (141) and a second region second lower electrode metal layer (15112) filling the second region lower electrode interconnection through hole (142), comprising: After forming the first region lower electrode interconnection through hole (141) and the second region lower electrode interconnection through hole (142), forming the second lower electrode metal first layer (1511) at least in the first region lower electrode interconnection through hole (141) region and the second region lower electrode interconnection through hole (142) region; The second lower electrode metal layer (1511) outside the region of the first region lower electrode interconnection through hole (141) and outside the region of the second region lower electrode interconnection through hole (142) is removed, so that the remaining portion in the first region lower electrode interconnection through hole (141) forms the first region second lower electrode metal layer (15111), and the remaining portion in the second region lower electrode interconnection through hole (142) forms the second region second lower electrode metal layer (15112), and the upper surface of the first region second lower electrode metal layer (15111) and the upper surface of the second region second lower electrode metal layer (15112) are flush with the upper surface of the first dielectric layer (130).

8. The preparation method according to claim 7, characterized in that: In the process of removing the second lower electrode metal layer (1511) outside the area of ​​the first region lower electrode interconnection through hole (141) and outside the area of ​​the second region lower electrode interconnection through hole (142), an etching process or a CMP process is used.

9. The preparation method according to claim 6, characterized in that: The material of the second lower electrode metal layer (15111) in the first region and the material of the second region functional layer (342) are the same.

10. The preparation method according to claim 6, characterized in that: The thickness of the second lower electrode metal layer (15111) in the first region is not less than the thickness of the functional layer (342) in the second region.

11. The preparation method according to claim 1, characterized in that: The memory cell stack layer (350) comprises a second lower electrode metal binary layer (1512), a second switching layer (152), a second upper electrode metal layer (153) and an upper electrode hard mask layer (154) which are stacked in sequence.

12. The preparation method according to claim 11, characterized in that: The bottom of the first region upper electrode metal connection layer (191) penetrates the upper electrode hard mask layer (154) and contacts the upper surface of the second upper electrode metal layer (153).

13. The preparation method according to claim 1, characterized in that: The first region includes a memory cell array region (80), and the second region includes a peripheral circuit region (90).

14. The preparation method according to claim 1, characterized in that: The cross-sectional shape of the lower electrode interconnection through hole (141) in the first region is an inverted trapezoid.

15. The preparation method according to claim 14, characterized in that: The width of the upper base of the inverted trapezoid is greater than the width of the lower base of the inverted trapezoid, and the width of the upper base of the inverted trapezoid is greater than The lower base width of the inverted trapezoid is greater than 16. The preparation method according to claim 15, characterized in that: The angle between the waist of the inverted trapezoid and the lower base of the inverted trapezoid is greater than 105 degrees.

17. A non-volatile two-terminal storage unit, characterized in that: The non-volatile two-terminal storage unit comprises: A first dielectric layer (130) is stacked on an upper surface of a first region lower electrode metal connection layer (111) in the first region and an upper surface of a second region lower electrode metal connection layer (112) in the second region; A first region lower electrode interconnection through hole (141) is formed in the first dielectric layer (130) based on a first patterned mask layer (391) and is in contact with an upper surface of the first region lower electrode metal connection layer (111); A second region lower electrode interconnection through hole (142) is formed in the first dielectric layer (130) based on a first patterned mask layer (391) and contacts an upper surface of the second region lower electrode metal connection layer (112); A memory cell stack layer (350) in contact with an upper surface of the lower electrode interconnection through hole (141) in the first region; A second dielectric layer (170) formed in the first region and the second region; A first region upper electrode interconnection through hole (181) and a second region upper electrode interconnection through hole (182), formed in the second dielectric layer (170) based on the first patterned mask layer (391) and penetrating the second dielectric layer (170); A first region upper electrode metal connection layer (191), formed in the first region upper electrode interconnection through hole (181), and electrically connected to the first region lower electrode metal connection layer (111); The second region upper electrode metal connection layer (192) is formed in the second region upper electrode interconnection through hole (182) and is electrically connected to the second region lower electrode metal connection layer (112).

18. The non-volatile two-terminal memory cell according to claim 17, characterized in that: The non-volatile two-terminal storage unit also includes: A second region functional layer (342), wherein the second region functional layer (342) is formed in the second region lower electrode interconnection through hole (142), the upper surface of the second region functional layer (342) is lower than the upper surface of the first dielectric layer (130), the second region functional layer (342) is electrically connected to the second region lower electrode metal connection layer (112), and the second region upper electrode metal connection layer (192) is electrically connected to the second region functional layer (342).

19. The non-volatile two-terminal memory cell according to claim 17, characterized in that: The non-volatile two-terminal storage unit also includes: The second lower electrode metal layer (15111) in the first region is electrically connected to the first region lower electrode metal connection layer (111), and the first region upper electrode metal connection layer (191) is electrically connected to the second lower electrode metal layer (15111) in the first region.

20. The non-volatile two-terminal memory cell according to claim 19, characterized in that: The memory cell stack layer (350) comprises a second lower electrode metal binary layer (1512), a second switching layer (152), a second upper electrode metal layer (153) and an upper electrode hard mask layer (154) which are stacked in sequence.

21. The non-volatile two-terminal memory cell according to claim 18, characterized in that: The bottom of the second region upper electrode metal connection layer (192) contacts the upper surface of the second region functional layer (342), and the bottom of the second region functional layer (342) contacts the upper surface of the second region lower electrode metal connection layer (112).

22. The non-volatile two-terminal memory cell according to claim 17, characterized in that: The bottom of the second region upper electrode metal connection layer (192) contacts the upper surface of the second region lower electrode metal connection layer (112).

23. A memory, characterized in that: The memory comprises one or more non-volatile two-terminal memory cells according to any one of claims 17-22.

24. An electronic device, characterized in that: The electronic device comprises the memory according to claim 23.

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