Manufacturing of silicon carbide epitaxial wafer
By growing a SiC conductive layer with a high doping concentration on a SiC substrate with a low doping concentration, the defects and stress problems in SiC epitaxial wafers are solved by using the sublimation growth process, the quality and yield of the wafer are improved, and efficient SiC epitaxial wafer manufacturing is achieved.
Patent Information
- Application Number
- CN202380073076.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-11-28
- Filing Date
- 2023-08-15
- Publication Date
- 2025-06-20
AI Technical Summary
In the prior art, when manufacturing SiC epitaxial wafers, it is difficult to completely avoid defects and stresses in the drift layer, and the doping uniformity of the conductive layer is insufficient, which affects the quality and yield of the wafer.
By growing a single crystal SiC conductive layer with a high doping concentration on a single crystal SiC substrate with a low doping concentration, a high level of process control and crystal growth control is provided using the sublimation growth process to produce high quality epitaxial wafers.
The manufacturing of high-quality epitaxial wafers is achieved, which reduces defect density and stress, improves the doping uniformity of the conductive layer and device yield, and enhances the reliability and performance of the wafer.
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Figure CN120187900A_ABST
Abstract
Description
Technical Field
[0001] The present invention generally relates to the manufacture of silicon carbide epitaxial wafers. Background Art
[0002] Semiconductor materials and devices can be found in a variety of electronic devices. One application is in power semiconductor devices or power devices. Power devices have the function of converting and / or controlling electrical energy between an energy source and an energy consumer. Power equipment can be found in power grids, computer power supplies, power management in smart phones, and automotive electronics, to name a few.
[0003] Silicon carbide (SiC) is a next-generation semiconductor material that has been attracting increasing attention in the power device industry. Using SiC can enable more energy-efficient power devices with lower cooling requirements and higher system integration densities. However, technical solutions related to the manufacture of SiC semiconductor materials are still needed.
[0004] SiC epitaxial wafers are thin semiconductor disks typically formed of two main layers, one layer having a high doping concentration and one layer having a low doping concentration. The layer with the high doping concentration is typically referred to as the conductive layer. The layer with the low doping concentration is typically referred to as the drift layer.
[0005] The quality of the drift layer is crucial for the quality of the final product. The quality of the drift layer is defined by the defect density. Typical defects in the drift layer are downward drops (carbon particles), carrot defects, triangular stacking faults, basal plane dislocations (BPDs), rod-shaped stacking faults, screw threading dislocations, and threading edge dislocations.
[0006] In the prior art, SiC epitaxial wafers are manufactured by depositing a drift layer on a conductive layer. More specifically, a conductive substrate (conductive layer) with a high doping concentration is manufactured in a physical vapor transport (PVT) furnace, and subsequently, after crystal slicing, grinding, and polishing, a layer with a low doping concentration (drift layer) is deposited on the substrate by means of chemical vapor deposition (CVD).
[0007] The quality of the drift layer deposited on the conductive substrate is determined by the process control level and also by the crystallization quality of the conductive substrate. This is because defects in the conductive substrate propagate into the drift layer during the growth of the drift layer. Therefore, the quality of the conductive substrate will be a limiting factor in the effort to manufacture high-quality epitaxial wafers. Currently, it is considered impossible to achieve a completely defect-free drift layer using the prior art.
[0008] Another problem with the prior art process is related to stress in the drift layer. When the drift layer is grown on the conductive layer, stress accumulates in the drift layer. This is caused, for example, by the drift layer having a smaller volume compared to the conductive layer. The volume difference is caused by doping, where the type of dopant atoms (and their respective radii) and the doping concentration cause lattice expansion or contraction. Stress in the drift layer can occur during growth and also during cooling after growth, and can lead to slip of crystal planes, thus forming, for example, stacking faults.
[0009] Another parameter affecting the quality of epitaxial wafers today is doping uniformity, where the problem is related to both the conductive layer and the drift layer. Currently, the doping uniformity of the conductive layer is typically about 20%, which means that the difference in doping concentration between the regions with the highest and lowest doping concentrations in the material is 20%. For example, doping uniformity at this level results in a change in resistivity in the material, which in turn has a negative impact on the yield (the usable area of the wafer). In addition, it has a negative impact on the temperature distribution in the material. Furthermore, during growth (when doping occurs), non-uniform doping may affect the growth characteristics, resulting in a less uniform growth surface, which naturally also affects the yield.
[0010] Therefore, technical solutions for manufacturing SiC epitaxial wafers are needed to further reduce the defect density in SiC epitaxial wafers.
[0011] Definition
[0012] Doping: Doping is the process of increasing the number of charge carriers in a crystal structure. The net doping concentration is defined as the difference between the number of electron donors (Nd) and the number of electron acceptors (Na). Nitrogen atoms are common electron donors. Boron and aluminum atoms are common electron acceptors. The net doping concentration can be measured in different ways, for example: the concentration of dopant atoms can be measured by secondary ion mass spectrometry (SIMS), the concentration of ionized dopant atoms can be measured by capacitance-voltage (CV), and the concentration of charge carriers can be measured by Hall measurement.
[0013] N-type doping: Doping with atoms that can provide negative charge carriers (electrons) to the crystal structure. Common n-type dopants are nitrogen. Doping is usually carried out by introducing a dopant gas (such as nitrogen) during material growth. The resulting doping type (n-type or p-type) of the material is determined by the most abundant p-type or n-type electroactive atoms.
[0014] P-type doping: Doping with atoms that can provide positive charge carriers (called holes). Aluminum is a common p-type dopant and is typically doped by introducing a dopant gas (such as trimethylaluminum (TMA) gas), or using a source material containing aluminum, or alternatively introducing a powder (such as aluminum carbide powder (Al4C3)). Boron is another common p-type dopant. The resulting doping type (n-type or p-type) of the material is determined by the most abundant p-type or n-type electroactive atoms.
[0015] Epitaxial wafer: A single-crystalline SiC wafer that includes a SiC conductive layer with a high doping concentration and a SiC drift layer with a low doping concentration. The high doping concentration should be understood herein as ≥ 1·10 18 cm -3 . The low doping concentration should be understood herein as ≤ 5·10 16 cm -3 , preferably ≤ 1·10 16 cm -3 . Summary of the Invention
[0016] An object of the present invention is to overcome at least some of the above problems.
[0017] In a first aspect of the present invention, this is achieved by providing a method for manufacturing a silicon carbide SiC epitaxial wafer in a wafer growth system, the wafer growth system including an outer container, a heat-insulating container disposed inside the outer container, a growth container disposed inside the heat-insulating container, and a heating device disposed outside the outer container to heat the inside of the growth container. The method includes: providing a source material of polycrystalline SiC in the growth container; providing a single-crystalline SiC substrate substantially parallel to the source material, the doping concentration of the substrate being ≤ 5·10 16 cm -3 ; raising the temperature in the growth container to the sublimation temperature of the source material; maintaining the temperature in the growth container until a conductive layer of single-crystalline SiC with a thickness ≥ 10 μm and a doping concentration ≥ 1·10 18 cm -3 is grown on the substrate, wherein the substrate and the grown conductive layer together define an epitaxial ingot; cooling the epitaxial ingot to room temperature; and slicing the epitaxial ingot through the substrate in a plane substantially parallel to the grown conductive layer into a remaining substrate and an epitaxial wafer, the epitaxial wafer including a substrate layer having the grown conductive layer thereon.
[0018] With this new method, high-quality epitaxial wafers can be manufactured, which will help improve device performance (e.g., reduce electrical losses due to lower resistance) and improve reliability (e.g., reduce the risk of bipolar degradation). By providing a high-quality low-doped substrate, the growth of low-doped material on high-doped material during the manufacture of epitaxial wafers can be completely avoided. One advantage of doing so is that the quality of the low-doped material (drift layer) is no longer limited by the quality of the conductive layer. That is, defects present in the conductive layer cannot propagate to the drift layer.
[0019] Another advantage is that there is no stress transferred from high-doped material to low-doped material as in the prior art. With the claimed method, this transfer stress is no longer a limiting quality factor for the low-doped material (drift layer).
[0020] Another advantage is the improvement in device yield. Device yield is related to the percentage of working components on the wafer. Due to the improved quality achieved by the claimed method and the reduction of defects formed during epitaxial growth, the device yield is improved.
[0021] Another advantage of growing the conductive layer on a low-doped substrate is the improvement in the doping uniformity of the conductive layer. The improved doping uniformity provides a more uniform temperature distribution, more uniform growth characteristics, more uniform resistivity, and improved yield.
[0022] Compared with the prior art, another advantage of growing the conductive layer on a low-doped substrate is that the requirements for substrate surface preparation are less strict because the defect density requirements in the conductive layer are not as strict as those in the drift layer. Defects caused by surface treatment defects (such as scratches or pits) are acceptable in the conductive layer, while the same defects in the drift layer will make it unusable.
[0023] The new method is made feasible at least by applying a sublimation growth process, which provides a high level of process control and crystal growth control, thus providing crystal quality control. In prior art processes, the sublimation growth process is not applicable when the drift layer is grown on the conductive layer because at the sublimation temperature of SiC, the dopants in the conductive layer will be released into the gas phase and poison the drift layer grown on it by diffusion.
[0024] In some instances, the doping concentration of the substrate ≤ 1·10 16 cm -3 .
[0025] In some instances, the substrate and thus the substrate layer of the epitaxial wafer are n-type doped.
[0026] In some instances, the substrate and thus the substrate layer of the epitaxial wafer are p-type doped.
[0027] In some instances, the thickness of the substrate is ≥ 100 μm.
[0028] In some instances, the substrate is substantially free of basal plane dislocations.
[0029] In some instances, the substrate is substantially free of stacking faults.
[0030] In some instances, the conductive layer is grown on the carbon face of the substrate.
[0031] Crystals grown on the carbon face generally have better crystal quality than comparable crystals grown on the silicon face. Additionally, surface preparation of the carbon face is easier, more time-efficient, and more cost-effective compared to the silicon face. In prior art processes, the conductive layer / highly doped substrate is typically grown on the carbon face of a seed. Subsequently, during, for example, CVD, a drift layer is grown on the silicon face of the highly doped substrate. Thus, the claimed method provides a manufacturing process in which the better crystalline quality provided by growth on the carbon face can be additionally utilized in the fabrication of epitaxial wafers. Specifically, the manufacturing process of growth on the silicon face can be completely avoided.
[0032] In some instances, the method includes repeating the method at least once, and the method further includes reusing the remaining substrate as the substrate in the growth vessel.
[0033] Reusing the substrate in subsequent growth runs / cycles provides a more time-efficient and cost-effective method.
[0034] In a second aspect of the present invention, there is provided a silicon carbide (SiC) epitaxial wafer comprising: a substrate layer of single crystal SiC having a doping concentration ≤ 5·10 16 cm -3 and a conductive layer of single crystal SiC having a doping concentration ≥ 1·10 18 cm -3 The epitaxial wafer is fabricated by the following process: providing in a growth vessel a single crystal SiC substrate substantially parallel to a source material, the substrate having a doping concentration ≤ 5·10 16 cm -3 raising the temperature in the growth vessel to the sublimation temperature of the source material; maintaining the temperature in the growth vessel until a conductive layer of ≥ 10 μm of single crystal SiC having a doping concentration ≥ 1·10 18 cm -3 is grown on the substrate, wherein the substrate and the grown conductive layer together define an epitaxial ingot; cooling the epitaxial ingot to room temperature; and slicing the epitaxial ingot in a plane substantially parallel to the grown conductive layer through the substrate into a remaining substrate and an epitaxial wafer, the epitaxial wafer comprising the substrate layer on which the grown conductive layer is grown.
[0035] In some instances, the doping concentration of the substrate layer of the epitaxial wafer is ≤ 1·1016 cm -3 。
[0036] In some instances, the substrate layer of the epitaxial wafer is n-type doped.
[0037] In some instances, the substrate layer of the epitaxial wafer is p-type doped.
[0038] In some instances, the substrate layer of the epitaxial wafer is substantially free of basal plane dislocations.
[0039] The presence of BPDs is detrimental to devices fabricated on the epitaxial wafer as they may cause bipolar device degradation.
[0040] In some instances, the substrate layer of the epitaxial wafer is substantially free of stacking faults.
[0041] In some instances, a conductive layer is grown on the carbon face of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0042] The present invention will now be described by way of example with reference to the accompanying drawings, in which:
[0043] FIG. 1 shows a system for growing an epitaxial wafer according to the present invention.
[0044] Figure 2 Illustrates a method according to the present invention.
[0045] Figures 3a - 3c Illustrates the various stages of fabricating an epitaxial wafer according to the present invention. DETAILED DESCRIPTION
[0046] In the following, specific embodiments of a method for fabricating a single crystal epitaxial wafer of silicon carbide (SiC) will be described by way of exemplary embodiments. It should be understood that these embodiments are merely exemplary and that those skilled in the art may practice many other embodiments within the scope of the present invention with the teachings therein. In the drawings, throughout several figures, the same reference numerals denote the same or corresponding elements. It should be understood that these drawings are for illustrative purposes only and do not limit the scope of the present invention in any way. When referring to directions such as up or down, above or below, this should be understood during the normal operation of the system disclosed herein.
[0047] An object of the present invention is to provide a new method for fabricating high-quality epitaxial wafers by growing a single crystal material with a high doping concentration on a single crystal material with a low doping concentration. This directly contradicts the current common practice. The following disclosure is based on the insight that by providing a substrate with a low doping concentration that is substantially free of basal plane dislocations and substantially free of stacking faults, high-quality epitaxial wafers can be fabricated according to the method of the present invention.
[0048] First, refer to Figure 1a and Figure 1b to describe the system 1 for growing an epitaxial wafer.
[0049] In Figure 1a and Figure 1b a growth system 1 for growing an epitaxial wafer is shown. Specifically, in the system 1 shown in Figure 1a and Figure 1b an epitaxial crystal is grown. According to the present invention, an epitaxial ingot is a precursor of an epitaxial wafer. It is defined herein as a single-crystalline SiC disk including two substantially parallel layers. The first layer is the substrate 4, which can be described as a precursor of a drift layer and has a greater thickness than the final drift layer. The second layer is the conductive layer 6.
[0050] Contrary to what is disclosed in the prior art, the present invention includes growing single-crystalline SiC with a high doping concentration on a substrate 4 of single-crystalline SiC having a low doping concentration. The high doping concentration should be understood as ≥ 1·10 18 cm -3 . The low doping concentration should be understood as ≤ 5·10 16 cm -3 , preferably ≤ 1·10 16 cm -3 . The doping concentration can be measured, for example, by secondary ion mass spectrometry.
[0051] The growth system 1 is a physical vapor transport system. The growth system 1 is configured for sublimation epitaxy, which means growing an epitaxial wafer or ingot by sublimation. The growth system 1 can be configured, for example, for a fast sublimation growth process (FSGP). The growth system 1 generally includes an inner container 2, a heat-insulating container, and an outer container. The inner container 2 is disposed inside the heat-insulating container during operation. During operation, the heat-insulating container is disposed inside the outer container. The growth system 1 further includes a heating element. The heating element is disposed outside the outer container and is configured to heat the cavity of the inner container 2. The heating element can be configured for inductive heating, for example, in the form of an induction coil. The heating element can be configured for resistive heating.
[0052] The heating element can be moved relative to the outer container. To this end, the growth system 1 can include a transport system configured to move the heating element. The heating element can be moved in the vertical direction. The heating element can move along the height of the outer container. Thereby, the temperature inside the cavity of the inner container 2 can be controlled with high precision. In addition, this enables controlling the rate of temperature increase and temperature decrease. In addition, this enables controlling the temperature drop in the cavity of the inner container 2. The temperature drop is the temperature difference between two positions in the cavity of the inner container 2, where during normal operation, one position is vertically above the other position.
[0053] In addition, the temperature in the cavity of the inner container 2 can be controlled by changing the designs of the inner container 2, the insulating container, and the outer container. The design can relate to the wall thickness of each container. The design can relate to the relative dimensions between the containers.
[0054] The inner container 2 can include an upper part 2a and a bottom part 2b. The upper part 2a can be disposed on top of the bottom part 2b. The upper part 2a can be sealingly joined to the bottom part 2b, for example, by having a tight fit between the top and the bottom part 2b, or by providing threads on the components. The interior of the upper part 2a and the interior of the bottom part 2b can together define the cavity of the inner container 2. The inner container 2 can also be cylindrical. The inner container 2 can be formed of high-density graphite. The inner container 2 can be formed of a material suitable for withstanding high temperatures (e.g., higher than 1500 °C). In each case, the inner container 2 can be formed of a material suitable for the type of heating element. For example, if the growth system 1 includes an induction heating element, the material of the inner container 2 should be suitable for induction heating, which can be high-density graphite.
[0055] The insulating container can be cylindrical and can be formed of insulating graphite foam. The outer container can be cylindrical and can be formed of quartz. The insulating container is preferably used to insulate the inner container 2.
[0056] The growth system 1 can include a pump for evacuating the cavity of the inner container 2. The pump can include an inlet disposed in the cavity of the inner container 2 for pumping gas into the cavity. The gas can be argon. The pump can include an outlet disposed in the cavity of the inner container 2 for pumping gas out of the cavity.
[0057] In addition, the pump and the associated inlets and outlets can be arranged for pumping dopant gas into the cavity. The dopant gas can be nitrogen. The dopant gas can be used to increase the doping concentration during the growth of the grown epitaxial layer. The system according to the present invention provides a uniform distribution of the dopant gas in the inner container 2, which can, for example, improve properties such as doping uniformity.
[0058] The growth system 1 can include a carbon getter, which is arranged to maintain a stable and suitable Si / C stoichiometry during growth. The carbon getter can be disposed in the cavity of the inner container 2. The growth system 1 can include a plurality of carbon getters.
[0059] During the growth of the conductive layer 6, a source material 3 and a substrate 4 are provided in the cavity of the inner container 2. The substrate 4 can be disposed above the source material 3 in the cavity of the inner container 2. The substrate 4 can be disposed below the source material 3 in the cavity of the inner container 2.
[0060] The source material 3 is a monolithic polycrystalline SiC source material 3. The source material 3 may have a columnar microcrystalline structure. The grain size of the source material 3 may be 1 - 250 μm. The grain size of the source material 3 may be 1 - 100 μm. The microstructure may be a cubic microstructure. The source material 3 may be n-type doped. The source material 3 may be p-type doped.
[0061] The substrate 4 is a monolithic single-crystalline SiC substrate. The crystal structure of the substrate 4 may be 4H polytype, 6H polytype, 15R polytype, 3C polytype, or another suitable polytype. The low doping concentration of the substrate 4 ≤ 5·10 16 cm -3 and preferably ≤ 1·10 16 cm -3 . This means that the concentration difference between electron donors and electron acceptors is lower than ≤ 5·10 16 cm -3 and preferably ≤ 1·10 16 cm -3 . The substrate 4 may be n-type doped. The substrate 4 may be manufactured by sublimation growth. The substrate 4 may be manufactured by a separate process performed in the growth system 1 according to the present invention.
[0062] The substrate 4 is substantially free of stacking faults. Preferably, the substrate 4 is completely free of stacking faults. Stacking faults are planar defects in the microstructure caused by lattice stress (referred to as a higher stacking fault energy).
[0063] The substrate 4 is substantially free of basal plane dislocations. Preferably, the substrate 4 is completely free of basal plane dislocations (BPD). BPD is a microstructure defect in the material, which may occur during the growth of the substrate 4 or during the cooling of the substrate 4 after growth. The presence of BPD is harmful to the epitaxial wafer because the defects can propagate from the substrate 4 to the growth layer during growth. The BPD concentration can be measured by counting the BPD. The counting can be manual or computer-aided. The counting is preferably performed after a suitable surface preparation (such as etching) and after a suitable magnification, for example, by means of an optical microscope or a scanning electron microscope.
[0064] The SiC substrate 4 has a crystal structure including alternating layers of carbon and silicon, which makes the substrate 4 include a carbon side called the carbon face or C-face and a silicon side called the silicon face or Si-face. The substrate 4 is preferably disposed in the cavity of the inner container 2 such that the C-face is disposed to face the source material 3. Thus, when the conductive layer 6 grows thereon, the conductive layer 6 will grow on the C-face.
[0065] The substrate 4 can be disposed on at least one support 5, preferably using at least two supports 5. By means of the support 5, the source material 3 and the substrate 4 are preferably arranged such that the distance between them is less than the mean free path of the gaseous substance sublimated from the source material 3. In one embodiment, at least one support 5 has an upper part and a bottom 2b, and the upper part 2a of the support 5 contacts the outer edge of the substrate 4. In one embodiment, the bottom 2b of the support 5 rests on the source material 3. In one embodiment, the bottom 2b rests on the bottom of the inner container 2. In an alternative embodiment, at least one support has a distal part and a proximal part, wherein the proximal part is fixedly arranged on the inner surface of the inner container 2, and the distal part extends horizontally towards the center of the inner container 2, and wherein the substrate 4 rests on the distal part. Figure 1a and Figure 1b The support 5 shown in Figure 1b is a conical support 5 which minimizes the contact area between the support 5 and the substrate 4.
[0066] Now reference will be made to Figure 2 describe the method.
[0067] Step S1 of the method includes providing a monolithic polycrystalline source material 3 in the inner container 2 of the growth system 1, and providing a monolithic single crystal substrate 4 above the source material 3 in the inner container 2. The substrate 4 is disposed at a distance of 0.5 mm to 2 mm above the source material 3, preferably at a distance of 0.7 mm to 1.3 mm above the source material 3, and more preferably at a distance of 1 mm above the source material 3. This arrangement is shown in Figure 1a Figure 1a .
[0068] Step S2 of the method includes evacuating the inner container 2 to provide a clean environment for growth. The inner container 2 can be evacuated to a pressure of 1 mbar, preferably ≤ 1 mbar, and even more preferably ≤ 0.1 mbar.
[0069] Step S3 of the method includes flushing the inner container 2 with an inert gas such as argon. Flushing the inner container 2 with an inert gas serves the purpose of ensuring a clean environment for growth, wherein the inert gas can flush out the residual air. The inert gas also serves the purpose of suppressing the sublimation of unwanted gaseous substances, which will be described in more detail below with reference to step S4. In an exemplary embodiment, the inert gas is introduced into the chamber until the pressure reaches 1 mbar to 10 mbar. In another exemplary embodiment, the inert gas is introduced until the pressure reaches 150 mbar to 950 mbar, preferably 700 mbar.
[0070] In step S4, the temperature in the inner container 2 is raised to the sublimation temperature of the source material 3 by a heating element. The theoretical temperature at which sublimation of the substrate 4 starts can also be 1500 °C or higher. During the raising step S4, the temperature in the inner container 2 can be raised to a sublimation temperature of 1650 °C to 2050 °C. The temperature can be raised, for example, to a sublimation temperature of 1800 °C, 1950 °C, 1975 °C, 2050 °C or another suitable sublimation temperature.
[0071] The inert gas in the inner container 2 introduced during step S3 has the effect of suppressing the sublimation of gaseous substances that sublime at a lower temperature (below the sublimation temperature), and thus prevents such gaseous substances from growing on the substrate 4 during the temperature-raising step S4. Therefore, controlled sublimation from the substrate 4 can be achieved by controlling the pressure in the inner container 2. In one embodiment, the pressure during the raising step S4 can be constant in the range of 1 mbar to 10 mbar. In one embodiment, the pressure during the raising step S4 can be reduced at a pumping rate of, for example, 1 mbar / min to 10 mbar / min, preferably 5 mbar / min, until a pressure of 0.01 mbar to 10 mbar, preferably 0.1 mbar to 10 mbar, more preferably 0.1 mbar to 5 mbar is reached.
[0072] In step S5, the temperature in the inner container 2 is maintained. In step S5, the conductive layer 6 starts to grow on the substrate 4. The desired growth rate can be in the range of 1 μm / h to 1 mm / h. The growth rate is preferably maintained at 10 μm / h to 500 μm / h. The desired growth rate depends on the balance between productivity and quality. In one embodiment, the sublimation temperature is maintained at 1950 °C, and a growth rate of approximately 90 μm / h is obtained under the above settings. Those skilled in the art know at what temperature the desired growth rate is obtained. This temperature is maintained until a conductive layer 6 of the desired thickness has grown on the substrate 4. The desired thickness of the conductive layer 6 can be ≥5 μm. The desired thickness of the conductive layer 6 can be ≥10 μm. The desired thickness of the conductive layer 6 can depend on the intended use of the epitaxial wafer.
[0073] In step S6, the heating element is turned off and the substrate 4 is allowed to cool to room temperature. The substrate 4 is preferably cooled inside the inner container 2. During step S6, the inner container 2 can be refilled with an inert gas to reach atmospheric pressure. The inert gas can be argon.
[0074] During steps S1 - S6, an epitaxial ingot is manufactured. The epitaxial ingot includes the substrate 4 and the conductive layer 6 grown thereon. This is shown in Figure 1b shown.
[0075] The conductive layer 6 grown during steps S1 to S6 has a doping uniformity of ≤15%, preferably ≤10%, more preferably ≤5%, and most preferably ≤2%. The doping uniformity is determined by comparing the measured values of the doping concentration in different regions of the conductive layer, preferably the measured values of the doping concentration between the regions with the highest and lowest doping concentrations.
[0076] In step S7, the epitaxial ingot is cut through the substrate 4. The epitaxial ingot is preferably sliced through the substrate 4 in a plane A-A that is substantially parallel to the plane of the grown conductive layer 6. The plane A-A is visible in Figure 3b In. By slicing, the epitaxial ingot is divided into two parts. The first part is an epitaxial wafer that includes the conductive layer 6 and the substrate layer that defines the drift layer 7. The second part is in the form of the remaining substrate 8. The thickness of the drift layer 7 depends on the intended use of the epitaxial wafer. The thickness can depend, for example, on what voltage class the device fabricated from the epitaxial layer will be used for. The epitaxial ingot can be sliced such that a drift layer 7 with a thickness of approximately 10 μm per 1000 V is achieved.
[0077] In one example, the drift layer 7 is 5 μm and is suitable for a device with a voltage class of 600 V. In another example, the drift layer 7 is 10 μm and is suitable for a device with a voltage class of 1000 V. In another example, the drift layer 7 is 10 μm and is suitable for a device with a voltage class of 1200 V. These exemplary epitaxial wafers can be used, for example, in Schottky barrier diodes.
[0078] In one example, the drift layer 7 is 16 μm and is suitable for a device with a voltage class of 1700 V. In one example, the drift layer 7 is 30 μm and is suitable for a device with a voltage class of 3300 V. In one example, the drift layer 7 is 60 μm and is suitable for a device with a voltage class of 6500 V. These exemplary epitaxial wafers can be used, for example, in metal-oxide-semiconductor field-effect transistors or junction barrier Schottky diodes.
[0079] The slicing can be carried out by a laser separation process or a laser lift-off process. The laser separation process can, for example, include irradiating the epitaxial ingot with a laser at a given depth corresponding to the desired thickness of the layer to be removed. The irradiation can affect the bond between the carbon crystal layer and the silicon crystal layer, for example, they can be separated from each other. Alternatively, the slicing can be carried out by means of a wire saw or another separation process. The slicing can also be referred to as dicing.
[0080] The method can also include post-processing of the epitaxial wafer, for example, in the form of stepwise surface and edge grinding, chemical mechanical polishing, or wafer cleaning.
[0081] The method according to the present invention further includes repeating the method at least once. When repeating step S1 of the method, the remaining substrate 8 generated during slicing in the previous run is provided as substrate 4 in step S1.
[0082] In one example, when substrate 4 is used for the first time, it has a thickness of 1400 μm. The conductive layer 6 is grown thereon until the conductive layer 6 has a thickness of 350 μm. Thus, the epitaxial ingot has a total thickness of 1750 μm. During slicing, the epitaxial ingot is divided into epitaxial wafers, which include a 350-μm-thick conductive layer 6 and a drift layer 7 with a thickness of 10 μm, as well as the remaining substrate 8. Theoretically, the remaining substrate 8 has a thickness of 1390 μm. However, additional material is removed during the slicing process, which is why the remaining substrate 8 in this example has a thickness of 1240 μm. Thereafter, during the repetition of the method, the 1240-μm-thick remaining substrate 8 can be used as substrate 4 in the next run. This can be repeated until substrate 4 is completely consumed. The number of times substrate 4 can be reused depends on the original thickness of substrate 4.
[0083] Figures 3a - 3c Schematically shows substrate 4 and conductive layer 6 at various stages of the process for manufacturing SiC epitaxial wafers. Figure 3a Only substrate 4 before the growth of conductive layer 6 is shown. Figure 3a Represents substrate 4 when substrate 4 is disposed in the inner container 2 of the growth system 1 (S1). Figure 3b Shows substrate 4 when the conductive layer 6 has been grown thereon (S6). Thus, Figure 3b Substrate 4 and conductive layer 6 in can be regarded as showing the epitaxial ingot. As described above, line A-A represents a plane substantially parallel to the grown conductive layer 6. Plane A-A can be regarded as perpendicular to the growth direction of the grown conductive layer 6. Figure 3c Shows the epitaxial wafer after the slicing step (S7) through the plane represented by line A-A, which includes the conductive layer 6 and the drift layer 7, as well as the remaining substrate 8. The relative thickness between substrate 4 and conductive layer 6 in the figure should not be regarded as limiting the scope of the present invention. The relative thickness between the remaining substrate 8 and the epitaxial wafer in the drawings should not be regarded as limiting the scope of the present invention.
[0084] Preferred embodiments of SiC epitaxial wafers, their manufacturing methods, and systems have been disclosed above. However, those skilled in the art recognize that this can vary within the scope of the appended claims without departing from the idea of the present invention.
[0085] Without departing from the idea of the present invention, all the above alternative embodiments or parts of the embodiments can be freely combined with each other or used separately, as long as the combination is not contradictory.
Claims
1. A method for manufacturing a silicon carbide (SiC) epitaxial wafer in a wafer growth system (1), the wafer growth system (1) comprising: Outer container; Heat-insulating container disposed inside the outer container; Growth container (2) disposed inside the heat-insulating container; And Heating device disposed outside the outer container to heat the interior of the growth container (2), The method includes: Providing a source material (3) of polycrystalline SiC in the growth container (2); Provide a substrate (4) of single crystal SiC substantially parallel to the source material (3) in the growth container (2), the doping concentration of the substrate (4) ≤ 5·10 16 cm -3 ; Raising the temperature in the growth container (2) to the sublimation temperature of the source material (3); Maintain the temperature in the growth container (2) until a conductive layer (6) of single-crystal SiC with a thickness ≥ 10 μm and a doping concentration ≥ 1·10 18 cm -3 is grown on the substrate (4), wherein the substrate (4) and the grown conductive layer (6) together define an epitaxial ingot; Cooling the epitaxial ingot to room temperature; and Slicing the epitaxial ingot through the substrate (4) in a plane substantially parallel to the plane of the grown conductive layer (6) into a remaining substrate (8) and an epitaxial wafer, the epitaxial wafer including a substrate layer (7) having the grown conductive layer (6) thereon.
2. The method according to claim 1, wherein the doping concentration of the substrate (4) is ≤ 1·10 16 cm -3 .
3. The method according to any one of the preceding claims, wherein the thickness of the substrate (4) is ≥ 100 μm.
4. The method according to any one of the preceding claims, wherein the substrate (4) is substantially free of basal plane dislocations.
5. The method according to any one of the preceding claims, wherein the substrate (4) is substantially free of stacking faults.
6. The method according to any one of the preceding claims, wherein the conductive layer (6) is grown on the carbon face of the substrate (4).
7. The method according to any one of the preceding claims, further comprising repeating the method at least once, the method further comprising: Reusing the remaining substrate (8) as the substrate (4) in the growth container (2).
8. A silicon carbide (SiC) epitaxial wafer, comprising: Doping concentration ≤ 5·10 16 cm -3 substrate layer (7) of single crystal SiC; and Doping concentration ≥ 1·10 18 cm -3 of the conductive layer (6) of single crystal SiC, Wherein the epitaxial wafer is manufactured by the following process: Providing a source material (3) of polycrystalline SiC in the growth container (2); Providing a substrate (4) of single-crystalline SiC substantially parallel to the source material (3) in the growth container (2), the doping concentration of the substrate (4) ≤ 5·10 16 cm -3 ; Raising the temperature in the growth container (2) to the sublimation temperature of the source material (3); Maintain the temperature in the growth container (2) until a conductive layer (6) of single-crystalline SiC with a doping concentration ≥ 1·10 18 cm -3 and a thickness ≥ 10 μm is grown on the substrate (4), wherein the substrate (4) and the grown conductive layer (6) together define an epitaxial ingot; Cooling the epitaxial ingot to room temperature; and Slicing the epitaxial ingot through the substrate (4) in a plane substantially parallel to the plane of the grown conductive layer (6) into a remaining substrate (8) and an epitaxial wafer, the epitaxial wafer including a substrate layer (7) on which the grown conductive layer (6) is grown.
9. The epitaxial wafer as claimed in claim 8, wherein the doping concentration of the substrate layer (7) of the epitaxial wafer ≤ 1·10 16 cm -3 .
10. The epitaxial wafer as claimed in claim 8 or 9, wherein the substrate layer (7) of the epitaxial wafer is substantially free of basal plane dislocations.
11. The epitaxial wafer as claimed in any one of claims 8 to 10, wherein the substrate layer (7) of the epitaxial wafer is substantially free of stacking faults.
12. The epitaxial wafer as claimed in any one of claims 8 to 11, wherein the conductive layer (6) is grown on the carbon face of the substrate (4).
13. The epitaxial wafer as claimed in any one of claims 8 to 12, wherein the conductive layer (6) exhibits a doping uniformity of ≤ 15%, preferably ≤ 10%, more preferably ≤ 5%, and most preferably ≤ 2%.