Intelligent microsystem for deep space exploration task

Abstract

The invention provides an intelligent microsystem for a deep space exploration task, which belongs to the technical field of spaceflight and comprises a high-performance processor, a graphics processing unit (GPU), a neural network processor (NPU), a storage system, a power supply system, a high-speed signal interface, a redundancy reinforcement unit and the like. The method can cover deep space exploration tasks such as landform recognition and mineral recognition, and has the advantages of being intelligent, high in universality, high in reliability and the like.

Description

Technical Field

[0001] The present invention belongs to the field of aerospace technology, and particularly relates to an intelligent microsystem for deep space exploration missions. Background Art

[0002] In the current field of deep space exploration, high requirements are put forward for the intelligence and networking of information systems. Taking deep space exploration missions as an example, due to the long distance and the difficulty of real-time ground measurement and control, it is required that the detector has strong autonomous management and information processing capabilities, and the transmission of a large amount of image data back to the earth poses a great challenge to the data transmission ability. The artificial intelligence microsystem is the carrier and basis for realizing tasks such as spacecraft information extraction, environment perception, autonomous judgment, and autonomous mission planning.

[0003] In the domestic commercial field, corresponding artificial intelligence chip products have been developed and certain achievements have been made. However, in the aerospace field, due to certain requirements for reliability, radiation resistance, efficiency, integration, applicability, and versatility, the artificial intelligence chips in the commercial field cannot be directly applied to spacecraft. Therefore, it is necessary to carry out research on the architecture design method of high reliability, lightweight, and radiation resistance based on COTS artificial intelligence chips to realize microsystem electronic products that meet the special requirements of the aerospace field.

[0004] The main problems existing in traditional microsystem electronic devices are as follows:

[0005] (1) Lack of the carrier and basis for intelligent task processing in deep space exploration. The present invention breaks through the design technology of multi-core heterogeneous intelligent microsystems to form a highly reliable artificial intelligence microsystem suitable for deep space exploration missions.

[0006] (2) The anti-radiation ability of the new artificial intelligence microsystem is insufficient. In view of the fact that the anti-radiation index of existing COTS artificial intelligence chips cannot meet the application requirements of deep space exploration, the present invention breaks through the protection design methods for anti-single event upset and anti-single event latch of microsystems to meet the applicability requirements of microsystems in deep space exploration environments.

[0007] (3) The problem that traditional microsystem electronic products cannot be applied to multiple task requirements. The present invention breaks through the multi-task scheduling and generalization architecture technology to meet the requirements of multiple deep space exploration model tasks. Summary of the Invention

[0008] In order to overcome the deficiencies of the prior art, the present invention provides an intelligent microsystem for deep space exploration missions, which can cover deep space exploration missions such as terrain and landform recognition and mineral recognition, and has the characteristics of intelligence, strong versatility, and high reliability.

[0009] To achieve the above object, the present invention adopts the following technical solutions:

[0010] An intelligent microsystem for deep space exploration missions, comprising:

[0011] A high-performance processor, which is used to control the task processing of a graphics processor and a neural network processor, and sends the task data received by the high-speed signal interface to the control graphics processor and the neural network processor respectively according to two task types: image processing and data inference;

[0012] A graphics processor, which is used to receive images related to terrain and landforms in deep space exploration tasks, encode and decode the images, and perform terrain and landform deep learning model training and inference to intelligently identify terrain and landforms;

[0013] A neural network processor, which is used to receive spectral information for mineral identification in deep space exploration tasks, perform mineral identification deep learning model training and inference to intelligently identify minerals;

[0014] A storage system, which is used to store data in the graphics processor and the neural network processor;

[0015] A high-speed signal interface, which is used to receive external data and transmit the data to the high-performance processor;

[0016] A single-event effect resistant unit, which is used to perform single-event effect resistance reinforcement on the high-performance processor, the graphics processor, the neural network processor, the storage system, and the high-speed signal interface;

[0017] A power supply system, which is used to supply power to the high-performance processor, the graphics processor, the neural network processor, the storage system, the high-speed signal interface, and the single-event effect resistant unit.

[0018] The present invention breaks through key technologies such as multi-core heterogeneous intelligent microsystem design technology, multi-task scheduling and general-purpose microsystem architecture design technology, and microsystem single-event upset and single-event latch-up protection technology, and forms an intelligent microsystem applicable to deep space exploration tasks. The beneficial effects are as follows:

[0019] (1) The present invention breaks through the multi-core heterogeneous intelligent microsystem design technology and forms a highly reliable artificial intelligence microsystem applicable to deep space exploration tasks.

[0020] (2) Aiming at the problem that the radiation resistance index of existing COTS artificial intelligence chips cannot meet the application requirements of deep space exploration, the present invention breaks through the single-event upset and single-event latch-up protection design method of the microsystem to meet the applicability requirements of the microsystem in the deep space exploration environment.

[0021] (3) The present invention breaks through the multi-task scheduling and general-purpose architecture technology to meet the requirements of multiple deep space exploration model tasks.

[0022] The present invention promotes the application of artificial intelligence microsystem electronic products in the field of deep space exploration, solves the problem of "being stuck" of artificial intelligence devices used in spacecraft in the field of deep space exploration, realizes the research and application of the first artificial intelligence microsystem electronic product in the field of deep space exploration, lays a solid foundation for the development of intelligent spacecraft, and realizes the independent and self-reliant development of the core key technologies of artificial intelligence microsystems in the field of China's spaceflight. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a block diagram of a smart microsystem for deep space exploration missions according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0025] As Figure 1 shown, a smart microsystem for deep space exploration missions according to an embodiment of the present invention includes a high-performance processor, a graphics processor, a neural network processor, a storage system, a power supply system, a high-speed signal interface, and a single-event effect hardening unit.

[0026] The high-performance processor is used to control the task processing of the graphics processor and the neural network processor, and send the task data received by the high-speed signal interface to the control graphics processor and the neural network processor respectively according to two task types of image processing and data reasoning.

[0027] The graphics processor is used to receive images such as terrain and landforms in deep space exploration missions, encode and decode the images, and use the graphics processor to train and infer a deep learning model for terrain and landforms for intelligent identification of terrain and landforms.

[0028] The neural network processor is used to receive spectral information for mineral identification in deep space exploration missions, and use the neural network processor to train and infer a deep learning model for mineral identification for intelligent identification of minerals.

[0029] The storage system is used to store data in the graphics processor and the neural network processor.

[0030] The high-speed signal interface is used to receive external data and transmit the data to the high-performance processor.

[0031] The power supply system is used to supply power to the high-performance processor, the graphics processor, the neural network processor, the storage system, the high-speed signal interface, and the single-event effect hardening unit.

[0032] The single-event effect hardening unit is used for single-event effect hardening of high-performance processors, graphics processors, neural network processors, storage systems, and high-speed signal interfaces.

[0033] Preferably, the high-performance processor includes a general-purpose processor CPU with a working main frequency above 1 GHz; the CPU is interconnected with the neural network processor through a 10 Gigabit Ethernet, and the CPU is connected to the GPU through the high-speed PCI Express 4.0 computer expansion bus standard. The CPU is used to control the graphics processor and the neural network processor NPU, and send transmission and working instructions according to two task types of image processing and data inference.

[0034] Preferably, the graphics processor includes a general-purpose GPU with a computing power of not less than 10 Tops and 4K high-definition video encoding and decoding capabilities. The GPU is used to receive images such as terrain and landforms in deep space exploration tasks, encode and decode the images, complete deep learning model training and inference within the graphics processor GPU, and send the intelligent recognition results of terrain and landforms to PCIe4.0.

[0035] Preferably, the neural network processor includes an NPU with a computing power of not less than 4 Tops and neural network inference computing and real-time encryption and decryption capabilities, which is used to receive spectral information for mineral identification in deep space exploration tasks, complete deep learning model training and inference for mineral identification within the NPU, and send the intelligent recognition results of terrain and landforms to the 10 Gigabit Ethernet.

[0036] Preferably, the storage system includes a Flash and a DDR storage system;

[0037] The Flash is used to store instructions and control information sent by the CPU.

[0038] The DDR storage system is used to store data of the GPU and NPU transmitted through PCIe.

[0039] The Flash has a capacity of at least 1G; the DDR storage system is of the fourth generation or above with a capacity greater than 16 Gb.

[0040] Preferably, the high-speed signal interface includes a 10 Gigabit Ethernet interface, PCIe4.0, mipi interface, USB interface, HDMI interface, and serial port.

[0041] Preferably, the power supply system includes a power control chip, which can supply voltages of 0.8V, 1.2V, 1.8V, 3.3V, and 5V to power the high-performance processor, graphics processor, neural network processor, storage system, high-speed signal interface, and single-event effect hardening unit.

[0042] Preferably, the single-event effect resistant unit includes a power supply monitoring chip, a watchdog circuit, and a triple modular redundancy radiation resistant circuit based on critical instructions.

[0043] The power supply monitoring chip is used to monitor the current anomaly caused by single-event latch-up in the intelligent micro-system device. If a large current occurs, it can automatically shut down the power supply system.

[0044] The watchdog circuit is used to monitor the functional errors caused by single-event upsets inside the electronic device. If a functional anomaly occurs, it can automatically send a reset instruction.

[0045] For the critical instructions in the program, the triple modular redundancy radiation resistant circuit based on critical instructions adopts the method of repeated execution, that is, the program is fortified by means of code redundancy; the critical instructions are processed with triple modular redundancy, and only when two judgments are consistent, the judgment result is considered correct.

[0046] In summary, the present invention can improve the task processing efficiency and the applicability to various tasks: through the collaborative work of the high-performance processor, GPU, and NPU, the image and spectral data in deep space exploration tasks can be processed quickly. In previous space missions, only the high-performance processor and GPU, or the high-performance processor and NPU were used to work. In view of the task diversity of deep space exploration, there are both visible light image data and non-visible light spectral data. It is necessary to break through the bottleneck of the traditional single processing mode of spacecraft tasks, adopt a multi-core heterogeneous architecture design, and make the high-performance processor, GPU, and NPU work together to process the visible light image data and non-visible light spectral data in real-time and in parallel, solving the problems of low processing efficiency of the traditional space electronic system and inability to adapt to the complexity of deep space exploration tasks.

[0047] The present invention can improve the space environment adaptability: the single-event effect resistant unit can effectively cope with the radiation problems in the deep space exploration environment and improve the stability and reliability of the system in deep space exploration tasks. The present invention innovatively applies industrial off-the-shelf GPU and NPU chips to deep space exploration tasks. Their radiation resistant indexes cannot meet the application requirements of the deep space exploration space environment, and the GPU and NPU are prone to problems such as single-event latch-up and single-function interruption. The present invention adopts a combination of a power supply monitoring chip, a watchdog circuit, and a triple modular redundancy radiation resistant circuit based on critical instructions to solve the single-event effect protection problem of industrial off-the-shelf products at the lowest hardware cost.

[0048] The present invention also enhances scalability: the design of multiple high-speed signal interfaces can meet the data transmission requirements between different devices and has scalability for deep space exploration missions. The CPU and neural network processor of the present invention are interconnected through a 10 Gigabit Ethernet, and the CPU and GPU are interconnected through the high-speed innovative computer expansion bus standard PCIe4.0. Different types of memories such as DDR, FALSH, SRAM, and solid-state memories can be accessed to achieve direct data interaction of different data types between the CPU, NPU, and GPU. The intelligent micro-system of the present invention also has an MIPI interface, a USB interface, an HDMI interface, and a serial port, which can realize data transmission to different external devices and has scalability for different task data such as visible light images, non-visible light spectra, and autonomous health management in deep space exploration, solving the problem that the signal interface data transmission of previous aerospace electronic systems lacks scalability.

[0049] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these changes and modifications.

[0050] The content not detailedly described in the specification of the present invention belongs to the well-known technology of those skilled in the art.

Claims

1. An intelligent microsystem for deep space exploration missions, characterized in that: include: A high-performance processor is used to control the task processing of the graphics processor and the neural network processor, and sends the task data received by the high-speed signal interface to the control graphics processor and the neural network processor respectively according to the two task types of image processing and data reasoning; Graphics processor, used to receive images involving topography in deep space exploration missions, encode and decode the images, and perform topography deep learning model training and reasoning to intelligently identify topography; A neural network processor is used to receive spectral information for mineral identification in deep space exploration missions, conduct deep learning model training and reasoning for mineral identification, and intelligently identify minerals; A storage system for storing data in a graphics processor and a neural network processor; High-speed signal interface, used to receive external data and transmit the data to a high-performance processor; Single particle hardening unit, used to harden high-performance processors, graphics processors, neural network processors, storage systems, and high-speed signal interfaces against single particles; The power supply system is used to supply power to high-performance processors, graphics processors, neural network processors, storage systems, high-speed signal interfaces, and single-particle reinforcement units.

2. The intelligent microsystem for deep space exploration missions according to claim 1, characterized in that: The high-performance processor includes a CPU with a working main frequency of more than 1 GHz; the CPU and the neural network processor are interconnected through 10 Gigabit Ethernet, and the CPU is connected to the graphics processor through the high-speed innovative computer expansion bus standard PCIe4.

0.

3. The intelligent microsystem for deep space exploration missions according to claim 1, characterized in that: The graphics processor includes a GPU with a computing power of no less than 10Tops and 4K high-definition video encoding and decoding capabilities.

4. The intelligent microsystem for deep space exploration missions according to claim 1, characterized in that: The neural network processor includes an NPU with a computing power of no less than 4Tops and neural network reasoning computing capabilities and real-time encryption and decryption capabilities. The NPU is connected to the high-performance processor via 10 Gigabit Ethernet.

5. The intelligent microsystem for deep space exploration missions according to claim 1, characterized in that: The storage system includes Flash and DDR storage systems; the Flash is used to store instructions and control information sent by the high-performance processor; the DDR storage system is used to store graphics processor data and neural network processor data transmitted via PCIe.

6. The intelligent microsystem for deep space exploration missions according to claim 5, characterized in that: The capacity of the Flash is at least 1G; the capacity of the DDR storage system is greater than 16Gb.

7. The intelligent microsystem for deep space exploration missions according to claim 1, characterized in that: The high-speed signal interface includes a 10 Gigabit Ethernet interface, PCIe4.0, a mipi interface, a USB interface, an HDMI interface and a serial port.

8. The intelligent microsystem for deep space exploration missions according to claim 1, characterized in that: The power supply system includes a power supply control chip, which provides 0.8V, 1.2V, 1.8V, 3.3V, and 5V voltages to power high-performance processors, graphics processors, neural network processors, storage systems, high-speed signal interfaces, and anti-single particle reinforcement units.

9. The intelligent microsystem for deep space exploration missions according to claim 1, characterized in that: The anti-single particle reinforcement unit includes a power monitoring chip, a watchdog circuit and a triple-mode redundant anti-radiation reinforcement circuit based on key instructions; The power monitoring chip is used to monitor the current anomaly caused by single particle locking in the intelligent microsystem; The watchdog circuit is used to monitor functional errors caused by single-particle upsets inside the electronic device; The triple-module redundant radiation-resistant reinforcement circuit based on key instructions adopts a method of repeated execution for key instructions in a program, that is, the reinforcement of the program is achieved through a code redundancy method.

10. The intelligent microsystem for deep space exploration missions according to claim 9, characterized in that: The functions of the power monitoring chip include: automatically shutting down the power system if a large current occurs; The functions of the watchdog circuit include: automatically sending a reset instruction if a functional abnormality occurs; The functions of the triple-module redundant radiation-resistant hardened circuit based on key instructions include: performing triple-module redundant processing on control and storage instructions, and only when two judgments are consistent can the judgment result be considered correct.

Images