Failure chip screening method and device, electronic equipment and storage medium

Abstract

The invention provides a failure chip screening method and device, electronic equipment and a storage medium, and relates to the technical field of semiconductors. The failure chip screening method comprises the following steps: collecting multiple groups of test data corresponding to a test chip in multiple test items; based on the outlier degree presented by the known failure chip in the single test item, configuring an initial weight and a reference false killing rate of the test item for failure screening; correcting the initial weight based on the multiple groups of test data to obtain a corrected weight; calculating an initial false killing rate of the test chip under the correction weight; and if the initial mistaken killing rate is greater than the reference mistaken killing rate, performing optimization processing on the correction weight to obtain a target weight, and performing failure screening on the to-be-screened chip based on the target weight. According to the technical scheme, the required data are all from the normal test data of the test chip and the data of the known failure chip, so that the test cost is reduced, the test period is shortened, and a better screening effect can be achieved.

Description

Background Art

[0002] A failed chip refers to a chip that, due to certain reasons, has changes in its size, shape, or the structure and properties of its material and cannot fully perform the specified functions. Before the chip is shipped out of the warehouse, a screening operation for failed chips needs to be carried out. To achieve the screening of failed chips, a failed screening model can be trained through machine learning, so that the failed screening model can perform failed screening on the chips to be screened. However, the machine learning method not only requires a large amount of test data, but also these test data are generated only when the chips reach the aging state, which not only has a high test cost, but also the screening effect of failed chips is not good.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a method for screening failed chips, a device for screening failed chips, and a computer-readable storage medium, which at least to a certain extent overcome the problems of high cost and poor screening effect in the screening scheme of failed chips in the related art.

[0005] Other features and advantages of the present disclosure will become apparent through the following detailed description, or be learned in part through the practice of the present disclosure.

[0006] According to one aspect of the present disclosure, there is provided a method for screening failed chips, including: collecting multiple sets of test data corresponding to a test chip in multiple test items; configuring an initial weight and a reference false rejection rate for failure screening of the test item based on the degree of outlier presented by a known failed chip in a single test item; correcting the initial weight based on the multiple sets of test data to obtain a corrected weight; calculating an initial false rejection rate of the test chip under the corrected weight; if the initial false rejection rate is greater than the reference false rejection rate, performing an optimization process on the corrected weight to obtain a target weight, so as to perform failure screening on the chips to be screened based on the target weight, where the test chip has a target false rejection rate under the target weight, and the target false rejection rate is less than or equal to the reference false rejection rate.

[0007] In one embodiment of the present disclosure, based on the degree of outlier presented by known failed chips in a single test item, the initial weight and reference false positive rate for failure screening are configured for the test item, including: calculating multiple first sigma levels of the multiple known failed chips under the single test item, where the first sigma level is used to present the degree of outlier of the known failed chips; determining the median of the multiple first sigma levels to obtain the median sigma level; calculating the initial weight of the single test item based on the median sigma level; and determining the corresponding reference false positive rate based on the initial weight.

[0008] In one embodiment of the present disclosure, determining the corresponding reference false positive rate based on the initial weight includes: determining the initial weight as a reference threshold; calculating the first median and the first standard deviation of each group of the test data; configuring a screening range based on the first median, the first standard deviation, and the reference threshold to perform reference screening on the test chips based on the screening range, and determining the reference false positive rate based on the reference screening results.

[0009] In one embodiment of the present disclosure, correcting the initial weight based on the multiple groups of test data to obtain a corrected weight includes: performing standardization processing on each group of the test data respectively to generate standardization parameters; determining corresponding screening ability parameters based on the standardization parameters of the single test item; and correcting the initial weight based on the screening ability parameters to obtain the corrected weight.

[0010] In one embodiment of the present disclosure, determining the corresponding screening ability parameters based on the standardization parameters of the single test item includes: constructing a corresponding receiver operating characteristic (ROC) curve for the single test item based on the standardization parameters respectively; calculating the area under the curve (AUC) of each ROC curve as the screening ability parameter.

[0011] In one embodiment of the present disclosure, constructing a corresponding receiver operating characteristic (ROC) curve for the single test item based on the standardization parameters respectively includes: configuring multiple standard deviation thresholds for constructing the ROC curve, and at each standard deviation threshold, determining the number of screened defective chips and the number of mis-killed good chips in the test chips based on each group of the standardization parameters; calculating a first percentage based on the number of screened defective chips and the actual number of defective chips in the test chips, and calculating a second percentage based on the number of mis-killed good chips and the actual number of good chips in the test chips; and constructing the ROC curve with the first percentage as the ordinate and the second percentage as the abscissa.

[0012] In one embodiment of the present disclosure, correcting the initial weight based on the screening ability parameter to obtain the corrected weight includes: determining a correction coefficient as the quotient between the AUC area and a preset correction parameter; correcting the corresponding initial weight based on the correction coefficient to obtain the corrected weight under each test item.

[0013] In one embodiment of the present disclosure, performing standardization processing on each group of the test data to generate a standardization parameter, including: counting the quantiles of each group of the test data; calculating a second standard deviation based on the quantiles; calculating a second sigma level of each test data based on the second standard deviation, and taking the second sigma level as the standardization parameter of the test data.

[0014] In one embodiment of the present disclosure, calculating an initial false kill rate for multiple test chips under the corrected weight, including: calculating the initial false kill rate under the corrected weight based on the standardization parameter.

[0015] In one embodiment of the present disclosure, calculating the initial false kill rate under the corrected weight based on the standardization parameter includes: for a single test item, calculating a single-item score based on the corresponding standardization parameter and the corrected weight; determining a test score of the test chip based on the sum of the multiple single-item scores of the multiple test items; configuring a corresponding screening threshold based on the corrected weight; preliminarily screening the test chip as a good chip or a bad chip based on the relationship between the test score of the test chip and the screening threshold; calculating the initial false kill rate based on the preliminary screening result.

[0016] In one embodiment of the present disclosure, configuring a corresponding screening threshold based on the corrected weight includes: calculating test scores of multiple known failed chips based on the corrected weight; calculating a second median of the test scores of the multiple known failed chips as the screening threshold.

[0017] In one embodiment of the present disclosure, calculating the initial false kill rate based on the preliminary screening result includes: determining the number of good chips initially mis-killed based on the preliminary screening result; determining the initial false kill rate based on the number of good chips initially mis-killed and the actual number of good chips in the test chips.

[0018] In one embodiment of the present disclosure, if the initial false kill rate is greater than the reference false kill rate, optimizing the correction weight to obtain a target weight includes: if the initial false kill rate is greater than the reference false kill rate, generating a correction optimization coefficient based on the AUC area; optimizing the initial weight based on the correction optimization coefficient to obtain an optimized weight, and configuring a corresponding optimized screening threshold based on the optimized weight; calculating a corresponding optimized false kill rate based on the optimized weight and the optimized screening threshold; if the optimized false kill rate is still greater than the reference false kill rate, continue to adjust the optimized coefficient and the optimized screening threshold based on the adjustment of the correction optimization coefficient; if the optimized false kill rate is less than or equal to the reference false kill rate, determining the corresponding optimized weight as the target weight.

[0019] In one embodiment of the present disclosure, generating a correction optimization coefficient based on the AUC area includes: calculating the difference between the AUC area and a preset optimization parameter, and using the difference as a non-common parameter; obtaining the correction optimization coefficient based on the non-common parameter and the descending gradient.

[0020] In one embodiment of the present disclosure, performing failure screening on the chips to be screened based on the target weight includes: determining the optimized screening threshold corresponding to the target weight as the target threshold; performing failure screening on the chips to be screened based on the target weight and the target threshold.

[0021] In one embodiment of the present disclosure, it further includes: determining a plurality of matching test items based on the failure screening target, where the plurality of test items are configured based on the current-related items, voltage-related items, and function-related items of the test chips.

[0022] According to one aspect of the present disclosure, there is provided a screening device for failed chips, including: a collection module for collecting multiple groups of test data corresponding to test chips in a plurality of test items; a configuration module for configuring an initial weight and a reference false kill rate for failure screening of the test items based on the degree of outlier presented by known failed chips in a single test item; a correction module for correcting the initial weight based on the multiple groups of test data to obtain a correction weight; a calculation module for calculating an initial false kill rate of the multiple test chips under the correction weight; a screening module for, if the initial false kill rate is greater than the reference false kill rate, optimizing the correction weight to obtain a target weight, so as to perform failure screening on the chips to be screened based on the target weight, where the multiple test chips have a target false kill rate under the target weight, and the target false kill rate is less than or equal to the reference false kill rate.

[0023] According to another aspect of the present disclosure, there is provided an electronic device, including: a processor; and a memory for storing executable instructions of the processor; the processor is configured to execute the screening method for defective chips in the above first aspect by executing the executable instructions.

[0024] According to yet another aspect of the present disclosure, there is provided a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the above-mentioned screening method for defective chips is implemented.

[0025] The screening solution for defective chips provided by the embodiments of the present disclosure is based on known defective chips such as returned chips to configure the initial weights of the calculation model for defective screening and the reference false rejection rate. Based on multiple groups of test data of the chips that have completed testing, the initial weights are corrected to obtain corrected weights to better adapt to different test items. And based on the evaluation of the chips using the corrected weights, the initial false rejection rate based on the test chips is obtained. If the initial error rate is greater than the reference error rate, that is, the correction coefficient obtained based on multiple groups of test data does not meet the screening requirements. At this time, the corrected weights are optimized until the target false rejection rate that meets the screening requirements is obtained. At this time, the weight corresponding to the target false rejection rate is the target weight, and the target weight is applied to defective screening to obtain a reliable defective screening solution. On the one hand, since there is no need to use the aging test method to obtain test data, the required data all come from the normal test data of the test chips and the data of the known defective chips, reducing the requirements for test data, thereby reducing the test cost and test cycle. On the other hand, the initial weights and the reference false rejection rate are determined based on known defective chips, making the goal of defective screening clearer, and thus having a better screening effect.

[0026] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 A flowchart showing a screening method for defective chips in an embodiment of the present disclosure;

[0029] Figure 2 A flowchart showing another screening method for defective chips in an embodiment of the present disclosure;

[0030] Figure 3 Schematic flowchart showing yet another method for screening failed chips in embodiments of the present disclosure;

[0031] Figure 4 Schematic diagram showing a ROC curve in embodiments of the present disclosure;

[0032] Figure 5 Schematic flowchart showing yet another method for screening failed chips in embodiments of the present disclosure;

[0033] Figure 6 Schematic flowchart showing yet another method for screening failed chips in embodiments of the present disclosure;

[0034] Figure 7 Schematic flowchart showing yet another method for screening failed chips in embodiments of the present disclosure;

[0035] Figure 8 Schematic flowchart showing yet another method for screening failed chips in embodiments of the present disclosure;

[0036] Figure 9 Schematic diagram showing a device for screening failed chips in embodiments of the present disclosure;

[0037] Figure 10 Schematic block diagram showing a structure of an electronic device in embodiments of the present disclosure. Detailed implementation manners

[0038] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments.

[0039] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0040] In order to improve the quality of semiconductor chips, it is necessary to perform statistical analysis and screening on the chips based on the test results after the products are tested. The issues that need to be considered first during screening include:

[0041] (1) The test items are related to the chip quality. However, it is necessary to determine which test items have a greater correlation with failures, select which test items as variables in the screening scheme, and how to determine the weight of each test item.

[0042] (2) The existing test scheme will generate a large amount of test data, and there is also a phenomenon of chip returns for the shipped chips. These existing test data and the related data of the returned chips can also be utilized in optimizing the screening scheme for failed chips to improve the reliability and sustainability of the optimization and reduce the test cost.

[0043] To solve at least one of the above-mentioned considered problems, a screening scheme for failed chips in the present disclosure is proposed.

[0044] For the sake of easy understanding, several terms involved in the present application are first explained below.

[0045] ROC curve (receiver operating characteristic curve), is a graphical tool for depicting the performance of a classifier. It shows the relationship between the true positive rate (TPR) and the false positive rate (FPR) of the classifier at different thresholds.

[0046] AUC (Area Under the Curve) is the area under the ROC curve, representing the area under the ROC curve, which is used to measure the performance of the classifier. The closer the AUC value is to 1, the better the performance of the classifier; conversely, the closer the AUC value is to 0, the worse the performance of the classifier.

[0047] CP (Circuit Probing, Chip Probing) test: Wafer test. The test object is each Die in the whole wafer, aiming to ensure that each Die in the whole wafer can basically meet the device characteristics or design specifications. It usually includes the verification of voltage, current, timing, and function.

[0048] FT (Final Test) test: The test object is the packaged chip. After the CP test, packaging will be carried out, and the FT test will be carried out after packaging, which can be used to detect the process level of the packaging factory.

[0049] MOS transistor, that is, metal (Metal)-oxide (Oxide)-semiconductor (Semiconductor) field effect transistor.

[0050] A chip is an element that integrates many transistors, diodes, and other passive devices on a semiconductor wafer.

[0051] High and low voltage Mbist (memory build-in-self test) refers to the self-test logic test of the memory for storage within a range above or below the normal operating voltage, and can automatically complete the tests of functions such as ROM / RAM / Flash.

[0052] Scan (scanning) step-up and step-down test: It means that under the condition of being lower than the normal operating voltage or higher than the normal operating frequency, a scanning test is performed, test vectors are generated, and it is detected whether the output is correct under the specified input.

[0053] As Figure 1 shown, a method for screening failed chips according to an embodiment of the present disclosure includes:

[0054] Step S102, collecting multiple groups of test data corresponding to the test chips in multiple test items.

[0055] Among them, the test item refers to a test item used to test one or more electrical parameters in the chip. The multiple test items include but are not limited to items for testing current-related items, voltage-related items, and function-related items of the test chip. A group of test data corresponds to the test values of a group of test chips under one electrical parameter. Exemplarily, the electrical parameters of the current-related items include the total power supply current I when all MOS transistors in the chip are in a static state DDQ , the impedance between the input pin and the operating voltage VDD of the chip (Input leakage low, IIL), the impedance between the input pin and VSS (Input leakage high, IIH). The electrical parameters of the voltage-related items include the minimum operating voltage MIN V DD , the maximum voltage when the output pin state of the chip is low (Output Low Voltage, VOL), the minimum voltage when the output pin state is high (Output High Voltage, VOH). The function-related items include high and low voltage MBIST, Scan step-up and step-down test, and digital chip leakage current test (Leakage Test), etc.

[0056] In addition, the multiple test items match the failure screening target, and the failure screening target includes but is not limited to overall reliability failure screening, etc., and a specific performance failure screening, etc.

[0057] Step S104, configuring the initial weight and reference false kill rate for the test item used for failure screening based on the degree of outlier presented by the known failed chips in a single test item.

[0058] Among them, the false kill rate refers to the ratio between the number of chips that are not failed but regarded as defective chips and the total number of good chips.

[0059] To screen out defective chips, a calculation model for judging the quality of chips can be configured. By calculating the scores of chips, it is judged whether they are good chips or defective chips. The calculation model is based on the test scores of chips in multiple test items and the corresponding weight configurations, and the initial weight is the initialized weight configured by the calculation model.

[0060] The reference false kill rate can be understood as the minimum false kill rate of known defective chips obtained statistically in a single test item.

[0061] In addition, one way to obtain known defective chips is to obtain returned chips.

[0062] Exemplarily, the degree of outlier can be represented by the variance σ level. In addition, it can also be represented by the average difference or the coefficient of variation.

[0063] Step S106: Modify the initial weight based on multiple groups of test data to obtain a modified weight.

[0064] Among them, multiple groups of test data characterize the test results. Modifying the initial weight means determining which test has a greater impact on aging based on the test results and modifying the initial weight based on the impact.

[0065] Step S108: Calculate the initial false kill rate of the test chips under the modified weight.

[0066] Among them, the initial false kill rate is the false kill rate corresponding to the modified weight.

[0067] Step S110: If the initial false kill rate is greater than the reference false kill rate, optimize the modified weight to obtain a target weight, and perform failure screening on the chips to be screened based on the target weight. The test chips have a target false kill rate under the target weight, and the target false kill rate is less than or equal to the reference false kill rate.

[0068] Among them, the initial false kill rate being greater than the reference false kill rate indicates that the false kill rate is relatively large, that is, there is a relatively high probability of misidentifying good chips as defective chips. At this time, it is necessary to continue to optimize the modified weight to ensure that the false kill rate during actual screening is less than or equal to the reference false kill rate.

[0069] In addition, after obtaining the target false kill rate, the defective chips can be screened based on the target false kill rate in combination with the scores of the chips.

[0070] In this embodiment, based on known failed chips such as returned chips, the initial weights and reference false rejection rates of the calculation model for failure screening are configured. The initial weights are corrected based on multiple sets of test data of the chips that have completed the tests to obtain corrected weights, so as to better adapt to different test items. And based on the evaluation of the chips using the corrected weights, the initial false rejection rate based on the test chips is obtained. If the initial error rate is greater than the reference error rate, that is, the correction coefficient obtained based on multiple sets of test data does not meet the screening requirements, at this time, the corrected weights are optimized until the target false rejection rate that meets the screening requirements is obtained. At this time, the weights corresponding to the target false rejection rate are the target weights, and the target weights are applied to failure screening, so as to obtain a reliable failure screening scheme. On the one hand, since there is no need to use the aging test method to obtain test data, the required data all come from the normal test data of the test chips and the data of the known failed chips, reducing the requirements for test data, thereby reducing the test cost and test cycle. On the other hand, the initial weights and reference false rejection rates are determined based on known failed chips, making the goals of failure screening clearer, and thus having a better screening effect.

[0071] In an embodiment of the present disclosure, a specific implementation method for configuring the initial weights and reference false rejection rates of a test item for failure screening based on the degree of outlier presented by known failed chips in a single test item includes:

[0072] Step S202, calculate multiple first sigma levels of multiple known failed chips under a single test item, and the first sigma level is used to present the degree of outlier of the known failed chips.

[0073] Among them, by statistically analyzing the relevant data of the known failed chips in a single test item, the first sigma level of each known failed chip can be obtained, and the first sigma level corresponds to the known failed chip.

[0074] Exemplarily, assume that the test items include item A, item B, and item C. For the known failed chips, the first sigma level in item A is σa, the first sigma level in item B is σb, and the first sigma level in item C is σc.

[0075] In addition, as a calculation method of the sigma level, the following calculation formula (1) is used to calculate the first sigma level.

[0076] ABS[(P - Q2) / σ](1)

[0077] Among them, P is the test value of the known failed chip in a test item, σ = (Q3 - Q1) / 1.35, Q1 is the first quartile, Q2 is the median of the test values of multiple test chips in a test item, Q3 is the third quartile, and the ABS function is used to find the absolute value.

[0078] Step S204: Determine the median of multiple first sigma levels to obtain the median sigma level.

[0079] Exemplarily, assume that the number of known failed chips is K, that is, take the median of K σa or K σb or K σc, denoted as σam, σbm, and σcm respectively.

[0080] Step S206: Calculate the initial weight of a single test item based on the median sigma level.

[0081] Exemplarily, as an implementation manner of calculating the initial weight of a single test item based on the median sigma level, σam, σbm, and σcm can be directly used as the initial weight corresponding to each test item.

[0082] Step S208: Determine the corresponding reference false rejection rate based on the initial weight.

[0083] In this embodiment, by calculating the first sigma level, the measurement and description of the outlier degree of known failed chips are realized. Based on the calculation of the median sigma level, the initial weight of a single test item is obtained. The initial weight can reflect the importance of the test item to the failed chips among the known failed chips, which helps to perform targeted screening according to different test items. Further, by determining the reference false rejection rate, a reliability evaluation threshold is set for the calculation model of failure screening, thereby helping to improve the accuracy and efficiency of failure screening and enhancing the level of chip quality control.

[0084] In an embodiment of the present disclosure, determining the corresponding reference false rejection rate based on the initial weight includes: determining the initial weight as the reference threshold; calculating the first median and the first standard deviation of each group of test data; configuring the screening range based on the first median, the first standard deviation, and the reference threshold to perform reference screening on the test chips based on the screening range, and determining the reference false rejection rate based on the reference screening result.

[0085] Wherein, the first median corresponds to the test chips.

[0086] Exemplarily, calculate the false rejection rates p1, p2, and p3 when using σam, σbm, and σcm as the thresholds for test item A, test item B, and test item C respectively, as the corresponding reference false rejection rates.

[0087] In a test item, set the threshold as the reference threshold S, and the screening range is expressed as: Q2 ± S×σ, where Q2 is the first median and σ is the first standard deviation. The test value within the screening range is regarded as a good chip, and outside the screening range is regarded as a bad chip. Since it is known whether all samples are failed (whether to be returned), the ratio of the number of samples that are not failed but regarded as bad chips to the total number of good chips is the false rejection rate.

[0088] In this embodiment, by obtaining the test data of multiple known failed chips, for each set of test data, statistical analysis is performed to calculate the first median and the first standard deviation. Among them, the first median is the middle value of a set of data and can be used as a representative index of the overall data, while the first standard deviation is a measure describing the degree of data dispersion and is used to measure the distribution of data around the average value. A screening range is configured based on the first median, the first standard deviation, and a reference threshold, so as to calculate a reference false rejection rate based on the screening range, thereby ensuring the reliability of the reference false rejection rate.

[0089] As Figure 3 shown, in an embodiment of the present disclosure, the initial weight is corrected based on multiple sets of test data to obtain a corrected weight, including:

[0090] Step S302, perform standardization processing on each set of test data respectively to generate standardization parameters.

[0091] In an embodiment, a specific implementation manner of performing standardization processing on each set of test data respectively to generate standardization parameters includes:

[0092] Count the quantiles of each set of test data, and calculate the second standard deviation based on the quantiles.

[0093] Exemplarily, calculate the median Q2, the first quartile Q1, and the third quartile Q3 of each test item based on each set of test data respectively, and the second standard deviation σ = (Q3 - Q1) / 1.35.

[0094] Calculate the second sigma level of each test data based on the second standard deviation, and use the second sigma level as the standardization parameter of the test data.

[0095] Exemplarily, the second sigma level can also be calculated using the above formula (1).

[0096] Assume that there are a total of T test chips. For test item A, the second sigma levels are σa1, σa2... σaT. For test item B, the second sigma levels are σb1, σb2... σbT. For test item C, the second sigma levels are σc1, σc2... σcT. Most of the second sigma levels are within the numerical range of (0 - 6).

[0097] Step S304, determine the corresponding screening ability parameter based on the standardization parameter of a single test item.

[0098] Among them, the screening ability parameter is used to characterize the screening ability shown by this test item in the screening of failed chips.

[0099] Step S306: Modify the initial weight based on the screening ability parameter to obtain the modified weight.

[0100] In this embodiment, by collecting multiple sets of test data corresponding to a test chip in multiple test items, calculating the screening ability parameter of each test item based on the standardized parameter obtained from the standardized processing of the multiple sets of test data, and further modifying the initial weight based on the screening ability parameter to obtain the modified weight, the reliability and classification ability of the test item are evaluated through the screening ability parameter, and the importance of each test item is more accurately reflected, thereby facilitating providing a more reliable basis for failure screening.

[0101] In an embodiment of the present disclosure, determining the corresponding screening ability parameter based on the standardized parameter of a single test item includes:

[0102] Construct a corresponding Receiver Operating Characteristic (ROC) curve for a single test item based on the standardized parameter.

[0103] Among them, the ROC curve is used to represent the ability of each test item to miskill the chip.

[0104] Calculate the area under the curve (AUC) of each ROC curve as the screening ability parameter.

[0105] Exemplarily, take the area under the curve (AUC) of each ROC curve as the screening ability parameter, and correspondingly obtain areas aa, ab, and ac for test item A, test item B, and test item C.

[0106] In an embodiment of the present disclosure, constructing a corresponding Receiver Operating Characteristic (ROC) curve for a single test item based on the standardized parameter includes:

[0107] Configure multiple standard deviation thresholds for constructing the ROC curve. At each standard deviation threshold, determine the number of defective chips screened and the number of good chips miskilled in the test chip based on each set of standardized parameters; calculate the first percentage based on the number of defective chips screened and the actual number of defective chips in the test chip, and calculate the second percentage based on the number of good chips miskilled and the actual number of good chips in the test chip; construct the ROC curve with the first percentage as the ordinate and the second percentage as the abscissa.

[0108] Exemplarily, according to the known final test results in CP testing or FT testing, by configuring multiple different σ thresholds, P or F is screened out respectively, where P represents good chips and F represents bad chips. Each σ threshold corresponds to a set of (x, y) values. x is the second percentage between the number of good chips misjudged as bad and the actual number of good chips in the test chips, and y is the first percentage between the number of bad chips screened out and the actual number of bad chips in the test chips. Thus, the ROC curve for each test is made. The use of existing test results such as CP / FT reduces the test pressure and reduces additional tests. The ROC curve is as Figure 4 shown.

[0109] In this embodiment, first, multiple standard deviation thresholds for constructing the ROC curve are configured. The standard deviation thresholds can be selected and adjusted according to specific requirements. For each standard deviation threshold, a set of screening results of good chips and bad chips can be obtained based on the test results. In addition, based on the discrimination result of whether each chip is actually a good chip or a bad chip, a set of actual screening results is also obtained. Based on these two sets of screening results, multiple sets of (x, y) values can be obtained. Taking the multiple sets of (x, y) values as multiple points, the ROC curve is plotted point by point. The ROC curve can provide effective performance evaluation indicators and references, and thus can be further used to optimize and improve the screening performance of test chips.

[0110] In an embodiment of the present disclosure, the initial weight is corrected based on the screening ability parameter to obtain the corrected weight, including:

[0111] Determine the quotient between the AUC area and the preset correction parameter as the correction coefficient.

[0112] Exemplarily, the correction parameter is taken as 0.5. The AUC areas obtained for test items A, B, and C are aa, ab, and ac respectively. If aa, ab, and ac are less than or equal to 0.5, the correction coefficient is set to 1. If aa, ab, and ac are greater than 0.5, then aa / 0.5 gives the correction coefficient xa, ab / 0.5 gives the correction coefficient xb, and ac / 0.5 gives the correction coefficient xc.

[0113] Correct the corresponding initial weight based on the correction coefficient to obtain the corrected weight under each test item.

[0114] Exemplarily, the corrected weights for test item A, test item B, and test item C are respectively: za = σam * xa, zb = σbm * xb, zc = σcm * xc, where σam, σbm, and σcm are the initial weights corresponding to each test item respectively.

[0115] In one embodiment of the present disclosure, calculating the initial false kill rate for multiple test chips under the corrected weights includes: calculating the initial false kill rate under the corrected weights based on the normalization parameters.

[0116] In this embodiment, by calculating the initial false kill rate under the corrected weights, the recognition ability and misjudgment rate of the test items for the chips can be evaluated, providing guidance for the subsequent optimization of the weights.

[0117] As Figure 5 shown, in one embodiment of the present disclosure, calculating the initial false kill rate under the corrected weights based on the normalization parameters includes:

[0118] Step S502, for a single test item, calculating the single-item score based on the corresponding normalization parameter and the corrected weight.

[0119] Among them, for a single test item, it is first necessary to use the corresponding normalization parameter and the corrected weight. The normalization parameter is generated by normalizing the original test data to eliminate the scale difference between different test items.

[0120] The corrected weight is used to weight the results of different test items, and the weight value is determined according to its importance and influence. Based on the normalization parameter and the corrected weight, the single-item score can be calculated to measure the performance of the test item in the test chip.

[0121] Step S504, determining the test score of the test chip based on the sum of the multiple single-item scores of the multiple test items.

[0122] Among them, the multiple single-item scores of the multiple test items are weighted and summed to obtain the test score of the test chip, which is used as the comprehensive score of the test chip. The single-item score of each test item is calculated through Step S502, and the weighted sum takes into account the weights and importance of each test item to comprehensively evaluate the overall quality of the chip.

[0123] Exemplarily, taking Chip 1 as an example, the test score of the test chip, that is, the comprehensive score y1 = σa1*za + σb1*zb + σc1*zc.

[0124] Step S506, configuring the corresponding screening threshold based on the corrected weight.

[0125] Among them, an appropriate screening threshold is configured according to the corrected weight. The screening threshold is used as the basis for determining whether the test chip is a good chip or a bad chip according to the test score of the test chip. By adjusting the screening threshold, the relationship between the determination accuracy of good chips and bad chips and the false kill rate can be balanced.

[0126] Step S508, initially screening the test chips as good chips or bad chips based on the relationship between the test score of the test chip and the screening threshold.

[0127] Among them, based on the relationship between the test scores of the test chips and the screening threshold, a preliminary screening operation is carried out. According to the magnitude relationship between the test scores and the screening threshold, the test chips are classified into two categories: good chips and bad chips. This step can quickly and preliminarily evaluate the quality of the chips, providing a basis for subsequent analysis and judgment.

[0128] Step S510, calculate the initial false kill rate based on the preliminary screening result.

[0129] Exemplarily, those with scores lower than the screening threshold are regarded as good chips, and those greater than the screening threshold are regarded as bad chips, and the initial false kill rate P0 at this time is calculated.

[0130] In this embodiment, through the calculation of individual scores based on the standardized parameters and the correction weights, the weighted sum of multiple individual scores is used to obtain the test scores of the test chips. According to the correction weights, the corresponding screening threshold is configured, and the test chips are preliminarily screened as good chips or bad chips. Then, the initial false kill rate is calculated based on the preliminary screening result to further detect whether the initial error rate meets the screening requirements.

[0131] In an embodiment of the present disclosure, step S506, a specific implementation manner of configuring the corresponding screening threshold based on the correction weights includes: calculating the test scores of multiple known failed chips based on the correction weights; calculating the second median of the test scores of multiple known failed chips as the screening threshold.

[0132] Among them, the second median corresponds to the known failed chips.

[0133] In this embodiment, by calculating the test scores of multiple known failed chips based on the correction weights and using the second median of the test scores as the screening threshold, the determination of the screening threshold comprehensively considers the importance of different test items and the test results of the failed chips, thus ensuring the reliability of the screening threshold.

[0134] In an embodiment of the present disclosure, step S510, a specific implementation manner of calculating the initial false kill rate based on the preliminary screening result includes: determining the number of good chips initially mis-killed based on the preliminary screening result; determining the initial false kill rate based on the number of good chips initially mis-killed and the actual number of good chips in the test chips.

[0135] In this embodiment, based on the relationship between the initial false kill rate and the reference false kill rate, it is detected whether the correction weights meet the requirement of calculating the scores of the chips for failure screening based on the scores. Therefore, the initial false kill rate can quantify the accuracy of the preliminary screening, provide feedback for the improvement and optimization of the scheme to reduce the initial false kill rate, and further realize the optimization of the correction weights to obtain the target weights.

[0136] Such as Figure 6As shown, in an embodiment of the present disclosure, in step S110, when the initial false positive rate is greater than the reference false positive rate, an implementation manner of optimizing the correction weight to obtain the target weight includes:

[0137] Step S602, when the initial false positive rate is greater than the reference false positive rate, generate a correction optimization coefficient based on the AUC area.

[0138] In an embodiment of the present disclosure, generating a correction optimization coefficient based on the AUC area includes: calculating the difference between the AUC area and a preset optimization parameter, and using the difference as a non-common parameter; obtaining the correction optimization coefficient based on the non-common parameter and the descent gradient.

[0139] Exemplarily, since the correction coefficient is a non-common term, if the initial false positive rate is greater than the reference false positive rate, it indicates that the correction weight is unreasonable, and the correction coefficient needs to be adjusted. The adjusted correction coefficient is denoted as the correction optimization coefficient, xn'. For test items A, B, and C, the corresponding correction optimization coefficients are xa', xb', and xc' respectively. The calculation formula of the correction optimization coefficient is shown in Equation (2).

[0140] xn' = 1 + vn * J (2)

[0141] Where, for test items A, B, and C, n = a, b, or c, vn is the non-common component, corresponding to va, vb, vc, obtained by calculating the difference between the AUC areas aa, ab, ac and 0.5. The value of parameter J can be determined based on the gradient descent method or other methods with regular changes. For example, the value of parameter J increases gradually from 0.1, 0.2, 0.3..., and the corresponding correction optimization coefficients are xa' = 1 + va * J, xa' = 1 + vb * J, xc' = 1 + vc * J respectively.

[0142] Step S604, optimize the initial weight based on the correction optimization coefficient to obtain the optimized weight, and configure the corresponding optimized screening threshold based on the optimized weight.

[0143] Exemplarily, the correction weights under test item A, test item B, and test item C are: za = σam * xa, zb = σbm * xb, zc = σcm * xc.

[0144] Replace xa with xa', replace xb with xb', and replace xc with xc', and the optimized weights under test item A, test item B, and test item C are: za = σam * xa', zb = σbm * xb', zc = σcm * xc'.

[0145] Recalculate the test scores of each known failed chip based on the optimized weights, and recalculate the second median of the test scores of multiple known failed chips as the corresponding optimized screening threshold.

[0146] Step S606, calculate the corresponding optimized false rejection rate based on the optimized weights and the optimized screening threshold.

[0147] Exemplarily, based on the optimized weights and the optimized screening threshold, calculate the optimized false rejection rate in the same way as calculating the initial false rejection rate.

[0148] Step S608, if the optimized false rejection rate is still greater than the reference false rejection rate, continue to adjust the optimized coefficients and the optimized screening threshold based on the adjustment of the correction optimized coefficient.

[0149] Exemplarily, as a way to continue adjusting the correction optimized coefficient, adjust the value of J in formula (2) based on the gradient descent method or other methods with regular changes.

[0150] Step S610, if the optimized false rejection rate is less than or equal to the reference false rejection rate, determine the corresponding optimized weights as the target weights.

[0151] In this embodiment, through the optimization of the correction coefficient, the correction and optimization of the initial false rejection rate are realized until the optimized false rejection rate is less than or equal to the reference false rejection rate. By continuously adjusting the correction optimized coefficient, the performance of failure screening can be gradually improved, the false rejection rate can be reduced, and the screening effect can be enhanced. Through the calculation of the AUC area and the generation of the correction optimized coefficient, the failure screening performance can be more accurately evaluated, and the optimized coefficient can be adjusted according to the non-common parameters to obtain the target weights that meet the requirements.

[0152] In an embodiment of the present disclosure, in step S110, an implementation manner of performing failure screening on the chips to be screened based on the target weights includes:

[0153] Determine the optimized screening threshold corresponding to the target weights as the target threshold; perform failure screening on the chips to be screened based on the target weights and the target threshold.

[0154] In this embodiment, through the optimized weights and the determination of the target threshold, the failure screening of the chips is realized. The target weights are obtained through the previous optimization process, which can reflect the importance of the test items in the chips. Use the target weights for calculation and judgment, and then compare with the target threshold. If the calculation result is greater than the target threshold, the chip is judged as a failed chip, otherwise it is judged as a normal chip, so that the failure screening of the chips to be screened can be effectively carried out, and the effects of quality control and quality assurance can be improved.

[0155] As Figure 7 shown, according to another embodiment of the present disclosure, the method for screening failed chips includes:

[0156] Step S702: Obtain and store multiple sets of test data of the chip in multiple test items.

[0157] Step S704: Configure the weight of each test item, calculate the test score of each chip based on the weight, and configure the screening threshold based on the test score.

[0158] Step S706: Detect in sequence whether the test score of each chip is less than the screening threshold. If "yes", go to Step S708; if "no", go to Step S712.

[0159] Step S708: Confirm that the chip is qualified and ship it.

[0160] Step S710: Obtain the returned chips that have accumulated a specified duration or a specified quantity, and update the weight and the screening threshold based on the returned chips.

[0161] Step S712: The chip is regarded as an outlier, and the parameters of the outlier chip are fed back to the production and testing links.

[0162] As Figure 8 shown, the screening method for defective chips according to another embodiment of the present disclosure includes:

[0163] Step S802: Collect the test data of the test chips and the test data of the return samples in multiple test items, and perform standardization processing on each item of test data to obtain the first standardized parameter and the second standardized parameter.

[0164] Step S804: Determine the first sigma level and the reference false rejection rate of the return samples in a single test based on the second standardized parameter of the return samples.

[0165] Among them, for each test item, determine the median of the return samples in this test item, obtain the initial weight based on the sigma level between the overall sample median, and calculate the false rejection rate generated by this test item for screening as the reference false rejection rate.

[0166] Step S806: Determine the screening ability of each test based on the first standardized parameter of the test chips.

[0167] Among them, according to the known final test results (P or F) of the test chips in CP or FT, analyze each test item in sequence and obtain the ROC curve of each test item, so as to determine the screening ability based on the ROC curve.

[0168] Step S808: Determine the initial weight based on the first sigma level.

[0169] Among them, determine the initial weight between test items from the total σ level in each test item

[0170] Step S810, determine the weight correction coefficient.

[0171] Among them, from the ROC curves of each test, calculate the AUC area. If the AUC area <= 0.5, set the correction coefficient to 1. If the AUC area > 0.5, calculate the ratio to 0.5 and set it as the correction coefficient of this test item.

[0172] Step S812, determine the corrected weight based on the initial weight and the correction coefficient.

[0173] Step S814, multiply the standardized values of each test item of the returned chips by the corrected weight, calculate the test scores of each returned chip, set a screening threshold based on the test scores of multiple returned chips, the screening threshold is the median of the comprehensive scores of the returned samples, and calculate the initial false rejection rate of the test chips based on the screening threshold.

[0174] Among them, the test score y = a1x1 + a2x2 + ….

[0175] Step S816, determine whether the initial false rejection rate is less than the reference false rejection rate. If "yes", go to step S820. If "no", go to step S818.

[0176] Step S818, proportionally transform the part where the correction coefficient is greater than 1 to optimize the corrected weight, and return to step S812.

[0177] Exemplarily, use the gradient descent method to iteratively find the minimum false rejection rate value and set the optimal threshold.

[0178] Step S820, determine the target weight and the target threshold.

[0179] In this embodiment, by setting an outlier screening method based on multiple variables (test items), a good screening effect can be achieved and the false rejection rate of chip screening can be reduced.

[0180] In addition, the solution of the present disclosure can directly use the existing test data and test items without adding additional test items, fully exploit the existing test data to reduce the test cost, optimize the weight corresponding to each test item, and optimize the weight setting and threshold setting scheme according to the newly generated customer returns, improve the reliability of the screening method, facilitate long-term optimization, and ultimately achieve the purpose of improving chip reliability.

[0181] It should be noted that the above-mentioned drawings are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present invention, rather than for limiting purposes. It is easy to understand that the processes shown in the above-mentioned drawings do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be executed synchronously or asynchronously in, for example, multiple modules.

[0182] Those skilled in the art can understand that various aspects of the present invention can be implemented as a system, a method, or a program product. Therefore, various aspects of the present invention can be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which can be collectively referred to as "circuits", "modules", or "systems" here.

[0183] The following will refer to Figure 9 to describe the screening device 900 for failed chips according to the embodiments of the present invention. Figure 9 The shown screening device 900 for failed chips is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of the present invention.

[0184] The screening device 900 for failed chips is presented in the form of a hardware module. The components of the screening device 900 for failed chips may include but are not limited to: a collection module 902 for collecting multiple sets of test data corresponding to test chips in multiple test items; a configuration module 904 for configuring the initial weight and reference false rejection rate for failure screening of test items based on the degree of outlier presented by known failed chips in a single test item; a correction module 906 for correcting the initial weight based on multiple sets of test data to obtain a corrected weight; a calculation module 908 for calculating the initial false rejection rate of multiple test chips under the corrected weight; a screening module 910 for, if the initial false rejection rate is greater than the reference false rejection rate, performing an optimization process on the corrected weight to obtain a target weight, so as to perform failure screening on the chips to be screened based on the target weight, and multiple test chips have a target false rejection rate under the target weight, and the target false rejection rate is less than or equal to the reference false rejection rate.

[0185] Those skilled in the art can understand that various aspects of the present invention can be implemented as a system, a method, or a program product. Therefore, various aspects of the present invention can be specifically implemented in the following forms, namely: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation combining hardware and software aspects, which can be collectively referred to as "circuits", "modules", or "systems" here.

[0186] The following will refer to Figure 10 to describe the electronic device 1000 according to this embodiment of the present invention. Figure 10 The shown electronic device 1000 is merely an example and should not impose any limitation on the functions and usage scope of the embodiments of the present invention.

[0187] As Figure 10As shown, the electronic device 1000 is presented in the form of a general computing device. The components of the electronic device 1000 may include, but are not limited to: at least one of the above-mentioned processing units 1010, at least one of the above-mentioned storage units 1020, and a bus 1030 that connects different system components (including the storage unit 1020 and the processing unit 1010).

[0188] Among them, the storage unit stores program code, and the program code can be executed by the processing unit 1010, so that the processing unit 1010 executes the steps according to various exemplary embodiments of the present invention described in the "Exemplary Method" section of the present specification. For example, the processing unit 1010 can execute the solution described in steps S102 to S110 as shown in Figure 1 what is shown in.

[0189] The storage unit 1020 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 10201 and / or a cache storage unit 10202, and may further include a read-only storage unit (ROM) 10203.

[0190] The storage unit 1020 may further include a program / utility 10204 having a set (at least one) of program modules 10205. Such program modules 10205 include, but are not limited to: an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include the implementation of a network environment.

[0191] The bus 1030 may represent one or more of several types of bus structures, including a storage unit bus or a storage unit controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0192] The electronic device 1000 can also communicate with one or more external devices 1070 (such as a keyboard, a pointing device, a Bluetooth device, etc.), and can also communicate with one or more devices that enable a user to interact with the electronic device 1000, and / or communicate with any device that enables the electronic device 1000 to communicate with one or more other computing devices (such as a router, a modem, etc.). Such communication can be carried out through the input / output (I / O) interface 1050. Moreover, the electronic device 1000 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) through the network adapter 1060. As shown in the figure, the network adapter 1060 communicates with other modules of the electronic device 1000 through the bus 1030. It should be understood that although not shown in the figure, other hardware and / or software modules can be used in combination with the electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0193] Through the description of the above embodiments, those skilled in the art can easily understand that the exemplary embodiments described herein can be implemented by software, or can be implemented by the way of software combined with necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, and the software product can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the embodiments of the present disclosure.

[0194] In an exemplary embodiment of the present disclosure, there is also provided a computer-readable storage medium, on which a program product capable of implementing the above method of this specification is stored. In some possible implementation manners, various aspects of the present invention can also be implemented in the form of a program product, which includes program code. When the program product runs on an electronic device, the program code is used to enable the electronic device to execute the steps according to various exemplary embodiments of the present invention described in the above "Exemplary Method" section of this specification.

[0195] The program product for implementing the above method according to the embodiments of the present invention can adopt a portable compact disc read-only memory (CD-ROM) and includes program code, and can run on an electronic device, such as a personal computer. However, the program product of the present invention is not limited thereto. In this document, the readable storage medium can be any tangible medium that contains or stores a program, and the program can be used by or in combination with an instruction execution system, device, or device.

[0196] The program product may adopt any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may, for example, but not be limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the readable storage medium (a non-exhaustive list) include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0197] The computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which the readable program code is carried. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable signal medium may also be any readable medium other than the readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0198] The program code contained on the readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical fiber cable, RF, etc., or any suitable combination of the above.

[0199] The program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages such as Java, C++, etc., and also including conventional procedural programming languages such as the "C" language or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's device, executed as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., by connecting through the Internet using an Internet service provider).

[0200] It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, such a division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of the two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided and embodied by multiple modules or units.

[0201] In addition, although the various steps of the methods in the present disclosure are described in a specific order in the drawings, this does not require or imply that these steps must be performed in that specific order, or that all of the steps shown must be performed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0202] From the description of the above embodiments, those skilled in the art can easily understand that the exemplary embodiments described herein can be implemented by software or by a combination of software and necessary hardware. Therefore, the technical solutions according to the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, mobile hard disk, etc.) or on a network, and includes several instructions to enable a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of the present disclosure.

[0203] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed herein. The specification and examples are only to be considered as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A screening method for failed chips, characterized in that, Including: Collecting multiple groups of test data corresponding to a test chip in multiple test items; Configuring an initial weight and a reference false rejection rate for failure screening of the test item based on the degree of outlier presented by known failed chips in a single test item; Correcting the initial weight based on the multiple groups of test data to obtain a corrected weight; Calculating an initial false rejection rate of the test chip under the corrected weight; If the initial false rejection rate is greater than the reference false rejection rate, optimizing the corrected weight to obtain a target weight, so as to perform failure screening on the chips to be screened based on the target weight. The test chip has a target false rejection rate under the target weight, and the target false rejection rate is less than or equal to the reference false rejection rate.

2. The screening method for failed chips according to claim 1, wherein, Configuring an initial weight and a reference false rejection rate for failure screening of the test item based on the degree of outlier presented by known failed chips in a single test item, including: Calculating multiple first sigma levels of the multiple known failed chips under a single test item, where the first sigma level is used to present the degree of outlier of the known failed chips; Determining the median of the multiple first sigma levels to obtain a median sigma level; Calculating the initial weight of a single test item based on the median sigma level; and Determining the corresponding reference false rejection rate based on the initial weight.

3. The screening method for failed chips according to claim 2, wherein, Determining the corresponding reference false rejection rate based on the initial weight, including: Determining the initial weight as a reference threshold; Calculating a first median and a first standard deviation of each group of test data; Configuring a screening range based on the first median, the first standard deviation, and the reference threshold, so as to perform reference screening on the test chip based on the screening range, and determining the reference false rejection rate based on the reference screening result.

4. The screening method for failed chips according to claim 1, characterized in that Correcting the initial weight based on the multiple groups of test data to obtain a corrected weight, including: Performing standardization processing on each group of test data respectively to generate standardization parameters; Determining corresponding screening ability parameters based on the standardization parameters of a single test item; Correcting the initial weight based on the screening ability parameters to obtain the corrected weight.

5. The screening method for failed chips according to claim 4, characterized in that, Determining corresponding screening ability parameters based on the standardization parameters of a single test item, including: Constructing a corresponding receiver operating characteristic (ROC) curve for a single test item based on the standardization parameters; Calculating the area under the curve (AUC) of each ROC curve as the screening ability parameter.

6. The screening method for failed chips according to claim 5, wherein Constructing a corresponding receiver operating characteristic (ROC) curve for a single test item based on the standardization parameters, including: Configuring multiple standard deviation thresholds for constructing the ROC curve; Under each standard deviation threshold, determining the number of screened defective chips and the number of misjudged good chips in the test chip based on each group of standardization parameters; Calculating a first percentage based on the number of screened defective chips and the actual number of defective chips in the test chip, and calculating a second percentage based on the number of misjudged good chips and the actual number of good chips in the test chip; Construct the ROC curve with the first percentage as the ordinate and the second percentage as the abscissa.

7. The screening method for failed chips according to claim 5, characterized in that Correct the initial weights based on the screening ability parameter to obtain the corrected weights, including: Determine the correction coefficient as the quotient between the AUC area and a preset correction parameter; Correct the corresponding initial weights based on the correction coefficient to obtain the corrected weights for each test item.

8. The screening method for failed chips according to claim 4, wherein Perform standardization processing on each group of the test data to generate standardization parameters, including: Statistical quantiles of each group of the test data; Calculate the second standard deviation based on the quantiles; Calculate the second sigma level of each test data based on the second standard deviation, and use the second sigma level as the standardization parameter of the test data.

9. The screening method for failed chips according to claim 4, characterized in that Calculate the initial false kill rate for multiple test chips under the corrected weights, including: Calculate the initial false kill rate under the corrected weights based on the standardization parameters.

10. The screening method for failed chips according to claim 9, characterized in that, Calculate the initial false kill rate under the corrected weights based on the standardization parameters, including: For a single test item, calculate a single item score based on the corresponding standardization parameter and the corrected weight; Determine the test score of the test chip based on the sum of the multiple single item scores of the multiple test items; Configure a corresponding screening threshold based on the corrected weights; Pre-screen the test chips as good chips or bad chips based on the relationship between the test score of the test chip and the screening threshold; Calculate the initial false kill rate based on the pre-screening results.

11. The screening method for failed chips according to claim 10, characterized in that, Configure a corresponding screening threshold based on the corrected weights, including: Calculate the test scores of multiple known failed chips based on the corrected weights; Calculate the second median of the test scores of multiple known failed chips as the screening threshold.

12. The screening method for defective chips according to claim 10, wherein Calculate the initial false kill rate based on the pre-screening results, including: Determine the number of good chips initially mis-killed based on the pre-screening results; Determine the initial false kill rate based on the number of good chips initially mis-killed and the actual number of good chips in the test chips.

13. The screening method for defective chips according to claim 5, wherein If the initial false kill rate is greater than the reference false kill rate, perform optimization processing on the corrected weights to obtain the target weights, including: If the initial false kill rate is greater than the reference false kill rate, generate a correction optimization coefficient based on the AUC area; Optimize the initial weights based on the correction optimization coefficient to obtain optimized weights, and configure corresponding optimized screening thresholds based on the optimized weights; Calculate the corresponding optimized false kill rate based on the optimized weights and the optimized screening thresholds; If the optimized false kill rate is still greater than the reference false kill rate, continue to adjust the optimization coefficient and the optimized screening threshold based on the adjustment of the correction optimization coefficient; If the optimized false kill rate is less than or equal to the reference false kill rate, determine the corresponding optimized weights as the target weights.

14. The screening method for failed chips according to claim 13, characterized in that, Generate a correction optimization coefficient based on the AUC area, including: Calculate the difference between the AUC area and a preset optimization parameter, and use the difference as the non-common parameter; Obtain the correction optimization coefficient based on the non-common parameter and the descent gradient.

15. The screening method for failed chips according to claim 13, wherein Performing failure screening on the chips to be screened based on the target weights, including: Determining the optimized screening threshold corresponding to the target weight as the target threshold; Performing failure screening on the chips to be screened based on the target weight and the target threshold.

16. The screening method for failed chips according to any one of claims 1 to 15, characterized in that It further includes: Determining the matching multiple test items based on the failure screening target, wherein the multiple test items are configured based on the current-related items, voltage-related items, and function-related items of the test chips.

17. A screening device for failed chips, characterized in that, It includes: A collection module for collecting multiple groups of test data corresponding to the test chips in multiple test items; A configuration module for configuring the initial weight and the reference false kill rate for failure screening of the test items based on the degree of outliers presented by the known failed chips in a single test item; A correction module for correcting the initial weight based on the multiple groups of test data to obtain a corrected weight; A calculation module for calculating the initial false kill rate of the multiple test chips under the corrected weight; A screening module for, if the initial false kill rate is greater than the reference false kill rate, performing optimization processing on the corrected weight to obtain a target weight, so as to perform failure screening on the chips to be screened based on the target weight, and the multiple test chips have a target false kill rate under the target weight, and the target false kill rate is less than or equal to the reference false kill rate.

18. An electronic device, characterized in that, It includes: A processor; And A memory for storing the executable instructions of the processor; wherein the processor is configured to execute the screening method of the failed chips according to any one of claims 1 to 16 by executing the executable instructions.

19. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the screening method of the failed chips according to any one of claims 1 to 16.

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