An Alliance toolchain logic synthesis method based on multiple logical domains

Abstract

The present invention discloses a logic synthesis method for an Alliance tool chain based on multiple logical domains, comprising the following steps: obtaining an intermediate representation structure of a target circuit; mapping a Boolean expression in the intermediate representation structure to an XMG network equivalent to the logical function of the target circuit; performing logic optimization aiming at optimizing the logic hierarchy on the mapped XMG network; converting the XMG network with optimized logic hierarchy into an AIG network; performing logic optimization aiming at optimizing the number of nodes on the converted AIG network, and outputting the optimized AIG network as an aig file; reading the aig file, parsing and outputting it as a VHDL file, and inputting the VHDL file to the Alliance tool chain to generate a gate-level netlist corresponding to the optimized target circuit. This method can greatly improve the efficiency and scalability of logic optimization, effectively solve the performance bottleneck of the existing Alliance tool chain, and significantly enhance the ability of the Alliance tool chain to process large-scale circuit designs.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and particularly relates to a logic synthesis method of an Alliance tool chain based on multiple logic domains, which is used to improve the performance of the Alliance tool chain in designing large-scale circuits and complex circuits. Background Art

[0002] Alliance is an open-source computer-aided design (CAD) tool suite for very large scale integration (VLSI) design, which has functions such as a VHDL compiler, a simulator, a logic synthesis tool, and automatic placement and routing. The Alliance tool chain is entirely written in C and provides a Hurricane database for storing and managing all relevant information in chip design, such as components, netlists, placement, and routing. The Alliance tool chain supports the entire process from logic design to physical design, covering a variety of file formats and conversion programs, and is one of the open-source electronic design automation (EDA) tools widely used in academia.

[0003] Most EDA tools were initially developed based on traditional Boolean logic. Therefore, early research on automatic synthesis and optimization technologies mainly focused on single logic domains. However, with the continuous increase in the complexity of integrated circuit design, the optimization methods for single logic domains are no longer able to meet the requirements of modern design. For multi-application scenarios such as high performance, low power consumption, and small area, tools developed based on single logic domains often struggle to effectively balance the conflicts between different design goals, resulting in limited optimization effects. In recent years, with the rapid development of multi-logic domain collaborative optimization technologies, significant progress has been made in this field for open-source EDA tools. ABC combines a logic synthesis method based on AIG (And-Inverter Graphs, AIG) and has good scalability. ABC implements an optimal delay technology mapping algorithm based on a directed acyclic graph (DAG) for two types of circuits: standard cells for ASICs and look-up tables (LUTs) for FPGAs. ALSO is developed and maintained by Ningbo University and provides a series of optimization and technology mapping commands based on multiple logic domains for comprehensive optimization of FPGAs, ASICs, and emerging computing paradigms.

[0004] In terms of logic synthesis, the Alliance toolchain provides the BOOM (Boolean Optimizer, BOOM) tool, which is used to convert high-level abstract descriptions such as VHDL into gate-level circuits. BOOM uses Binary Decision Diagrams (BDDs) to represent circuit information in.vbe files..vbe and.vst are unique intermediate file formats in the Alliance toolchain, used for the behavioral and structural descriptions of hardware design languages (HDLs) respectively. The Alliance toolchain has the following problems:

[0005] 1) Insufficient ability to handle large-scale circuit designs: The BOOM tool provided by the Alliance toolchain relies on BDDs for logic optimization. Although BDDs are very effective in representing small circuits, when dealing with large-scale complex circuit designs, BDDs can lead to significant slowdowns and memory explosion problems. This is because the size of BDDs grows exponentially with the increase in circuit complexity, thus limiting the performance of the BOOM tool, resulting in low design efficiency and difficulty in meeting the requirements of large-scale complex circuit designs;

[0006] 2) Lack of multi-logic domain optimization ability: The existing Alliance toolchain is difficult to efficiently support the collaborative optimization of multiple logic domains such as area and power consumption, and cannot meet the multi-objective requirements of modern VLSI designs;

[0007] 3) Insufficient scalability of the toolchain: The Alliance toolchain lacks the ability to efficiently integrate with external optimization tools, restricting its functional expansion and performance improvement. Summary of the Invention

[0008] The technical problem to be solved by the present invention is, aiming at the deficiencies of the prior art, to provide a multi-logic domain-based Alliance toolchain logic synthesis method, which can significantly improve the efficiency and scalability of logic optimization, effectively solve the performance bottleneck of the existing Alliance toolchain in large-scale and complex circuit designs, and significantly enhance the ability of the Alliance toolchain to handle large-scale circuit designs.

[0009] The technical solution adopted by the present invention to solve the above technical problem is: A multi-logic domain-based Alliance toolchain logic synthesis method, including the following steps:

[0010] Step 1: Design the read_vbe method using the lorina library and integrate it into the open-source tool ALSO. By using the read_vbe method, read the vbe format file of the target circuit to be optimized, extract the topological structure information of the target circuit, and obtain the intermediate representation structure of the target circuit that includes the input and output port definitions, internal signal connection relationships, and instantiation descriptions of logic gates, where the logic gates are represented by Boolean expressions.

[0011] Step 2: Map the Boolean expressions in the intermediate representation structure to an XMG network equivalent to the logical function of the target circuit.

[0012] Step 3: Perform logic optimization targeting at optimizing the logic level on the mapped XMG network to obtain the XMG network with optimized logic level.

[0013] Step 4: Output the XMG network with optimized logic level into a Verilog file and convert it to an AIG network using the logic synthesis tool ABC.

[0014] Step 5: Use the logic synthesis tool ABC to perform logic optimization targeting at optimizing the number of nodes on the converted AIG network to obtain the optimized AIG network, and output the optimized AIG network into an aig file.

[0015] Step 6: Design the write_vhd method using the lorina library and integrate it into the open-source tool ALSO. By using the write_vhd method, read the aig file, parse it and output it into a VHDL file. Input the VHDL file to the VASY tool of the Alliance tool chain. Convert the VHDL file to a vbe file through the VASY tool, then perform technology mapping on the vbe file using the BOOG tool of the Alliance tool chain, and use the LOON tool of the Alliance tool chain for post-optimization to generate the gate-level netlist corresponding to the optimized target circuit according to its target technology library.

[0016] Preferably, the specific process of Step 2 is as follows: Based on the XMG network type in the open-source tool ALSO, parse the Boolean expressions in the intermediate representation structure level by level and construct a graph structure, identify the logic subgraphs that can be converted into three-input majority gates, perform algebraic transformation on multiple exclusive-or chains in the logic subgraphs and convert them into shared node structures, and generate an XMG network equivalent to the logical function of the target circuit.

[0017] Preferably, the specific process of Step 3 is as follows:

[0018] Step 3.1: Define the globally logically optimal XMG network as the XMG network with the smallest logic level in the logic optimization process.

[0019] Step 3.2: Iteratively use the XMG network logic rewriting method, XMG network logic re-replacement method, and method for balancing the XMG network in the open-source tool ALSO to optimize the logical level of the mapped XMG network. Among them, the XMG network logic rewriting method performs matching and structural rewriting of logical subgraphs through a preset XOR-MAJ local replacement rule, streamlining the number of nodes in the XMG network and optimizing the depth of the logical level; the XMG network logic re-replacement method reconstructs the Boolean expressions of logic gates in the XMG network based on cut analysis and Boolean function reconstruction technology while ensuring logical function equivalence; the method for balancing the XMG network makes each part of the XMG network more balanced by rearranging the connections of input signals and logic gates in the XMG network, reducing unnecessary complexity and redundancy, thereby improving the overall efficiency of the XMG network.

[0020] Step 3.3: Compare the depth change of the logical level of the XMG network before and after optimization. If each round of iteration meets the convergence condition: (logical level before optimization - logical level after optimization) / logical level before optimization ≥ the preset convergence rate r1, stop the optimization and output the globally optimal XMG network with the logical level, otherwise continue the optimization until the convergence condition is met or there is no further optimization.

[0021] Preferably, the specific process of step 5 is as follows:

[0022] Step 5.1: Define the globally optimal AIG network with the number of nodes as the AIG network with the smallest number of nodes during the logical optimization process.

[0023] Step 5.2: Iteratively use the optimization script resyn2rs and recadd3 composed of four basic operators rewrite, refactor, resubstitution, and balance in the logic synthesis tool ABC to optimize the number of nodes of the converted AIG network. If each round of iteration meets the convergence condition: (number of nodes before optimization - number of nodes after optimization) / number of nodes before optimization ≥ the preset convergence rate r2, stop the optimization, output the globally optimal AIG network with the number of nodes and output it as an aig file, otherwise continue the optimization until the convergence condition is met or there is no further optimization.

[0024] Compared with the prior art, the present invention has the following advantages:

[0025] (1)The logic synthesis method of the Alliance toolchain based on multiple logical domains proposed by the present invention is a DAG-based logic synthesis optimization method. By optimizing the XMG network and the AIG network and combining multi-logical domain optimization techniques, it overcomes the problems of memory explosion and low computational efficiency existing in the traditional method of relying on BDD for logic optimization when dealing with large-scale circuits and complex circuit designs. The method of the present invention can greatly improve the efficiency and scalability of logic optimization, effectively solve the performance bottleneck of the existing Alliance toolchain in large-scale circuit and complex circuit designs, significantly enhance the ability of the Alliance toolchain to process large-scale circuit designs, and obtain a gate-level netlist with good results. In the method of the present invention, the application of the XMG network and the AIG network reduces the time and memory consumption in the optimization process, enabling more large-scale and complex circuit designs to be efficiently processed.

[0026] (2)The method of the present invention can achieve the interaction between the Alliance toolchain and the existing tools ALSO and ABC, support balancing and optimization between different targets, thereby improving the comprehensive performance of circuit design and better meeting the requirements of multi-objective optimization in modern VLSI design. By generating VHDL files, the method of the present invention can be seamlessly connected to the subsequent technology mapping, simulation, and physical design processes of the Alliance toolchain, significantly enhancing the scalability and compatibility of the Alliance toolchain.

[0027] (3)Compared with the BOOM tool provided by the Alliance toolchain itself, the logic synthesis method of the Alliance toolchain based on multiple logical domains proposed by the present invention has significant advantages in terms of logic optimization effect. Through multi-logical domain collaborative optimization, the method of the present invention significantly reduces the circuit area and delay. Experimental results show that the optimized circuit area is reduced by 15% and the delay is reduced by 20%. In addition, the experimental results also show that after completing logic optimization using the method of the present invention and using the BOOG tool provided by the Alliance toolchain for technology mapping with the SXLIB process library, the circuit performance is significantly improved in terms of delay (delay) and area: delay (ps) and area (λ 2 ,λ = 55nm) are reduced by 20% and 15% respectively. This result shows that the method of the present invention not only greatly improves the logic optimization effect, processing efficiency, and circuit performance, but also effectively avoids the problems caused by the long calculation time and frequent memory shortage of the BOOM tool. The proposed method of the present invention provides an efficient and flexible logic synthesis method for modern VLSI design, and has important practical significance and teaching value for improving the performance of the Alliance toolchain, an EDA tool in the academic community, and shortening the gap between EDA tools in the academic community and those in the industrial community. Brief Description of the Drawings

[0028] Figure 1 It is a schematic diagram of the front - end process of the existing Alliance tool chain;

[0029] Figure 2 It is a schematic diagram of the optimization process of the c17 circuit by the method of the present invention;

[0030] Figure 3 It is a schematic diagram of the specific optimization process of the c17 circuit by the method of the present invention;

[0031] Figure 4 It is a schematic diagram of the XMG network corresponding to the mapped c17 circuit;

[0032] Figure 5 It is a schematic diagram of the AIG network corresponding to the c17 circuit after logical - level optimization processing;

[0033] Figures 4 - 5 In it, 1, 2, 3, 4, 5 respectively represent the inputs of the target circuit, 0 represents the constant node required for the three - input exclusive - or logic operation (XOR) calculation, po0 and po1 represent the outputs of the target circuit; the solid line with a single arrow represents the connection relationship of nodes, the dashed line with a single arrow represents logical NOT, the AND node represents logical AND, and the OR node represents logical OR. Detailed implementation manners

[0034] The following further describes the present invention in detail with reference to the embodiments accompanied by drawings.

[0035] Figure 1 It shows the front - end process of the existing Alliance tool chain. The traditional method relies on the BDD of the Alliance tool chain for logic optimization. However, when dealing with large - scale circuits, the memory consumption and computational complexity of the BDD data structure increase exponentially, causing system performance bottlenecks. The BOOM tool provided by the Alliance tool chain will report an error due to insufficient memory when processing the EPFL benchmark circuit arbiter, reflecting the limitations of BDD in large - scale circuit design.

[0036] Embodiment: To overcome the problem of the insufficient ability of the Alliance tool chain to handle large - scale circuit design, the c17 circuit in the ISCAS’85 benchmark circuit is used as the target circuit to be optimized, and the logic synthesis method of the Alliance tool chain based on multiple logic domains proposed by the present invention is adopted for optimization. Figure 2 It shows the optimization process of the c17 circuit by the method of the present invention. Figure 3 Then it details the specific optimization process of the c17 circuit by the method of the present invention, including the following steps:

[0037] Step 1: Design the read_vbe method using the lorina library and integrate it into the open-source tool ALSO. By using the read_vbe method, read the vbe format file of the target circuit to be optimized to obtain the vbe file, i.e., the c17.vbe file shown in Table 1, extract the topological structure information of the target circuit, and obtain the intermediate representation structure of the target circuit that includes the input and output port definitions, the internal signal connection relationships, and the instantiation descriptions of logic gates. Among them, the logic gates are represented by Boolean expressions. For example, the logic gate AND is converted to &, the logic gate OR is converted to |, and the logic gate NOT is converted to ~.

[0038] Table 1 c17.vbe

[0039]

[0040] Step 2: Map the Boolean expressions in the intermediate representation structure to an XMG network that is equivalent to the logical function of the target circuit. The specific process is as follows: Based on the XMG network type in the open-source tool ALSO, parse the Boolean expressions in the intermediate representation structure level by level and construct a graph structure, identify the logical subgraphs that can be transformed into three-input majority gates (MAJ-3), perform algebraic transformations on multiple exclusive-OR chains in the logical subgraphs and transform them into shared node structures, and generate an XMG network that is equivalent to the logical function of the target circuit. The above mapping process relies on the node cache and common sub-expression recognition mechanism to achieve efficient reuse of Boolean functions, thereby significantly reducing the number of nodes and logical redundancy. For the c17.vbe file shown in Table 1, after being parsed by the read_vbe method of the open-source tool ALSO, the Figure 4 shown XMG network is generated.

[0041] Step 3: Perform logic optimization on the mapped XMG network with the goal of optimizing the logical level to obtain the XMG network with optimized logical level. The specific process of Step 3 is as follows:

[0042] Step 3.1: Define the globally logically optimal XMG network as the XMG network with the smallest logical level in the logic optimization process;

[0043] Step 3.2: Iteratively use the XMG network logic rewriting method, XMG network logic replacement method, and XMG network balancing method in the open-source tool ALSO to optimize the logical hierarchy of the mapped XMG network. Among them, the XMG network logic rewriting method performs matching and structural rewriting of logical subgraphs through a preset XOR-MAJ local replacement rule, reducing the number of nodes in the XMG network and optimizing the depth of the logical hierarchy; the XMG network logic replacement method reconstructs the Boolean expressions of logic gates in the XMG network based on cut analysis and Boolean function reconstruction technology while ensuring logical function equivalence; the XMG network balancing method rearranges the connections of input signals and logic gates in the XMG network to make each part of the XMG network more balanced, reducing unnecessary complexity and redundancy, thereby improving the overall efficiency of the XMG network;

[0044] Through the above logical rewriting and logical replacement, the sharing degree of logical subgraphs can be improved, the critical path can be further shortened, and thus the delay of the overall circuit can be reduced;

[0045] Step 3.3: Compare the depth change of the logical hierarchy of the XMG network before and after optimization. If each round of iteration meets the convergence condition: (logical hierarchy before optimization - logical hierarchy after optimization) / logical hierarchy before optimization ≥ the preset convergence rate r1, stop the optimization and output the globally optimal XMG network with the logical hierarchy, otherwise continue the optimization until the convergence condition is met or there is no further optimization.

[0046] Step 4: Output the XMG network with the optimized logical hierarchy into a Verilog file and convert it into an AIG network using the logic synthesis tool ABC. During the conversion process, keep the topological structure of the XMG network with the optimized logical hierarchy unchanged, decompose the majority gate MAJ-3 into an equivalent AND / OR combinational logic, and at the same time map the XOR gate into a structured AIG network to ensure that the converted network has good synthesis characteristics and verifiability while maintaining logical function equivalence. As Figure 5 shown, it shows the AIG network corresponding to the c17 circuit after logical hierarchy optimization processing.

[0047] Step 5: Use the logic synthesis tool ABC to perform logical optimization on the converted AIG network with the goal of optimizing the number of nodes, obtain the optimized AIG network, and output the optimized AIG network into an aig file. The specific process of Step 5 is as follows:

[0048] Step 5.1: Define the globally optimal AIG network with the number of nodes as the AIG network with the smallest number of nodes during the logical optimization process;

[0049] Step 5.2: Iteratively use the optimization scripts resyn2rs and recadd3 composed of four basic operators rewrite, refactor, resubstitution, and balance in the logic synthesis tool ABC to optimize the number of nodes of the converted AIG network to further reduce the number of nodes. If the convergence condition is satisfied in each round of iteration: (the number of nodes before optimization - the number of nodes after optimization) / the number of nodes before optimization ≥ the preset convergence rate r2, stop the optimization, output the AIG network with the optimal global number of nodes, and output it as an aig file. Otherwise, continue the optimization until the convergence condition is satisfied or there is no further optimization.

[0050] Step 6: Use the lorina library to design the write_vhd method and integrate it into the open-source tool ALSO. By using the write_vhd method to read the aig file, parse it and output it as a VHDL file, that is, the c17.vhd file shown in Table 2. Input the VHDL file to the VASY tool of the Alliance tool chain. Through the VASY tool, convert the VHDL file into a vbe file, then perform technology mapping on the vbe file through the BOOG tool of the Alliance tool chain, and then use the LOON tool of the Alliance tool chain for post-optimization to generate the gate-level netlist corresponding to the optimized target circuit according to its target technology library.

[0051] Table 2 c17.vhd

[0052]

[0053] Through the above steps, the method of the present invention replaces the traditional BOOM tool. Through the optimized XMG network and AIG network, the present invention significantly improves the efficiency and performance of circuit design. Compared with the existing Alliance tool chain, the method of the present invention can effectively solve the performance bottleneck in the design of large-scale circuits and complex circuits, and provide a more flexible and scalable optimization process.

[0054] The comparison of the optimization effects of the logic synthesis method based on multiple logic domains of the Alliance tool chain proposed by the present invention and the traditional method relying on the BDD of the Alliance tool chain for EPFL benchmark circuits is shown in Table 3. The circuit performance achieved by the method of the present invention is reduced by 20% and 15% respectively in terms of delay (ps) and area (λ 2 , λ = 55nm), and the calculation of the improvement effect does not include the circuits of arbiter and voter that cannot be processed by Alliance.

[0055] Table 3

[0056]

[0057] It can be seen that the method of the present invention can achieve the interaction between the Alliance tool chain and the existing tools ALSO and ABC. By optimizing the XMG network and the AIG network and combining the multi-logical domain optimization technology, not only the logical optimization effect, processing efficiency and circuit performance are greatly improved, but also the problems caused by the BOOM tool due to long calculation time and frequent memory shortage are effectively avoided. The method of the present invention provides a new and efficient solution for the Alliance tool chain to design large-scale circuits and complex circuits. The proposed method of the present invention will provide an important reference for future circuit design and optimization.

Claims

1. A multi-logic domain-based Alliance tool chain logic synthesis method, characterized in that: The following steps are involved: Step 1: Design the read_vbe method using the lorina library and integrate it into the open source tool ALSO. The read_vbe method reads the vbe format file of the target circuit to be optimized, extracts the topological structure information of the target circuit, and obtains the intermediate representation structure of the target circuit, which includes the input and output port definitions, internal signal connection relationships, and instantiation descriptions of logic gates. The logic gates are represented by Boolean expressions. Step 2: Map the Boolean expression in the intermediate representation structure into an XMG network equivalent to the logical function of the target circuit; Step 3: Perform logic optimization on the mapped XMG network with the goal of optimizing the logical level to obtain an XMG network with optimized logical level. The specific process of step 3 is as follows: Step 3.1: Define the optimal XMG network at the global logical level as the XMG network with the smallest logical level during the logic optimization process. Step 3.

2. Iteratively optimize the logical hierarchy of the mapped XMG network using the XMG network logic rewriting method, XMG network logic re-replacement method, and XMG network balancing method in the open source tool ALSO. The XMG network logic rewriting method uses the preset XOR-MAJ local replacement rule to match and rewrite the logic subgraph, streamlining the number of nodes in the XMG network and optimizing the depth of the logic hierarchy. The XMG network logic re-replacement method uses cut analysis and Boolean function reconstruction technology to reconstruct the Boolean expressions of the logic gates in the XMG network while ensuring logical functional equivalence. The XMG network balancing method rearranges the connections between input signals and logic gates in the XMG network to make each part of the XMG network more balanced. Step 3.3: Compare the depth changes of the logical levels of the XMG network before and after optimization. If each iteration meets the convergence condition: (logical level before optimization - logical level after optimization) / logical level before optimization ≥ the preset convergence rate r1, then stop the optimization and output the optimal XMG network at the global logical level. Otherwise, continue the optimization until the convergence condition is met or there is no further optimization. Step 4: Output the optimized XMG network at the logic level into a Verilog file and convert it into an AIG network using the logic synthesis tool ABC. Step 5: Use the logic synthesis tool ABC to perform logic optimization on the converted AIG network with the goal of optimizing the number of nodes to obtain the optimized AIG network, and output the optimized AIG network into an aig file; Step 6. Use the lorina library to design the write_vhd method and integrate it into the open source tool ALSO. Use the write_vhd method to read the aig file, parse it and output it into a VHDL file, input the VHDL file into the VASY tool of the Alliance tool chain, use the VASY tool to convert the VHDL file into a vbe file, and then use the BOOG tool of the Alliance tool chain to process map the vbe file. Then use the LOON tool of the Alliance tool chain for post-optimization, and generate the gate-level netlist corresponding to the optimized target circuit according to its target process library.

2. The Alliance tool chain logic synthesis method based on multiple logic domains according to claim 1, characterized in that: The specific process of step 2 is as follows: based on the XMG network type in the open source tool ALSO, the Boolean expression in the intermediate representation structure is parsed step by step and a graph structure is constructed, a logic subgraph that can be converted into a three-input majority gate is identified, multiple XOR chains in the logic subgraph are algebraically transformed and converted into a shared node structure, and an XMG network equivalent to the logical function of the target circuit is generated.

3. The Alliance tool chain logic synthesis method based on multiple logic domains according to claim 2, characterized in that: The specific process of step 5 is as follows: Step 5.1, define the AIG network with the optimal number of global nodes as the AIG network with the minimum number of nodes during the logic optimization process; Step 5.2, iteratively use the optimization scripts resyn2rs and recadd3 composed of the four basic operators rewrite, refactor, resubstitution and balance in the logic synthesis tool ABC to optimize the number of nodes in the converted AIG network. If each round of iteration meets the convergence condition: (number of nodes before optimization - number of nodes after optimization) / number of nodes before optimization ≥ the preset convergence rate r2, then stop the optimization, output the AIG network with the optimal number of nodes globally and output it to the aig file, otherwise continue the optimization until the convergence condition is met or there is no further optimization.

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